From a820190204aef0739aa3a067d00273d117f9367c Mon Sep 17 00:00:00 2001 From: "Leung, Martin" Date: Fri, 13 May 2022 17:40:42 -0400 Subject: drm/amdgpu/display: Prepare for new interfaces why: lut pipeline will be hooked up differently in some asics need to add new interfaces how: add them Reviewed-by: Krunoslav Kovac Acked-by: Jasdeep Dhillon Tested-by: Daniel Wheeler Signed-off-by: Martin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 17 ++++++- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 52 +++++++++++++--------- drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../amd/display/dc/dce110/dce110_hw_sequencer.c | 23 +++++++--- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 13 +++--- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 4 +- drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 5 +++ .../drm/amd/display/dc/inc/hw_sequencer_private.h | 2 + 10 files changed, 83 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 70be67a56673..661a35473c4d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1507,6 +1507,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) DRM_INFO("Seamless boot condition check passed\n"); } + init_data.flags.enable_mipi_converter_optimization = true; + INIT_LIST_HEAD(&adev->dm.da_list); /* Display Core create. */ adev->dm.dc = dc_create(&init_data); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index a789ea8af27f..55a8f58ee239 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -235,7 +235,8 @@ bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type) if (link->connector_signal == SIGNAL_TYPE_EDP) { /*in case it is not on*/ - link->dc->hwss.edp_power_control(link, true); + if (!link->dc->config.edp_no_power_sequencing) + link->dc->hwss.edp_power_control(link, true); link->dc->hwss.edp_wait_for_hpd_ready(link, true); } @@ -1016,6 +1017,7 @@ static bool detect_link_and_local_sink(struct dc_link *link, bool same_edid = false; enum dc_edid_status edid_status; struct dc_context *dc_ctx = link->ctx; + struct dc *dc = dc_ctx->dc; struct dc_sink *sink = NULL; struct dc_sink *prev_sink = NULL; struct dpcd_caps prev_dpcd_caps; @@ -1095,6 +1097,16 @@ static bool detect_link_and_local_sink(struct dc_link *link, detect_edp_sink_caps(link); read_current_link_settings_on_detect(link); + + /* Disable power sequence on MIPI panel + converter + */ + if (dc->config.enable_mipi_converter_optimization && + dc_ctx->dce_version == DCN_VERSION_3_01 && + link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 && + memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580, + sizeof(link->dpcd_caps.branch_dev_name)) == 0) + dc->config.edp_no_power_sequencing = true; + sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; sink_caps.signal = SIGNAL_TYPE_EDP; break; @@ -1993,7 +2005,8 @@ static enum dc_status enable_link_dp(struct dc_state *state, if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { /*in case it is not on*/ - link->dc->hwss.edp_power_control(link, true); + if (!link->dc->config.edp_no_power_sequencing) + link->dc->hwss.edp_power_control(link, true); link->dc->hwss.edp_wait_for_hpd_ready(link, true); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 03eedffbb5b2..bea77172bd14 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2074,7 +2074,8 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence( uint32_t wait_time = 0; union lane_align_status_updated dpcd_lane_status_updated = {0}; union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; - enum link_training_result status = LINK_TRAINING_SUCCESS; + enum dc_status status = DC_OK; + enum link_training_result result = LINK_TRAINING_SUCCESS; union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; /* Transmit 128b/132b_TPS1 over Main-Link */ @@ -2099,22 +2100,24 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence( lt_settings->pattern_for_eq, DPRX); /* poll for channel EQ done */ - while (status == LINK_TRAINING_SUCCESS) { + while (result == LINK_TRAINING_SUCCESS) { dp_wait_for_training_aux_rd_interval(link, aux_rd_interval); wait_time += aux_rd_interval; - dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status, + status = dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status, &dpcd_lane_status_updated, dpcd_lane_adjust, DPRX); dp_decide_lane_settings(lt_settings, dpcd_lane_adjust, lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); dpcd_128b_132b_get_aux_rd_interval(link, &aux_rd_interval); - if (dp_is_ch_eq_done(lt_settings->link_settings.lane_count, + if (status != DC_OK) { + result = LINK_TRAINING_ABORT; + } else if (dp_is_ch_eq_done(lt_settings->link_settings.lane_count, dpcd_lane_status)) { /* pass */ break; } else if (loop_count >= lt_settings->eq_loop_count_limit) { - status = DP_128b_132b_MAX_LOOP_COUNT_REACHED; + result = DP_128b_132b_MAX_LOOP_COUNT_REACHED; } else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) { - status = DP_128b_132b_LT_FAILED; + result = DP_128b_132b_LT_FAILED; } else { dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX); dpcd_set_lane_settings(link, lt_settings, DPRX); @@ -2123,24 +2126,26 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence( } /* poll for EQ interlane align done */ - while (status == LINK_TRAINING_SUCCESS) { - if (dpcd_lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b) { + while (result == LINK_TRAINING_SUCCESS) { + if (status != DC_OK) { + result = LINK_TRAINING_ABORT; + } else if (dpcd_lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b) { /* pass */ break; } else if (wait_time >= lt_settings->eq_wait_time_limit) { - status = DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT; + result = DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT; } else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) { - status = DP_128b_132b_LT_FAILED; + result = DP_128b_132b_LT_FAILED; } else { dp_wait_for_training_aux_rd_interval(link, lt_settings->eq_pattern_time); wait_time += lt_settings->eq_pattern_time; - dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status, + status = dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status, &dpcd_lane_status_updated, dpcd_lane_adjust, DPRX); } } - return status; + return result; } static enum link_training_result dp_perform_128b_132b_cds_done_sequence( @@ -2149,7 +2154,8 @@ static enum link_training_result dp_perform_128b_132b_cds_done_sequence( struct link_training_settings *lt_settings) { /* Assumption: assume hardware has transmitted eq pattern */ - enum link_training_result status = LINK_TRAINING_SUCCESS; + enum dc_status status = DC_OK; + enum link_training_result result = LINK_TRAINING_SUCCESS; union lane_align_status_updated dpcd_lane_status_updated = {0}; union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } }; @@ -2159,24 +2165,26 @@ static enum link_training_result dp_perform_128b_132b_cds_done_sequence( dpcd_set_training_pattern(link, lt_settings->pattern_for_cds); /* poll for CDS interlane align done and symbol lock */ - while (status == LINK_TRAINING_SUCCESS) { + while (result == LINK_TRAINING_SUCCESS) { dp_wait_for_training_aux_rd_interval(link, lt_settings->cds_pattern_time); wait_time += lt_settings->cds_pattern_time; - dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status, + status = dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status, &dpcd_lane_status_updated, dpcd_lane_adjust, DPRX); - if (dp_is_symbol_locked(lt_settings->link_settings.lane_count, dpcd_lane_status) && + if (status != DC_OK) { + result = LINK_TRAINING_ABORT; + } else if (dp_is_symbol_locked(lt_settings->link_settings.lane_count, dpcd_lane_status) && dpcd_lane_status_updated.bits.CDS_INTERLANE_ALIGN_DONE_128b_132b) { /* pass */ break; } else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) { - status = DP_128b_132b_LT_FAILED; + result = DP_128b_132b_LT_FAILED; } else if (wait_time >= lt_settings->cds_wait_time_limit) { - status = DP_128b_132b_CDS_DONE_TIMEOUT; + result = DP_128b_132b_CDS_DONE_TIMEOUT; } } - return status; + return result; } static enum link_training_result dp_perform_8b_10b_link_training( @@ -7099,7 +7107,8 @@ void dp_enable_link_phy( unsigned int i; if (link->connector_signal == SIGNAL_TYPE_EDP) { - link->dc->hwss.edp_power_control(link, true); + if (!link->dc->config.edp_no_power_sequencing) + link->dc->hwss.edp_power_control(link, true); link->dc->hwss.edp_wait_for_hpd_ready(link, true); } @@ -7226,7 +7235,8 @@ void dp_disable_link_phy(struct dc_link *link, const struct link_resource *link_ link->dc->hwss.edp_backlight_control(link, false); if (link_hwss->ext.disable_dp_link_output) link_hwss->ext.disable_dp_link_output(link, link_res, signal); - link->dc->hwss.edp_power_control(link, false); + if (!link->dc->config.edp_no_power_sequencing) + link->dc->hwss.edp_power_control(link, false); } else { if (dmcu != NULL && dmcu->funcs->lock_phy) dmcu->funcs->lock_phy(dmcu); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 817028d3c4a0..11b02a98cf0f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -337,6 +337,7 @@ struct dc_config { bool is_single_rank_dimm; bool use_pipe_ctx_sync_logic; bool ignore_dpref_ss; + bool enable_mipi_converter_optimization; }; enum visual_confirm { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 7eff7811769d..a76523c95ab2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1245,8 +1245,18 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx) * has changed or they enter protection state and hang. */ msleep(60); - } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) - edp_receiver_ready_T9(link); + } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { + if (!link->dc->config.edp_no_power_sequencing) { + /* + * Sometimes, DP receiver chip power-controlled externally by an + * Embedded Controller could be treated and used as eDP, + * if it drives mobile display. In this case, + * we shouldn't be doing power-sequencing, hence we can skip + * waiting for T9-ready. + */ + edp_receiver_ready_T9(link); + } + } } } @@ -2181,15 +2191,18 @@ static void dce110_setup_audio_dto( build_audio_output(context, pipe_ctx, &audio_output); if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { - /* disable audio DTBCLK DTO */ - dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( - dc->res_pool->dccg, 0); + struct dtbclk_dto_params dto_params = {0}; pipe_ctx->stream_res.audio->funcs->wall_dto_setup( pipe_ctx->stream_res.audio, pipe_ctx->stream->signal, &audio_output.crtc_info, &audio_output.pll_info); + + dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( + dc->res_pool->dccg, + &dto_params); + } else pipe_ctx->stream_res.audio->funcs->wall_dto_setup( pipe_ctx->stream_res.audio, diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c index bbc58d167c63..4519ecef2e7b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c @@ -513,7 +513,7 @@ void dccg31_set_physymclk( /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */ static void dccg31_set_dtbclk_dto( struct dccg *dccg, - struct dtbclk_dto_params *params) + const struct dtbclk_dto_params *params) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); int req_dtbclk_khz = params->pixclk_khz; @@ -579,18 +579,17 @@ static void dccg31_set_dtbclk_dto( void dccg31_set_audio_dtbclk_dto( struct dccg *dccg, - uint32_t req_audio_dtbclk_khz) + const struct dtbclk_dto_params *params) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - if (dccg->ref_dtbclk_khz && req_audio_dtbclk_khz) { + if (params->ref_dtbclk_khz && params->req_audio_dtbclk_khz) { uint32_t modulo, phase; // phase / modulo = dtbclk / dtbclk ref - modulo = dccg->ref_dtbclk_khz * 1000; - phase = div_u64((((unsigned long long)modulo * req_audio_dtbclk_khz) + dccg->ref_dtbclk_khz - 1), - dccg->ref_dtbclk_khz); - + modulo = params->ref_dtbclk_khz * 1000; + phase = div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1), + params->ref_dtbclk_khz); REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, modulo); REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, phase); diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h index 269cabbea72a..f158c1ea214b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h @@ -192,7 +192,7 @@ void dccg31_set_physymclk( void dccg31_set_audio_dtbclk_dto( struct dccg *dccg, - uint32_t req_audio_dtbclk_khz); + const struct dtbclk_dto_params *params); void dccg31_set_hdmistreamclk( struct dccg *dccg, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index c7021915bac8..c1023cc84f55 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -120,11 +120,11 @@ struct dccg_funcs { void (*set_dtbclk_dto)( struct dccg *dccg, - struct dtbclk_dto_params *dto_params); + const struct dtbclk_dto_params *params); void (*set_audio_dtbclk_dto)( struct dccg *dccg, - uint32_t req_audio_dtbclk_khz); + const struct dtbclk_dto_params *params); void (*set_dispclk_change_mode)( struct dccg *dccg, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index f5fd2a067323..5097037e3962 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -346,6 +346,11 @@ struct mpc_funcs { int mpcc_id, const struct mpc_grph_gamut_adjustment *adjust); + bool (*program_1dlut)( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t rmu_idx); + bool (*program_shaper)( struct mpc *mpc, const struct pwl_params *params, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h index 8c2f190c4712..d2cb0e794500 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h @@ -140,6 +140,8 @@ struct hwseq_private_funcs { const struct dc_plane_state *plane_state); bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state); + bool (*set_mcm_luts)(struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state); void (*PLAT_58856_wa)(struct dc_state *context, struct pipe_ctx *pipe_ctx); void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable); -- cgit v1.2.3 From b8b64595d6a1ccd5cdf56c528e921332d1366b22 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 24 May 2022 10:10:18 -0400 Subject: drm/amdgpu: simplify amdgpu_device_asic_has_dc_support() Drop extra cases in the default case. Reviewed-by: Guchun Chen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 26 -------------------------- 1 file changed, 26 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 625424f3082b..ce2293e92db6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3322,32 +3322,6 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) * cause regressions. */ return amdgpu_dc > 0; - case CHIP_HAWAII: - case CHIP_CARRIZO: - case CHIP_STONEY: - case CHIP_POLARIS10: - case CHIP_POLARIS11: - case CHIP_POLARIS12: - case CHIP_VEGAM: - case CHIP_TONGA: - case CHIP_FIJI: - case CHIP_VEGA10: - case CHIP_VEGA12: - case CHIP_VEGA20: -#if defined(CONFIG_DRM_AMD_DC_DCN) - case CHIP_RAVEN: - case CHIP_NAVI10: - case CHIP_NAVI14: - case CHIP_NAVI12: - case CHIP_RENOIR: - case CHIP_CYAN_SKILLFISH: - case CHIP_SIENNA_CICHLID: - case CHIP_NAVY_FLOUNDER: - case CHIP_DIMGREY_CAVEFISH: - case CHIP_BEIGE_GOBY: - case CHIP_VANGOGH: - case CHIP_YELLOW_CARP: -#endif default: return amdgpu_dc != 0; #else -- cgit v1.2.3 From ab9d97d6f9f1bb5de83411581dc6cdf425a83a15 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 24 May 2022 10:17:43 -0400 Subject: drm/amdgpu: convert sienna_cichlid_get_default_config_table_settings() to IP version Use IP version rather than asic type. Reviewed-by: Guchun Chen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 78f3d9e722bb..6b452e3f5ee3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -4192,7 +4192,7 @@ static int sienna_cichlid_get_default_config_table_settings(struct smu_context * table->gfx_activity_average_tau = 10; table->mem_activity_average_tau = 10; table->socket_power_average_tau = 100; - if (adev->asic_type != CHIP_SIENNA_CICHLID) + if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) table->apu_socket_power_average_tau = 100; return 0; -- cgit v1.2.3 From f74e78ca90bd21b47746b90c439709007681f44c Mon Sep 17 00:00:00 2001 From: Mitchell Augustin Date: Wed, 25 May 2022 14:09:14 -0500 Subject: amdgpu: amdgpu_device.c: Removed trailing whitespace Removed trailing whitespace from end of line in amdgpu_device.c Signed-off-by: Mitchell Augustin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index ce2293e92db6..e9155dc1c30c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3343,7 +3343,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) */ bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) { - if (amdgpu_sriov_vf(adev) || + if (amdgpu_sriov_vf(adev) || adev->enable_virtual_display || (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)) return false; -- cgit v1.2.3 From d5fe83d26dae59c5b52105075e8950dea8ce7c19 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Tue, 10 May 2022 16:08:50 +0800 Subject: drm/amd/pm: correct the way for retrieving current uclk frequency There is some problem with average frequency reading. Thus, we switch to the target frequency reading instead. Signed-off-by: Evan Quan Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index 7432b3e76d3d..52b20fad7d1f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -840,7 +840,7 @@ static int smu_v13_0_0_read_sensor(struct smu_context *smu, break; case AMDGPU_PP_SENSOR_GFX_MCLK: ret = smu_v13_0_0_get_smu_metrics_data(smu, - METRICS_AVERAGE_UCLK, + METRICS_CURR_UCLK, (uint32_t *)data); *(uint32_t *)data *= 100; *size = 4; -- cgit v1.2.3 From 66f54992981444cb418f31018e190d15c92d3599 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Mon, 16 May 2022 09:50:31 +0800 Subject: drm/amd/pm: update SMU 13.0.0 driver_if header To fit the latest 78.39.0 PMFW. Signed-off-by: Evan Quan Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h | 6 ++++++ drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h index c1f76236da26..6a817c7ce110 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h @@ -1359,8 +1359,14 @@ typedef struct { uint16_t AverageDclk0Frequency ; uint16_t AverageVclk1Frequency ; uint16_t AverageDclk1Frequency ; + uint16_t PCIeBusy; + uint16_t dGPU_W_MAX; + uint16_t padding; + + uint32_t MetricsCounter; uint16_t AvgVoltage[SVI_PLANE_COUNT]; + uint16_t AvgCurrent[SVI_PLANE_COUNT]; uint16_t AverageGfxActivity ; uint16_t AverageUclkActivity ; diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h index afa1991e26f9..036fd2810ecc 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h @@ -30,7 +30,7 @@ #define SMU13_DRIVER_IF_VERSION_ALDE 0x08 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x04 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04 -#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x28 +#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x29 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x28 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms -- cgit v1.2.3 From e309434ac56774c86e79a50980e8611ce7cc31a3 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Wed, 18 May 2022 11:40:54 +0800 Subject: drm/amd/pm: enable fclk ds feature for SMU 13.0.0 The feature is ready with latest 78.39.0 PMFW. Signed-off-by: Evan Quan Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index 52b20fad7d1f..5c74a72577c6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -300,6 +300,8 @@ smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu, *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT); + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT); + return 0; } -- cgit v1.2.3 From faf26f2b12e1e03956f7e628183e422d94713e4b Mon Sep 17 00:00:00 2001 From: pengfuyuan Date: Thu, 26 May 2022 17:29:09 +0800 Subject: drm/amd: Fix spelling typo in comments Fix spelling typo in comments. Reported-by: k2ci Signed-off-by: pengfuyuan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 4 ++-- drivers/gpu/drm/amd/display/modules/vmid/vmid.c | 2 +- drivers/gpu/drm/amd/include/mes_api_def.h | 2 +- drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/arcturus_ppsmc.h | 2 +- 6 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 30ce6bb6fa77..3ec7427c018c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -274,7 +274,7 @@ extern int amdgpu_vcnfw_log; #define CIK_CURSOR_WIDTH 128 #define CIK_CURSOR_HEIGHT 128 -/* smasrt shift bias level limits */ +/* smart shift bias level limits */ #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 661a35473c4d..1c23a844b161 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6679,7 +6679,7 @@ static void dm_disable_vblank(struct drm_crtc *crtc) dm_set_vblank(crtc, false); } -/* Implemented only the options currently availible for the driver */ +/* Implemented only the options currently available for the driver */ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .reset = dm_crtc_reset_state, .destroy = amdgpu_dm_crtc_destroy, diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index fa39a06eed1d..d52cbc0e9b67 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -619,7 +619,7 @@ static int get_max_dsc_slices(union dsc_enc_slice_caps slice_caps) } -// Increment sice number in available sice numbers stops if possible, or just increment if not +// Increment slice number in available slice numbers stops if possible, or just increment if not static int inc_num_slices(union dsc_enc_slice_caps slice_caps, int num_slices) { // Get next bigger num slices available in common caps @@ -650,7 +650,7 @@ static int inc_num_slices(union dsc_enc_slice_caps slice_caps, int num_slices) } -// Decrement sice number in available sice numbers stops if possible, or just decrement if not. Stop at zero. +// Decrement slice number in available slice numbers stops if possible, or just decrement if not. Stop at zero. static int dec_num_slices(union dsc_enc_slice_caps slice_caps, int num_slices) { // Get next bigger num slices available in common caps diff --git a/drivers/gpu/drm/amd/display/modules/vmid/vmid.c b/drivers/gpu/drm/amd/display/modules/vmid/vmid.c index 61ee4be35d27..2c40212d86da 100644 --- a/drivers/gpu/drm/amd/display/modules/vmid/vmid.c +++ b/drivers/gpu/drm/amd/display/modules/vmid/vmid.c @@ -66,7 +66,7 @@ static void evict_vmids(struct core_vmid *core_vmid) } } -// Return value of -1 indicates vmid table unitialized or ptb dne in the table +// Return value of -1 indicates vmid table uninitialized or ptb dne in the table static int get_existing_vmid_for_ptb(struct core_vmid *core_vmid, uint64_t ptb) { int i; diff --git a/drivers/gpu/drm/amd/include/mes_api_def.h b/drivers/gpu/drm/amd/include/mes_api_def.h index b2a8503feec0..bf3d6ad263f9 100644 --- a/drivers/gpu/drm/amd/include/mes_api_def.h +++ b/drivers/gpu/drm/amd/include/mes_api_def.h @@ -33,7 +33,7 @@ */ enum { API_FRAME_SIZE_IN_DWORDS = 64 }; -/* To avoid command in scheduler context to be overwritten whenenver mutilple +/* To avoid command in scheduler context to be overwritten whenever multiple * interrupts come in, this creates another queue. */ enum { API_NUMBER_OF_COMMAND_MAX = 32 }; diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/arcturus_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/arcturus_ppsmc.h index 45f5d29bc705..15b313baa0ee 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/arcturus_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/arcturus_ppsmc.h @@ -120,7 +120,7 @@ #define PPSMC_MSG_ReadSerialNumTop32 0x40 #define PPSMC_MSG_ReadSerialNumBottom32 0x41 -/* paramater for MSG_LightSBR +/* parameter for MSG_LightSBR * 1 -- Enable light secondary bus reset, only do nbio respond without further handling, * leave driver to handle the real reset * 0 -- Disable LightSBR, default behavior, SMU will pass the reset to PSP -- cgit v1.2.3 From 2f6247dad2c56cfe2df3c6e00586ead5ee905b46 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Fri, 20 May 2022 18:22:21 +0800 Subject: drm/amdgpu/pm: support mca_ceumc_addr in ecctable SMU add a new variable mca_ceumc_addr to record umc correctable error address in EccInfo table, driver side add EccInfo_V2_t to support this feature Signed-off-by: Stanley.Yang Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 1 + .../swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h | 16 ++++++- drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 53 +++++++++++++++++----- 3 files changed, 57 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index b9a6fac2b8b2..28e603243b67 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -328,6 +328,7 @@ struct ecc_info_per_ch { uint16_t ce_count_hi_chip; uint64_t mca_umc_status; uint64_t mca_umc_addr; + uint64_t mca_ceumc_addr; }; struct umc_ecc_info { diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h index 0f67c56c2863..6f92038470ec 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h @@ -519,7 +519,21 @@ typedef struct { } EccInfo_t; typedef struct { - EccInfo_t EccInfo[ALDEBARAN_UMC_CHANNEL_NUM]; + uint64_t mca_umc_status; + uint64_t mca_umc_addr; + uint64_t mca_ceumc_addr; + + uint16_t ce_count_lo_chip; + uint16_t ce_count_hi_chip; + + uint32_t eccPadding; +} EccInfo_V2_t; + +typedef struct { + union { + EccInfo_t EccInfo[ALDEBARAN_UMC_CHANNEL_NUM]; + EccInfo_V2_t EccInfo_V2[ALDEBARAN_UMC_CHANNEL_NUM]; + }; } EccInfoTable_t; // These defines are used with the following messages: diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index fb130409309c..bf124bc98b80 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -82,6 +82,12 @@ */ #define SUPPORT_ECCTABLE_SMU_VERSION 0x00442a00 +/* + * SMU support mca_ceumc_addr in ECCTABLE since version 68.55.0, + * use this to check mca_ceumc_addr record whether support + */ +#define SUPPORT_ECCTABLE_V2_SMU_VERSION 0x00443700 + /* * SMU support BAD CHENNEL info MSG since version 68.51.00, * use this to check ECCTALE feature whether support @@ -1803,7 +1809,8 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, return sizeof(struct gpu_metrics_v1_3); } -static int aldebaran_check_ecc_table_support(struct smu_context *smu) +static int aldebaran_check_ecc_table_support(struct smu_context *smu, + int *ecctable_version) { uint32_t if_version = 0xff, smu_version = 0xff; int ret = 0; @@ -1816,6 +1823,11 @@ static int aldebaran_check_ecc_table_support(struct smu_context *smu) if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION) ret = -EOPNOTSUPP; + else if (smu_version >= SUPPORT_ECCTABLE_SMU_VERSION && + smu_version < SUPPORT_ECCTABLE_V2_SMU_VERSION) + *ecctable_version = 1; + else + *ecctable_version = 2; return ret; } @@ -1827,9 +1839,10 @@ static ssize_t aldebaran_get_ecc_info(struct smu_context *smu, EccInfoTable_t *ecc_table = NULL; struct ecc_info_per_ch *ecc_info_per_channel = NULL; int i, ret = 0; + int table_version = 0; struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table; - ret = aldebaran_check_ecc_table_support(smu); + ret = aldebaran_check_ecc_table_support(smu, &table_version); if (ret) return ret; @@ -1845,16 +1858,32 @@ static ssize_t aldebaran_get_ecc_info(struct smu_context *smu, ecc_table = (EccInfoTable_t *)smu_table->ecc_table; - for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) { - ecc_info_per_channel = &(eccinfo->ecc[i]); - ecc_info_per_channel->ce_count_lo_chip = - ecc_table->EccInfo[i].ce_count_lo_chip; - ecc_info_per_channel->ce_count_hi_chip = - ecc_table->EccInfo[i].ce_count_hi_chip; - ecc_info_per_channel->mca_umc_status = - ecc_table->EccInfo[i].mca_umc_status; - ecc_info_per_channel->mca_umc_addr = - ecc_table->EccInfo[i].mca_umc_addr; + if (table_version == 1) { + for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) { + ecc_info_per_channel = &(eccinfo->ecc[i]); + ecc_info_per_channel->ce_count_lo_chip = + ecc_table->EccInfo[i].ce_count_lo_chip; + ecc_info_per_channel->ce_count_hi_chip = + ecc_table->EccInfo[i].ce_count_hi_chip; + ecc_info_per_channel->mca_umc_status = + ecc_table->EccInfo[i].mca_umc_status; + ecc_info_per_channel->mca_umc_addr = + ecc_table->EccInfo[i].mca_umc_addr; + } + } else if (table_version == 2) { + for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) { + ecc_info_per_channel = &(eccinfo->ecc[i]); + ecc_info_per_channel->ce_count_lo_chip = + ecc_table->EccInfo_V2[i].ce_count_lo_chip; + ecc_info_per_channel->ce_count_hi_chip = + ecc_table->EccInfo_V2[i].ce_count_hi_chip; + ecc_info_per_channel->mca_umc_status = + ecc_table->EccInfo_V2[i].mca_umc_status; + ecc_info_per_channel->mca_umc_addr = + ecc_table->EccInfo_V2[i].mca_umc_addr; + ecc_info_per_channel->mca_ceumc_addr = + ecc_table->EccInfo_V2[i].mca_ceumc_addr; + } } return ret; -- cgit v1.2.3 From b801d8ad1b516a951535241c9cf60cac8f9a5c2b Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Mon, 21 Feb 2022 15:34:41 -0500 Subject: drm/amd: Add atomfirmware.h definitions needed for DCN32/321 Add new structures for DCN 3.2.x. Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/atomfirmware.h | 209 ++++++++++++++++++++++++++--- 1 file changed, 187 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index ae8f6d299ed9..ff855cb21d3f 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -726,18 +726,20 @@ struct vram_usagebyfirmware_v2_1 *************************************************************************** */ -enum atom_object_record_type_id -{ - ATOM_I2C_RECORD_TYPE =1, - ATOM_HPD_INT_RECORD_TYPE =2, - ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9, - ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16, - ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17, - ATOM_ENCODER_CAP_RECORD_TYPE=20, - ATOM_BRACKET_LAYOUT_RECORD_TYPE=21, - ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22, - ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE=23, - ATOM_RECORD_END_TYPE =0xFF, +enum atom_object_record_type_id { + ATOM_I2C_RECORD_TYPE = 1, + ATOM_HPD_INT_RECORD_TYPE = 2, + ATOM_CONNECTOR_CAP_RECORD_TYPE = 3, + ATOM_CONNECTOR_SPEED_UPTO = 4, + ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE = 9, + ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE = 16, + ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE = 17, + ATOM_ENCODER_CAP_RECORD_TYPE = 20, + ATOM_BRACKET_LAYOUT_RECORD_TYPE = 21, + ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE = 22, + ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE = 23, + ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE = 25, + ATOM_RECORD_END_TYPE = 0xFF, }; struct atom_common_record_header @@ -760,6 +762,19 @@ struct atom_hpd_int_record uint8_t plugin_pin_state; }; +struct atom_connector_caps_record { + struct atom_common_record_header + record_header; //record_type = ATOM_CONN_CAP_RECORD_TYPE + uint16_t connector_caps; //01b if internal display is checked; 10b if internal BL is checked; 0 of Not +}; + +struct atom_connector_speed_record { + struct atom_common_record_header + record_header; //record_type = ATOM_CONN_SPEED_UPTO + uint32_t connector_max_speed; // connector Max speed attribute, it sets 8100 in Mhz when DP connector @8.1Ghz. + uint16_t reserved; +}; + // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap enum atom_encoder_caps_def { @@ -885,6 +900,21 @@ struct atom_bracket_layout_record uint8_t reserved; struct atom_connector_layout_info conn_info[1]; }; +struct atom_bracket_layout_record_v2 { + struct atom_common_record_header + record_header; //record_type = ATOM_BRACKET_LAYOUT_RECORD_TYPE + uint8_t bracketlen; //Bracket Length in mm + uint8_t bracketwidth; //Bracket Width in mm + uint8_t conn_num; //Connector numbering + uint8_t mini_type; //Mini Type (0 = Normal; 1 = Mini) + uint8_t reserved1; + uint8_t reserved2; +}; + +enum atom_connector_layout_info_mini_type_def { + MINI_TYPE_NORMAL = 0, + MINI_TYPE_MINI = 1, +}; enum atom_display_device_tag_def{ ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display @@ -911,6 +941,19 @@ struct atom_display_object_path_v2 uint8_t reserved; }; +struct atom_display_object_path_v3 { + uint16_t display_objid; //Connector Object ID or Misc Object ID + uint16_t disp_recordoffset; + uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder + uint16_t reserved1; //only on USBC case, otherwise always = 0 + uint16_t reserved2; //reserved and always = 0 + uint16_t reserved3; //reserved and always = 0 + //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, + //a path appears first + uint16_t device_tag; + uint16_t reserved4; //reserved and always = 0 +}; + struct display_object_info_table_v1_4 { struct atom_common_table_header table_header; @@ -920,6 +963,15 @@ struct display_object_info_table_v1_4 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path }; +struct display_object_info_table_v1_5 { + struct atom_common_table_header table_header; + uint16_t supporteddevices; + uint8_t number_of_path; + uint8_t reserved; + // the real number of this included in the structure is calculated by using the + // (whole structure size - the header size- number_of_path)/size of atom_display_object_path + struct atom_display_object_path_v3 display_path[8]; +}; /* *************************************************************************** @@ -1080,17 +1132,73 @@ struct atom_dc_golden_table_v1 uint32_t reserved[23]; }; -enum dce_info_caps_def +enum dce_info_caps_def { + // only for VBIOS + DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED = 0x02, + // only for VBIOS + DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 = 0x04, + // only for VBIOS + DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING = 0x08, + // only for VBIOS + DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE = 0x20, + DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40, +}; + +struct atom_display_controller_info_v4_5 { - // only for VBIOS - DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02, - // only for VBIOS - DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04, - // only for VBIOS - DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08, - // only for VBIOS - DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE =0x20, - DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40, + struct atom_common_table_header table_header; + uint32_t display_caps; + uint32_t bootup_dispclk_10khz; + uint16_t dce_refclk_10khz; + uint16_t i2c_engine_refclk_10khz; + uint16_t dvi_ss_percentage; // in unit of 0.001% + uint16_t dvi_ss_rate_10hz; + uint16_t hdmi_ss_percentage; // in unit of 0.001% + uint16_t hdmi_ss_rate_10hz; + uint16_t dp_ss_percentage; // in unit of 0.001% + uint16_t dp_ss_rate_10hz; + uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode + uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode + uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode + uint8_t ss_reserved; + // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available + uint8_t dfp_hardcode_mode_num; + // DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available + uint8_t dfp_hardcode_refreshrate; + // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable + uint8_t vga_hardcode_mode_num; + // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable + uint8_t vga_hardcode_refreshrate; + uint16_t dpphy_refclk_10khz; + uint16_t hw_chip_id; + uint8_t dcnip_min_ver; + uint8_t dcnip_max_ver; + uint8_t max_disp_pipe_num; + uint8_t max_vbios_active_disp_pipe_num; + uint8_t max_ppll_num; + uint8_t max_disp_phy_num; + uint8_t max_aux_pairs; + uint8_t remotedisplayconfig; + uint32_t dispclk_pll_vco_freq; + uint32_t dp_ref_clk_freq; + // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us) + uint32_t max_mclk_chg_lat; + // Worst case memory self refresh exit time, units of 100ns of ns (0.1us) + uint32_t max_sr_exit_lat; + // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us) + uint32_t max_sr_enter_exit_lat; + uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx + uint16_t dc_golden_table_ver; + uint32_t aux_dphy_rx_control0_val; + uint32_t aux_dphy_tx_control_val; + uint32_t aux_dphy_rx_control1_val; + uint32_t dc_gpio_aux_ctrl_0_val; + uint32_t dc_gpio_aux_ctrl_1_val; + uint32_t dc_gpio_aux_ctrl_2_val; + uint32_t dc_gpio_aux_ctrl_3_val; + uint32_t dc_gpio_aux_ctrl_4_val; + uint32_t dc_gpio_aux_ctrl_5_val; + uint32_t reserved[26]; }; /* @@ -1806,6 +1914,63 @@ struct atom_smu_info_v3_3 { uint32_t reserved; }; +struct atom_smu_info_v3_5 +{ + struct atom_common_table_header table_header; + uint8_t smuip_min_ver; + uint8_t smuip_max_ver; + uint8_t waflclk_ss_mode; + uint8_t gpuclk_ss_mode; + uint16_t sclk_ss_percentage; + uint16_t sclk_ss_rate_10hz; + uint16_t gpuclk_ss_percentage; // in unit of 0.001% + uint16_t gpuclk_ss_rate_10hz; + uint32_t core_refclk_10khz; + uint32_t syspll0_1_vco_freq_10khz; + uint32_t syspll0_2_vco_freq_10khz; + uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid + uint8_t pcc_gpio_polarity; // GPIO polarity for CTF + uint16_t smugoldenoffset; + uint32_t syspll0_0_vco_freq_10khz; + uint32_t bootup_smnclk_10khz; + uint32_t bootup_socclk_10khz; + uint32_t bootup_mp0clk_10khz; + uint32_t bootup_mp1clk_10khz; + uint32_t bootup_lclk_10khz; + uint32_t bootup_dcefclk_10khz; + uint32_t ctf_threshold_override_value; + uint32_t syspll3_0_vco_freq_10khz; + uint32_t syspll3_1_vco_freq_10khz; + uint32_t bootup_fclk_10khz; + uint32_t bootup_waflclk_10khz; + uint32_t smu_info_caps; + uint16_t waflclk_ss_percentage; // in unit of 0.001% + uint16_t smuinitoffset; + uint32_t bootup_dprefclk_10khz; + uint32_t bootup_usbclk_10khz; + uint32_t smb_slave_address; + uint32_t cg_fdo_ctrl0_val; + uint32_t cg_fdo_ctrl1_val; + uint32_t cg_fdo_ctrl2_val; + uint32_t gdfll_as_wait_ctrl_val; + uint32_t gdfll_as_step_ctrl_val; + uint32_t bootup_dtbclk_10khz; + uint32_t fclk_syspll_refclk_10khz; + uint32_t smusvi_svc0_val; + uint32_t smusvi_svc1_val; + uint32_t smusvi_svd0_val; + uint32_t smusvi_svd1_val; + uint32_t smusvi_svt0_val; + uint32_t smusvi_svt1_val; + uint32_t cg_tach_ctrl_val; + uint32_t cg_pump_ctrl1_val; + uint32_t cg_pump_tach_ctrl_val; + uint32_t thm_ctf_delay_val; + uint32_t thm_thermal_int_ctrl_val; + uint32_t thm_tmon_config_val; + uint32_t reserved[16]; +}; + struct atom_smu_info_v3_6 { struct atom_common_table_header table_header; -- cgit v1.2.3 From 79b470e5ee83e979f8ff465efa8b7ced160bcae7 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Mon, 21 Feb 2022 15:49:20 -0500 Subject: drm/amd/display: Add DCN32/321 version identifiers Add DCN3.2 asic identifiers. Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 2 ++ drivers/gpu/drm/amd/display/include/dal_asic_id.h | 8 ++++++++ drivers/gpu/drm/amd/display/include/dal_types.h | 2 ++ 3 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index f5cb8932bd5c..7dbc9fb55459 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -100,6 +100,8 @@ enum dmub_asic { DMUB_ASIC_DCN31B, DMUB_ASIC_DCN315, DMUB_ASIC_DCN316, + DMUB_ASIC_DCN32, + DMUB_ASIC_DCN321, DMUB_ASIC_MAX, }; diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index 310f8779db67..11391eead954 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -247,6 +247,14 @@ enum { #define ASICREV_IS_GC_10_3_7(eChipRev) ((eChipRev >= GC_10_3_7_A0) && (eChipRev < GC_10_3_7_UNKNOWN)) +#define AMDGPU_FAMILY_GC_11_0_0 145 +#define GC_11_0_0_A0 0x1 +#define GC_11_0_2_A0 0x10 +#define GC_11_UNKNOWN 0xFF + +#define ASICREV_IS_GC_11_0_0(eChipRev) (eChipRev < GC_11_0_2_A0) +#define ASICREV_IS_GC_11_0_2(eChipRev) (eChipRev >= GC_11_0_2_A0 && eChipRev < GC_11_UNKNOWN) + /* * ASIC chip ID */ diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h index bf9085fc5105..775c640fc820 100644 --- a/drivers/gpu/drm/amd/display/include/dal_types.h +++ b/drivers/gpu/drm/amd/display/include/dal_types.h @@ -59,6 +59,8 @@ enum dce_version { DCN_VERSION_3_1, DCN_VERSION_3_15, DCN_VERSION_3_16, + DCN_VERSION_3_2, + DCN_VERSION_3_21, DCN_VERSION_MAX }; -- cgit v1.2.3 From 4f29f9cf092b2d331ba2081566be3272962b7f96 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Thu, 14 Apr 2022 15:19:16 -0400 Subject: drm/amd: add register headers for DCN32/321 Add register headers for DCN 3.2.0 and 3.2.1. Signed-off-by: Aurabindo Pillai Signed-off-by: Alex Deucher --- .../amd/include/asic_reg/dcn/dcn_3_2_0_offset.h | 14675 ++ .../amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h | 222890 ++++++++++++++++++ .../amd/include/asic_reg/dcn/dcn_3_2_1_offset.h | 14559 ++ .../amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h | 56578 +++++ 4 files changed, 308702 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h new file mode 100644 index 000000000000..6f84ea5c006f --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h @@ -0,0 +1,14675 @@ +/* + * Copyright (C) 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _dcn_3_2_0_OFFSET_HEADER +#define _dcn_3_2_0_OFFSET_HEADER + + + +// addressBlock: dcn_dc_dccg_dccg_dfs_dispdec +// base address: 0x0 +#define regDENTIST_DISPCLK_CNTL 0x0064 +#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1 + + +// addressBlock: dcn_dc_dccg_dccg_dispdec +// base address: 0x0 +#define regPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 +#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 +#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 +#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 +#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regDP_DTO_DBUF_EN 0x0044 +#define regDP_DTO_DBUF_EN_BASE_IDX 1 +#define regDSCCLK3_DTO_PARAM 0x0045 +#define regDSCCLK3_DTO_PARAM_BASE_IDX 1 +#define regDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 +#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL4 0x0049 +#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX 1 +#define regDPSTREAMCLK_CNTL 0x004a +#define regDPSTREAMCLK_CNTL_BASE_IDX 1 +#define regREFCLK_CGTT_BLK_CTRL_REG 0x004b +#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c +#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regDCCG_GLOBAL_FGCG_REP_CNTL 0x0050 +#define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX 1 +#define regDCCG_DS_DTO_INCR 0x0053 +#define regDCCG_DS_DTO_INCR_BASE_IDX 1 +#define regDCCG_DS_DTO_MODULO 0x0054 +#define regDCCG_DS_DTO_MODULO_BASE_IDX 1 +#define regDCCG_DS_CNTL 0x0055 +#define regDCCG_DS_CNTL_BASE_IDX 1 +#define regDCCG_DS_HW_CAL_INTERVAL 0x0056 +#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 +#define regDPREFCLK_CNTL 0x0058 +#define regDPREFCLK_CNTL_BASE_IDX 1 +#define regDCE_VERSION 0x005e +#define regDCE_VERSION_BASE_IDX 1 +#define regDCCG_GTC_CNTL 0x0060 +#define regDCCG_GTC_CNTL_BASE_IDX 1 +#define regDCCG_GTC_DTO_INCR 0x0061 +#define regDCCG_GTC_DTO_INCR_BASE_IDX 1 +#define regDCCG_GTC_DTO_MODULO 0x0062 +#define regDCCG_GTC_DTO_MODULO_BASE_IDX 1 +#define regDCCG_GTC_CURRENT 0x0063 +#define regDCCG_GTC_CURRENT_BASE_IDX 1 +#define regSYMCLK32_SE_CNTL 0x0065 +#define regSYMCLK32_SE_CNTL_BASE_IDX 1 +#define regSYMCLK32_LE_CNTL 0x0066 +#define regSYMCLK32_LE_CNTL_BASE_IDX 1 +#define regDTBCLK_P_CNTL 0x0068 +#define regDTBCLK_P_CNTL_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL5 0x0069 +#define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX 1 +#define regDSCCLK0_DTO_PARAM 0x006c +#define regDSCCLK0_DTO_PARAM_BASE_IDX 1 +#define regDSCCLK1_DTO_PARAM 0x006d +#define regDSCCLK1_DTO_PARAM_BASE_IDX 1 +#define regDSCCLK2_DTO_PARAM 0x006e +#define regDSCCLK2_DTO_PARAM_BASE_IDX 1 +#define regOTG_PIXEL_RATE_DIV 0x006f +#define regOTG_PIXEL_RATE_DIV_BASE_IDX 1 +#define regMILLISECOND_TIME_BASE_DIV 0x0070 +#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 +#define regDISPCLK_FREQ_CHANGE_CNTL 0x0071 +#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 +#define regDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 +#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL 0x0074 +#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 +#define regDISPCLK_CGTT_BLK_CTRL_REG 0x0075 +#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regSOCCLK_CGTT_BLK_CTRL_REG 0x0076 +#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDCCG_CAC_STATUS 0x0077 +#define regDCCG_CAC_STATUS_BASE_IDX 1 +#define regMICROSECOND_TIME_BASE_DIV 0x007b +#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL2 0x007c +#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 +#define regSYMCLK_CGTT_BLK_CTRL_REG 0x007d +#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDCCG_DISP_CNTL_REG 0x007f +#define regDCCG_DISP_CNTL_REG_BASE_IDX 1 +#define regOTG0_PIXEL_RATE_CNTL 0x0080 +#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO0_PHASE 0x0081 +#define regDP_DTO0_PHASE_BASE_IDX 1 +#define regDP_DTO0_MODULO 0x0082 +#define regDP_DTO0_MODULO_BASE_IDX 1 +#define regOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 +#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regOTG1_PIXEL_RATE_CNTL 0x0084 +#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO1_PHASE 0x0085 +#define regDP_DTO1_PHASE_BASE_IDX 1 +#define regDP_DTO1_MODULO 0x0086 +#define regDP_DTO1_MODULO_BASE_IDX 1 +#define regOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 +#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regOTG2_PIXEL_RATE_CNTL 0x0088 +#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO2_PHASE 0x0089 +#define regDP_DTO2_PHASE_BASE_IDX 1 +#define regDP_DTO2_MODULO 0x008a +#define regDP_DTO2_MODULO_BASE_IDX 1 +#define regOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b +#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regOTG3_PIXEL_RATE_CNTL 0x008c +#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO3_PHASE 0x008d +#define regDP_DTO3_PHASE_BASE_IDX 1 +#define regDP_DTO3_MODULO 0x008e +#define regDP_DTO3_MODULO_BASE_IDX 1 +#define regOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f +#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDPPCLK_CGTT_BLK_CTRL_REG 0x0098 +#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDPPCLK0_DTO_PARAM 0x0099 +#define regDPPCLK0_DTO_PARAM_BASE_IDX 1 +#define regDPPCLK1_DTO_PARAM 0x009a +#define regDPPCLK1_DTO_PARAM_BASE_IDX 1 +#define regDPPCLK2_DTO_PARAM 0x009b +#define regDPPCLK2_DTO_PARAM_BASE_IDX 1 +#define regDPPCLK3_DTO_PARAM 0x009c +#define regDPPCLK3_DTO_PARAM_BASE_IDX 1 +#define regDCCG_CAC_STATUS2 0x009f +#define regDCCG_CAC_STATUS2_BASE_IDX 1 +#define regSYMCLKA_CLOCK_ENABLE 0x00a0 +#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKB_CLOCK_ENABLE 0x00a1 +#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKC_CLOCK_ENABLE 0x00a2 +#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKD_CLOCK_ENABLE 0x00a3 +#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKE_CLOCK_ENABLE 0x00a4 +#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 +#define regDCCG_SOFT_RESET 0x00a6 +#define regDCCG_SOFT_RESET_BASE_IDX 1 +#define regDSCCLK_DTO_CTRL 0x00a7 +#define regDSCCLK_DTO_CTRL_BASE_IDX 1 +#define regDCCG_AUDIO_DTO_SOURCE 0x00ab +#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO0_PHASE 0x00ac +#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO0_MODULE 0x00ad +#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO1_PHASE 0x00ae +#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO1_MODULE 0x00af +#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 +#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 +#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 +#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 +#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 +#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 +#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 +#define regDPPCLK_DTO_CTRL 0x00b6 +#define regDPPCLK_DTO_CTRL_BASE_IDX 1 +#define regDCCG_VSYNC_CNT_CTRL 0x00b8 +#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 +#define regDCCG_VSYNC_CNT_INT_CTRL 0x00b9 +#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 +#define regFORCE_SYMCLK_DISABLE 0x00ba +#define regFORCE_SYMCLK_DISABLE_BASE_IDX 1 +#define regDCCG_TEST_CLK_SEL 0x00be +#define regDCCG_TEST_CLK_SEL_BASE_IDX 1 +#define regDTBCLK_DTO0_PHASE 0x0018 +#define regDTBCLK_DTO0_PHASE_BASE_IDX 2 +#define regDTBCLK_DTO1_PHASE 0x0019 +#define regDTBCLK_DTO1_PHASE_BASE_IDX 2 +#define regDTBCLK_DTO2_PHASE 0x001a +#define regDTBCLK_DTO2_PHASE_BASE_IDX 2 +#define regDTBCLK_DTO3_PHASE 0x001b +#define regDTBCLK_DTO3_PHASE_BASE_IDX 2 +#define regDTBCLK_DTO0_MODULO 0x001f +#define regDTBCLK_DTO0_MODULO_BASE_IDX 2 +#define regDTBCLK_DTO1_MODULO 0x0020 +#define regDTBCLK_DTO1_MODULO_BASE_IDX 2 +#define regDTBCLK_DTO2_MODULO 0x0021 +#define regDTBCLK_DTO2_MODULO_BASE_IDX 2 +#define regDTBCLK_DTO3_MODULO 0x0022 +#define regDTBCLK_DTO3_MODULO_BASE_IDX 2 +#define regHDMICHARCLK0_CLOCK_CNTL 0x004a +#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX 2 +#define regPHYASYMCLK_CLOCK_CNTL 0x0052 +#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYBSYMCLK_CLOCK_CNTL 0x0053 +#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYCSYMCLK_CLOCK_CNTL 0x0054 +#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYDSYMCLK_CLOCK_CNTL 0x0055 +#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYESYMCLK_CLOCK_CNTL 0x0056 +#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regHDMISTREAMCLK_CNTL 0x0059 +#define regHDMISTREAMCLK_CNTL_BASE_IDX 2 +#define regDCCG_GATE_DISABLE_CNTL3 0x005a +#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2 +#define regHDMISTREAMCLK0_DTO_PARAM 0x005b +#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX 2 +#define regDCCG_AUDIO_DTBCLK_DTO_PHASE 0x0061 +#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX 2 +#define regDCCG_AUDIO_DTBCLK_DTO_MODULO 0x0062 +#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX 2 +#define regDTBCLK_DTO_DBUF_EN 0x0063 +#define regDTBCLK_DTO_DBUF_EN_BASE_IDX 2 +#define regDMCUBCLK_CNTL 0x0067 +#define regDMCUBCLK_CNTL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dmu_rbbmif_dispdec +// base address: 0x0 +#define regRBBMIF_TIMEOUT 0x017f +#define regRBBMIF_TIMEOUT_BASE_IDX 2 +#define regRBBMIF_STATUS 0x0180 +#define regRBBMIF_STATUS_BASE_IDX 2 +#define regRBBMIF_STATUS_2 0x0181 +#define regRBBMIF_STATUS_2_BASE_IDX 2 +#define regRBBMIF_INT_STATUS 0x0182 +#define regRBBMIF_INT_STATUS_BASE_IDX 2 +#define regRBBMIF_TIMEOUT_DIS 0x0183 +#define regRBBMIF_TIMEOUT_DIS_BASE_IDX 2 +#define regRBBMIF_TIMEOUT_DIS_2 0x0184 +#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 +#define regRBBMIF_STATUS_FLAG 0x0185 +#define regRBBMIF_STATUS_FLAG_BASE_IDX 2 + + +// addressBlock: dcn_dc_dmu_ihc_dispdec +// base address: 0x0 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 +#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 +#define regDC_GPU_TIMER_READ 0x0128 +#define regDC_GPU_TIMER_READ_BASE_IDX 2 +#define regDC_GPU_TIMER_READ_CNTL 0x0129 +#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS 0x012a +#define regDISP_INTERRUPT_STATUS_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE 0x012b +#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE2 0x012c +#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE3 0x012d +#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE4 0x012e +#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE5 0x012f +#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 +#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 +#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 +#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 +#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 +#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 +#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 +#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 +#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 +#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 +#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE16 0x013a +#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE17 0x013b +#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE18 0x013c +#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE19 0x013d +#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE20 0x013e +#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE21 0x013f +#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 +#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_VREADY 0x0141 +#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_FLIP 0x0142 +#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 +#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 +#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 +#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 +#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 +#define regDCCG_INTERRUPT_DEST 0x0148 +#define regDCCG_INTERRUPT_DEST_BASE_IDX 2 +#define regDMU_INTERRUPT_DEST 0x0149 +#define regDMU_INTERRUPT_DEST_BASE_IDX 2 +#define regDMU_INTERRUPT_DEST2 0x014a +#define regDMU_INTERRUPT_DEST2_BASE_IDX 2 +#define regDCPG_INTERRUPT_DEST 0x014b +#define regDCPG_INTERRUPT_DEST_BASE_IDX 2 +#define regDCPG_INTERRUPT_DEST2 0x014c +#define regDCPG_INTERRUPT_DEST2_BASE_IDX 2 +#define regMMHUBBUB_INTERRUPT_DEST 0x014d +#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 +#define regWB_INTERRUPT_DEST 0x014e +#define regWB_INTERRUPT_DEST_BASE_IDX 2 +#define regDCHUB_INTERRUPT_DEST 0x014f +#define regDCHUB_INTERRUPT_DEST_BASE_IDX 2 +#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 +#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 +#define regDCHUB_INTERRUPT_DEST2 0x0151 +#define regDCHUB_INTERRUPT_DEST2_BASE_IDX 2 +#define regDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 +#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 +#define regMPC_INTERRUPT_DEST 0x0153 +#define regMPC_INTERRUPT_DEST_BASE_IDX 2 +#define regOPP_INTERRUPT_DEST 0x0154 +#define regOPP_INTERRUPT_DEST_BASE_IDX 2 +#define regOPTC_INTERRUPT_DEST 0x0155 +#define regOPTC_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG0_INTERRUPT_DEST 0x0156 +#define regOTG0_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG1_INTERRUPT_DEST 0x0157 +#define regOTG1_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG2_INTERRUPT_DEST 0x0158 +#define regOTG2_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG3_INTERRUPT_DEST 0x0159 +#define regOTG3_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG4_INTERRUPT_DEST 0x015a +#define regOTG4_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG5_INTERRUPT_DEST 0x015b +#define regOTG5_INTERRUPT_DEST_BASE_IDX 2 +#define regDIG_INTERRUPT_DEST 0x015c +#define regDIG_INTERRUPT_DEST_BASE_IDX 2 +#define regI2C_DDC_HPD_INTERRUPT_DEST 0x015d +#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 +#define regDIO_INTERRUPT_DEST 0x015f +#define regDIO_INTERRUPT_DEST_BASE_IDX 2 +#define regDCIO_INTERRUPT_DEST 0x0160 +#define regDCIO_INTERRUPT_DEST_BASE_IDX 2 +#define regHPD_INTERRUPT_DEST 0x0161 +#define regHPD_INTERRUPT_DEST_BASE_IDX 2 +#define regAZ_INTERRUPT_DEST 0x0162 +#define regAZ_INTERRUPT_DEST_BASE_IDX 2 +#define regAUX_INTERRUPT_DEST 0x0163 +#define regAUX_INTERRUPT_DEST_BASE_IDX 2 +#define regDSC_INTERRUPT_DEST 0x0164 +#define regDSC_INTERRUPT_DEST_BASE_IDX 2 +#define regHPO_INTERRUPT_DEST 0x0165 +#define regHPO_INTERRUPT_DEST_BASE_IDX 2 + + +// addressBlock: dcn_dc_dmu_dmu_misc_dispdec +// base address: 0x0 +#define regCC_DC_PIPE_DIS 0x00ca +#define regCC_DC_PIPE_DIS_BASE_IDX 2 +#define regDMU_CLK_CNTL 0x00cb +#define regDMU_CLK_CNTL_BASE_IDX 2 +#define regDMCUB_SMU_INTERRUPT_CNTL 0x00cd +#define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX 2 +#define regSMU_INTERRUPT_CONTROL 0x00ce +#define regSMU_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDMU_MISC_ALLOW_DS_FORCE 0x00d6 +#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 + + +// addressBlock: dcn_dc_dmu_dc_pg_dispdec +// base address: 0x0 +#define regDOMAIN0_PG_CONFIG 0x0080 +#define regDOMAIN0_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN0_PG_STATUS 0x0081 +#define regDOMAIN0_PG_STATUS_BASE_IDX 2 +#define regDOMAIN1_PG_CONFIG 0x0082 +#define regDOMAIN1_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN1_PG_STATUS 0x0083 +#define regDOMAIN1_PG_STATUS_BASE_IDX 2 +#define regDOMAIN2_PG_CONFIG 0x0084 +#define regDOMAIN2_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN2_PG_STATUS 0x0085 +#define regDOMAIN2_PG_STATUS_BASE_IDX 2 +#define regDOMAIN3_PG_CONFIG 0x0086 +#define regDOMAIN3_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN3_PG_STATUS 0x0087 +#define regDOMAIN3_PG_STATUS_BASE_IDX 2 +#define regDOMAIN16_PG_CONFIG 0x0089 +#define regDOMAIN16_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN16_PG_STATUS 0x008a +#define regDOMAIN16_PG_STATUS_BASE_IDX 2 +#define regDOMAIN17_PG_CONFIG 0x008b +#define regDOMAIN17_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN17_PG_STATUS 0x008c +#define regDOMAIN17_PG_STATUS_BASE_IDX 2 +#define regDOMAIN18_PG_CONFIG 0x008d +#define regDOMAIN18_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN18_PG_STATUS 0x008e +#define regDOMAIN18_PG_STATUS_BASE_IDX 2 +#define regDOMAIN19_PG_CONFIG 0x008f +#define regDOMAIN19_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN19_PG_STATUS 0x0090 +#define regDOMAIN19_PG_STATUS_BASE_IDX 2 +#define regDCPG_INTERRUPT_STATUS 0x0091 +#define regDCPG_INTERRUPT_STATUS_BASE_IDX 2 +#define regDCPG_INTERRUPT_STATUS_2 0x0092 +#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 +#define regDCPG_INTERRUPT_CONTROL_1 0x0093 +#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 +#define regDCPG_INTERRUPT_CONTROL_3 0x0094 +#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 +#define regDC_IP_REQUEST_CNTL 0x0095 +#define regDC_IP_REQUEST_CNTL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dmu_dmcub_dispdec +// base address: 0x0 +#define regDMCUB_REGION0_OFFSET 0x018e +#define regDMCUB_REGION0_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION0_OFFSET_HIGH 0x018f +#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION1_OFFSET 0x0190 +#define regDMCUB_REGION1_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION1_OFFSET_HIGH 0x0191 +#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION2_OFFSET 0x0192 +#define regDMCUB_REGION2_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION2_OFFSET_HIGH 0x0193 +#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION4_OFFSET 0x0196 +#define regDMCUB_REGION4_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION4_OFFSET_HIGH 0x0197 +#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION5_OFFSET 0x0198 +#define regDMCUB_REGION5_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION5_OFFSET_HIGH 0x0199 +#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION6_OFFSET 0x019a +#define regDMCUB_REGION6_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION6_OFFSET_HIGH 0x019b +#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION7_OFFSET 0x019c +#define regDMCUB_REGION7_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION7_OFFSET_HIGH 0x019d +#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION0_TOP_ADDRESS 0x019e +#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION1_TOP_ADDRESS 0x019f +#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION2_TOP_ADDRESS 0x01a0 +#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION4_TOP_ADDRESS 0x01a1 +#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION5_TOP_ADDRESS 0x01a2 +#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION6_TOP_ADDRESS 0x01a3 +#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION7_TOP_ADDRESS 0x01a4 +#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 +#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 +#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 +#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 +#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 +#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa +#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab +#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac +#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad +#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae +#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af +#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 +#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 +#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 +#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 +#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 +#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_OFFSET 0x01b5 +#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 +#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_OFFSET 0x01b7 +#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 +#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_OFFSET 0x01b9 +#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba +#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_OFFSET 0x01bb +#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc +#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_OFFSET 0x01bd +#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be +#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_OFFSET 0x01bf +#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 +#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_OFFSET 0x01c1 +#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 +#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_OFFSET 0x01c3 +#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 +#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_INTERRUPT_ENABLE 0x01c5 +#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 +#define regDMCUB_INTERRUPT_ACK 0x01c6 +#define regDMCUB_INTERRUPT_ACK_BASE_IDX 2 +#define regDMCUB_INTERRUPT_STATUS 0x01c7 +#define regDMCUB_INTERRUPT_STATUS_BASE_IDX 2 +#define regDMCUB_INTERRUPT_TYPE 0x01c8 +#define regDMCUB_INTERRUPT_TYPE_BASE_IDX 2 +#define regDMCUB_EXT_INTERRUPT_STATUS 0x01c9 +#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 +#define regDMCUB_EXT_INTERRUPT_CTXID 0x01ca +#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 +#define regDMCUB_EXT_INTERRUPT_ACK 0x01cb +#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 +#define regDMCUB_INST_FETCH_FAULT_ADDR 0x01cc +#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 +#define regDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd +#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 +#define regDMCUB_SEC_CNTL 0x01ce +#define regDMCUB_SEC_CNTL_BASE_IDX 2 +#define regDMCUB_MEM_CNTL 0x01cf +#define regDMCUB_MEM_CNTL_BASE_IDX 2 +#define regDMCUB_INBOX0_BASE_ADDRESS 0x01d0 +#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_INBOX0_SIZE 0x01d1 +#define regDMCUB_INBOX0_SIZE_BASE_IDX 2 +#define regDMCUB_INBOX0_WPTR 0x01d2 +#define regDMCUB_INBOX0_WPTR_BASE_IDX 2 +#define regDMCUB_INBOX0_RPTR 0x01d3 +#define regDMCUB_INBOX0_RPTR_BASE_IDX 2 +#define regDMCUB_INBOX1_BASE_ADDRESS 0x01d4 +#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_INBOX1_SIZE 0x01d5 +#define regDMCUB_INBOX1_SIZE_BASE_IDX 2 +#define regDMCUB_INBOX1_WPTR 0x01d6 +#define regDMCUB_INBOX1_WPTR_BASE_IDX 2 +#define regDMCUB_INBOX1_RPTR 0x01d7 +#define regDMCUB_INBOX1_RPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 +#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_OUTBOX0_SIZE 0x01d9 +#define regDMCUB_OUTBOX0_SIZE_BASE_IDX 2 +#define regDMCUB_OUTBOX0_WPTR 0x01da +#define regDMCUB_OUTBOX0_WPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX0_RPTR 0x01db +#define regDMCUB_OUTBOX0_RPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc +#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_OUTBOX1_SIZE 0x01dd +#define regDMCUB_OUTBOX1_SIZE_BASE_IDX 2 +#define regDMCUB_OUTBOX1_WPTR 0x01de +#define regDMCUB_OUTBOX1_WPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX1_RPTR 0x01df +#define regDMCUB_OUTBOX1_RPTR_BASE_IDX 2 +#define regDMCUB_TIMER_TRIGGER0 0x01e0 +#define regDMCUB_TIMER_TRIGGER0_BASE_IDX 2 +#define regDMCUB_TIMER_TRIGGER1 0x01e1 +#define regDMCUB_TIMER_TRIGGER1_BASE_IDX 2 +#define regDMCUB_TIMER_WINDOW 0x01e2 +#define regDMCUB_TIMER_WINDOW_BASE_IDX 2 +#define regDMCUB_SCRATCH0 0x01e3 +#define regDMCUB_SCRATCH0_BASE_IDX 2 +#define regDMCUB_SCRATCH1 0x01e4 +#define regDMCUB_SCRATCH1_BASE_IDX 2 +#define regDMCUB_SCRATCH2 0x01e5 +#define regDMCUB_SCRATCH2_BASE_IDX 2 +#define regDMCUB_SCRATCH3 0x01e6 +#define regDMCUB_SCRATCH3_BASE_IDX 2 +#define regDMCUB_SCRATCH4 0x01e7 +#define regDMCUB_SCRATCH4_BASE_IDX 2 +#define regDMCUB_SCRATCH5 0x01e8 +#define regDMCUB_SCRATCH5_BASE_IDX 2 +#define regDMCUB_SCRATCH6 0x01e9 +#define regDMCUB_SCRATCH6_BASE_IDX 2 +#define regDMCUB_SCRATCH7 0x01ea +#define regDMCUB_SCRATCH7_BASE_IDX 2 +#define regDMCUB_SCRATCH8 0x01eb +#define regDMCUB_SCRATCH8_BASE_IDX 2 +#define regDMCUB_SCRATCH9 0x01ec +#define regDMCUB_SCRATCH9_BASE_IDX 2 +#define regDMCUB_SCRATCH10 0x01ed +#define regDMCUB_SCRATCH10_BASE_IDX 2 +#define regDMCUB_SCRATCH11 0x01ee +#define regDMCUB_SCRATCH11_BASE_IDX 2 +#define regDMCUB_SCRATCH12 0x01ef +#define regDMCUB_SCRATCH12_BASE_IDX 2 +#define regDMCUB_SCRATCH13 0x01f0 +#define regDMCUB_SCRATCH13_BASE_IDX 2 +#define regDMCUB_SCRATCH14 0x01f1 +#define regDMCUB_SCRATCH14_BASE_IDX 2 +#define regDMCUB_SCRATCH15 0x01f2 +#define regDMCUB_SCRATCH15_BASE_IDX 2 +#define regDMCUB_SCRATCH16 0x01f3 +#define regDMCUB_SCRATCH16_BASE_IDX 2 +#define regDMCUB_SCRATCH17 0x01f4 +#define regDMCUB_SCRATCH17_BASE_IDX 2 +#define regDMCUB_SCRATCH18 0x01f5 +#define regDMCUB_SCRATCH18_BASE_IDX 2 +#define regDMCUB_CNTL 0x01f6 +#define regDMCUB_CNTL_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN0 0x01f7 +#define regDMCUB_GPINT_DATAIN0_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN1 0x01f8 +#define regDMCUB_GPINT_DATAIN1_BASE_IDX 2 +#define regDMCUB_GPINT_DATAOUT 0x01f9 +#define regDMCUB_GPINT_DATAOUT_BASE_IDX 2 +#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa +#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 +#define regDMCUB_LS_WAKE_INT_ENABLE 0x01fb +#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 +#define regDMCUB_MEM_PWR_CNTL 0x01fc +#define regDMCUB_MEM_PWR_CNTL_BASE_IDX 2 +#define regDMCUB_TIMER_CURRENT 0x01fd +#define regDMCUB_TIMER_CURRENT_BASE_IDX 2 +#define regDMCUB_PROC_ID 0x01ff +#define regDMCUB_PROC_ID_BASE_IDX 2 +#define regDMCUB_CNTL2 0x0200 +#define regDMCUB_CNTL2_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN2 0x0215 +#define regDMCUB_GPINT_DATAIN2_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN3 0x0216 +#define regDMCUB_GPINT_DATAIN3_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN4 0x0217 +#define regDMCUB_GPINT_DATAIN4_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN5 0x0218 +#define regDMCUB_GPINT_DATAIN5_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN6 0x0219 +#define regDMCUB_GPINT_DATAIN6_BASE_IDX 2 +#define regDMCUB_REGION3_TMR_AXI_SPACE 0x021a +#define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX 2 +#define regDMCUB_SCRATCH19 0x022e +#define regDMCUB_SCRATCH19_BASE_IDX 2 +#define regDMCUB_SCRATCH20 0x022f +#define regDMCUB_SCRATCH20_BASE_IDX 2 +#define regDMCUB_SCRATCH21 0x0230 +#define regDMCUB_SCRATCH21_BASE_IDX 2 +#define regDMCUB_SCRATCH22 0x0231 +#define regDMCUB_SCRATCH22_BASE_IDX 2 +#define regDMCUB_SCRATCH23 0x0232 +#define regDMCUB_SCRATCH23_BASE_IDX 2 + + +// addressBlock: dcn_dc_wb0_dispdec_dwb_top_dispdec +// base address: 0x0 +#define regDWB_ENABLE_CLK_CTRL 0x3228 +#define regDWB_ENABLE_CLK_CTRL_BASE_IDX 2 +#define regDWB_MEM_PWR_CTRL 0x3229 +#define regDWB_MEM_PWR_CTRL_BASE_IDX 2 +#define regFC_MODE_CTRL 0x322a +#define regFC_MODE_CTRL_BASE_IDX 2 +#define regFC_FLOW_CTRL 0x322b +#define regFC_FLOW_CTRL_BASE_IDX 2 +#define regFC_WINDOW_START 0x322c +#define regFC_WINDOW_START_BASE_IDX 2 +#define regFC_WINDOW_SIZE 0x322d +#define regFC_WINDOW_SIZE_BASE_IDX 2 +#define regFC_SOURCE_SIZE 0x322e +#define regFC_SOURCE_SIZE_BASE_IDX 2 +#define regDWB_UPDATE_CTRL 0x322f +#define regDWB_UPDATE_CTRL_BASE_IDX 2 +#define regDWB_CRC_CTRL 0x3230 +#define regDWB_CRC_CTRL_BASE_IDX 2 +#define regDWB_CRC_MASK_R_G 0x3231 +#define regDWB_CRC_MASK_R_G_BASE_IDX 2 +#define regDWB_CRC_MASK_B_A 0x3232 +#define regDWB_CRC_MASK_B_A_BASE_IDX 2 +#define regDWB_CRC_VAL_R_G 0x3233 +#define regDWB_CRC_VAL_R_G_BASE_IDX 2 +#define regDWB_CRC_VAL_B_A 0x3234 +#define regDWB_CRC_VAL_B_A_BASE_IDX 2 +#define regDWB_OUT_CTRL 0x3235 +#define regDWB_OUT_CTRL_BASE_IDX 2 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 +#define regDWB_HOST_READ_CONTROL 0x3238 +#define regDWB_HOST_READ_CONTROL_BASE_IDX 2 +#define regDWB_OVERFLOW_STATUS 0x3239 +#define regDWB_OVERFLOW_STATUS_BASE_IDX 2 +#define regDWB_OVERFLOW_COUNTER 0x323a +#define regDWB_OVERFLOW_COUNTER_BASE_IDX 2 +#define regDWB_SOFT_RESET 0x323b +#define regDWB_SOFT_RESET_BASE_IDX 2 + + +// addressBlock: dcn_dc_wb0_dispdec_dwbcp_dispdec +// base address: 0x0 +#define regDWB_HDR_MULT_COEF 0x3294 +#define regDWB_HDR_MULT_COEF_BASE_IDX 2 +#define regDWB_GAMUT_REMAP_MODE 0x3295 +#define regDWB_GAMUT_REMAP_MODE_BASE_IDX 2 +#define regDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 +#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C11_C12 0x3297 +#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C13_C14 0x3298 +#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C21_C22 0x3299 +#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C23_C24 0x329a +#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C31_C32 0x329b +#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C33_C34 0x329c +#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C11_C12 0x329d +#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C13_C14 0x329e +#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C21_C22 0x329f +#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C23_C24 0x32a0 +#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C31_C32 0x32a1 +#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C33_C34 0x32a2 +#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 +#define regDWB_OGAM_CONTROL 0x32a3 +#define regDWB_OGAM_CONTROL_BASE_IDX 2 +#define regDWB_OGAM_LUT_INDEX 0x32a4 +#define regDWB_OGAM_LUT_INDEX_BASE_IDX 2 +#define regDWB_OGAM_LUT_DATA 0x32a5 +#define regDWB_OGAM_LUT_DATA_BASE_IDX 2 +#define regDWB_OGAM_LUT_CONTROL 0x32a6 +#define regDWB_OGAM_LUT_CONTROL_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_CNTL_B 0x32a7 +#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_CNTL_G 0x32a8 +#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_CNTL_R 0x32a9 +#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa +#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac +#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae +#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 +#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 +#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 +#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 +#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 +#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 +#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_OFFSET_B 0x32b6 +#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_OFFSET_G 0x32b7 +#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_OFFSET_R 0x32b8 +#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_0_1 0x32b9 +#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_2_3 0x32ba +#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_4_5 0x32bb +#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_6_7 0x32bc +#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_8_9 0x32bd +#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_10_11 0x32be +#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_12_13 0x32bf +#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_14_15 0x32c0 +#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_16_17 0x32c1 +#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_18_19 0x32c2 +#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_20_21 0x32c3 +#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_22_23 0x32c4 +#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_24_25 0x32c5 +#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_26_27 0x32c6 +#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_28_29 0x32c7 +#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_30_31 0x32c8 +#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_32_33 0x32c9 +#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_CNTL_B 0x32ca +#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_CNTL_G 0x32cb +#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_CNTL_R 0x32cc +#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd +#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf +#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 +#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 +#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 +#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 +#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 +#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 +#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_OFFSET_B 0x32d9 +#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_OFFSET_G 0x32da +#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_OFFSET_R 0x32db +#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_0_1 0x32dc +#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_2_3 0x32dd +#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_4_5 0x32de +#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_6_7 0x32df +#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_8_9 0x32e0 +#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_10_11 0x32e1 +#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_12_13 0x32e2 +#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_14_15 0x32e3 +#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_16_17 0x32e4 +#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_18_19 0x32e5 +#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_20_21 0x32e6 +#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_22_23 0x32e7 +#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_24_25 0x32e8 +#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_26_27 0x32e9 +#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_28_29 0x32ea +#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_30_31 0x32eb +#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_32_33 0x32ec +#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 + + +// addressBlock: dcn_dc_mmhubbub_vga_dispdec +// base address: 0x0 +#define regVGA_MEM_WRITE_PAGE_ADDR 0x0000 +#define regVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 +#define regVGA_MEM_READ_PAGE_ADDR 0x0001 +#define regVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 +#define regVGA_RENDER_CONTROL 0x0000 +#define regVGA_RENDER_CONTROL_BASE_IDX 1 +#define regVGA_SEQUENCER_RESET_CONTROL 0x0001 +#define regVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 +#define regVGA_MODE_CONTROL 0x0002 +#define regVGA_MODE_CONTROL_BASE_IDX 1 +#define regVGA_SURFACE_PITCH_SELECT 0x0003 +#define regVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 +#define regVGA_MEMORY_BASE_ADDRESS 0x0004 +#define regVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 +#define regVGA_DISPBUF1_SURFACE_ADDR 0x0006 +#define regVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 +#define regVGA_DISPBUF2_SURFACE_ADDR 0x0008 +#define regVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 +#define regVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 +#define regVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 +#define regVGA_HDP_CONTROL 0x000a +#define regVGA_HDP_CONTROL_BASE_IDX 1 +#define regVGA_CACHE_CONTROL 0x000b +#define regVGA_CACHE_CONTROL_BASE_IDX 1 +#define regD1VGA_CONTROL 0x000c +#define regD1VGA_CONTROL_BASE_IDX 1 +#define regD2VGA_CONTROL 0x000e +#define regD2VGA_CONTROL_BASE_IDX 1 +#define regVGA_STATUS 0x0010 +#define regVGA_STATUS_BASE_IDX 1 +#define regVGA_INTERRUPT_CONTROL 0x0011 +#define regVGA_INTERRUPT_CONTROL_BASE_IDX 1 +#define regVGA_STATUS_CLEAR 0x0012 +#define regVGA_STATUS_CLEAR_BASE_IDX 1 +#define regVGA_INTERRUPT_STATUS 0x0013 +#define regVGA_INTERRUPT_STATUS_BASE_IDX 1 +#define regVGA_MAIN_CONTROL 0x0014 +#define regVGA_MAIN_CONTROL_BASE_IDX 1 +#define regVGA_TEST_CONTROL 0x0015 +#define regVGA_TEST_CONTROL_BASE_IDX 1 +#define regVGA_QOS_CTRL 0x0018 +#define regVGA_QOS_CTRL_BASE_IDX 1 +#define regCRTC8_IDX 0x002d +#define regCRTC8_IDX_BASE_IDX 1 +#define regCRTC8_DATA 0x002d +#define regCRTC8_DATA_BASE_IDX 1 +#define regGENFC_WT 0x002e +#define regGENFC_WT_BASE_IDX 1 +#define regGENS1 0x002e +#define regGENS1_BASE_IDX 1 +#define regATTRDW 0x0030 +#define regATTRDW_BASE_IDX 1 +#define regATTRX 0x0030 +#define regATTRX_BASE_IDX 1 +#define regATTRDR 0x0030 +#define regATTRDR_BASE_IDX 1 +#define regGENMO_WT 0x0030 +#define regGENMO_WT_BASE_IDX 1 +#define regGENS0 0x0030 +#define regGENS0_BASE_IDX 1 +#define regGENENB 0x0030 +#define regGENENB_BASE_IDX 1 +#define regSEQ8_IDX 0x0031 +#define regSEQ8_IDX_BASE_IDX 1 +#define regSEQ8_DATA 0x0031 +#define regSEQ8_DATA_BASE_IDX 1 +#define regDAC_MASK 0x0031 +#define regDAC_MASK_BASE_IDX 1 +#define regDAC_R_INDEX 0x0031 +#define regDAC_R_INDEX_BASE_IDX 1 +#define regDAC_W_INDEX 0x0032 +#define regDAC_W_INDEX_BASE_IDX 1 +#define regDAC_DATA 0x0032 +#define regDAC_DATA_BASE_IDX 1 +#define regGENFC_RD 0x0032 +#define regGENFC_RD_BASE_IDX 1 +#define regGENMO_RD 0x0033 +#define regGENMO_RD_BASE_IDX 1 +#define regGRPH8_IDX 0x0033 +#define regGRPH8_IDX_BASE_IDX 1 +#define regGRPH8_DATA 0x0033 +#define regGRPH8_DATA_BASE_IDX 1 +#define regCRTC8_IDX_1 0x0035 +#define regCRTC8_IDX_1_BASE_IDX 1 +#define regCRTC8_DATA_1 0x0035 +#define regCRTC8_DATA_1_BASE_IDX 1 +#define regGENFC_WT_1 0x0036 +#define regGENFC_WT_1_BASE_IDX 1 +#define regGENS1_1 0x0036 +#define regGENS1_1_BASE_IDX 1 +#define regD3VGA_CONTROL 0x0038 +#define regD3VGA_CONTROL_BASE_IDX 1 +#define regD4VGA_CONTROL 0x0039 +#define regD4VGA_CONTROL_BASE_IDX 1 +#define regD5VGA_CONTROL 0x003a +#define regD5VGA_CONTROL_BASE_IDX 1 +#define regD6VGA_CONTROL 0x003b +#define regD6VGA_CONTROL_BASE_IDX 1 +#define regVGA_SOURCE_SELECT 0x003c +#define regVGA_SOURCE_SELECT_BASE_IDX 1 + + +// addressBlock: dcn_dc_mmhubbub_vgaif_dispdec +// base address: 0x0 +#define regMCIF_CONTROL 0x034a +#define regMCIF_CONTROL_BASE_IDX 2 +#define regMCIF_WRITE_COMBINE_CONTROL 0x034b +#define regMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 +#define regMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e +#define regMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 +#define regMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f +#define regMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 +#define regMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 +#define regMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 + + +// addressBlock: dcn_dc_mmhubbub_mcif_wb0_dispdec +// base address: 0x0 +#define regMCIF_WB_BUFMGR_SW_CONTROL 0x0272 +#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 +#define regMCIF_WB_BUFMGR_STATUS 0x0274 +#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_PITCH 0x0275 +#define regMCIF_WB_BUF_PITCH_BASE_IDX 2 +#define regMCIF_WB_BUF_1_STATUS 0x0276 +#define regMCIF_WB_BUF_1_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_1_STATUS2 0x0277 +#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 +#define regMCIF_WB_BUF_2_STATUS 0x0278 +#define regMCIF_WB_BUF_2_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_2_STATUS2 0x0279 +#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 +#define regMCIF_WB_BUF_3_STATUS 0x027a +#define regMCIF_WB_BUF_3_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_3_STATUS2 0x027b +#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 +#define regMCIF_WB_BUF_4_STATUS 0x027c +#define regMCIF_WB_BUF_4_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_4_STATUS2 0x027d +#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 +#define regMCIF_WB_ARBITRATION_CONTROL 0x027e +#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 +#define regMCIF_WB_SCLK_CHANGE 0x027f +#define regMCIF_WB_SCLK_CHANGE_BASE_IDX 2 +#define regMCIF_WB_TEST_DEBUG_INDEX 0x0280 +#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regMCIF_WB_TEST_DEBUG_DATA 0x0281 +#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_Y 0x0282 +#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_C 0x0284 +#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_Y 0x0286 +#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_C 0x0288 +#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_Y 0x028a +#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_C 0x028c +#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_Y 0x028e +#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_C 0x0290 +#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 +#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 +#define regMCIF_WB_NB_PSTATE_CONTROL 0x0293 +#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 +#define regMCIF_WB_CLOCK_GATER_CONTROL 0x0294 +#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 +#define regMCIF_WB_SELF_REFRESH_CONTROL 0x0296 +#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 +#define regMULTI_LEVEL_QOS_CTRL 0x0297 +#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 +#define regMCIF_WB_SECURITY_LEVEL 0x0298 +#define regMCIF_WB_SECURITY_LEVEL_BASE_IDX 2 +#define regMCIF_WB_BUF_LUMA_SIZE 0x0299 +#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 +#define regMCIF_WB_BUF_CHROMA_SIZE 0x029a +#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b +#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c +#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d +#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e +#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f +#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 +#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 +#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 +#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_1_RESOLUTION 0x02a3 +#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_BUF_2_RESOLUTION 0x02a4 +#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_BUF_3_RESOLUTION 0x02a5 +#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_BUF_4_RESOLUTION 0x02a6 +#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI 0x02a7 +#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX 2 +#define regMCIF_WB_VMID_CONTROL 0x02a8 +#define regMCIF_WB_VMID_CONTROL_BASE_IDX 2 +#define regMCIF_WB_MIN_TTO 0x02a9 +#define regMCIF_WB_MIN_TTO_BASE_IDX 2 + + +// addressBlock: dcn_dc_mmhubbub_mmhubbub_dispdec +// base address: 0x0 +#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa +#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 +#define regMCIF_WB_WATERMARK 0x02ab +#define regMCIF_WB_WATERMARK_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_CONFIG 0x02ac +#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad +#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae +#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af +#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 +#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 +#define regMMHUBBUB_MIN_TTO 0x02b1 +#define regMMHUBBUB_MIN_TTO_BASE_IDX 2 +#define regMMHUBBUB_CTRL 0x0333 +#define regMMHUBBUB_CTRL_BASE_IDX 2 +#define regWBIF_SMU_WM_CONTROL 0x0334 +#define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 +#define regWBIF0_MISC_CTRL 0x0335 +#define regWBIF0_MISC_CTRL_BASE_IDX 2 +#define regWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0336 +#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 +#define regWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0337 +#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 +#define regVGA_SRC_SPLIT_CNTL 0x033e +#define regVGA_SRC_SPLIT_CNTL_BASE_IDX 2 +#define regMMHUBBUB_MEM_PWR_STATUS 0x033f +#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 +#define regMMHUBBUB_MEM_PWR_CNTL 0x0340 +#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 +#define regMMHUBBUB_CLOCK_CNTL 0x0341 +#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 +#define regMMHUBBUB_SOFT_RESET 0x0342 +#define regMMHUBBUB_SOFT_RESET_BASE_IDX 2 +#define regDMU_IF_ERR_STATUS 0x0346 +#define regDMU_IF_ERR_STATUS_BASE_IDX 2 +#define regMMHUBBUB_CLIENT_UNIT_ID 0x0347 +#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_VMID_CONTROL 0x0349 +#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0controller_dispdec +// base address: 0x0 +#define regAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 +#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 +#define regAZALIA_AUDIO_DTO 0x03c3 +#define regAZALIA_AUDIO_DTO_BASE_IDX 2 +#define regAZALIA_AUDIO_DTO_CONTROL 0x03c4 +#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 +#define regAZALIA_SOCCLK_CONTROL 0x03c5 +#define regAZALIA_SOCCLK_CONTROL_BASE_IDX 2 +#define regAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 +#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 +#define regAZALIA_DATA_DMA_CONTROL 0x03c7 +#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 +#define regAZALIA_BDL_DMA_CONTROL 0x03c8 +#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 +#define regAZALIA_RIRB_AND_DP_CONTROL 0x03c9 +#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 +#define regAZALIA_CORB_DMA_CONTROL 0x03ca +#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 +#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 +#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 +#define regAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 +#define regAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 +#define regAZALIA_GLOBAL_CAPABILITIES 0x03d3 +#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 +#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 +#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 +#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 +#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 +#define regAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 +#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL0 0x03d9 +#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL1 0x03da +#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL2 0x03db +#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL3 0x03dc +#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_RESULT 0x03dd +#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL0 0x03de +#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL1 0x03df +#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL2 0x03e0 +#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL3 0x03e1 +#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_RESULT 0x03e2 +#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL0 0x03e3 +#define regAZALIA_CRC0_CONTROL0_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL1 0x03e4 +#define regAZALIA_CRC0_CONTROL1_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL2 0x03e5 +#define regAZALIA_CRC0_CONTROL2_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL3 0x03e6 +#define regAZALIA_CRC0_CONTROL3_BASE_IDX 2 +#define regAZALIA_CRC0_RESULT 0x03e7 +#define regAZALIA_CRC0_RESULT_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL0 0x03e8 +#define regAZALIA_CRC1_CONTROL0_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL1 0x03e9 +#define regAZALIA_CRC1_CONTROL1_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL2 0x03ea +#define regAZALIA_CRC1_CONTROL2_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL3 0x03eb +#define regAZALIA_CRC1_CONTROL3_BASE_IDX 2 +#define regAZALIA_CRC1_RESULT 0x03ec +#define regAZALIA_CRC1_RESULT_BASE_IDX 2 +#define regAZALIA_MEM_PWR_CTRL 0x03ee +#define regAZALIA_MEM_PWR_CTRL_BASE_IDX 2 +#define regAZALIA_MEM_PWR_STATUS 0x03ef +#define regAZALIA_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0root_dispdec +// base address: 0x0 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 +#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 +#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 +#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 +#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 +#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 +#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 +#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 +#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 +#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 +#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 +#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 +#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 +#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET5 0x041a +#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET6 0x041b +#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 +#define regREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c +#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 +#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d +#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_az_misc_dispdec +// base address: 0x0 +#define regAZ_CLOCK_CNTL 0x0372 +#define regAZ_CLOCK_CNTL_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0stream0_dispdec +// base address: 0x0 +#define regAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e +#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM0_AZALIA_STREAM_DATA 0x035f +#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0stream1_dispdec +// base address: 0x8 +#define regAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 +#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 +#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0stream2_dispdec +// base address: 0x10 +#define regAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 +#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 +#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0stream3_dispdec +// base address: 0x18 +#define regAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 +#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 +#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0stream4_dispdec +// base address: 0x20 +#define regAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 +#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 +#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0stream5_dispdec +// base address: 0x28 +#define regAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 +#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 +#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0stream6_dispdec +// base address: 0x30 +#define regAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a +#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM6_AZALIA_STREAM_DATA 0x036b +#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0stream7_dispdec +// base address: 0x38 +#define regAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c +#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM7_AZALIA_STREAM_DATA 0x036d +#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0stream8_dispdec +// base address: 0x320 +#define regAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 +#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 +#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0stream9_dispdec +// base address: 0x328 +#define regAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 +#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 +#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0stream10_dispdec +// base address: 0x330 +#define regAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a +#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM10_AZALIA_STREAM_DATA 0x042b +#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0stream11_dispdec +// base address: 0x338 +#define regAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c +#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM11_AZALIA_STREAM_DATA 0x042d +#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0stream12_dispdec +// base address: 0x340 +#define regAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e +#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM12_AZALIA_STREAM_DATA 0x042f +#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0stream13_dispdec +// base address: 0x348 +#define regAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 +#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 +#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0stream14_dispdec +// base address: 0x350 +#define regAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 +#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 +#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0stream15_dispdec +// base address: 0x358 +#define regAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 +#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 +#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0endpoint0_dispdec +// base address: 0x0 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0endpoint1_dispdec +// base address: 0x18 +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0endpoint2_dispdec +// base address: 0x30 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0endpoint3_dispdec +// base address: 0x48 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0endpoint4_dispdec +// base address: 0x60 +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0endpoint5_dispdec +// base address: 0x78 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0endpoint6_dispdec +// base address: 0x90 +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0endpoint7_dispdec +// base address: 0xa8 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0inputendpoint0_dispdec +// base address: 0x0 +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0inputendpoint1_dispdec +// base address: 0x10 +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0inputendpoint2_dispdec +// base address: 0x20 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0inputendpoint3_dispdec +// base address: 0x30 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0inputendpoint4_dispdec +// base address: 0x40 +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0inputendpoint5_dispdec +// base address: 0x50 +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0inputendpoint6_dispdec +// base address: 0x60 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azf0inputendpoint7_dispdec +// base address: 0x70 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_dchubbubl_hubbub_dispdec +// base address: 0x0 +#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x04f9 +#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 +#define regDCHUBBUB_ARB_SAT_LEVEL 0x04fa +#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 +#define regDCHUBBUB_ARB_QOS_FORCE 0x04fb +#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 +#define regDCHUBBUB_ARB_DRAM_STATE_CNTL 0x04fc +#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL 0x04fd +#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x04fe +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A 0x04ff +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x0500 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x0501 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x0502 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A 0x0503 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A 0x0504 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x0505 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0506 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x0507 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B 0x0508 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x0509 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x050a +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x050b +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B 0x050c +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B 0x050d +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x050e +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x050f +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0510 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C 0x0511 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0512 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0513 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0514 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C 0x0515 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C 0x0516 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0517 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0518 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0519 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D 0x051a +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x051b +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051c +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051d +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D 0x051e +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D 0x051f +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x0520 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0521 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x0522 +#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_MALL_CNTL 0x0523 +#define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_TIMEOUT_ENABLE 0x0524 +#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 +#define regDCHUBBUB_GLOBAL_TIMER_CNTL 0x0525 +#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 +#define regSURFACE_CHECK0_ADDRESS_LSB 0x0526 +#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK0_ADDRESS_MSB 0x0527 +#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 +#define regSURFACE_CHECK1_ADDRESS_LSB 0x0528 +#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK1_ADDRESS_MSB 0x0529 +#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 +#define regSURFACE_CHECK2_ADDRESS_LSB 0x052a +#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK2_ADDRESS_MSB 0x052b +#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 +#define regSURFACE_CHECK3_ADDRESS_LSB 0x052c +#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK3_ADDRESS_MSB 0x052d +#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 +#define regVTG0_CONTROL 0x052e +#define regVTG0_CONTROL_BASE_IDX 2 +#define regVTG1_CONTROL 0x052f +#define regVTG1_CONTROL_BASE_IDX 2 +#define regVTG2_CONTROL 0x0530 +#define regVTG2_CONTROL_BASE_IDX 2 +#define regVTG3_CONTROL 0x0531 +#define regVTG3_CONTROL_BASE_IDX 2 +#define regDCHUBBUB_SOFT_RESET 0x0532 +#define regDCHUBBUB_SOFT_RESET_BASE_IDX 2 +#define regDCHUBBUB_CLOCK_CNTL 0x0533 +#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 +#define regDCFCLK_CNTL 0x0534 +#define regDCFCLK_CNTL_BASE_IDX 2 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0535 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0536 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 +#define regDCHUBBUB_VLINE_SNAPSHOT 0x0537 +#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 +#define regDCHUBBUB_CTRL_STATUS 0x0538 +#define regDCHUBBUB_CTRL_STATUS_BASE_IDX 2 +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053e +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053f +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 +#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x0540 +#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 +#define regFMON_CTRL 0x0541 +#define regFMON_CTRL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dchubbubl_hubbub_sdpif_dispdec +// base address: 0x0 +#define regDCHUBBUB_SDPIF_CFG0 0x046f +#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_CFG1 0x0470 +#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_CFG2 0x0471 +#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 +#define regVM_REQUEST_PHYSICAL 0x0472 +#define regVM_REQUEST_PHYSICAL_BASE_IDX 2 +#define regDCHUBBUB_FORCE_IO_STATUS_0 0x0473 +#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 +#define regDCHUBBUB_FORCE_IO_STATUS_1 0x0474 +#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 +#define regDCN_VM_FB_LOCATION_BASE 0x0475 +#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 +#define regDCN_VM_FB_LOCATION_TOP 0x0476 +#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 +#define regDCN_VM_FB_OFFSET 0x0477 +#define regDCN_VM_FB_OFFSET_BASE_IDX 2 +#define regDCN_VM_AGP_BOT 0x0478 +#define regDCN_VM_AGP_BOT_BASE_IDX 2 +#define regDCN_VM_AGP_TOP 0x0479 +#define regDCN_VM_AGP_TOP_BASE_IDX 2 +#define regDCN_VM_AGP_BASE 0x047a +#define regDCN_VM_AGP_BASE_BASE_IDX 2 +#define regDCN_VM_LOCAL_HBM_ADDRESS_START 0x047b +#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 +#define regDCN_VM_LOCAL_HBM_ADDRESS_END 0x047c +#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 +#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x047d +#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x047e +#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_NOALLOC 0x047f +#define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL 0x0480 +#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL 0x0481 +#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL 0x0482 +#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL 0x0483 +#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX 2 +#define regSDPIF_REQUEST_RATE_LIMIT 0x0484 +#define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x0485 +#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x0486 +#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dcn_dc_dchubbubl_hubbub_ret_path_dispdec +// base address: 0x0 +#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04af +#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04b0 +#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 +#define regDCHUBBUB_CRC_CTRL 0x04b1 +#define regDCHUBBUB_CRC_CTRL_BASE_IDX 2 +#define regDCHUBBUB_CRC0_VAL_R_G 0x04b2 +#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 +#define regDCHUBBUB_CRC0_VAL_B_A 0x04b3 +#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 +#define regDCHUBBUB_CRC1_VAL_R_G 0x04b4 +#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 +#define regDCHUBBUB_CRC1_VAL_B_A 0x04b5 +#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT_CNTL 0x04b6 +#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT0 0x04b7 +#define regDCHUBBUB_DCC_STAT0_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT1 0x04b8 +#define regDCHUBBUB_DCC_STAT1_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT2 0x04b9 +#define regDCHUBBUB_DCC_STAT2_BASE_IDX 2 +#define regDCHUBBUB_COMPBUF_CTRL 0x04ba +#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET0_CTRL 0x04bb +#define regDCHUBBUB_DET0_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET1_CTRL 0x04bc +#define regDCHUBBUB_DET1_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET2_CTRL 0x04bd +#define regDCHUBBUB_DET2_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET3_CTRL 0x04be +#define regDCHUBBUB_DET3_CTRL_BASE_IDX 2 +#define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04c0 +#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2 +#define regCOMPBUF_MEM_PWR_CTRL_1 0x04c1 +#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX 2 +#define regCOMPBUF_MEM_PWR_CTRL_2 0x04c2 +#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX 2 +#define regDCHUBBUB_MEM_PWR_STATUS 0x04c3 +#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 +#define regCOMPBUF_RESERVED_SPACE 0x04c4 +#define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2 + + +// addressBlock: dcn_dc_dchubbubl_hubbub_vmrq_if_dispdec +// base address: 0x0 +#define regDCN_VM_CONTEXT0_CNTL 0x0559 +#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_CNTL 0x0560 +#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_CNTL 0x0567 +#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_CNTL 0x056e +#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_CNTL 0x0575 +#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_CNTL 0x057c +#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_CNTL 0x0583 +#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_CNTL 0x058a +#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_CNTL 0x0591 +#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_CNTL 0x0598 +#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_CNTL 0x059f +#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_CNTL 0x05a6 +#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_CNTL 0x05ad +#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_CNTL 0x05b4 +#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_CNTL 0x05bb +#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_CNTL 0x05c2 +#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_DEFAULT_ADDR_MSB 0x05c9 +#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 +#define regDCN_VM_DEFAULT_ADDR_LSB 0x05ca +#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 +#define regDCN_VM_FAULT_CNTL 0x05cb +#define regDCN_VM_FAULT_CNTL_BASE_IDX 2 +#define regDCN_VM_FAULT_STATUS 0x05cc +#define regDCN_VM_FAULT_STATUS_BASE_IDX 2 +#define regDCN_VM_FAULT_ADDR_MSB 0x05cd +#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 +#define regDCN_VM_FAULT_ADDR_LSB 0x05ce +#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcbubp0_dispdec_hubp_dispdec +// base address: 0x0 +#define regHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 +#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP0_DCSURF_ADDR_CONFIG 0x05e6 +#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP0_DCSURF_TILING_CONFIG 0x05e7 +#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 +#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb +#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed +#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef +#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP0_DCHUBP_CNTL 0x05f3 +#define regHUBP0_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP0_HUBP_CLK_CNTL 0x05f4 +#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 +#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP0_DCHUBP_MALL_CONFIG 0x05f6 +#define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX 2 +#define regHUBP0_DCHUBP_MALL_SUB_VP 0x05f7 +#define regHUBP0_DCHUBP_MALL_SUB_VP_BASE_IDX 2 +#define regHUBP0_HUBPREQ_DEBUG_DB 0x05f8 +#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP0_HUBPREQ_DEBUG 0x05f9 +#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fd +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fe +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 +#define regHUBP0_HUBP_MALL_STATUS 0x05ff +#define regHUBP0_HUBP_MALL_STATUS_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcbubp0_dispdec_hubpreq_dispdec +// base address: 0x0 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ0_VMID_SETTINGS_0 0x0609 +#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a +#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b +#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c +#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x061f +#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE 0x0620 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0621 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0622 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0623 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0624 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0625 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0626 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0627 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCN_EXPANSION_MODE 0x0628 +#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ0_DCN_TTU_QOS_WM 0x0629 +#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062a +#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062b +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062c +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062d +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062e +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x062f +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0630 +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0631 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0632 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0633 +#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0634 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0635 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0642 +#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ0_BLANK_OFFSET_0 0x0643 +#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ0_BLANK_OFFSET_1 0x0644 +#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ0_DST_DIMENSIONS 0x0645 +#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ0_DST_AFTER_SCALER 0x0646 +#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ0_PREFETCH_SETTINGS 0x0647 +#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ0_PREFETCH_SETTINGS_C 0x0648 +#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_0 0x0649 +#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_1 0x064a +#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_2 0x064b +#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_3 0x064c +#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_4 0x064d +#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_0 0x064e +#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_1 0x064f +#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_2 0x0650 +#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_0 0x0651 +#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_1 0x0652 +#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_2 0x0653 +#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_3 0x0654 +#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_4 0x0655 +#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_5 0x0656 +#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_6 0x0657 +#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_7 0x0658 +#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ0_PER_LINE_DELIVERY_PRE 0x0659 +#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ0_PER_LINE_DELIVERY 0x065a +#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ0_CURSOR_SETTINGS 0x065b +#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065c +#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065d +#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065e +#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x065f +#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_5 0x0662 +#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_6 0x0663 +#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_3 0x0664 +#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_4 0x0665 +#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_5 0x0666 +#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_6 0x0667 +#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ0_UCLK_PSTATE_FORCE 0x0668 +#define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_STATUS_REG0 0x0669 +#define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_STATUS_REG1 0x066a +#define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_STATUS_REG2 0x066b +#define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcbubp0_dispdec_hubpret_dispdec +// base address: 0x0 +#define regHUBPRET0_HUBPRET_CONTROL 0x066c +#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d +#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e +#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE0 0x0671 +#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE1 0x0672 +#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_INTERRUPT 0x0673 +#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 +#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 +#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcbubp0_dispdec_cursor0_dispdec +// base address: 0x0 +#define regCURSOR0_0_CURSOR_CONTROL 0x0678 +#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_SIZE 0x067b +#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_POSITION 0x067c +#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_HOT_SPOT 0x067d +#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e +#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_DST_OFFSET 0x067f +#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 +#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 +#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 +#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 +#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_CNTL 0x0684 +#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_QOS_CNTL 0x0685 +#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_STATUS 0x0686 +#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_SW_CNTL 0x0687 +#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_SW_DATA 0x0688 +#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 + + + +// addressBlock: dcn_dc_dcbubp1_dispdec_hubp_dispdec +// base address: 0x370 +#define regHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 +#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP1_DCSURF_ADDR_CONFIG 0x06c2 +#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP1_DCSURF_TILING_CONFIG 0x06c3 +#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 +#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb +#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP1_DCHUBP_CNTL 0x06cf +#define regHUBP1_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP1_HUBP_CLK_CNTL 0x06d0 +#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 +#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP1_DCHUBP_MALL_CONFIG 0x06d2 +#define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX 2 +#define regHUBP1_DCHUBP_MALL_SUB_VP 0x06d3 +#define regHUBP1_DCHUBP_MALL_SUB_VP_BASE_IDX 2 +#define regHUBP1_HUBPREQ_DEBUG_DB 0x06d4 +#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP1_HUBPREQ_DEBUG 0x06d5 +#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d9 +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06da +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 +#define regHUBP1_HUBP_MALL_STATUS 0x06db +#define regHUBP1_HUBP_MALL_STATUS_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcbubp1_dispdec_hubpreq_dispdec +// base address: 0x370 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ1_VMID_SETTINGS_0 0x06e5 +#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 +#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fb +#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fc +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fd +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06fe +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x06ff +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0700 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0701 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0702 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0703 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCN_EXPANSION_MODE 0x0704 +#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ1_DCN_TTU_QOS_WM 0x0705 +#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0706 +#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0707 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0708 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x0709 +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070a +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070b +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070c +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070d +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070e +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_DMDATA_VM_CNTL 0x070f +#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0710 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0711 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071e +#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ1_BLANK_OFFSET_0 0x071f +#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ1_BLANK_OFFSET_1 0x0720 +#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ1_DST_DIMENSIONS 0x0721 +#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ1_DST_AFTER_SCALER 0x0722 +#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ1_PREFETCH_SETTINGS 0x0723 +#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ1_PREFETCH_SETTINGS_C 0x0724 +#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_0 0x0725 +#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_1 0x0726 +#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_2 0x0727 +#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_3 0x0728 +#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_4 0x0729 +#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_0 0x072a +#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_1 0x072b +#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_2 0x072c +#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_0 0x072d +#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_1 0x072e +#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_2 0x072f +#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_3 0x0730 +#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_4 0x0731 +#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_5 0x0732 +#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_6 0x0733 +#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_7 0x0734 +#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0735 +#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ1_PER_LINE_DELIVERY 0x0736 +#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ1_CURSOR_SETTINGS 0x0737 +#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0738 +#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x0739 +#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073a +#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073b +#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_5 0x073e +#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_6 0x073f +#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_3 0x0740 +#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_4 0x0741 +#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_5 0x0742 +#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_6 0x0743 +#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ1_UCLK_PSTATE_FORCE 0x0744 +#define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_STATUS_REG0 0x0745 +#define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_STATUS_REG1 0x0746 +#define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_STATUS_REG2 0x0747 +#define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcbubp1_dispdec_hubpret_dispdec +// base address: 0x370 +#define regHUBPRET1_HUBPRET_CONTROL 0x0748 +#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 +#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a +#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE0 0x074d +#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE1 0x074e +#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_INTERRUPT 0x074f +#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 +#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 +#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcbubp1_dispdec_cursor0_dispdec +// base address: 0x370 +#define regCURSOR0_1_CURSOR_CONTROL 0x0754 +#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_SIZE 0x0757 +#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_POSITION 0x0758 +#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_HOT_SPOT 0x0759 +#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a +#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_DST_OFFSET 0x075b +#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c +#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d +#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e +#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f +#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_CNTL 0x0760 +#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_QOS_CNTL 0x0761 +#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_STATUS 0x0762 +#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_SW_CNTL 0x0763 +#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_SW_DATA 0x0764 +#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcbubp2_dispdec_hubp_dispdec +// base address: 0x6e0 +#define regHUBP2_DCSURF_SURFACE_CONFIG 0x079d +#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP2_DCSURF_ADDR_CONFIG 0x079e +#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP2_DCSURF_TILING_CONFIG 0x079f +#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP2_DCHUBP_CNTL 0x07ab +#define regHUBP2_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP2_HUBP_CLK_CNTL 0x07ac +#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP2_DCHUBP_VMPG_CONFIG 0x07ad +#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP2_DCHUBP_MALL_CONFIG 0x07ae +#define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX 2 +#define regHUBP2_DCHUBP_MALL_SUB_VP 0x07af +#define regHUBP2_DCHUBP_MALL_SUB_VP_BASE_IDX 2 +#define regHUBP2_HUBPREQ_DEBUG_DB 0x07b0 +#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP2_HUBPREQ_DEBUG 0x07b1 +#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b5 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b6 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 +#define regHUBP2_HUBP_MALL_STATUS 0x07b7 +#define regHUBP2_HUBP_MALL_STATUS_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcbubp2_dispdec_hubpreq_dispdec +// base address: 0x6e0 +#define regHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf +#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 +#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ2_VMID_SETTINGS_0 0x07c1 +#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 +#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d7 +#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d8 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07d9 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07da +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07db +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dc +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07dd +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07de +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07df +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCN_EXPANSION_MODE 0x07e0 +#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ2_DCN_TTU_QOS_WM 0x07e1 +#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e2 +#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e3 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e4 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e5 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e6 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e7 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e8 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07e9 +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07ea +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07eb +#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ec +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ed +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fa +#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ2_BLANK_OFFSET_0 0x07fb +#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ2_BLANK_OFFSET_1 0x07fc +#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ2_DST_DIMENSIONS 0x07fd +#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ2_DST_AFTER_SCALER 0x07fe +#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ2_PREFETCH_SETTINGS 0x07ff +#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ2_PREFETCH_SETTINGS_C 0x0800 +#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_0 0x0801 +#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_1 0x0802 +#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_2 0x0803 +#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_3 0x0804 +#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_4 0x0805 +#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_0 0x0806 +#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_1 0x0807 +#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_2 0x0808 +#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_0 0x0809 +#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_1 0x080a +#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_2 0x080b +#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_3 0x080c +#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_4 0x080d +#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_5 0x080e +#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_6 0x080f +#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_7 0x0810 +#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0811 +#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ2_PER_LINE_DELIVERY 0x0812 +#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ2_CURSOR_SETTINGS 0x0813 +#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0814 +#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0815 +#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0816 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0817 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_5 0x081a +#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_6 0x081b +#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_3 0x081c +#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_4 0x081d +#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_5 0x081e +#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_6 0x081f +#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ2_UCLK_PSTATE_FORCE 0x0820 +#define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_STATUS_REG0 0x0821 +#define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_STATUS_REG1 0x0822 +#define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_STATUS_REG2 0x0823 +#define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcbubp2_dispdec_hubpret_dispdec +// base address: 0x6e0 +#define regHUBPRET2_HUBPRET_CONTROL 0x0824 +#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 +#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 +#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE0 0x0829 +#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE1 0x082a +#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_INTERRUPT 0x082b +#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c +#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d +#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcbubp2_dispdec_cursor0_dispdec +// base address: 0x6e0 +#define regCURSOR0_2_CURSOR_CONTROL 0x0830 +#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_SIZE 0x0833 +#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_POSITION 0x0834 +#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_HOT_SPOT 0x0835 +#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 +#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_DST_OFFSET 0x0837 +#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 +#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 +#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a +#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b +#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_CNTL 0x083c +#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_QOS_CNTL 0x083d +#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_STATUS 0x083e +#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_SW_CNTL 0x083f +#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_SW_DATA 0x0840 +#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcbubp3_dispdec_hubp_dispdec +// base address: 0xa50 +#define regHUBP3_DCSURF_SURFACE_CONFIG 0x0879 +#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP3_DCSURF_ADDR_CONFIG 0x087a +#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP3_DCSURF_TILING_CONFIG 0x087b +#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d +#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f +#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP3_DCHUBP_CNTL 0x0887 +#define regHUBP3_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP3_HUBP_CLK_CNTL 0x0888 +#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP3_DCHUBP_VMPG_CONFIG 0x0889 +#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP3_DCHUBP_MALL_CONFIG 0x088a +#define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX 2 +#define regHUBP3_DCHUBP_MALL_SUB_VP 0x088b +#define regHUBP3_DCHUBP_MALL_SUB_VP_BASE_IDX 2 +#define regHUBP3_HUBPREQ_DEBUG_DB 0x088c +#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP3_HUBPREQ_DEBUG 0x088d +#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0891 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0892 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 +#define regHUBP3_HUBP_MALL_STATUS 0x0893 +#define regHUBP3_HUBP_MALL_STATUS_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcbubp3_dispdec_hubpreq_dispdec +// base address: 0xa50 +#define regHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b +#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c +#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ3_VMID_SETTINGS_0 0x089d +#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae +#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af +#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 +#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b3 +#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b4 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b5 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b6 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b7 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b8 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08b9 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08ba +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bb +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCN_EXPANSION_MODE 0x08bc +#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ3_DCN_TTU_QOS_WM 0x08bd +#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08be +#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08bf +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c0 +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c1 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c2 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c3 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c4 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c5 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c6 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c7 +#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c8 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08c9 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d6 +#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ3_BLANK_OFFSET_0 0x08d7 +#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ3_BLANK_OFFSET_1 0x08d8 +#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ3_DST_DIMENSIONS 0x08d9 +#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ3_DST_AFTER_SCALER 0x08da +#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ3_PREFETCH_SETTINGS 0x08db +#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ3_PREFETCH_SETTINGS_C 0x08dc +#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_0 0x08dd +#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_1 0x08de +#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_2 0x08df +#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_3 0x08e0 +#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_4 0x08e1 +#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_0 0x08e2 +#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_1 0x08e3 +#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_2 0x08e4 +#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_0 0x08e5 +#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_1 0x08e6 +#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_2 0x08e7 +#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_3 0x08e8 +#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_4 0x08e9 +#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_5 0x08ea +#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_6 0x08eb +#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_7 0x08ec +#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ed +#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ3_PER_LINE_DELIVERY 0x08ee +#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ3_CURSOR_SETTINGS 0x08ef +#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f0 +#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f1 +#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f2 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f3 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_5 0x08f6 +#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_6 0x08f7 +#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_3 0x08f8 +#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_4 0x08f9 +#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_5 0x08fa +#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_6 0x08fb +#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ3_UCLK_PSTATE_FORCE 0x08fc +#define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_STATUS_REG0 0x08fd +#define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_STATUS_REG1 0x08fe +#define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_STATUS_REG2 0x08ff +#define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcbubp3_dispdec_hubpret_dispdec +// base address: 0xa50 +#define regHUBPRET3_HUBPRET_CONTROL 0x0900 +#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 +#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 +#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE0 0x0905 +#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE1 0x0906 +#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_INTERRUPT 0x0907 +#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 +#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 +#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcbubp3_dispdec_cursor0_dispdec +// base address: 0xa50 +#define regCURSOR0_3_CURSOR_CONTROL 0x090c +#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_SIZE 0x090f +#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_POSITION 0x0910 +#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_HOT_SPOT 0x0911 +#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 +#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_DST_OFFSET 0x0913 +#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 +#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 +#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 +#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 +#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_CNTL 0x0918 +#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_QOS_CNTL 0x0919 +#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_STATUS 0x091a +#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_SW_CNTL 0x091b +#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_SW_DATA 0x091c +#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp0_dispdec_cnvc_cfg_dispdec +// base address: 0x0 +#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf +#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG0_FORMAT_CONTROL 0x0cd0 +#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 +#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 +#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 +#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 +#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 +#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 +#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 +#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 +#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 +#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda +#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb +#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd +#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 +#define regCNVC_CFG0_PRE_DEALPHA 0x0cde +#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_MODE 0x0cdf +#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0 +#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1 +#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2 +#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3 +#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4 +#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5 +#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6 +#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7 +#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8 +#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9 +#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea +#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb +#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec +#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG0_PRE_DEGAM 0x0ced +#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG0_PRE_REALPHA 0x0cee +#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp0_dispdec_cnvc_cur_dispdec +// base address: 0x0 +#define regCNVC_CUR0_CURSOR0_CONTROL 0x0cf1 +#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 +#define regCNVC_CUR0_CURSOR0_COLOR0 0x0cf2 +#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 +#define regCNVC_CUR0_CURSOR0_COLOR1 0x0cf3 +#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 +#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4 +#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp0_dispdec_dscl_dispdec +// base address: 0x0 +#define regDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9 +#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa +#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL0_SCL_MODE 0x0cfb +#define regDSCL0_SCL_MODE_BASE_IDX 2 +#define regDSCL0_SCL_TAP_CONTROL 0x0cfc +#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL0_DSCL_CONTROL 0x0cfd +#define regDSCL0_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL0_DSCL_2TAP_CONTROL 0x0cfe +#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff +#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00 +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_INIT 0x0d01 +#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02 +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03 +#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT 0x0d05 +#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08 +#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL0_SCL_BLACK_COLOR 0x0d0a +#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL0_DSCL_UPDATE 0x0d0b +#define regDSCL0_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL0_DSCL_AUTOCAL 0x0d0c +#define regDSCL0_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d +#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e +#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL0_OTG_H_BLANK 0x0d0f +#define regDSCL0_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL0_OTG_V_BLANK 0x0d10 +#define regDSCL0_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL0_RECOUT_START 0x0d11 +#define regDSCL0_RECOUT_START_BASE_IDX 2 +#define regDSCL0_RECOUT_SIZE 0x0d12 +#define regDSCL0_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL0_MPC_SIZE 0x0d13 +#define regDSCL0_MPC_SIZE_BASE_IDX 2 +#define regDSCL0_LB_DATA_FORMAT 0x0d14 +#define regDSCL0_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL0_LB_MEMORY_CTRL 0x0d15 +#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL0_LB_V_COUNTER 0x0d16 +#define regDSCL0_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL0_DSCL_MEM_PWR_CTRL 0x0d17 +#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL0_DSCL_MEM_PWR_STATUS 0x0d18 +#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL0_OBUF_CONTROL 0x0d19 +#define regDSCL0_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a +#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp0_dispdec_cm_dispdec +// base address: 0x0 +#define regCM0_CM_CONTROL 0x0d20 +#define regCM0_CM_CONTROL_BASE_IDX 2 +#define regCM0_CM_POST_CSC_CONTROL 0x0d21 +#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C11_C12 0x0d22 +#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C13_C14 0x0d23 +#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C21_C22 0x0d24 +#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C23_C24 0x0d25 +#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C31_C32 0x0d26 +#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C33_C34 0x0d27 +#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C11_C12 0x0d28 +#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C13_C14 0x0d29 +#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C21_C22 0x0d2a +#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C23_C24 0x0d2b +#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C31_C32 0x0d2c +#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C33_C34 0x0d2d +#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e +#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f +#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_C13_C14 0x0d30 +#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_C21_C22 0x0d31 +#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_C23_C24 0x0d32 +#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_C31_C32 0x0d33 +#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_C33_C34 0x0d34 +#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35 +#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36 +#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37 +#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38 +#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39 +#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a +#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 +#define regCM0_CM_BIAS_CR_R 0x0d3b +#define regCM0_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM0_CM_BIAS_Y_G_CB_B 0x0d3c +#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_CONTROL 0x0d3d +#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM0_CM_GAMCOR_LUT_INDEX 0x0d3e +#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM0_CM_GAMCOR_LUT_DATA 0x0d3f +#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM0_CM_GAMCOR_LUT_CONTROL 0x0d40 +#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53 +#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54 +#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55 +#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56 +#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57 +#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58 +#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59 +#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a +#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b +#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c +#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d +#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e +#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f +#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60 +#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61 +#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62 +#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63 +#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76 +#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77 +#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78 +#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79 +#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a +#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b +#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c +#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d +#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e +#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f +#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80 +#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81 +#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82 +#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83 +#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84 +#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85 +#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86 +#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM0_CM_HDR_MULT_COEF 0x0d87 +#define regCM0_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM0_CM_MEM_PWR_CTRL 0x0d88 +#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM0_CM_MEM_PWR_STATUS 0x0d89 +#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM0_CM_DEALPHA 0x0d8b +#define regCM0_CM_DEALPHA_BASE_IDX 2 +#define regCM0_CM_COEF_FORMAT 0x0d8c +#define regCM0_CM_COEF_FORMAT_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp0_dispdec_dpp_top_dispdec +// base address: 0x0 +#define regDPP_TOP0_DPP_CONTROL 0x0cc5 +#define regDPP_TOP0_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP0_DPP_SOFT_RESET 0x0cc6 +#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 +#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 +#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_CTRL 0x0cc9 +#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP0_HOST_READ_CONTROL 0x0cca +#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp1_dispdec_cnvc_cfg_dispdec +// base address: 0x5ac +#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a +#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG1_FORMAT_CONTROL 0x0e3b +#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c +#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d +#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e +#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f +#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 +#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 +#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 +#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 +#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_RED 0x0e44 +#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 +#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 +#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 +#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 +#define regCNVC_CFG1_PRE_DEALPHA 0x0e49 +#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_MODE 0x0e4a +#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b +#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c +#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d +#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e +#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f +#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C33_C34 0x0e50 +#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51 +#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52 +#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53 +#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54 +#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55 +#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56 +#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57 +#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG1_PRE_DEGAM 0x0e58 +#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG1_PRE_REALPHA 0x0e59 +#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp1_dispdec_cnvc_cur_dispdec +// base address: 0x5ac +#define regCNVC_CUR1_CURSOR0_CONTROL 0x0e5c +#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 +#define regCNVC_CUR1_CURSOR0_COLOR0 0x0e5d +#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 +#define regCNVC_CUR1_CURSOR0_COLOR1 0x0e5e +#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 +#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f +#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp1_dispdec_dscl_dispdec +// base address: 0x5ac +#define regDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64 +#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65 +#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL1_SCL_MODE 0x0e66 +#define regDSCL1_SCL_MODE_BASE_IDX 2 +#define regDSCL1_SCL_TAP_CONTROL 0x0e67 +#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL1_DSCL_CONTROL 0x0e68 +#define regDSCL1_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL1_DSCL_2TAP_CONTROL 0x0e69 +#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a +#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c +#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e +#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT 0x0e70 +#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72 +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73 +#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL1_SCL_BLACK_COLOR 0x0e75 +#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL1_DSCL_UPDATE 0x0e76 +#define regDSCL1_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL1_DSCL_AUTOCAL 0x0e77 +#define regDSCL1_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78 +#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79 +#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL1_OTG_H_BLANK 0x0e7a +#define regDSCL1_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL1_OTG_V_BLANK 0x0e7b +#define regDSCL1_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL1_RECOUT_START 0x0e7c +#define regDSCL1_RECOUT_START_BASE_IDX 2 +#define regDSCL1_RECOUT_SIZE 0x0e7d +#define regDSCL1_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL1_MPC_SIZE 0x0e7e +#define regDSCL1_MPC_SIZE_BASE_IDX 2 +#define regDSCL1_LB_DATA_FORMAT 0x0e7f +#define regDSCL1_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL1_LB_MEMORY_CTRL 0x0e80 +#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL1_LB_V_COUNTER 0x0e81 +#define regDSCL1_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL1_DSCL_MEM_PWR_CTRL 0x0e82 +#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL1_DSCL_MEM_PWR_STATUS 0x0e83 +#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL1_OBUF_CONTROL 0x0e84 +#define regDSCL1_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL1_OBUF_MEM_PWR_CTRL 0x0e85 +#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp1_dispdec_cm_dispdec +// base address: 0x5ac +#define regCM1_CM_CONTROL 0x0e8b +#define regCM1_CM_CONTROL_BASE_IDX 2 +#define regCM1_CM_POST_CSC_CONTROL 0x0e8c +#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C11_C12 0x0e8d +#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C13_C14 0x0e8e +#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C21_C22 0x0e8f +#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C23_C24 0x0e90 +#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C31_C32 0x0e91 +#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C33_C34 0x0e92 +#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C11_C12 0x0e93 +#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C13_C14 0x0e94 +#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C21_C22 0x0e95 +#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C23_C24 0x0e96 +#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C31_C32 0x0e97 +#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C33_C34 0x0e98 +#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_CONTROL 0x0e99 +#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a +#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b +#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c +#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d +#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e +#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f +#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0 +#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1 +#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2 +#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3 +#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4 +#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5 +#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 +#define regCM1_CM_BIAS_CR_R 0x0ea6 +#define regCM1_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM1_CM_BIAS_Y_G_CB_B 0x0ea7 +#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_CONTROL 0x0ea8 +#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM1_CM_GAMCOR_LUT_INDEX 0x0ea9 +#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM1_CM_GAMCOR_LUT_DATA 0x0eaa +#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM1_CM_GAMCOR_LUT_CONTROL 0x0eab +#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb +#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc +#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd +#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe +#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf +#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0 +#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1 +#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2 +#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3 +#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4 +#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5 +#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6 +#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7 +#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8 +#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9 +#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca +#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb +#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc +#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd +#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece +#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede +#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf +#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0 +#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1 +#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2 +#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3 +#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4 +#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5 +#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6 +#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7 +#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8 +#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9 +#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea +#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb +#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec +#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed +#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee +#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef +#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0 +#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1 +#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM1_CM_HDR_MULT_COEF 0x0ef2 +#define regCM1_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM1_CM_MEM_PWR_CTRL 0x0ef3 +#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM1_CM_MEM_PWR_STATUS 0x0ef4 +#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM1_CM_DEALPHA 0x0ef6 +#define regCM1_CM_DEALPHA_BASE_IDX 2 +#define regCM1_CM_COEF_FORMAT 0x0ef7 +#define regCM1_CM_COEF_FORMAT_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp1_dispdec_dpp_top_dispdec +// base address: 0x5ac +#define regDPP_TOP1_DPP_CONTROL 0x0e30 +#define regDPP_TOP1_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP1_DPP_SOFT_RESET 0x0e31 +#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 +#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 +#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_CTRL 0x0e34 +#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP1_HOST_READ_CONTROL 0x0e35 +#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp2_dispdec_cnvc_cfg_dispdec +// base address: 0xb58 +#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 +#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG2_FORMAT_CONTROL 0x0fa6 +#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 +#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 +#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 +#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa +#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab +#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac +#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad +#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae +#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_RED 0x0faf +#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 +#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 +#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 +#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 +#define regCNVC_CFG2_PRE_DEALPHA 0x0fb4 +#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_MODE 0x0fb5 +#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6 +#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7 +#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8 +#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9 +#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C31_C32 0x0fba +#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb +#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc +#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd +#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe +#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf +#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0 +#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1 +#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2 +#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG2_PRE_DEGAM 0x0fc3 +#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG2_PRE_REALPHA 0x0fc4 +#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp2_dispdec_cnvc_cur_dispdec +// base address: 0xb58 +#define regCNVC_CUR2_CURSOR0_CONTROL 0x0fc7 +#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 +#define regCNVC_CUR2_CURSOR0_COLOR0 0x0fc8 +#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 +#define regCNVC_CUR2_CURSOR0_COLOR1 0x0fc9 +#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 +#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fca +#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp2_dispdec_dscl_dispdec +// base address: 0xb58 +#define regDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fcf +#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fd0 +#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL2_SCL_MODE 0x0fd1 +#define regDSCL2_SCL_MODE_BASE_IDX 2 +#define regDSCL2_SCL_TAP_CONTROL 0x0fd2 +#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL2_DSCL_CONTROL 0x0fd3 +#define regDSCL2_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL2_DSCL_2TAP_CONTROL 0x0fd4 +#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fd5 +#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fd6 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_INIT 0x0fd7 +#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fd8 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fd9 +#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fda +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT 0x0fdb +#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fdc +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fdd +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT_C 0x0fde +#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fdf +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL2_SCL_BLACK_COLOR 0x0fe0 +#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL2_DSCL_UPDATE 0x0fe1 +#define regDSCL2_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL2_DSCL_AUTOCAL 0x0fe2 +#define regDSCL2_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fe3 +#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fe4 +#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL2_OTG_H_BLANK 0x0fe5 +#define regDSCL2_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL2_OTG_V_BLANK 0x0fe6 +#define regDSCL2_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL2_RECOUT_START 0x0fe7 +#define regDSCL2_RECOUT_START_BASE_IDX 2 +#define regDSCL2_RECOUT_SIZE 0x0fe8 +#define regDSCL2_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL2_MPC_SIZE 0x0fe9 +#define regDSCL2_MPC_SIZE_BASE_IDX 2 +#define regDSCL2_LB_DATA_FORMAT 0x0fea +#define regDSCL2_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL2_LB_MEMORY_CTRL 0x0feb +#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL2_LB_V_COUNTER 0x0fec +#define regDSCL2_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL2_DSCL_MEM_PWR_CTRL 0x0fed +#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL2_DSCL_MEM_PWR_STATUS 0x0fee +#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL2_OBUF_CONTROL 0x0fef +#define regDSCL2_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL2_OBUF_MEM_PWR_CTRL 0x0ff0 +#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp2_dispdec_cm_dispdec +// base address: 0xb58 +#define regCM2_CM_CONTROL 0x0ff6 +#define regCM2_CM_CONTROL_BASE_IDX 2 +#define regCM2_CM_POST_CSC_CONTROL 0x0ff7 +#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C11_C12 0x0ff8 +#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C13_C14 0x0ff9 +#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C21_C22 0x0ffa +#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C23_C24 0x0ffb +#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C31_C32 0x0ffc +#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C33_C34 0x0ffd +#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C11_C12 0x0ffe +#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C13_C14 0x0fff +#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C21_C22 0x1000 +#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C23_C24 0x1001 +#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C31_C32 0x1002 +#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C33_C34 0x1003 +#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_CONTROL 0x1004 +#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_C11_C12 0x1005 +#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_C13_C14 0x1006 +#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_C21_C22 0x1007 +#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_C23_C24 0x1008 +#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_C31_C32 0x1009 +#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_C33_C34 0x100a +#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_B_C11_C12 0x100b +#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_B_C13_C14 0x100c +#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_B_C21_C22 0x100d +#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_B_C23_C24 0x100e +#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_B_C31_C32 0x100f +#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_B_C33_C34 0x1010 +#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 +#define regCM2_CM_BIAS_CR_R 0x1011 +#define regCM2_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM2_CM_BIAS_Y_G_CB_B 0x1012 +#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_CONTROL 0x1013 +#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM2_CM_GAMCOR_LUT_INDEX 0x1014 +#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM2_CM_GAMCOR_LUT_DATA 0x1015 +#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM2_CM_GAMCOR_LUT_CONTROL 0x1016 +#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1017 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1018 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1019 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x101a +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x101b +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x101c +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x101d +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x101e +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x101f +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x1020 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x1021 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x1022 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x1023 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1024 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1025 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1026 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1027 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1028 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1029 +#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_2_3 0x102a +#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_4_5 0x102b +#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_6_7 0x102c +#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_8_9 0x102d +#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_10_11 0x102e +#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_12_13 0x102f +#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_14_15 0x1030 +#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_16_17 0x1031 +#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_18_19 0x1032 +#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_20_21 0x1033 +#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1034 +#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1035 +#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1036 +#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1037 +#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1038 +#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1039 +#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x103a +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x103b +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x103c +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x103d +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x103e +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x103f +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1040 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1041 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1042 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x1043 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1044 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1045 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1046 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1047 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1048 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1049 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_G 0x104a +#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_R 0x104b +#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_0_1 0x104c +#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_2_3 0x104d +#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_4_5 0x104e +#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_6_7 0x104f +#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_8_9 0x1050 +#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_10_11 0x1051 +#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_12_13 0x1052 +#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_14_15 0x1053 +#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1054 +#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1055 +#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1056 +#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1057 +#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1058 +#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1059 +#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_28_29 0x105a +#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_30_31 0x105b +#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_32_33 0x105c +#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM2_CM_HDR_MULT_COEF 0x105d +#define regCM2_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM2_CM_MEM_PWR_CTRL 0x105e +#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM2_CM_MEM_PWR_STATUS 0x105f +#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM2_CM_DEALPHA 0x1061 +#define regCM2_CM_DEALPHA_BASE_IDX 2 +#define regCM2_CM_COEF_FORMAT 0x1062 +#define regCM2_CM_COEF_FORMAT_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp2_dispdec_dpp_top_dispdec +// base address: 0xb58 +#define regDPP_TOP2_DPP_CONTROL 0x0f9b +#define regDPP_TOP2_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP2_DPP_SOFT_RESET 0x0f9c +#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d +#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e +#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_CTRL 0x0f9f +#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP2_HOST_READ_CONTROL 0x0fa0 +#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp3_dispdec_cnvc_cfg_dispdec +// base address: 0x1104 +#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 +#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG3_FORMAT_CONTROL 0x1111 +#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 +#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 +#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 +#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 +#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 +#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 +#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 +#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 +#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_RED 0x111a +#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_GREEN 0x111b +#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_BLUE 0x111c +#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG3_ALPHA_2BIT_LUT 0x111e +#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 +#define regCNVC_CFG3_PRE_DEALPHA 0x111f +#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_MODE 0x1120 +#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C11_C12 0x1121 +#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C13_C14 0x1122 +#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C21_C22 0x1123 +#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C23_C24 0x1124 +#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C31_C32 0x1125 +#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C33_C34 0x1126 +#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127 +#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128 +#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129 +#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a +#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b +#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c +#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG3_CNVC_COEF_FORMAT 0x112d +#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG3_PRE_DEGAM 0x112e +#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG3_PRE_REALPHA 0x112f +#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp3_dispdec_cnvc_cur_dispdec +// base address: 0x1104 +#define regCNVC_CUR3_CURSOR0_CONTROL 0x1132 +#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 +#define regCNVC_CUR3_CURSOR0_COLOR0 0x1133 +#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 +#define regCNVC_CUR3_CURSOR0_COLOR1 0x1134 +#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 +#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1135 +#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp3_dispdec_dscl_dispdec +// base address: 0x1104 +#define regDSCL3_SCL_COEF_RAM_TAP_SELECT 0x113a +#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL3_SCL_COEF_RAM_TAP_DATA 0x113b +#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL3_SCL_MODE 0x113c +#define regDSCL3_SCL_MODE_BASE_IDX 2 +#define regDSCL3_SCL_TAP_CONTROL 0x113d +#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL3_DSCL_CONTROL 0x113e +#define regDSCL3_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL3_DSCL_2TAP_CONTROL 0x113f +#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1140 +#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1141 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_INIT 0x1142 +#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1143 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_INIT_C 0x1144 +#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1145 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT 0x1146 +#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1147 +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1148 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT_C 0x1149 +#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x114a +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL3_SCL_BLACK_COLOR 0x114b +#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL3_DSCL_UPDATE 0x114c +#define regDSCL3_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL3_DSCL_AUTOCAL 0x114d +#define regDSCL3_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x114e +#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x114f +#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL3_OTG_H_BLANK 0x1150 +#define regDSCL3_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL3_OTG_V_BLANK 0x1151 +#define regDSCL3_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL3_RECOUT_START 0x1152 +#define regDSCL3_RECOUT_START_BASE_IDX 2 +#define regDSCL3_RECOUT_SIZE 0x1153 +#define regDSCL3_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL3_MPC_SIZE 0x1154 +#define regDSCL3_MPC_SIZE_BASE_IDX 2 +#define regDSCL3_LB_DATA_FORMAT 0x1155 +#define regDSCL3_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL3_LB_MEMORY_CTRL 0x1156 +#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL3_LB_V_COUNTER 0x1157 +#define regDSCL3_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL3_DSCL_MEM_PWR_CTRL 0x1158 +#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL3_DSCL_MEM_PWR_STATUS 0x1159 +#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL3_OBUF_CONTROL 0x115a +#define regDSCL3_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL3_OBUF_MEM_PWR_CTRL 0x115b +#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp3_dispdec_cm_dispdec +// base address: 0x1104 +#define regCM3_CM_CONTROL 0x1161 +#define regCM3_CM_CONTROL_BASE_IDX 2 +#define regCM3_CM_POST_CSC_CONTROL 0x1162 +#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C11_C12 0x1163 +#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C13_C14 0x1164 +#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C21_C22 0x1165 +#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C23_C24 0x1166 +#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C31_C32 0x1167 +#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C33_C34 0x1168 +#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C11_C12 0x1169 +#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C13_C14 0x116a +#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C21_C22 0x116b +#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C23_C24 0x116c +#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C31_C32 0x116d +#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C33_C34 0x116e +#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_CONTROL 0x116f +#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_C11_C12 0x1170 +#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_C13_C14 0x1171 +#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_C21_C22 0x1172 +#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_C23_C24 0x1173 +#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_C31_C32 0x1174 +#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_C33_C34 0x1175 +#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_B_C11_C12 0x1176 +#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_B_C13_C14 0x1177 +#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_B_C21_C22 0x1178 +#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_B_C23_C24 0x1179 +#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_B_C31_C32 0x117a +#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_B_C33_C34 0x117b +#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 +#define regCM3_CM_BIAS_CR_R 0x117c +#define regCM3_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM3_CM_BIAS_Y_G_CB_B 0x117d +#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_CONTROL 0x117e +#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM3_CM_GAMCOR_LUT_INDEX 0x117f +#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM3_CM_GAMCOR_LUT_DATA 0x1180 +#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM3_CM_GAMCOR_LUT_CONTROL 0x1181 +#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x1182 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x1183 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x1184 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1185 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1186 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1187 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1188 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1189 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x118a +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x118b +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x118c +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x118d +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x118e +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x118f +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x1190 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_B 0x1191 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_G 0x1192 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_R 0x1193 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_0_1 0x1194 +#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_2_3 0x1195 +#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_4_5 0x1196 +#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_6_7 0x1197 +#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_8_9 0x1198 +#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_10_11 0x1199 +#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_12_13 0x119a +#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_14_15 0x119b +#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_16_17 0x119c +#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_18_19 0x119d +#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_20_21 0x119e +#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_22_23 0x119f +#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11a0 +#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11a1 +#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11a2 +#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11a3 +#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11a4 +#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11a5 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11a6 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11a7 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11a8 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11a9 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11aa +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11ab +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11ac +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11ad +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ae +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11af +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11b0 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11b1 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11b2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11b3 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11b4 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11b5 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11b6 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11b7 +#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11b8 +#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11b9 +#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11ba +#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11bb +#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11bc +#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11bd +#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11be +#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11bf +#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11c0 +#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11c1 +#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11c2 +#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11c3 +#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11c4 +#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11c5 +#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_30_31 0x11c6 +#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_32_33 0x11c7 +#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM3_CM_HDR_MULT_COEF 0x11c8 +#define regCM3_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM3_CM_MEM_PWR_CTRL 0x11c9 +#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM3_CM_MEM_PWR_STATUS 0x11ca +#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM3_CM_DEALPHA 0x11cc +#define regCM3_CM_DEALPHA_BASE_IDX 2 +#define regCM3_CM_COEF_FORMAT 0x11cd +#define regCM3_CM_COEF_FORMAT_BASE_IDX 2 + + +// addressBlock: dcn_dc_dpp3_dispdec_dpp_top_dispdec +// base address: 0x1104 +#define regDPP_TOP3_DPP_CONTROL 0x1106 +#define regDPP_TOP3_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP3_DPP_SOFT_RESET 0x1107 +#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_VAL_R_G 0x1108 +#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_VAL_B_A 0x1109 +#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_CTRL 0x110a +#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP3_HOST_READ_CONTROL 0x110b +#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_mpc_mpcc0_dispdec +// base address: 0x0 +#define regMPCC0_MPCC_TOP_SEL 0x0000 +#define regMPCC0_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC0_MPCC_BOT_SEL 0x0001 +#define regMPCC0_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC0_MPCC_OPP_ID 0x0002 +#define regMPCC0_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC0_MPCC_CONTROL 0x0003 +#define regMPCC0_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC0_MPCC_SM_CONTROL 0x0004 +#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005 +#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC0_MPCC_TOP_GAIN 0x0006 +#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007 +#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008 +#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0009 +#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 +#define regMPCC0_MPCC_BG_R_CR 0x000a +#define regMPCC0_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC0_MPCC_BG_G_Y 0x000b +#define regMPCC0_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC0_MPCC_BG_B_CB 0x000c +#define regMPCC0_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC0_MPCC_MEM_PWR_CTRL 0x000d +#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC0_MPCC_STATUS 0x000e +#define regMPCC0_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dcn_dc_mpc_mpcc1_dispdec +// base address: 0x54 +#define regMPCC1_MPCC_TOP_SEL 0x0015 +#define regMPCC1_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC1_MPCC_BOT_SEL 0x0016 +#define regMPCC1_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC1_MPCC_OPP_ID 0x0017 +#define regMPCC1_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC1_MPCC_CONTROL 0x0018 +#define regMPCC1_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC1_MPCC_SM_CONTROL 0x0019 +#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC1_MPCC_UPDATE_LOCK_SEL 0x001a +#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC1_MPCC_TOP_GAIN 0x001b +#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC1_MPCC_BOT_GAIN_INSIDE 0x001c +#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x001d +#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x001e +#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 +#define regMPCC1_MPCC_BG_R_CR 0x001f +#define regMPCC1_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC1_MPCC_BG_G_Y 0x0020 +#define regMPCC1_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC1_MPCC_BG_B_CB 0x0021 +#define regMPCC1_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC1_MPCC_MEM_PWR_CTRL 0x0022 +#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC1_MPCC_STATUS 0x0023 +#define regMPCC1_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dcn_dc_mpc_mpcc2_dispdec +// base address: 0xa8 +#define regMPCC2_MPCC_TOP_SEL 0x002a +#define regMPCC2_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC2_MPCC_BOT_SEL 0x002b +#define regMPCC2_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC2_MPCC_OPP_ID 0x002c +#define regMPCC2_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC2_MPCC_CONTROL 0x002d +#define regMPCC2_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC2_MPCC_SM_CONTROL 0x002e +#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC2_MPCC_UPDATE_LOCK_SEL 0x002f +#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC2_MPCC_TOP_GAIN 0x0030 +#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC2_MPCC_BOT_GAIN_INSIDE 0x0031 +#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0032 +#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0033 +#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 +#define regMPCC2_MPCC_BG_R_CR 0x0034 +#define regMPCC2_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC2_MPCC_BG_G_Y 0x0035 +#define regMPCC2_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC2_MPCC_BG_B_CB 0x0036 +#define regMPCC2_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC2_MPCC_MEM_PWR_CTRL 0x0037 +#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC2_MPCC_STATUS 0x0038 +#define regMPCC2_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dcn_dc_mpc_mpcc3_dispdec +// base address: 0xfc +#define regMPCC3_MPCC_TOP_SEL 0x003f +#define regMPCC3_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC3_MPCC_BOT_SEL 0x0040 +#define regMPCC3_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC3_MPCC_OPP_ID 0x0041 +#define regMPCC3_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC3_MPCC_CONTROL 0x0042 +#define regMPCC3_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC3_MPCC_SM_CONTROL 0x0043 +#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC3_MPCC_UPDATE_LOCK_SEL 0x0044 +#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC3_MPCC_TOP_GAIN 0x0045 +#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC3_MPCC_BOT_GAIN_INSIDE 0x0046 +#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0047 +#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0048 +#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 +#define regMPCC3_MPCC_BG_R_CR 0x0049 +#define regMPCC3_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC3_MPCC_BG_G_Y 0x004a +#define regMPCC3_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC3_MPCC_BG_B_CB 0x004b +#define regMPCC3_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC3_MPCC_MEM_PWR_CTRL 0x004c +#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC3_MPCC_STATUS 0x004d +#define regMPCC3_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dcn_dc_mpc_mpc_cfg_dispdec +// base address: 0x0 +#define regMPC_CLOCK_CONTROL 0x0398 +#define regMPC_CLOCK_CONTROL_BASE_IDX 3 +#define regMPC_SOFT_RESET 0x0399 +#define regMPC_SOFT_RESET_BASE_IDX 3 +#define regMPC_CRC_CTRL 0x039a +#define regMPC_CRC_CTRL_BASE_IDX 3 +#define regMPC_CRC_SEL_CONTROL 0x039b +#define regMPC_CRC_SEL_CONTROL_BASE_IDX 3 +#define regMPC_CRC_RESULT_AR 0x039c +#define regMPC_CRC_RESULT_AR_BASE_IDX 3 +#define regMPC_CRC_RESULT_GB 0x039d +#define regMPC_CRC_RESULT_GB_BASE_IDX 3 +#define regMPC_CRC_RESULT_C 0x039e +#define regMPC_CRC_RESULT_C_BASE_IDX 3 +#define regMPC_BYPASS_BG_AR 0x03a2 +#define regMPC_BYPASS_BG_AR_BASE_IDX 3 +#define regMPC_BYPASS_BG_GB 0x03a3 +#define regMPC_BYPASS_BG_GB_BASE_IDX 3 +#define regMPC_HOST_READ_CONTROL 0x03a4 +#define regMPC_HOST_READ_CONTROL_BASE_IDX 3 +#define regMPC_DPP_PENDING_STATUS 0x03a5 +#define regMPC_DPP_PENDING_STATUS_BASE_IDX 3 +#define regMPC_PENDING_STATUS_MISC 0x03a6 +#define regMPC_PENDING_STATUS_MISC_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET0 0x03a7 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET0 0x03a8 +#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET0 0x03a9 +#define regADR_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET0 0x03aa +#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET0 0x03ab +#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET1 0x03ac +#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET1 0x03ad +#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET1 0x03ae +#define regADR_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET1 0x03af +#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET1 0x03b0 +#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET2 0x03b1 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET2 0x03b2 +#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET2 0x03b3 +#define regADR_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET2 0x03b4 +#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET2 0x03b5 +#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET3 0x03b6 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET3 0x03b7 +#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET3 0x03b8 +#define regADR_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET3 0x03b9 +#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET3 0x03ba +#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regMPC_DWB0_MUX 0x03c6 +#define regMPC_DWB0_MUX_BASE_IDX 3 + + +// addressBlock: dcn_dc_mpc_mpcc_ogam0_dispdec +// base address: 0x0 +#define regMPCC_OGAM0_MPCC_OGAM_CONTROL 0x00a8 +#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x00a9 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x00aa +#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x00ab +#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x00ac +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x00ad +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x00ae +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x00af +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x00b0 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x00b1 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x00b2 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x00b3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x00b4 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x00b5 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x00b6 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x00b7 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x00b8 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x00b9 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x00ba +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x00bb +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x00bc +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x00bd +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x00be +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x00bf +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x00c0 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x00c1 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x00c2 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x00c3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x00c4 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x00c5 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x00c6 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x00c7 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x00c8 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x00c9 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x00ca +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x00cb +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x00cc +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x00cd +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x00ce +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x00cf +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x00d0 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x00d1 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x00d2 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x00d3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x00d4 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x00d5 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x00d6 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x00d7 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x00d8 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x00d9 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x00da +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x00db +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x00dc +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x00dd +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x00de +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x00df +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x00e0 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x00e1 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x00e2 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x00e3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x00e4 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x00e5 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x00e6 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x00e7 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x00e8 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x00e9 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x00ea +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x00eb +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x00ec +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x00ed +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x00ee +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x00ef +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x00f0 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x00f1 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x00f2 +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x00f3 +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x00f4 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x00f5 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x00f6 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x00f7 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x00f8 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x00f9 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x00fa +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x00fb +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x00fc +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x00fd +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x00fe +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x00ff +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dcn_dc_mpc_mpcc_ogam1_dispdec +// base address: 0x178 +#define regMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0106 +#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0107 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0108 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0109 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x010a +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x010b +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x010c +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x010d +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x010e +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x010f +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x0110 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x0111 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x0112 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x0113 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x0114 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x0115 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0116 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0117 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0118 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0119 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x011a +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x011b +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x011c +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x011d +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x011e +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x011f +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x0120 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x0121 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x0122 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x0123 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x0124 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x0125 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x0126 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x0127 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x0128 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x0129 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x012a +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x012b +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x012c +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x012d +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x012e +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x012f +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x0130 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x0131 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0132 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0133 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x0134 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x0135 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x0136 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x0137 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x0138 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x0139 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x013a +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x013b +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x013c +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x013d +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x013e +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x013f +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x0140 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x0141 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x0142 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x0143 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x0144 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x0145 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x0146 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x0147 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x0148 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x0149 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x014a +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x014b +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x014c +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x014d +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x014e +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x014f +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x0150 +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x0151 +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x0152 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x0153 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x0154 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x0155 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x0156 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x0157 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x0158 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x0159 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x015a +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x015b +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x015c +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x015d +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dcn_dc_mpc_mpcc_ogam2_dispdec +// base address: 0x2f0 +#define regMPCC_OGAM2_MPCC_OGAM_CONTROL 0x0164 +#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x0165 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x0166 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x0167 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x0168 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x0169 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x016a +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x016b +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x016c +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x016d +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x016e +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x016f +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x0170 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x0171 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x0172 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x0173 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x0174 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x0175 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x0176 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x0177 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x0178 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x0179 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x017a +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x017b +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x017c +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x017d +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x017e +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x017f +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x0180 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x0181 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x0182 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x0183 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x0184 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x0185 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x0186 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x0187 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x0188 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x0189 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x018a +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x018b +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x018c +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x018d +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x018e +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x018f +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0190 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0191 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x0192 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x0193 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x0194 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x0195 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x0196 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x0197 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x0198 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x0199 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x019a +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x019b +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x019c +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x019d +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x019e +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x019f +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x01a0 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x01a1 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x01a2 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x01a3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x01a4 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x01a5 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x01a6 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x01a7 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x01a8 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x01a9 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x01aa +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x01ab +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x01ac +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x01ad +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ae +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x01af +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x01b0 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x01b1 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x01b2 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x01b3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x01b4 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x01b5 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x01b6 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x01b7 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x01b8 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x01b9 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x01ba +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x01bb +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dcn_dc_mpc_mpcc_ogam3_dispdec +// base address: 0x468 +#define regMPCC_OGAM3_MPCC_OGAM_CONTROL 0x01c2 +#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x01c3 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x01c4 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x01c5 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x01c6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x01c7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x01c8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x01c9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x01ca +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x01cb +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x01cc +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x01cd +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x01ce +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x01cf +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x01d0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x01d1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x01d2 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x01d3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x01d4 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x01d5 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x01d6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x01d7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x01d8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x01d9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x01da +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x01db +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x01dc +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x01dd +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x01de +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x01df +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x01e0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x01e1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x01e2 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x01e3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x01e4 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x01e5 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x01e6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x01e7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x01e8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x01e9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x01ea +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x01eb +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01ec +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ed +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ee +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ef +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01f0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01f1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x01f2 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x01f3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x01f4 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x01f5 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x01f6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x01f7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x01f8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x01f9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x01fa +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x01fb +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x01fc +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x01fd +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x01fe +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x01ff +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x0200 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x0201 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x0202 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x0203 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x0204 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x0205 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x0206 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x0207 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x0208 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x0209 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x020a +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x020b +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x020c +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x020d +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x020e +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x020f +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x0210 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x0211 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x0212 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x0213 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x0214 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x0215 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x0216 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x0217 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x0218 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x0219 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dcn_dc_mpc_mpcc_mcm0_dispdec +// base address: 0x0 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL 0x0453 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R 0x0454 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G 0x0455 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B 0x0456 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R 0x0457 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B 0x0458 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX 0x0459 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA 0x045a +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x045b +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x045c +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x045d +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x045e +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x045f +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0460 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0461 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0462 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0463 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0464 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0465 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0466 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0467 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0468 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0469 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x046a +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x046b +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x046c +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x046d +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x046e +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x046f +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0470 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0471 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0472 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0473 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0474 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0475 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0476 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0477 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0478 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0479 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x047a +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x047b +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x047c +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x047d +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x047e +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x047f +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0480 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0481 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0482 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0483 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0484 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0485 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0486 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0487 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0488 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0489 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE 0x048a +#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX 0x048b +#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA 0x048c +#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT 0x048d +#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x048e +#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x048f +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0490 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0491 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0492 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL 0x0493 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX 0x0494 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA 0x0495 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL 0x0496 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0497 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0498 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0499 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x049a +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x049b +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x049c +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x049d +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x049e +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x049f +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x04a0 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x04a1 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x04a2 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x04a3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x04a4 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x04a5 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x04a6 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x04a7 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x04a8 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x04a9 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x04aa +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x04ab +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x04ac +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x04ad +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x04ae +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x04af +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x04b0 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x04b1 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x04b2 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x04b3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x04b4 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x04b5 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x04b6 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x04b7 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x04b8 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x04b9 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x04ba +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x04bb +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x04bc +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x04bd +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x04be +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x04bf +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x04c0 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x04c1 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x04c2 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x04c3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x04c4 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x04c5 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x04c6 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x04c7 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x04c8 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x04c9 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x04ca +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x04cb +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x04cc +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x04cd +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x04ce +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x04cf +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x04d0 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x04d1 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x04d2 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x04d3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x04d4 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x04d5 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x04d6 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x04d7 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x04d8 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x04d9 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x04da +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x04db +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x04dc +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL 0x04dd +#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 + + +// addressBlock: dcn_dc_mpc_mpcc_mcm1_dispdec +// base address: 0x240 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL 0x04e3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R 0x04e4 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G 0x04e5 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B 0x04e6 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R 0x04e7 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B 0x04e8 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX 0x04e9 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA 0x04ea +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x04eb +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x04ec +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x04ed +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x04ee +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x04ef +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x04f0 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x04f1 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x04f2 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x04f3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x04f4 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x04f5 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x04f6 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x04f7 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x04f8 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x04f9 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x04fa +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x04fb +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x04fc +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x04fd +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x04fe +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x04ff +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0500 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0501 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0502 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0503 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0504 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0505 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0506 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0507 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0508 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0509 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x050a +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x050b +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x050c +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x050d +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x050e +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x050f +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0510 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0511 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0512 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0513 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0514 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0515 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0516 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0517 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0518 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0519 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE 0x051a +#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX 0x051b +#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA 0x051c +#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT 0x051d +#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x051e +#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x051f +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0520 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0521 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0522 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL 0x0523 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX 0x0524 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA 0x0525 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL 0x0526 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0527 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0528 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0529 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x052a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x052b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x052c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x052d +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x052e +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x052f +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0530 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0531 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0532 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0533 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0534 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0535 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0536 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0537 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0538 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0539 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x053a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x053b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x053c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x053d +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x053e +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x053f +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0540 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0541 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0542 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0543 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0544 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0545 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0546 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0547 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0548 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0549 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x054a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x054b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x054c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x054d +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x054e +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x054f +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0550 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0551 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0552 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0553 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0554 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0555 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0556 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0557 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0558 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0559 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x055a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x055b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x055c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x055d +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x055e +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x055f +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0560 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0561 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0562 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0563 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0564 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0565 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0566 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0567 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0568 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0569 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x056a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x056b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x056c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL 0x056d +#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 + + +// addressBlock: dcn_dc_mpc_mpcc_mcm2_dispdec +// base address: 0x480 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL 0x0573 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R 0x0574 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G 0x0575 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B 0x0576 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R 0x0577 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B 0x0578 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX 0x0579 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA 0x057a +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x057b +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x057c +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x057d +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x057e +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x057f +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0580 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0581 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0582 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0583 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0584 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0585 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0586 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0587 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0588 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0589 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x058a +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x058b +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x058c +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x058d +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x058e +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x058f +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0590 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0591 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0592 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0593 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0594 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0595 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0596 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0597 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0598 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0599 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x059a +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x059b +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x059c +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x059d +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x059e +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x059f +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x05a0 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x05a1 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x05a2 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x05a3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x05a4 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x05a5 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x05a6 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x05a7 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x05a8 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x05a9 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE 0x05aa +#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX 0x05ab +#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA 0x05ac +#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT 0x05ad +#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x05ae +#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x05af +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x05b0 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x05b1 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x05b2 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL 0x05b3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX 0x05b4 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA 0x05b5 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL 0x05b6 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x05b7 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x05b8 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x05b9 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x05ba +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x05bb +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x05bc +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x05bd +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x05be +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x05bf +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x05c0 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x05c1 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x05c2 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x05c3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x05c4 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x05c5 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x05c6 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x05c7 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x05c8 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x05c9 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x05ca +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x05cb +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x05cc +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x05cd +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x05ce +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x05cf +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x05d0 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x05d1 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x05d2 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x05d3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x05d4 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x05d5 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x05d6 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x05d7 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x05d8 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x05d9 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x05da +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x05db +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x05dc +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x05dd +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x05de +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x05df +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x05e0 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x05e1 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x05e2 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x05e3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x05e4 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x05e5 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x05e6 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x05e7 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x05e8 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x05e9 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x05ea +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x05eb +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x05ec +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x05ed +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x05ee +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x05ef +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x05f0 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x05f1 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x05f2 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x05f3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x05f4 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x05f5 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x05f6 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x05f7 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x05f8 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x05f9 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x05fa +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x05fb +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x05fc +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL 0x05fd +#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 + + +// addressBlock: dcn_dc_mpc_mpcc_mcm3_dispdec +// base address: 0x6c0 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL 0x0603 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R 0x0604 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G 0x0605 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B 0x0606 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R 0x0607 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B 0x0608 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX 0x0609 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA 0x060a +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x060b +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x060c +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x060d +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x060e +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x060f +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0610 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0611 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0612 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0613 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0614 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0615 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0616 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0617 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0618 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0619 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x061a +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x061b +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x061c +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x061d +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x061e +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x061f +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0620 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0621 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0622 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0623 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0624 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0625 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0626 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0627 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0628 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0629 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x062a +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x062b +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x062c +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x062d +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x062e +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x062f +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0630 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0631 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0632 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0633 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0634 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0635 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0636 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0637 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0638 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0639 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE 0x063a +#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX 0x063b +#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA 0x063c +#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT 0x063d +#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x063e +#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x063f +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0640 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0641 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0642 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL 0x0643 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX 0x0644 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA 0x0645 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL 0x0646 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0647 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0648 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0649 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x064a +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x064b +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x064c +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x064d +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x064e +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x064f +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0650 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0651 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0652 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0653 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0654 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0655 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0656 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0657 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0658 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0659 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x065a +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x065b +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x065c +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x065d +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x065e +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x065f +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0660 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0661 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0662 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0663 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0664 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0665 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0666 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0667 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0668 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0669 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x066a +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x066b +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x066c +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x066d +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x066e +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x066f +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0670 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0671 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0672 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0673 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0674 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0675 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0676 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0677 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0678 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0679 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x067a +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x067b +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x067c +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x067d +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x067e +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x067f +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0680 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0681 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0682 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0683 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0684 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0685 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0686 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0687 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0688 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0689 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x068a +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x068b +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x068c +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL 0x068d +#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 + + +// addressBlock: dcn_dc_mpc_mpc_ocsc_dispdec +// base address: 0x0 +#define regMPC_OUT0_MUX 0x03d8 +#define regMPC_OUT0_MUX_BASE_IDX 3 +#define regMPC_OUT0_DENORM_CONTROL 0x03d9 +#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT0_DENORM_CLAMP_G_Y 0x03da +#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT0_DENORM_CLAMP_B_CB 0x03db +#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT1_MUX 0x03dc +#define regMPC_OUT1_MUX_BASE_IDX 3 +#define regMPC_OUT1_DENORM_CONTROL 0x03dd +#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT1_DENORM_CLAMP_G_Y 0x03de +#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT1_DENORM_CLAMP_B_CB 0x03df +#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT2_MUX 0x03e0 +#define regMPC_OUT2_MUX_BASE_IDX 3 +#define regMPC_OUT2_DENORM_CONTROL 0x03e1 +#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT2_DENORM_CLAMP_G_Y 0x03e2 +#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT2_DENORM_CLAMP_B_CB 0x03e3 +#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT3_MUX 0x03e4 +#define regMPC_OUT3_MUX_BASE_IDX 3 +#define regMPC_OUT3_DENORM_CONTROL 0x03e5 +#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT3_DENORM_CLAMP_G_Y 0x03e6 +#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT3_DENORM_CLAMP_B_CB 0x03e7 +#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT_CSC_COEF_FORMAT 0x03f0 +#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 +#define regMPC_OUT0_CSC_MODE 0x03f1 +#define regMPC_OUT0_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT0_CSC_C11_C12_A 0x03f2 +#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C13_C14_A 0x03f3 +#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C21_C22_A 0x03f4 +#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C23_C24_A 0x03f5 +#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C31_C32_A 0x03f6 +#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C33_C34_A 0x03f7 +#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C11_C12_B 0x03f8 +#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C13_C14_B 0x03f9 +#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C21_C22_B 0x03fa +#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C23_C24_B 0x03fb +#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C31_C32_B 0x03fc +#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C33_C34_B 0x03fd +#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_MODE 0x03fe +#define regMPC_OUT1_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT1_CSC_C11_C12_A 0x03ff +#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C13_C14_A 0x0400 +#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C21_C22_A 0x0401 +#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C23_C24_A 0x0402 +#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C31_C32_A 0x0403 +#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C33_C34_A 0x0404 +#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C11_C12_B 0x0405 +#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C13_C14_B 0x0406 +#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C21_C22_B 0x0407 +#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C23_C24_B 0x0408 +#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C31_C32_B 0x0409 +#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C33_C34_B 0x040a +#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_MODE 0x040b +#define regMPC_OUT2_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT2_CSC_C11_C12_A 0x040c +#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C13_C14_A 0x040d +#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C21_C22_A 0x040e +#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C23_C24_A 0x040f +#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C31_C32_A 0x0410 +#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C33_C34_A 0x0411 +#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C11_C12_B 0x0412 +#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C13_C14_B 0x0413 +#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C21_C22_B 0x0414 +#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C23_C24_B 0x0415 +#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C31_C32_B 0x0416 +#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C33_C34_B 0x0417 +#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_MODE 0x0418 +#define regMPC_OUT3_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT3_CSC_C11_C12_A 0x0419 +#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C13_C14_A 0x041a +#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C21_C22_A 0x041b +#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C23_C24_A 0x041c +#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C31_C32_A 0x041d +#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C33_C34_A 0x041e +#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C11_C12_B 0x041f +#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C13_C14_B 0x0420 +#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C21_C22_B 0x0421 +#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C23_C24_B 0x0422 +#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C31_C32_B 0x0423 +#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C33_C34_B 0x0424 +#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dcn_dc_opp_abm0_dispdec +// base address: 0x0 +#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a +#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_USER_LEVEL 0x0e7b +#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c +#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d +#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e +#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f +#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM0_BL1_PWM_ABM_CNTL 0x0e80 +#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 +#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82 +#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 +#define regABM0_DC_ABM1_CNTL 0x0e83 +#define regABM0_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84 +#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_THRES_12 0x0e8a +#define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_THRES_34 0x0e8b +#define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c +#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e +#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f +#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90 +#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91 +#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92 +#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93 +#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94 +#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95 +#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96 +#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97 +#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98 +#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99 +#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a +#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b +#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c +#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d +#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_1 0x0e9e +#define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_2 0x0e9f +#define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_3 0x0ea0 +#define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_4 0x0ea1 +#define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_5 0x0ea2 +#define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_6 0x0ea3 +#define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_7 0x0ea4 +#define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_8 0x0ea5 +#define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_9 0x0ea6 +#define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_10 0x0ea7 +#define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_11 0x0ea8 +#define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_12 0x0ea9 +#define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_13 0x0eaa +#define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_14 0x0eab +#define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_15 0x0eac +#define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_16 0x0ead +#define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_17 0x0eae +#define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_18 0x0eaf +#define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_19 0x0eb0 +#define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_20 0x0eb1 +#define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_21 0x0eb2 +#define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_22 0x0eb3 +#define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_23 0x0eb4 +#define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_24 0x0eb5 +#define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3 +#define regABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6 +#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dcn_dc_opp_abm1_dispdec +// base address: 0x104 +#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb +#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_USER_LEVEL 0x0ebc +#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd +#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe +#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf +#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 +#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM1_BL1_PWM_ABM_CNTL 0x0ec1 +#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 +#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3 +#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 +#define regABM1_DC_ABM1_CNTL 0x0ec4 +#define regABM1_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5 +#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_THRES_12 0x0ecb +#define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_THRES_34 0x0ecc +#define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd +#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf +#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0 +#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1 +#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2 +#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3 +#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4 +#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5 +#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6 +#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7 +#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8 +#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9 +#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda +#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb +#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc +#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd +#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede +#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_1 0x0edf +#define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_2 0x0ee0 +#define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_3 0x0ee1 +#define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_4 0x0ee2 +#define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_5 0x0ee3 +#define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_6 0x0ee4 +#define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_7 0x0ee5 +#define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_8 0x0ee6 +#define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_9 0x0ee7 +#define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_10 0x0ee8 +#define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_11 0x0ee9 +#define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_12 0x0eea +#define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_13 0x0eeb +#define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_14 0x0eec +#define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_15 0x0eed +#define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_16 0x0eee +#define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_17 0x0eef +#define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_18 0x0ef0 +#define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_19 0x0ef1 +#define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_20 0x0ef2 +#define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_21 0x0ef3 +#define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_22 0x0ef4 +#define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_23 0x0ef5 +#define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_24 0x0ef6 +#define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3 +#define regABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7 +#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dcn_dc_opp_abm2_dispdec +// base address: 0x208 +#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc +#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_USER_LEVEL 0x0efd +#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe +#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff +#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00 +#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01 +#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM2_BL1_PWM_ABM_CNTL 0x0f02 +#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03 +#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04 +#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 +#define regABM2_DC_ABM1_CNTL 0x0f05 +#define regABM2_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06 +#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f07 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f08 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f09 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f0a +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f0b +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_THRES_12 0x0f0c +#define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_THRES_34 0x0f0d +#define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0e +#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f10 +#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_MISC_CTRL 0x0f11 +#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f12 +#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f13 +#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f14 +#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f15 +#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f16 +#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f17 +#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f18 +#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f19 +#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f1a +#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f1b +#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f1c +#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1d +#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1e +#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1f +#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_1 0x0f20 +#define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_2 0x0f21 +#define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_3 0x0f22 +#define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_4 0x0f23 +#define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_5 0x0f24 +#define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_6 0x0f25 +#define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_7 0x0f26 +#define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_8 0x0f27 +#define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_9 0x0f28 +#define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_10 0x0f29 +#define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_11 0x0f2a +#define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_12 0x0f2b +#define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_13 0x0f2c +#define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_14 0x0f2d +#define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_15 0x0f2e +#define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_16 0x0f2f +#define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_17 0x0f30 +#define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_18 0x0f31 +#define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_19 0x0f32 +#define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_20 0x0f33 +#define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_21 0x0f34 +#define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_22 0x0f35 +#define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_23 0x0f36 +#define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_24 0x0f37 +#define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX 3 +#define regABM2_DC_ABM1_BL_MASTER_LOCK 0x0f38 +#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dcn_dc_opp_abm3_dispdec +// base address: 0x30c +#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d +#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_USER_LEVEL 0x0f3e +#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f +#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40 +#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41 +#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42 +#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM3_BL1_PWM_ABM_CNTL 0x0f43 +#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44 +#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45 +#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 +#define regABM3_DC_ABM1_CNTL 0x0f46 +#define regABM3_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47 +#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f48 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f49 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f4a +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f4b +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f4c +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_THRES_12 0x0f4d +#define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_THRES_34 0x0f4e +#define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4f +#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f51 +#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_MISC_CTRL 0x0f52 +#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f53 +#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f54 +#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f55 +#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f56 +#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f57 +#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f58 +#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f59 +#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f5a +#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f5b +#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f5c +#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5d +#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5e +#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5f +#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f60 +#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_1 0x0f61 +#define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_2 0x0f62 +#define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_3 0x0f63 +#define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_4 0x0f64 +#define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_5 0x0f65 +#define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_6 0x0f66 +#define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_7 0x0f67 +#define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_8 0x0f68 +#define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_9 0x0f69 +#define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_10 0x0f6a +#define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_11 0x0f6b +#define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_12 0x0f6c +#define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_13 0x0f6d +#define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_14 0x0f6e +#define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_15 0x0f6f +#define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_16 0x0f70 +#define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_17 0x0f71 +#define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_18 0x0f72 +#define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_19 0x0f73 +#define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_20 0x0f74 +#define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_21 0x0f75 +#define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_22 0x0f76 +#define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_23 0x0f77 +#define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_24 0x0f78 +#define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX 3 +#define regABM3_DC_ABM1_BL_MASTER_LOCK 0x0f79 +#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dcn_dc_opp_dpg0_dispdec +// base address: 0x0 +#define regDPG0_DPG_CONTROL 0x1854 +#define regDPG0_DPG_CONTROL_BASE_IDX 2 +#define regDPG0_DPG_RAMP_CONTROL 0x1855 +#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG0_DPG_DIMENSIONS 0x1856 +#define regDPG0_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG0_DPG_COLOUR_R_CR 0x1857 +#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG0_DPG_COLOUR_G_Y 0x1858 +#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG0_DPG_COLOUR_B_CB 0x1859 +#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG0_DPG_OFFSET_SEGMENT 0x185a +#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG0_DPG_STATUS 0x185b +#define regDPG0_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_fmt0_dispdec +// base address: 0x0 +#define regFMT0_FMT_CLAMP_COMPONENT_R 0x183c +#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT0_FMT_CLAMP_COMPONENT_G 0x183d +#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT0_FMT_CLAMP_COMPONENT_B 0x183e +#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f +#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT0_FMT_CONTROL 0x1840 +#define regFMT0_FMT_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 +#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_DITHER_RAND_R_SEED 0x1842 +#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT0_FMT_DITHER_RAND_G_SEED 0x1843 +#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT0_FMT_DITHER_RAND_B_SEED 0x1844 +#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT0_FMT_CLAMP_CNTL 0x1845 +#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 +#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 +#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_422_CONTROL 0x1849 +#define regFMT0_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_oppbuf0_dispdec +// base address: 0x0 +#define regOPPBUF0_OPPBUF_CONTROL 0x1884 +#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF0_OPPBUF_CONTROL1 0x1889 +#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_opp_pipe0_dispdec +// base address: 0x0 +#define regOPP_PIPE0_OPP_PIPE_CONTROL 0x188c +#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_opp_pipe_crc0_dispdec +// base address: 0x0 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_dpg1_dispdec +// base address: 0x168 +#define regDPG1_DPG_CONTROL 0x18ae +#define regDPG1_DPG_CONTROL_BASE_IDX 2 +#define regDPG1_DPG_RAMP_CONTROL 0x18af +#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG1_DPG_DIMENSIONS 0x18b0 +#define regDPG1_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG1_DPG_COLOUR_R_CR 0x18b1 +#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG1_DPG_COLOUR_G_Y 0x18b2 +#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG1_DPG_COLOUR_B_CB 0x18b3 +#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG1_DPG_OFFSET_SEGMENT 0x18b4 +#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG1_DPG_STATUS 0x18b5 +#define regDPG1_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_fmt1_dispdec +// base address: 0x168 +#define regFMT1_FMT_CLAMP_COMPONENT_R 0x1896 +#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT1_FMT_CLAMP_COMPONENT_G 0x1897 +#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT1_FMT_CLAMP_COMPONENT_B 0x1898 +#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 +#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT1_FMT_CONTROL 0x189a +#define regFMT1_FMT_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_BIT_DEPTH_CONTROL 0x189b +#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_DITHER_RAND_R_SEED 0x189c +#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT1_FMT_DITHER_RAND_G_SEED 0x189d +#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT1_FMT_DITHER_RAND_B_SEED 0x189e +#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT1_FMT_CLAMP_CNTL 0x189f +#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 +#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 +#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_422_CONTROL 0x18a3 +#define regFMT1_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_oppbuf1_dispdec +// base address: 0x168 +#define regOPPBUF1_OPPBUF_CONTROL 0x18de +#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF1_OPPBUF_CONTROL1 0x18e3 +#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_opp_pipe1_dispdec +// base address: 0x168 +#define regOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 +#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_opp_pipe_crc1_dispdec +// base address: 0x168 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_dpg2_dispdec +// base address: 0x2d0 +#define regDPG2_DPG_CONTROL 0x1908 +#define regDPG2_DPG_CONTROL_BASE_IDX 2 +#define regDPG2_DPG_RAMP_CONTROL 0x1909 +#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG2_DPG_DIMENSIONS 0x190a +#define regDPG2_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG2_DPG_COLOUR_R_CR 0x190b +#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG2_DPG_COLOUR_G_Y 0x190c +#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG2_DPG_COLOUR_B_CB 0x190d +#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG2_DPG_OFFSET_SEGMENT 0x190e +#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG2_DPG_STATUS 0x190f +#define regDPG2_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_fmt2_dispdec +// base address: 0x2d0 +#define regFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 +#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 +#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 +#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 +#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT2_FMT_CONTROL 0x18f4 +#define regFMT2_FMT_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 +#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 +#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 +#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 +#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT2_FMT_CLAMP_CNTL 0x18f9 +#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa +#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb +#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_422_CONTROL 0x18fd +#define regFMT2_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_oppbuf2_dispdec +// base address: 0x2d0 +#define regOPPBUF2_OPPBUF_CONTROL 0x1938 +#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF2_OPPBUF_CONTROL1 0x193d +#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_opp_pipe2_dispdec +// base address: 0x2d0 +#define regOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 +#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_opp_pipe_crc2_dispdec +// base address: 0x2d0 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_dpg3_dispdec +// base address: 0x438 +#define regDPG3_DPG_CONTROL 0x1962 +#define regDPG3_DPG_CONTROL_BASE_IDX 2 +#define regDPG3_DPG_RAMP_CONTROL 0x1963 +#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG3_DPG_DIMENSIONS 0x1964 +#define regDPG3_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG3_DPG_COLOUR_R_CR 0x1965 +#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG3_DPG_COLOUR_G_Y 0x1966 +#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG3_DPG_COLOUR_B_CB 0x1967 +#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG3_DPG_OFFSET_SEGMENT 0x1968 +#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG3_DPG_STATUS 0x1969 +#define regDPG3_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_fmt3_dispdec +// base address: 0x438 +#define regFMT3_FMT_CLAMP_COMPONENT_R 0x194a +#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT3_FMT_CLAMP_COMPONENT_G 0x194b +#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT3_FMT_CLAMP_COMPONENT_B 0x194c +#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d +#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT3_FMT_CONTROL 0x194e +#define regFMT3_FMT_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_BIT_DEPTH_CONTROL 0x194f +#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_DITHER_RAND_R_SEED 0x1950 +#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT3_FMT_DITHER_RAND_G_SEED 0x1951 +#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT3_FMT_DITHER_RAND_B_SEED 0x1952 +#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT3_FMT_CLAMP_CNTL 0x1953 +#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 +#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 +#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_422_CONTROL 0x1957 +#define regFMT3_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_oppbuf3_dispdec +// base address: 0x438 +#define regOPPBUF3_OPPBUF_CONTROL 0x1992 +#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF3_OPPBUF_CONTROL1 0x1997 +#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_opp_pipe3_dispdec +// base address: 0x438 +#define regOPP_PIPE3_OPP_PIPE_CONTROL 0x199a +#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_opp_pipe_crc3_dispdec +// base address: 0x438 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_dscrm0_dispdec +// base address: 0x0 +#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 +#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_dscrm1_dispdec +// base address: 0x4 +#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 +#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_dscrm2_dispdec +// base address: 0x8 +#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 +#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_dscrm3_dispdec +// base address: 0xc +#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67 +#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dcn_dc_opp_opp_top_dispdec +// base address: 0x0 +#define regOPP_TOP_CLK_CONTROL 0x1a5e +#define regOPP_TOP_CLK_CONTROL_BASE_IDX 2 +#define regOPP_ABM_CONTROL 0x1a60 +#define regOPP_ABM_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_optc_odm0_dispdec +// base address: 0x0 +#define regODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca +#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_DATA_SOURCE_SELECT 0x1acb +#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc +#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_BYTES_PER_PIXEL 0x1acd +#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM0_OPTC_WIDTH_CONTROL 0x1ace +#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf +#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_MEMORY_CONFIG 0x1ad0 +#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 +#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dcn_dc_optc_odm1_dispdec +// base address: 0x40 +#define regODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada +#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_DATA_SOURCE_SELECT 0x1adb +#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc +#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_BYTES_PER_PIXEL 0x1add +#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM1_OPTC_WIDTH_CONTROL 0x1ade +#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf +#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_MEMORY_CONFIG 0x1ae0 +#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 +#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dcn_dc_optc_odm2_dispdec +// base address: 0x80 +#define regODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea +#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb +#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec +#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_BYTES_PER_PIXEL 0x1aed +#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM2_OPTC_WIDTH_CONTROL 0x1aee +#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef +#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_MEMORY_CONFIG 0x1af0 +#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1 +#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dcn_dc_optc_odm3_dispdec +// base address: 0xc0 +#define regODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa +#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_DATA_SOURCE_SELECT 0x1afb +#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc +#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_BYTES_PER_PIXEL 0x1afd +#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM3_OPTC_WIDTH_CONTROL 0x1afe +#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff +#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_MEMORY_CONFIG 0x1b00 +#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01 +#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dcn_dc_optc_otg0_dispdec +// base address: 0x0 +#define regOTG0_OTG_H_TOTAL 0x1b2a +#define regOTG0_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG0_OTG_H_BLANK_START_END 0x1b2b +#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG0_OTG_H_SYNC_A 0x1b2c +#define regOTG0_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG0_OTG_H_SYNC_A_CNTL 0x1b2d +#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG0_OTG_H_TIMING_CNTL 0x1b2e +#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL 0x1b2f +#define regOTG0_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_MIN 0x1b30 +#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_MAX 0x1b31 +#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_MID 0x1b32 +#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_CONTROL 0x1b33 +#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 +#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 +#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_V_BLANK_START_END 0x1b36 +#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG0_OTG_V_SYNC_A 0x1b37 +#define regOTG0_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG0_OTG_V_SYNC_A_CNTL 0x1b38 +#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG0_OTG_TRIGA_CNTL 0x1b39 +#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a +#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG0_OTG_TRIGB_CNTL 0x1b3b +#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c +#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d +#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG0_OTG_FLOW_CONTROL 0x1b3e +#define regOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f +#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG0_OTG_CONTROL 0x1b41 +#define regOTG0_OTG_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_INTERLACE_CONTROL 0x1b44 +#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_INTERLACE_STATUS 0x1b45 +#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 +#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 +#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG0_OTG_STATUS 0x1b49 +#define regOTG0_OTG_STATUS_BASE_IDX 2 +#define regOTG0_OTG_STATUS_POSITION 0x1b4a +#define regOTG0_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG0_OTG_NOM_VERT_POSITION 0x1b4b +#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c +#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG0_OTG_STATUS_VF_COUNT 0x1b4d +#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG0_OTG_STATUS_HV_COUNT 0x1b4e +#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG0_OTG_COUNT_CONTROL 0x1b4f +#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_COUNT_RESET 0x1b50 +#define regOTG0_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 +#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 +#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_STEREO_STATUS 0x1b53 +#define regOTG0_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG0_OTG_STEREO_CONTROL 0x1b54 +#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_STATUS 0x1b55 +#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 +#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_POSITION 0x1b57 +#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_FRAME 0x1b58 +#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG0_OTG_INTERRUPT_CONTROL 0x1b59 +#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_UPDATE_LOCK 0x1b5a +#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b +#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_MASTER_EN 0x1b5c +#define regOTG0_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC_CNTL 0x1b68 +#define regOTG0_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b69 +#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6a +#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6b +#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6c +#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_DATA_RG 0x1b6d +#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define regOTG0_OTG_CRC0_DATA_B 0x1b6e +#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b6f +#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b70 +#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b71 +#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b72 +#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_DATA_RG 0x1b73 +#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define regOTG0_OTG_CRC1_DATA_B 0x1b74 +#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC2_DATA_RG 0x1b75 +#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define regOTG0_OTG_CRC2_DATA_B 0x1b76 +#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC3_DATA_RG 0x1b77 +#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define regOTG0_OTG_CRC3_DATA_B 0x1b78 +#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b79 +#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7a +#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b81 +#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b82 +#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_GSL_VSYNC_GAP 0x1b83 +#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG0_OTG_MASTER_UPDATE_MODE 0x1b84 +#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG0_OTG_CLOCK_CONTROL 0x1b85 +#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_VSTARTUP_PARAM 0x1b86 +#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG0_OTG_VUPDATE_PARAM 0x1b87 +#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG0_OTG_VREADY_PARAM 0x1b88 +#define regOTG0_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b89 +#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8a +#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG0_OTG_GSL_CONTROL 0x1b8b +#define regOTG0_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_GSL_WINDOW_X 0x1b8c +#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG0_OTG_GSL_WINDOW_Y 0x1b8d +#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG0_OTG_VUPDATE_KEEPOUT 0x1b8e +#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL0 0x1b8f +#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL1 0x1b90 +#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL2 0x1b91 +#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL3 0x1b92 +#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL4 0x1b93 +#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b94 +#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b95 +#define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b96 +#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b97 +#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b98 +#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b99 +#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG0_OTG_DRR_CONTROL 0x1b9a +#define regOTG0_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_M_CONST_DTO0 0x1b9b +#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG0_OTG_M_CONST_DTO1 0x1b9c +#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG0_OTG_REQUEST_CONTROL 0x1b9d +#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_DSC_START_POSITION 0x1b9e +#define regOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 +#define regOTG0_OTG_PIPE_UPDATE_STATUS 0x1b9f +#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG0_OTG_SPARE_REGISTER 0x1ba1 +#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dcn_dc_optc_otg1_dispdec +// base address: 0x200 +#define regOTG1_OTG_H_TOTAL 0x1baa +#define regOTG1_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG1_OTG_H_BLANK_START_END 0x1bab +#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG1_OTG_H_SYNC_A 0x1bac +#define regOTG1_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG1_OTG_H_SYNC_A_CNTL 0x1bad +#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG1_OTG_H_TIMING_CNTL 0x1bae +#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL 0x1baf +#define regOTG1_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_MIN 0x1bb0 +#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_MAX 0x1bb1 +#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_MID 0x1bb2 +#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 +#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 +#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 +#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_V_BLANK_START_END 0x1bb6 +#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG1_OTG_V_SYNC_A 0x1bb7 +#define regOTG1_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 +#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG1_OTG_TRIGA_CNTL 0x1bb9 +#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba +#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG1_OTG_TRIGB_CNTL 0x1bbb +#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc +#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd +#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG1_OTG_FLOW_CONTROL 0x1bbe +#define regOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf +#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG1_OTG_CONTROL 0x1bc1 +#define regOTG1_OTG_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_INTERLACE_CONTROL 0x1bc4 +#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_INTERLACE_STATUS 0x1bc5 +#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 +#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 +#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG1_OTG_STATUS 0x1bc9 +#define regOTG1_OTG_STATUS_BASE_IDX 2 +#define regOTG1_OTG_STATUS_POSITION 0x1bca +#define regOTG1_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG1_OTG_NOM_VERT_POSITION 0x1bcb +#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc +#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG1_OTG_STATUS_VF_COUNT 0x1bcd +#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG1_OTG_STATUS_HV_COUNT 0x1bce +#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG1_OTG_COUNT_CONTROL 0x1bcf +#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_COUNT_RESET 0x1bd0 +#define regOTG1_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 +#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 +#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_STEREO_STATUS 0x1bd3 +#define regOTG1_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG1_OTG_STEREO_CONTROL 0x1bd4 +#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 +#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 +#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 +#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 +#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG1_OTG_INTERRUPT_CONTROL 0x1bd9 +#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_UPDATE_LOCK 0x1bda +#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb +#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_MASTER_EN 0x1bdc +#define regOTG1_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4 +#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5 +#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6 +#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7 +#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC_CNTL 0x1be8 +#define regOTG1_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1be9 +#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1bea +#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1beb +#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bec +#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_DATA_RG 0x1bed +#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define regOTG1_OTG_CRC0_DATA_B 0x1bee +#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bef +#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf0 +#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf1 +#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf2 +#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_DATA_RG 0x1bf3 +#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define regOTG1_OTG_CRC1_DATA_B 0x1bf4 +#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC2_DATA_RG 0x1bf5 +#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define regOTG1_OTG_CRC2_DATA_B 0x1bf6 +#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC3_DATA_RG 0x1bf7 +#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define regOTG1_OTG_CRC3_DATA_B 0x1bf8 +#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bf9 +#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfa +#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c01 +#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c02 +#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_GSL_VSYNC_GAP 0x1c03 +#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG1_OTG_MASTER_UPDATE_MODE 0x1c04 +#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG1_OTG_CLOCK_CONTROL 0x1c05 +#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_VSTARTUP_PARAM 0x1c06 +#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG1_OTG_VUPDATE_PARAM 0x1c07 +#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG1_OTG_VREADY_PARAM 0x1c08 +#define regOTG1_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c09 +#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0a +#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG1_OTG_GSL_CONTROL 0x1c0b +#define regOTG1_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_GSL_WINDOW_X 0x1c0c +#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG1_OTG_GSL_WINDOW_Y 0x1c0d +#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG1_OTG_VUPDATE_KEEPOUT 0x1c0e +#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL0 0x1c0f +#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL1 0x1c10 +#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL2 0x1c11 +#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL3 0x1c12 +#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL4 0x1c13 +#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c14 +#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c15 +#define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c16 +#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c17 +#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c18 +#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c19 +#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG1_OTG_DRR_CONTROL 0x1c1a +#define regOTG1_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_M_CONST_DTO0 0x1c1b +#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG1_OTG_M_CONST_DTO1 0x1c1c +#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG1_OTG_REQUEST_CONTROL 0x1c1d +#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_DSC_START_POSITION 0x1c1e +#define regOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 +#define regOTG1_OTG_PIPE_UPDATE_STATUS 0x1c1f +#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG1_OTG_SPARE_REGISTER 0x1c21 +#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dcn_dc_optc_otg2_dispdec +// base address: 0x400 +#define regOTG2_OTG_H_TOTAL 0x1c2a +#define regOTG2_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG2_OTG_H_BLANK_START_END 0x1c2b +#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG2_OTG_H_SYNC_A 0x1c2c +#define regOTG2_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG2_OTG_H_SYNC_A_CNTL 0x1c2d +#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG2_OTG_H_TIMING_CNTL 0x1c2e +#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL 0x1c2f +#define regOTG2_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_MIN 0x1c30 +#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_MAX 0x1c31 +#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_MID 0x1c32 +#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_CONTROL 0x1c33 +#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34 +#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35 +#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_V_BLANK_START_END 0x1c36 +#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG2_OTG_V_SYNC_A 0x1c37 +#define regOTG2_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG2_OTG_V_SYNC_A_CNTL 0x1c38 +#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG2_OTG_TRIGA_CNTL 0x1c39 +#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a +#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG2_OTG_TRIGB_CNTL 0x1c3b +#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c +#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d +#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG2_OTG_FLOW_CONTROL 0x1c3e +#define regOTG2_OTG_FLOW_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f +#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG2_OTG_CONTROL 0x1c41 +#define regOTG2_OTG_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_INTERLACE_CONTROL 0x1c44 +#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_INTERLACE_STATUS 0x1c45 +#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 +#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 +#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG2_OTG_STATUS 0x1c49 +#define regOTG2_OTG_STATUS_BASE_IDX 2 +#define regOTG2_OTG_STATUS_POSITION 0x1c4a +#define regOTG2_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG2_OTG_NOM_VERT_POSITION 0x1c4b +#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c +#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG2_OTG_STATUS_VF_COUNT 0x1c4d +#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG2_OTG_STATUS_HV_COUNT 0x1c4e +#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG2_OTG_COUNT_CONTROL 0x1c4f +#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_COUNT_RESET 0x1c50 +#define regOTG2_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51 +#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG2_OTG_VERT_SYNC_CONTROL 0x1c52 +#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_STEREO_STATUS 0x1c53 +#define regOTG2_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG2_OTG_STEREO_CONTROL 0x1c54 +#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_STATUS 0x1c55 +#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_CONTROL 0x1c56 +#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_POSITION 0x1c57 +#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_FRAME 0x1c58 +#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG2_OTG_INTERRUPT_CONTROL 0x1c59 +#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_UPDATE_LOCK 0x1c5a +#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b +#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_MASTER_EN 0x1c5c +#define regOTG2_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC_CNTL 0x1c68 +#define regOTG2_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c69 +#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6a +#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6b +#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6c +#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_DATA_RG 0x1c6d +#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define regOTG2_OTG_CRC0_DATA_B 0x1c6e +#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c6f +#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c70 +#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c71 +#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c72 +#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_DATA_RG 0x1c73 +#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define regOTG2_OTG_CRC1_DATA_B 0x1c74 +#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC2_DATA_RG 0x1c75 +#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define regOTG2_OTG_CRC2_DATA_B 0x1c76 +#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC3_DATA_RG 0x1c77 +#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define regOTG2_OTG_CRC3_DATA_B 0x1c78 +#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c79 +#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7a +#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c81 +#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c82 +#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_GSL_VSYNC_GAP 0x1c83 +#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG2_OTG_MASTER_UPDATE_MODE 0x1c84 +#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG2_OTG_CLOCK_CONTROL 0x1c85 +#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_VSTARTUP_PARAM 0x1c86 +#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG2_OTG_VUPDATE_PARAM 0x1c87 +#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG2_OTG_VREADY_PARAM 0x1c88 +#define regOTG2_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c89 +#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8a +#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG2_OTG_GSL_CONTROL 0x1c8b +#define regOTG2_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_GSL_WINDOW_X 0x1c8c +#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG2_OTG_GSL_WINDOW_Y 0x1c8d +#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG2_OTG_VUPDATE_KEEPOUT 0x1c8e +#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL0 0x1c8f +#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL1 0x1c90 +#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL2 0x1c91 +#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL3 0x1c92 +#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL4 0x1c93 +#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c94 +#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c95 +#define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c96 +#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c97 +#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c98 +#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c99 +#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG2_OTG_DRR_CONTROL 0x1c9a +#define regOTG2_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_M_CONST_DTO0 0x1c9b +#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG2_OTG_M_CONST_DTO1 0x1c9c +#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG2_OTG_REQUEST_CONTROL 0x1c9d +#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_DSC_START_POSITION 0x1c9e +#define regOTG2_OTG_DSC_START_POSITION_BASE_IDX 2 +#define regOTG2_OTG_PIPE_UPDATE_STATUS 0x1c9f +#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG2_OTG_SPARE_REGISTER 0x1ca1 +#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dcn_dc_optc_otg3_dispdec +// base address: 0x600 +#define regOTG3_OTG_H_TOTAL 0x1caa +#define regOTG3_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG3_OTG_H_BLANK_START_END 0x1cab +#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG3_OTG_H_SYNC_A 0x1cac +#define regOTG3_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG3_OTG_H_SYNC_A_CNTL 0x1cad +#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG3_OTG_H_TIMING_CNTL 0x1cae +#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL 0x1caf +#define regOTG3_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_MIN 0x1cb0 +#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_MAX 0x1cb1 +#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_MID 0x1cb2 +#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 +#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4 +#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5 +#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_V_BLANK_START_END 0x1cb6 +#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG3_OTG_V_SYNC_A 0x1cb7 +#define regOTG3_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG3_OTG_V_SYNC_A_CNTL 0x1cb8 +#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG3_OTG_TRIGA_CNTL 0x1cb9 +#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba +#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG3_OTG_TRIGB_CNTL 0x1cbb +#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc +#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd +#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG3_OTG_FLOW_CONTROL 0x1cbe +#define regOTG3_OTG_FLOW_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf +#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG3_OTG_CONTROL 0x1cc1 +#define regOTG3_OTG_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_INTERLACE_CONTROL 0x1cc4 +#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_INTERLACE_STATUS 0x1cc5 +#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 +#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 +#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG3_OTG_STATUS 0x1cc9 +#define regOTG3_OTG_STATUS_BASE_IDX 2 +#define regOTG3_OTG_STATUS_POSITION 0x1cca +#define regOTG3_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG3_OTG_NOM_VERT_POSITION 0x1ccb +#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc +#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG3_OTG_STATUS_VF_COUNT 0x1ccd +#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG3_OTG_STATUS_HV_COUNT 0x1cce +#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG3_OTG_COUNT_CONTROL 0x1ccf +#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_COUNT_RESET 0x1cd0 +#define regOTG3_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1 +#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2 +#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_STEREO_STATUS 0x1cd3 +#define regOTG3_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG3_OTG_STEREO_CONTROL 0x1cd4 +#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_STATUS 0x1cd5 +#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6 +#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_POSITION 0x1cd7 +#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_FRAME 0x1cd8 +#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG3_OTG_INTERRUPT_CONTROL 0x1cd9 +#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_UPDATE_LOCK 0x1cda +#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb +#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_MASTER_EN 0x1cdc +#define regOTG3_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4 +#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5 +#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6 +#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7 +#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC_CNTL 0x1ce8 +#define regOTG3_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1ce9 +#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1cea +#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1ceb +#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1cec +#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_DATA_RG 0x1ced +#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define regOTG3_OTG_CRC0_DATA_B 0x1cee +#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cef +#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf0 +#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf1 +#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf2 +#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_DATA_RG 0x1cf3 +#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define regOTG3_OTG_CRC1_DATA_B 0x1cf4 +#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC2_DATA_RG 0x1cf5 +#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define regOTG3_OTG_CRC2_DATA_B 0x1cf6 +#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC3_DATA_RG 0x1cf7 +#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define regOTG3_OTG_CRC3_DATA_B 0x1cf8 +#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cf9 +#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfa +#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d01 +#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d02 +#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_GSL_VSYNC_GAP 0x1d03 +#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG3_OTG_MASTER_UPDATE_MODE 0x1d04 +#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG3_OTG_CLOCK_CONTROL 0x1d05 +#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_VSTARTUP_PARAM 0x1d06 +#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG3_OTG_VUPDATE_PARAM 0x1d07 +#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG3_OTG_VREADY_PARAM 0x1d08 +#define regOTG3_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d09 +#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0a +#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG3_OTG_GSL_CONTROL 0x1d0b +#define regOTG3_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_GSL_WINDOW_X 0x1d0c +#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG3_OTG_GSL_WINDOW_Y 0x1d0d +#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG3_OTG_VUPDATE_KEEPOUT 0x1d0e +#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL0 0x1d0f +#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL1 0x1d10 +#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL2 0x1d11 +#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL3 0x1d12 +#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL4 0x1d13 +#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d14 +#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d15 +#define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d16 +#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d17 +#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d18 +#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d19 +#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG3_OTG_DRR_CONTROL 0x1d1a +#define regOTG3_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_M_CONST_DTO0 0x1d1b +#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG3_OTG_M_CONST_DTO1 0x1d1c +#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG3_OTG_REQUEST_CONTROL 0x1d1d +#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_DSC_START_POSITION 0x1d1e +#define regOTG3_OTG_DSC_START_POSITION_BASE_IDX 2 +#define regOTG3_OTG_PIPE_UPDATE_STATUS 0x1d1f +#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG3_OTG_SPARE_REGISTER 0x1d21 +#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dcn_dc_optc_optc_misc_dispdec +// base address: 0x0 +#define regGSL_SOURCE_SELECT 0x1e2b +#define regGSL_SOURCE_SELECT_BASE_IDX 2 +#define regOPTC_CLOCK_CONTROL 0x1e2c +#define regOPTC_CLOCK_CONTROL_BASE_IDX 2 +#define regODM_MEM_PWR_CTRL 0x1e2d +#define regODM_MEM_PWR_CTRL_BASE_IDX 2 +#define regODM_MEM_PWR_CTRL3 0x1e2f +#define regODM_MEM_PWR_CTRL3_BASE_IDX 2 +#define regODM_MEM_PWR_STATUS 0x1e30 +#define regODM_MEM_PWR_STATUS_BASE_IDX 2 +#define regOPTC_MISC_SPARE_REGISTER 0x1e31 +#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_hpd0_dispdec +// base address: 0x0 +#define regHPD0_DC_HPD_INT_STATUS 0x1f14 +#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD0_DC_HPD_INT_CONTROL 0x1f15 +#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD0_DC_HPD_CONTROL 0x1f16 +#define regHPD0_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 +#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 +#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_hpd1_dispdec +// base address: 0x20 +#define regHPD1_DC_HPD_INT_STATUS 0x1f1c +#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD1_DC_HPD_INT_CONTROL 0x1f1d +#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD1_DC_HPD_CONTROL 0x1f1e +#define regHPD1_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f +#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 +#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_hpd2_dispdec +// base address: 0x40 +#define regHPD2_DC_HPD_INT_STATUS 0x1f24 +#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD2_DC_HPD_INT_CONTROL 0x1f25 +#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD2_DC_HPD_CONTROL 0x1f26 +#define regHPD2_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 +#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 +#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_hpd3_dispdec +// base address: 0x60 +#define regHPD3_DC_HPD_INT_STATUS 0x1f2c +#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD3_DC_HPD_INT_CONTROL 0x1f2d +#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD3_DC_HPD_CONTROL 0x1f2e +#define regHPD3_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f +#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 +#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_hpd4_dispdec +// base address: 0x80 +#define regHPD4_DC_HPD_INT_STATUS 0x1f34 +#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD4_DC_HPD_INT_CONTROL 0x1f35 +#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD4_DC_HPD_CONTROL 0x1f36 +#define regHPD4_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 +#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 +#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dp0_dispdec +// base address: 0x0 +#define regDP0_DP_LINK_CNTL 0x2108 +#define regDP0_DP_LINK_CNTL_BASE_IDX 2 +#define regDP0_DP_PIXEL_FORMAT 0x2109 +#define regDP0_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP0_DP_MSA_COLORIMETRY 0x210a +#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP0_DP_CONFIG 0x210b +#define regDP0_DP_CONFIG_BASE_IDX 2 +#define regDP0_DP_VID_STREAM_CNTL 0x210c +#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP0_DP_STEER_FIFO 0x210d +#define regDP0_DP_STEER_FIFO_BASE_IDX 2 +#define regDP0_DP_MSA_MISC 0x210e +#define regDP0_DP_MSA_MISC_BASE_IDX 2 +#define regDP0_DP_DPHY_INTERNAL_CTRL 0x210f +#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP0_DP_VID_TIMING 0x2110 +#define regDP0_DP_VID_TIMING_BASE_IDX 2 +#define regDP0_DP_VID_N 0x2111 +#define regDP0_DP_VID_N_BASE_IDX 2 +#define regDP0_DP_VID_M 0x2112 +#define regDP0_DP_VID_M_BASE_IDX 2 +#define regDP0_DP_LINK_FRAMING_CNTL 0x2113 +#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP0_DP_HBR2_EYE_PATTERN 0x2114 +#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP0_DP_VID_MSA_VBID 0x2115 +#define regDP0_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP0_DP_VID_INTERRUPT_CNTL 0x2116 +#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_CNTL 0x2117 +#define regDP0_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 +#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP0_DP_DPHY_SYM0 0x2119 +#define regDP0_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP0_DP_DPHY_SYM1 0x211a +#define regDP0_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP0_DP_DPHY_SYM2 0x211b +#define regDP0_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP0_DP_DPHY_8B10B_CNTL 0x211c +#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_PRBS_CNTL 0x211d +#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_SCRAM_CNTL 0x211e +#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_EN 0x211f +#define regDP0_DP_DPHY_CRC_EN_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_CNTL 0x2120 +#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_RESULT 0x2121 +#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_MST_CNTL 0x2122 +#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_MST_STATUS 0x2123 +#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define regDP0_DP_DPHY_FAST_TRAINING 0x2124 +#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 +#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL 0x212b +#define regDP0_DP_SEC_CNTL_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL1 0x212c +#define regDP0_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING1 0x212d +#define regDP0_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING2 0x212e +#define regDP0_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING3 0x212f +#define regDP0_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING4 0x2130 +#define regDP0_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_N 0x2131 +#define regDP0_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_N_READBACK 0x2132 +#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_M 0x2133 +#define regDP0_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_M_READBACK 0x2134 +#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP0_DP_SEC_TIMESTAMP 0x2135 +#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP0_DP_SEC_PACKET_CNTL 0x2136 +#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP0_DP_MSE_RATE_CNTL 0x2137 +#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP0_DP_MSE_RATE_UPDATE 0x2139 +#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP0_DP_MSE_SAT0 0x213a +#define regDP0_DP_MSE_SAT0_BASE_IDX 2 +#define regDP0_DP_MSE_SAT1 0x213b +#define regDP0_DP_MSE_SAT1_BASE_IDX 2 +#define regDP0_DP_MSE_SAT2 0x213c +#define regDP0_DP_MSE_SAT2_BASE_IDX 2 +#define regDP0_DP_MSE_SAT_UPDATE 0x213d +#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP0_DP_MSE_LINK_TIMING 0x213e +#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP0_DP_MSE_MISC_CNTL 0x213f +#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 +#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 +#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP0_DP_MSE_SAT0_STATUS 0x2147 +#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP0_DP_MSE_SAT1_STATUS 0x2148 +#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP0_DP_MSE_SAT2_STATUS 0x2149 +#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP0_DP_DPIA_SPARE 0x214a +#define regDP0_DP_DPIA_SPARE_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM1 0x214c +#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM2 0x214d +#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM3 0x214e +#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM4 0x214f +#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP0_DP_MSO_CNTL 0x2150 +#define regDP0_DP_MSO_CNTL_BASE_IDX 2 +#define regDP0_DP_MSO_CNTL1 0x2151 +#define regDP0_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP0_DP_DSC_CNTL 0x2152 +#define regDP0_DP_DSC_CNTL_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL2 0x2153 +#define regDP0_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL3 0x2154 +#define regDP0_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL4 0x2155 +#define regDP0_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL5 0x2156 +#define regDP0_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL6 0x2157 +#define regDP0_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL7 0x2158 +#define regDP0_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP0_DP_DB_CNTL 0x2159 +#define regDP0_DP_DB_CNTL_BASE_IDX 2 +#define regDP0_DP_MSA_VBID_MISC 0x215a +#define regDP0_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP0_DP_SEC_METADATA_TRANSMISSION 0x215b +#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP0_DP_ALPM_CNTL 0x215d +#define regDP0_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP8_CNTL 0x215e +#define regDP0_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP9_CNTL 0x215f +#define regDP0_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP10_CNTL 0x2160 +#define regDP0_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP11_CNTL 0x2161 +#define regDP0_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP_EN_DB_STATUS 0x2162 +#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL1 0x2163 +#define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL2 0x2164 +#define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL3 0x2165 +#define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL4 0x2166 +#define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL5 0x2167 +#define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig0_dispdec +// base address: 0x0 +#define regDIG0_DIG_FE_CNTL 0x208b +#define regDIG0_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG0_DIG_OUTPUT_CRC_CNTL 0x208c +#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG0_DIG_OUTPUT_CRC_RESULT 0x208d +#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG0_DIG_CLOCK_PATTERN 0x208e +#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG0_DIG_TEST_PATTERN 0x208f +#define regDIG0_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG0_DIG_RANDOM_PATTERN_SEED 0x2090 +#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG0_DIG_FIFO_CTRL0 0x2091 +#define regDIG0_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG0_DIG_FIFO_CTRL1 0x2092 +#define regDIG0_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG0_HDMI_METADATA_PACKET_CONTROL 0x2093 +#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_CONTROL 0x2094 +#define regDIG0_HDMI_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_STATUS 0x2095 +#define regDIG0_HDMI_STATUS_BASE_IDX 2 +#define regDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2096 +#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_ACR_PACKET_CONTROL 0x2097 +#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_VBI_PACKET_CONTROL 0x2098 +#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_INFOFRAME_CONTROL0 0x2099 +#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG0_HDMI_INFOFRAME_CONTROL1 0x209a +#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x209b +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x209c +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x209d +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG0_HDMI_GC 0x209e +#define regDIG0_HDMI_GC_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x209f +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x20a0 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20a1 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20a2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20a3 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20a4 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20a5 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20a6 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG0_HDMI_DB_CONTROL 0x20a7 +#define regDIG0_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_ACR_32_0 0x20a8 +#define regDIG0_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_32_1 0x20a9 +#define regDIG0_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG0_HDMI_ACR_44_0 0x20aa +#define regDIG0_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_44_1 0x20ab +#define regDIG0_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG0_HDMI_ACR_48_0 0x20ac +#define regDIG0_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_48_1 0x20ad +#define regDIG0_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG0_HDMI_ACR_STATUS_0 0x20ae +#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_STATUS_1 0x20af +#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG0_AFMT_CNTL 0x20b0 +#define regDIG0_AFMT_CNTL_BASE_IDX 2 +#define regDIG0_DIG_BE_CNTL 0x20b1 +#define regDIG0_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG0_DIG_BE_EN_CNTL 0x20b2 +#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG0_TMDS_CNTL 0x20d8 +#define regDIG0_TMDS_CNTL_BASE_IDX 2 +#define regDIG0_TMDS_CONTROL_CHAR 0x20d9 +#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG0_TMDS_CONTROL0_FEEDBACK 0x20da +#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20db +#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20dc +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20dd +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG0_TMDS_CTL_BITS 0x20df +#define regDIG0_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG0_TMDS_DCBALANCER_CONTROL 0x20e0 +#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20e1 +#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG0_TMDS_CTL0_1_GEN_CNTL 0x20e2 +#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG0_TMDS_CTL2_3_GEN_CNTL 0x20e3 +#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG0_DIG_VERSION 0x20e5 +#define regDIG0_DIG_VERSION_BASE_IDX 2 +#define regDIG0_FORCE_DIG_DISABLE 0x20e6 +#define regDIG0_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dp1_dispdec +// base address: 0x400 +#define regDP1_DP_LINK_CNTL 0x2208 +#define regDP1_DP_LINK_CNTL_BASE_IDX 2 +#define regDP1_DP_PIXEL_FORMAT 0x2209 +#define regDP1_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP1_DP_MSA_COLORIMETRY 0x220a +#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP1_DP_CONFIG 0x220b +#define regDP1_DP_CONFIG_BASE_IDX 2 +#define regDP1_DP_VID_STREAM_CNTL 0x220c +#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP1_DP_STEER_FIFO 0x220d +#define regDP1_DP_STEER_FIFO_BASE_IDX 2 +#define regDP1_DP_MSA_MISC 0x220e +#define regDP1_DP_MSA_MISC_BASE_IDX 2 +#define regDP1_DP_DPHY_INTERNAL_CTRL 0x220f +#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP1_DP_VID_TIMING 0x2210 +#define regDP1_DP_VID_TIMING_BASE_IDX 2 +#define regDP1_DP_VID_N 0x2211 +#define regDP1_DP_VID_N_BASE_IDX 2 +#define regDP1_DP_VID_M 0x2212 +#define regDP1_DP_VID_M_BASE_IDX 2 +#define regDP1_DP_LINK_FRAMING_CNTL 0x2213 +#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP1_DP_HBR2_EYE_PATTERN 0x2214 +#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP1_DP_VID_MSA_VBID 0x2215 +#define regDP1_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP1_DP_VID_INTERRUPT_CNTL 0x2216 +#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_CNTL 0x2217 +#define regDP1_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 +#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP1_DP_DPHY_SYM0 0x2219 +#define regDP1_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP1_DP_DPHY_SYM1 0x221a +#define regDP1_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP1_DP_DPHY_SYM2 0x221b +#define regDP1_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP1_DP_DPHY_8B10B_CNTL 0x221c +#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_PRBS_CNTL 0x221d +#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_SCRAM_CNTL 0x221e +#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_EN 0x221f +#define regDP1_DP_DPHY_CRC_EN_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_CNTL 0x2220 +#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_RESULT 0x2221 +#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_MST_CNTL 0x2222 +#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_MST_STATUS 0x2223 +#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define regDP1_DP_DPHY_FAST_TRAINING 0x2224 +#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 +#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL 0x222b +#define regDP1_DP_SEC_CNTL_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL1 0x222c +#define regDP1_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING1 0x222d +#define regDP1_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING2 0x222e +#define regDP1_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING3 0x222f +#define regDP1_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING4 0x2230 +#define regDP1_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_N 0x2231 +#define regDP1_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_N_READBACK 0x2232 +#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_M 0x2233 +#define regDP1_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_M_READBACK 0x2234 +#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP1_DP_SEC_TIMESTAMP 0x2235 +#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP1_DP_SEC_PACKET_CNTL 0x2236 +#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP1_DP_MSE_RATE_CNTL 0x2237 +#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP1_DP_MSE_RATE_UPDATE 0x2239 +#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP1_DP_MSE_SAT0 0x223a +#define regDP1_DP_MSE_SAT0_BASE_IDX 2 +#define regDP1_DP_MSE_SAT1 0x223b +#define regDP1_DP_MSE_SAT1_BASE_IDX 2 +#define regDP1_DP_MSE_SAT2 0x223c +#define regDP1_DP_MSE_SAT2_BASE_IDX 2 +#define regDP1_DP_MSE_SAT_UPDATE 0x223d +#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP1_DP_MSE_LINK_TIMING 0x223e +#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP1_DP_MSE_MISC_CNTL 0x223f +#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 +#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 +#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP1_DP_MSE_SAT0_STATUS 0x2247 +#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP1_DP_MSE_SAT1_STATUS 0x2248 +#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP1_DP_MSE_SAT2_STATUS 0x2249 +#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP1_DP_DPIA_SPARE 0x224a +#define regDP1_DP_DPIA_SPARE_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM1 0x224c +#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM2 0x224d +#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM3 0x224e +#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM4 0x224f +#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP1_DP_MSO_CNTL 0x2250 +#define regDP1_DP_MSO_CNTL_BASE_IDX 2 +#define regDP1_DP_MSO_CNTL1 0x2251 +#define regDP1_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP1_DP_DSC_CNTL 0x2252 +#define regDP1_DP_DSC_CNTL_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL2 0x2253 +#define regDP1_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL3 0x2254 +#define regDP1_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL4 0x2255 +#define regDP1_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL5 0x2256 +#define regDP1_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL6 0x2257 +#define regDP1_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL7 0x2258 +#define regDP1_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP1_DP_DB_CNTL 0x2259 +#define regDP1_DP_DB_CNTL_BASE_IDX 2 +#define regDP1_DP_MSA_VBID_MISC 0x225a +#define regDP1_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP1_DP_SEC_METADATA_TRANSMISSION 0x225b +#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP1_DP_ALPM_CNTL 0x225d +#define regDP1_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP8_CNTL 0x225e +#define regDP1_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP9_CNTL 0x225f +#define regDP1_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP10_CNTL 0x2260 +#define regDP1_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP11_CNTL 0x2261 +#define regDP1_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP_EN_DB_STATUS 0x2262 +#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL1 0x2263 +#define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL2 0x2264 +#define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL3 0x2265 +#define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL4 0x2266 +#define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL5 0x2267 +#define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig1_dispdec +// base address: 0x400 +#define regDIG1_DIG_FE_CNTL 0x218b +#define regDIG1_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG1_DIG_OUTPUT_CRC_CNTL 0x218c +#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG1_DIG_OUTPUT_CRC_RESULT 0x218d +#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG1_DIG_CLOCK_PATTERN 0x218e +#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG1_DIG_TEST_PATTERN 0x218f +#define regDIG1_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG1_DIG_RANDOM_PATTERN_SEED 0x2190 +#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG1_DIG_FIFO_CTRL0 0x2191 +#define regDIG1_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG1_DIG_FIFO_CTRL1 0x2192 +#define regDIG1_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG1_HDMI_METADATA_PACKET_CONTROL 0x2193 +#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_CONTROL 0x2194 +#define regDIG1_HDMI_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_STATUS 0x2195 +#define regDIG1_HDMI_STATUS_BASE_IDX 2 +#define regDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2196 +#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_ACR_PACKET_CONTROL 0x2197 +#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_VBI_PACKET_CONTROL 0x2198 +#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_INFOFRAME_CONTROL0 0x2199 +#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG1_HDMI_INFOFRAME_CONTROL1 0x219a +#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x219b +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x219c +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x219d +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG1_HDMI_GC 0x219e +#define regDIG1_HDMI_GC_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x219f +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x21a0 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21a1 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21a2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21a3 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21a4 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21a5 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21a6 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG1_HDMI_DB_CONTROL 0x21a7 +#define regDIG1_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_ACR_32_0 0x21a8 +#define regDIG1_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_32_1 0x21a9 +#define regDIG1_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG1_HDMI_ACR_44_0 0x21aa +#define regDIG1_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_44_1 0x21ab +#define regDIG1_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG1_HDMI_ACR_48_0 0x21ac +#define regDIG1_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_48_1 0x21ad +#define regDIG1_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG1_HDMI_ACR_STATUS_0 0x21ae +#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_STATUS_1 0x21af +#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG1_AFMT_CNTL 0x21b0 +#define regDIG1_AFMT_CNTL_BASE_IDX 2 +#define regDIG1_DIG_BE_CNTL 0x21b1 +#define regDIG1_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG1_DIG_BE_EN_CNTL 0x21b2 +#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG1_TMDS_CNTL 0x21d8 +#define regDIG1_TMDS_CNTL_BASE_IDX 2 +#define regDIG1_TMDS_CONTROL_CHAR 0x21d9 +#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG1_TMDS_CONTROL0_FEEDBACK 0x21da +#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21db +#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21dc +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21dd +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG1_TMDS_CTL_BITS 0x21df +#define regDIG1_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG1_TMDS_DCBALANCER_CONTROL 0x21e0 +#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21e1 +#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG1_TMDS_CTL0_1_GEN_CNTL 0x21e2 +#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG1_TMDS_CTL2_3_GEN_CNTL 0x21e3 +#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG1_DIG_VERSION 0x21e5 +#define regDIG1_DIG_VERSION_BASE_IDX 2 +#define regDIG1_FORCE_DIG_DISABLE 0x21e6 +#define regDIG1_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dp2_dispdec +// base address: 0x800 +#define regDP2_DP_LINK_CNTL 0x2308 +#define regDP2_DP_LINK_CNTL_BASE_IDX 2 +#define regDP2_DP_PIXEL_FORMAT 0x2309 +#define regDP2_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP2_DP_MSA_COLORIMETRY 0x230a +#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP2_DP_CONFIG 0x230b +#define regDP2_DP_CONFIG_BASE_IDX 2 +#define regDP2_DP_VID_STREAM_CNTL 0x230c +#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP2_DP_STEER_FIFO 0x230d +#define regDP2_DP_STEER_FIFO_BASE_IDX 2 +#define regDP2_DP_MSA_MISC 0x230e +#define regDP2_DP_MSA_MISC_BASE_IDX 2 +#define regDP2_DP_DPHY_INTERNAL_CTRL 0x230f +#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP2_DP_VID_TIMING 0x2310 +#define regDP2_DP_VID_TIMING_BASE_IDX 2 +#define regDP2_DP_VID_N 0x2311 +#define regDP2_DP_VID_N_BASE_IDX 2 +#define regDP2_DP_VID_M 0x2312 +#define regDP2_DP_VID_M_BASE_IDX 2 +#define regDP2_DP_LINK_FRAMING_CNTL 0x2313 +#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP2_DP_HBR2_EYE_PATTERN 0x2314 +#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP2_DP_VID_MSA_VBID 0x2315 +#define regDP2_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP2_DP_VID_INTERRUPT_CNTL 0x2316 +#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_CNTL 0x2317 +#define regDP2_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318 +#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP2_DP_DPHY_SYM0 0x2319 +#define regDP2_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP2_DP_DPHY_SYM1 0x231a +#define regDP2_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP2_DP_DPHY_SYM2 0x231b +#define regDP2_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP2_DP_DPHY_8B10B_CNTL 0x231c +#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_PRBS_CNTL 0x231d +#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_SCRAM_CNTL 0x231e +#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_EN 0x231f +#define regDP2_DP_DPHY_CRC_EN_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_CNTL 0x2320 +#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_RESULT 0x2321 +#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_MST_CNTL 0x2322 +#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_MST_STATUS 0x2323 +#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define regDP2_DP_DPHY_FAST_TRAINING 0x2324 +#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325 +#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL 0x232b +#define regDP2_DP_SEC_CNTL_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL1 0x232c +#define regDP2_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING1 0x232d +#define regDP2_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING2 0x232e +#define regDP2_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING3 0x232f +#define regDP2_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING4 0x2330 +#define regDP2_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_N 0x2331 +#define regDP2_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_N_READBACK 0x2332 +#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_M 0x2333 +#define regDP2_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_M_READBACK 0x2334 +#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP2_DP_SEC_TIMESTAMP 0x2335 +#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP2_DP_SEC_PACKET_CNTL 0x2336 +#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP2_DP_MSE_RATE_CNTL 0x2337 +#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP2_DP_MSE_RATE_UPDATE 0x2339 +#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP2_DP_MSE_SAT0 0x233a +#define regDP2_DP_MSE_SAT0_BASE_IDX 2 +#define regDP2_DP_MSE_SAT1 0x233b +#define regDP2_DP_MSE_SAT1_BASE_IDX 2 +#define regDP2_DP_MSE_SAT2 0x233c +#define regDP2_DP_MSE_SAT2_BASE_IDX 2 +#define regDP2_DP_MSE_SAT_UPDATE 0x233d +#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP2_DP_MSE_LINK_TIMING 0x233e +#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP2_DP_MSE_MISC_CNTL 0x233f +#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344 +#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345 +#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP2_DP_MSE_SAT0_STATUS 0x2347 +#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP2_DP_MSE_SAT1_STATUS 0x2348 +#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP2_DP_MSE_SAT2_STATUS 0x2349 +#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP2_DP_DPIA_SPARE 0x234a +#define regDP2_DP_DPIA_SPARE_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM1 0x234c +#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM2 0x234d +#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM3 0x234e +#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM4 0x234f +#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP2_DP_MSO_CNTL 0x2350 +#define regDP2_DP_MSO_CNTL_BASE_IDX 2 +#define regDP2_DP_MSO_CNTL1 0x2351 +#define regDP2_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP2_DP_DSC_CNTL 0x2352 +#define regDP2_DP_DSC_CNTL_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL2 0x2353 +#define regDP2_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL3 0x2354 +#define regDP2_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL4 0x2355 +#define regDP2_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL5 0x2356 +#define regDP2_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL6 0x2357 +#define regDP2_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL7 0x2358 +#define regDP2_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP2_DP_DB_CNTL 0x2359 +#define regDP2_DP_DB_CNTL_BASE_IDX 2 +#define regDP2_DP_MSA_VBID_MISC 0x235a +#define regDP2_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP2_DP_SEC_METADATA_TRANSMISSION 0x235b +#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP2_DP_ALPM_CNTL 0x235d +#define regDP2_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP8_CNTL 0x235e +#define regDP2_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP9_CNTL 0x235f +#define regDP2_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP10_CNTL 0x2360 +#define regDP2_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP11_CNTL 0x2361 +#define regDP2_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP_EN_DB_STATUS 0x2362 +#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL1 0x2363 +#define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL2 0x2364 +#define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL3 0x2365 +#define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL4 0x2366 +#define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL5 0x2367 +#define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig2_dispdec +// base address: 0x800 +#define regDIG2_DIG_FE_CNTL 0x228b +#define regDIG2_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG2_DIG_OUTPUT_CRC_CNTL 0x228c +#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG2_DIG_OUTPUT_CRC_RESULT 0x228d +#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG2_DIG_CLOCK_PATTERN 0x228e +#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG2_DIG_TEST_PATTERN 0x228f +#define regDIG2_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG2_DIG_RANDOM_PATTERN_SEED 0x2290 +#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG2_DIG_FIFO_CTRL0 0x2291 +#define regDIG2_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG2_DIG_FIFO_CTRL1 0x2292 +#define regDIG2_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG2_HDMI_METADATA_PACKET_CONTROL 0x2293 +#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_CONTROL 0x2294 +#define regDIG2_HDMI_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_STATUS 0x2295 +#define regDIG2_HDMI_STATUS_BASE_IDX 2 +#define regDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2296 +#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_ACR_PACKET_CONTROL 0x2297 +#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_VBI_PACKET_CONTROL 0x2298 +#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_INFOFRAME_CONTROL0 0x2299 +#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG2_HDMI_INFOFRAME_CONTROL1 0x229a +#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x229b +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x229c +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x229d +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG2_HDMI_GC 0x229e +#define regDIG2_HDMI_GC_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x229f +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x22a0 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22a1 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22a2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22a3 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22a4 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22a5 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22a6 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG2_HDMI_DB_CONTROL 0x22a7 +#define regDIG2_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_ACR_32_0 0x22a8 +#define regDIG2_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_32_1 0x22a9 +#define regDIG2_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG2_HDMI_ACR_44_0 0x22aa +#define regDIG2_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_44_1 0x22ab +#define regDIG2_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG2_HDMI_ACR_48_0 0x22ac +#define regDIG2_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_48_1 0x22ad +#define regDIG2_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG2_HDMI_ACR_STATUS_0 0x22ae +#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_STATUS_1 0x22af +#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG2_AFMT_CNTL 0x22b0 +#define regDIG2_AFMT_CNTL_BASE_IDX 2 +#define regDIG2_DIG_BE_CNTL 0x22b1 +#define regDIG2_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG2_DIG_BE_EN_CNTL 0x22b2 +#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG2_TMDS_CNTL 0x22d8 +#define regDIG2_TMDS_CNTL_BASE_IDX 2 +#define regDIG2_TMDS_CONTROL_CHAR 0x22d9 +#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG2_TMDS_CONTROL0_FEEDBACK 0x22da +#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22db +#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22dc +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22dd +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG2_TMDS_CTL_BITS 0x22df +#define regDIG2_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG2_TMDS_DCBALANCER_CONTROL 0x22e0 +#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22e1 +#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG2_TMDS_CTL0_1_GEN_CNTL 0x22e2 +#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG2_TMDS_CTL2_3_GEN_CNTL 0x22e3 +#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG2_DIG_VERSION 0x22e5 +#define regDIG2_DIG_VERSION_BASE_IDX 2 +#define regDIG2_FORCE_DIG_DISABLE 0x22e6 +#define regDIG2_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dp3_dispdec +// base address: 0xc00 +#define regDP3_DP_LINK_CNTL 0x2408 +#define regDP3_DP_LINK_CNTL_BASE_IDX 2 +#define regDP3_DP_PIXEL_FORMAT 0x2409 +#define regDP3_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP3_DP_MSA_COLORIMETRY 0x240a +#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP3_DP_CONFIG 0x240b +#define regDP3_DP_CONFIG_BASE_IDX 2 +#define regDP3_DP_VID_STREAM_CNTL 0x240c +#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP3_DP_STEER_FIFO 0x240d +#define regDP3_DP_STEER_FIFO_BASE_IDX 2 +#define regDP3_DP_MSA_MISC 0x240e +#define regDP3_DP_MSA_MISC_BASE_IDX 2 +#define regDP3_DP_DPHY_INTERNAL_CTRL 0x240f +#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP3_DP_VID_TIMING 0x2410 +#define regDP3_DP_VID_TIMING_BASE_IDX 2 +#define regDP3_DP_VID_N 0x2411 +#define regDP3_DP_VID_N_BASE_IDX 2 +#define regDP3_DP_VID_M 0x2412 +#define regDP3_DP_VID_M_BASE_IDX 2 +#define regDP3_DP_LINK_FRAMING_CNTL 0x2413 +#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP3_DP_HBR2_EYE_PATTERN 0x2414 +#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP3_DP_VID_MSA_VBID 0x2415 +#define regDP3_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP3_DP_VID_INTERRUPT_CNTL 0x2416 +#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_CNTL 0x2417 +#define regDP3_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418 +#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP3_DP_DPHY_SYM0 0x2419 +#define regDP3_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP3_DP_DPHY_SYM1 0x241a +#define regDP3_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP3_DP_DPHY_SYM2 0x241b +#define regDP3_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP3_DP_DPHY_8B10B_CNTL 0x241c +#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_PRBS_CNTL 0x241d +#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_SCRAM_CNTL 0x241e +#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_EN 0x241f +#define regDP3_DP_DPHY_CRC_EN_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_CNTL 0x2420 +#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_RESULT 0x2421 +#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_MST_CNTL 0x2422 +#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_MST_STATUS 0x2423 +#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define regDP3_DP_DPHY_FAST_TRAINING 0x2424 +#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425 +#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL 0x242b +#define regDP3_DP_SEC_CNTL_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL1 0x242c +#define regDP3_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING1 0x242d +#define regDP3_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING2 0x242e +#define regDP3_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING3 0x242f +#define regDP3_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING4 0x2430 +#define regDP3_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_N 0x2431 +#define regDP3_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_N_READBACK 0x2432 +#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_M 0x2433 +#define regDP3_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_M_READBACK 0x2434 +#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP3_DP_SEC_TIMESTAMP 0x2435 +#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP3_DP_SEC_PACKET_CNTL 0x2436 +#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP3_DP_MSE_RATE_CNTL 0x2437 +#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP3_DP_MSE_RATE_UPDATE 0x2439 +#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP3_DP_MSE_SAT0 0x243a +#define regDP3_DP_MSE_SAT0_BASE_IDX 2 +#define regDP3_DP_MSE_SAT1 0x243b +#define regDP3_DP_MSE_SAT1_BASE_IDX 2 +#define regDP3_DP_MSE_SAT2 0x243c +#define regDP3_DP_MSE_SAT2_BASE_IDX 2 +#define regDP3_DP_MSE_SAT_UPDATE 0x243d +#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP3_DP_MSE_LINK_TIMING 0x243e +#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP3_DP_MSE_MISC_CNTL 0x243f +#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444 +#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445 +#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP3_DP_MSE_SAT0_STATUS 0x2447 +#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP3_DP_MSE_SAT1_STATUS 0x2448 +#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP3_DP_MSE_SAT2_STATUS 0x2449 +#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP3_DP_DPIA_SPARE 0x244a +#define regDP3_DP_DPIA_SPARE_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM1 0x244c +#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM2 0x244d +#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM3 0x244e +#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM4 0x244f +#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP3_DP_MSO_CNTL 0x2450 +#define regDP3_DP_MSO_CNTL_BASE_IDX 2 +#define regDP3_DP_MSO_CNTL1 0x2451 +#define regDP3_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP3_DP_DSC_CNTL 0x2452 +#define regDP3_DP_DSC_CNTL_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL2 0x2453 +#define regDP3_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL3 0x2454 +#define regDP3_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL4 0x2455 +#define regDP3_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL5 0x2456 +#define regDP3_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL6 0x2457 +#define regDP3_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL7 0x2458 +#define regDP3_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP3_DP_DB_CNTL 0x2459 +#define regDP3_DP_DB_CNTL_BASE_IDX 2 +#define regDP3_DP_MSA_VBID_MISC 0x245a +#define regDP3_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP3_DP_SEC_METADATA_TRANSMISSION 0x245b +#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP3_DP_ALPM_CNTL 0x245d +#define regDP3_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP8_CNTL 0x245e +#define regDP3_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP9_CNTL 0x245f +#define regDP3_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP10_CNTL 0x2460 +#define regDP3_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP11_CNTL 0x2461 +#define regDP3_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP_EN_DB_STATUS 0x2462 +#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL1 0x2463 +#define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL2 0x2464 +#define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL3 0x2465 +#define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL4 0x2466 +#define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL5 0x2467 +#define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig3_dispdec +// base address: 0xc00 +#define regDIG3_DIG_FE_CNTL 0x238b +#define regDIG3_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG3_DIG_OUTPUT_CRC_CNTL 0x238c +#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG3_DIG_OUTPUT_CRC_RESULT 0x238d +#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG3_DIG_CLOCK_PATTERN 0x238e +#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG3_DIG_TEST_PATTERN 0x238f +#define regDIG3_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG3_DIG_RANDOM_PATTERN_SEED 0x2390 +#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG3_DIG_FIFO_CTRL0 0x2391 +#define regDIG3_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG3_DIG_FIFO_CTRL1 0x2392 +#define regDIG3_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG3_HDMI_METADATA_PACKET_CONTROL 0x2393 +#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_CONTROL 0x2394 +#define regDIG3_HDMI_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_STATUS 0x2395 +#define regDIG3_HDMI_STATUS_BASE_IDX 2 +#define regDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2396 +#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_ACR_PACKET_CONTROL 0x2397 +#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_VBI_PACKET_CONTROL 0x2398 +#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_INFOFRAME_CONTROL0 0x2399 +#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG3_HDMI_INFOFRAME_CONTROL1 0x239a +#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x239b +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x239c +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x239d +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG3_HDMI_GC 0x239e +#define regDIG3_HDMI_GC_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x239f +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x23a0 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x23a1 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x23a2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x23a3 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x23a4 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x23a5 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x23a6 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG3_HDMI_DB_CONTROL 0x23a7 +#define regDIG3_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_ACR_32_0 0x23a8 +#define regDIG3_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_32_1 0x23a9 +#define regDIG3_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG3_HDMI_ACR_44_0 0x23aa +#define regDIG3_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_44_1 0x23ab +#define regDIG3_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG3_HDMI_ACR_48_0 0x23ac +#define regDIG3_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_48_1 0x23ad +#define regDIG3_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG3_HDMI_ACR_STATUS_0 0x23ae +#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_STATUS_1 0x23af +#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG3_AFMT_CNTL 0x23b0 +#define regDIG3_AFMT_CNTL_BASE_IDX 2 +#define regDIG3_DIG_BE_CNTL 0x23b1 +#define regDIG3_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG3_DIG_BE_EN_CNTL 0x23b2 +#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG3_TMDS_CNTL 0x23d8 +#define regDIG3_TMDS_CNTL_BASE_IDX 2 +#define regDIG3_TMDS_CONTROL_CHAR 0x23d9 +#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG3_TMDS_CONTROL0_FEEDBACK 0x23da +#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23db +#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23dc +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23dd +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG3_TMDS_CTL_BITS 0x23df +#define regDIG3_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG3_TMDS_DCBALANCER_CONTROL 0x23e0 +#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23e1 +#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG3_TMDS_CTL0_1_GEN_CNTL 0x23e2 +#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG3_TMDS_CTL2_3_GEN_CNTL 0x23e3 +#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG3_DIG_VERSION 0x23e5 +#define regDIG3_DIG_VERSION_BASE_IDX 2 +#define regDIG3_FORCE_DIG_DISABLE 0x23e6 +#define regDIG3_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dp4_dispdec +// base address: 0x1000 +#define regDP4_DP_LINK_CNTL 0x2508 +#define regDP4_DP_LINK_CNTL_BASE_IDX 2 +#define regDP4_DP_PIXEL_FORMAT 0x2509 +#define regDP4_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP4_DP_MSA_COLORIMETRY 0x250a +#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP4_DP_CONFIG 0x250b +#define regDP4_DP_CONFIG_BASE_IDX 2 +#define regDP4_DP_VID_STREAM_CNTL 0x250c +#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP4_DP_STEER_FIFO 0x250d +#define regDP4_DP_STEER_FIFO_BASE_IDX 2 +#define regDP4_DP_MSA_MISC 0x250e +#define regDP4_DP_MSA_MISC_BASE_IDX 2 +#define regDP4_DP_DPHY_INTERNAL_CTRL 0x250f +#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP4_DP_VID_TIMING 0x2510 +#define regDP4_DP_VID_TIMING_BASE_IDX 2 +#define regDP4_DP_VID_N 0x2511 +#define regDP4_DP_VID_N_BASE_IDX 2 +#define regDP4_DP_VID_M 0x2512 +#define regDP4_DP_VID_M_BASE_IDX 2 +#define regDP4_DP_LINK_FRAMING_CNTL 0x2513 +#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP4_DP_HBR2_EYE_PATTERN 0x2514 +#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP4_DP_VID_MSA_VBID 0x2515 +#define regDP4_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP4_DP_VID_INTERRUPT_CNTL 0x2516 +#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_CNTL 0x2517 +#define regDP4_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518 +#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP4_DP_DPHY_SYM0 0x2519 +#define regDP4_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP4_DP_DPHY_SYM1 0x251a +#define regDP4_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP4_DP_DPHY_SYM2 0x251b +#define regDP4_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP4_DP_DPHY_8B10B_CNTL 0x251c +#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_PRBS_CNTL 0x251d +#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_SCRAM_CNTL 0x251e +#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_EN 0x251f +#define regDP4_DP_DPHY_CRC_EN_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_CNTL 0x2520 +#define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_RESULT 0x2521 +#define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_MST_CNTL 0x2522 +#define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_MST_STATUS 0x2523 +#define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define regDP4_DP_DPHY_FAST_TRAINING 0x2524 +#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525 +#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL 0x252b +#define regDP4_DP_SEC_CNTL_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL1 0x252c +#define regDP4_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING1 0x252d +#define regDP4_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING2 0x252e +#define regDP4_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING3 0x252f +#define regDP4_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING4 0x2530 +#define regDP4_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_N 0x2531 +#define regDP4_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_N_READBACK 0x2532 +#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_M 0x2533 +#define regDP4_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_M_READBACK 0x2534 +#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP4_DP_SEC_TIMESTAMP 0x2535 +#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP4_DP_SEC_PACKET_CNTL 0x2536 +#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP4_DP_MSE_RATE_CNTL 0x2537 +#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP4_DP_MSE_RATE_UPDATE 0x2539 +#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP4_DP_MSE_SAT0 0x253a +#define regDP4_DP_MSE_SAT0_BASE_IDX 2 +#define regDP4_DP_MSE_SAT1 0x253b +#define regDP4_DP_MSE_SAT1_BASE_IDX 2 +#define regDP4_DP_MSE_SAT2 0x253c +#define regDP4_DP_MSE_SAT2_BASE_IDX 2 +#define regDP4_DP_MSE_SAT_UPDATE 0x253d +#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP4_DP_MSE_LINK_TIMING 0x253e +#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP4_DP_MSE_MISC_CNTL 0x253f +#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544 +#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545 +#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP4_DP_MSE_SAT0_STATUS 0x2547 +#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP4_DP_MSE_SAT1_STATUS 0x2548 +#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP4_DP_MSE_SAT2_STATUS 0x2549 +#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP4_DP_DPIA_SPARE 0x254a +#define regDP4_DP_DPIA_SPARE_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM1 0x254c +#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM2 0x254d +#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM3 0x254e +#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM4 0x254f +#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP4_DP_MSO_CNTL 0x2550 +#define regDP4_DP_MSO_CNTL_BASE_IDX 2 +#define regDP4_DP_MSO_CNTL1 0x2551 +#define regDP4_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP4_DP_DSC_CNTL 0x2552 +#define regDP4_DP_DSC_CNTL_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL2 0x2553 +#define regDP4_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL3 0x2554 +#define regDP4_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL4 0x2555 +#define regDP4_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL5 0x2556 +#define regDP4_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL6 0x2557 +#define regDP4_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL7 0x2558 +#define regDP4_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP4_DP_DB_CNTL 0x2559 +#define regDP4_DP_DB_CNTL_BASE_IDX 2 +#define regDP4_DP_MSA_VBID_MISC 0x255a +#define regDP4_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP4_DP_SEC_METADATA_TRANSMISSION 0x255b +#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP4_DP_ALPM_CNTL 0x255d +#define regDP4_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP8_CNTL 0x255e +#define regDP4_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP9_CNTL 0x255f +#define regDP4_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP10_CNTL 0x2560 +#define regDP4_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP11_CNTL 0x2561 +#define regDP4_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP_EN_DB_STATUS 0x2562 +#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL1 0x2563 +#define regDP4_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL2 0x2564 +#define regDP4_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL3 0x2565 +#define regDP4_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL4 0x2566 +#define regDP4_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL5 0x2567 +#define regDP4_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig4_dispdec +// base address: 0x1000 +#define regDIG4_DIG_FE_CNTL 0x248b +#define regDIG4_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG4_DIG_OUTPUT_CRC_CNTL 0x248c +#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG4_DIG_OUTPUT_CRC_RESULT 0x248d +#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG4_DIG_CLOCK_PATTERN 0x248e +#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG4_DIG_TEST_PATTERN 0x248f +#define regDIG4_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG4_DIG_RANDOM_PATTERN_SEED 0x2490 +#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG4_DIG_FIFO_CTRL0 0x2491 +#define regDIG4_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG4_DIG_FIFO_CTRL1 0x2492 +#define regDIG4_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG4_HDMI_METADATA_PACKET_CONTROL 0x2493 +#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_CONTROL 0x2494 +#define regDIG4_HDMI_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_STATUS 0x2495 +#define regDIG4_HDMI_STATUS_BASE_IDX 2 +#define regDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2496 +#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_ACR_PACKET_CONTROL 0x2497 +#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_VBI_PACKET_CONTROL 0x2498 +#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_INFOFRAME_CONTROL0 0x2499 +#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG4_HDMI_INFOFRAME_CONTROL1 0x249a +#define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x249b +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x249c +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x249d +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG4_HDMI_GC 0x249e +#define regDIG4_HDMI_GC_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x249f +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x24a0 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x24a1 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x24a2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x24a3 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x24a4 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x24a5 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x24a6 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG4_HDMI_DB_CONTROL 0x24a7 +#define regDIG4_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_ACR_32_0 0x24a8 +#define regDIG4_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_32_1 0x24a9 +#define regDIG4_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG4_HDMI_ACR_44_0 0x24aa +#define regDIG4_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_44_1 0x24ab +#define regDIG4_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG4_HDMI_ACR_48_0 0x24ac +#define regDIG4_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_48_1 0x24ad +#define regDIG4_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG4_HDMI_ACR_STATUS_0 0x24ae +#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_STATUS_1 0x24af +#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG4_AFMT_CNTL 0x24b0 +#define regDIG4_AFMT_CNTL_BASE_IDX 2 +#define regDIG4_DIG_BE_CNTL 0x24b1 +#define regDIG4_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG4_DIG_BE_EN_CNTL 0x24b2 +#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG4_TMDS_CNTL 0x24d8 +#define regDIG4_TMDS_CNTL_BASE_IDX 2 +#define regDIG4_TMDS_CONTROL_CHAR 0x24d9 +#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG4_TMDS_CONTROL0_FEEDBACK 0x24da +#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24db +#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24dc +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24dd +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG4_TMDS_CTL_BITS 0x24df +#define regDIG4_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG4_TMDS_DCBALANCER_CONTROL 0x24e0 +#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24e1 +#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG4_TMDS_CTL0_1_GEN_CNTL 0x24e2 +#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG4_TMDS_CTL2_3_GEN_CNTL 0x24e3 +#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG4_DIG_VERSION 0x24e5 +#define regDIG4_DIG_VERSION_BASE_IDX 2 +#define regDIG4_FORCE_DIG_DISABLE 0x24e6 +#define regDIG4_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig0_afmt_afmt_dispdec +// base address: 0x154cc +#define regAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074 +#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075 +#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_INFO0 0x2076 +#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_INFO1 0x2077 +#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define regAFMT0_AFMT_60958_0 0x2078 +#define regAFMT0_AFMT_60958_0_BASE_IDX 2 +#define regAFMT0_AFMT_60958_1 0x2079 +#define regAFMT0_AFMT_60958_1_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a +#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAFMT0_AFMT_RAMP_CONTROL0 0x207b +#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define regAFMT0_AFMT_RAMP_CONTROL1 0x207c +#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define regAFMT0_AFMT_RAMP_CONTROL2 0x207d +#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define regAFMT0_AFMT_RAMP_CONTROL3 0x207e +#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define regAFMT0_AFMT_60958_2 0x207f +#define regAFMT0_AFMT_60958_2_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080 +#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAFMT0_AFMT_STATUS 0x2081 +#define regAFMT0_AFMT_STATUS_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082 +#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083 +#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regAFMT0_AFMT_INTERRUPT_STATUS 0x2084 +#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085 +#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define regAFMT0_AFMT_MEM_PWR 0x2087 +#define regAFMT0_AFMT_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig1_afmt_afmt_dispdec +// base address: 0x158cc +#define regAFMT1_AFMT_VBI_PACKET_CONTROL 0x2174 +#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2175 +#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_INFO0 0x2176 +#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_INFO1 0x2177 +#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define regAFMT1_AFMT_60958_0 0x2178 +#define regAFMT1_AFMT_60958_0_BASE_IDX 2 +#define regAFMT1_AFMT_60958_1 0x2179 +#define regAFMT1_AFMT_60958_1_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_CRC_CONTROL 0x217a +#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAFMT1_AFMT_RAMP_CONTROL0 0x217b +#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define regAFMT1_AFMT_RAMP_CONTROL1 0x217c +#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define regAFMT1_AFMT_RAMP_CONTROL2 0x217d +#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define regAFMT1_AFMT_RAMP_CONTROL3 0x217e +#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define regAFMT1_AFMT_60958_2 0x217f +#define regAFMT1_AFMT_60958_2_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_CRC_RESULT 0x2180 +#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAFMT1_AFMT_STATUS 0x2181 +#define regAFMT1_AFMT_STATUS_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x2182 +#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT1_AFMT_INFOFRAME_CONTROL0 0x2183 +#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regAFMT1_AFMT_INTERRUPT_STATUS 0x2184 +#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_SRC_CONTROL 0x2185 +#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define regAFMT1_AFMT_MEM_PWR 0x2187 +#define regAFMT1_AFMT_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig2_afmt_afmt_dispdec +// base address: 0x15ccc +#define regAFMT2_AFMT_VBI_PACKET_CONTROL 0x2274 +#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x2275 +#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_INFO0 0x2276 +#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_INFO1 0x2277 +#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define regAFMT2_AFMT_60958_0 0x2278 +#define regAFMT2_AFMT_60958_0_BASE_IDX 2 +#define regAFMT2_AFMT_60958_1 0x2279 +#define regAFMT2_AFMT_60958_1_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_CRC_CONTROL 0x227a +#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAFMT2_AFMT_RAMP_CONTROL0 0x227b +#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define regAFMT2_AFMT_RAMP_CONTROL1 0x227c +#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define regAFMT2_AFMT_RAMP_CONTROL2 0x227d +#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define regAFMT2_AFMT_RAMP_CONTROL3 0x227e +#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define regAFMT2_AFMT_60958_2 0x227f +#define regAFMT2_AFMT_60958_2_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_CRC_RESULT 0x2280 +#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAFMT2_AFMT_STATUS 0x2281 +#define regAFMT2_AFMT_STATUS_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x2282 +#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT2_AFMT_INFOFRAME_CONTROL0 0x2283 +#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regAFMT2_AFMT_INTERRUPT_STATUS 0x2284 +#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_SRC_CONTROL 0x2285 +#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define regAFMT2_AFMT_MEM_PWR 0x2287 +#define regAFMT2_AFMT_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig3_afmt_afmt_dispdec +// base address: 0x160cc +#define regAFMT3_AFMT_VBI_PACKET_CONTROL 0x2374 +#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x2375 +#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_INFO0 0x2376 +#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_INFO1 0x2377 +#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define regAFMT3_AFMT_60958_0 0x2378 +#define regAFMT3_AFMT_60958_0_BASE_IDX 2 +#define regAFMT3_AFMT_60958_1 0x2379 +#define regAFMT3_AFMT_60958_1_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_CRC_CONTROL 0x237a +#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAFMT3_AFMT_RAMP_CONTROL0 0x237b +#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define regAFMT3_AFMT_RAMP_CONTROL1 0x237c +#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define regAFMT3_AFMT_RAMP_CONTROL2 0x237d +#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define regAFMT3_AFMT_RAMP_CONTROL3 0x237e +#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define regAFMT3_AFMT_60958_2 0x237f +#define regAFMT3_AFMT_60958_2_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_CRC_RESULT 0x2380 +#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAFMT3_AFMT_STATUS 0x2381 +#define regAFMT3_AFMT_STATUS_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x2382 +#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT3_AFMT_INFOFRAME_CONTROL0 0x2383 +#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regAFMT3_AFMT_INTERRUPT_STATUS 0x2384 +#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_SRC_CONTROL 0x2385 +#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define regAFMT3_AFMT_MEM_PWR 0x2387 +#define regAFMT3_AFMT_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig4_afmt_afmt_dispdec +// base address: 0x164cc +#define regAFMT4_AFMT_VBI_PACKET_CONTROL 0x2474 +#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x2475 +#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_INFO0 0x2476 +#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_INFO1 0x2477 +#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define regAFMT4_AFMT_60958_0 0x2478 +#define regAFMT4_AFMT_60958_0_BASE_IDX 2 +#define regAFMT4_AFMT_60958_1 0x2479 +#define regAFMT4_AFMT_60958_1_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_CRC_CONTROL 0x247a +#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAFMT4_AFMT_RAMP_CONTROL0 0x247b +#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define regAFMT4_AFMT_RAMP_CONTROL1 0x247c +#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define regAFMT4_AFMT_RAMP_CONTROL2 0x247d +#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define regAFMT4_AFMT_RAMP_CONTROL3 0x247e +#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define regAFMT4_AFMT_60958_2 0x247f +#define regAFMT4_AFMT_60958_2_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_CRC_RESULT 0x2480 +#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAFMT4_AFMT_STATUS 0x2481 +#define regAFMT4_AFMT_STATUS_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x2482 +#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT4_AFMT_INFOFRAME_CONTROL0 0x2483 +#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regAFMT4_AFMT_INTERRUPT_STATUS 0x2484 +#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_SRC_CONTROL 0x2485 +#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define regAFMT4_AFMT_MEM_PWR 0x2487 +#define regAFMT4_AFMT_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig0_dme_dme_dispdec +// base address: 0x15524 +#define regDME0_DME_CONTROL 0x2089 +#define regDME0_DME_CONTROL_BASE_IDX 2 +#define regDME0_DME_MEMORY_CONTROL 0x208a +#define regDME0_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig0_vpg_vpg_dispdec +// base address: 0x154a0 +#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 +#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG0_VPG_GENERIC_PACKET_DATA 0x2069 +#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a +#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b +#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG0_VPG_GENERIC_STATUS 0x206c +#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG0_VPG_MEM_PWR 0x206d +#define regVPG0_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e +#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG0_VPG_ISRC1_2_DATA 0x206f +#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG0_VPG_MPEG_INFO0 0x2070 +#define regVPG0_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG0_VPG_MPEG_INFO1 0x2071 +#define regVPG0_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig1_dme_dme_dispdec +// base address: 0x15924 +#define regDME1_DME_CONTROL 0x2189 +#define regDME1_DME_CONTROL_BASE_IDX 2 +#define regDME1_DME_MEMORY_CONTROL 0x218a +#define regDME1_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig1_vpg_vpg_dispdec +// base address: 0x158a0 +#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2168 +#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG1_VPG_GENERIC_PACKET_DATA 0x2169 +#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x216a +#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x216b +#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG1_VPG_GENERIC_STATUS 0x216c +#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG1_VPG_MEM_PWR 0x216d +#define regVPG1_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x216e +#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG1_VPG_ISRC1_2_DATA 0x216f +#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG1_VPG_MPEG_INFO0 0x2170 +#define regVPG1_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG1_VPG_MPEG_INFO1 0x2171 +#define regVPG1_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig2_dme_dme_dispdec +// base address: 0x15d24 +#define regDME2_DME_CONTROL 0x2289 +#define regDME2_DME_CONTROL_BASE_IDX 2 +#define regDME2_DME_MEMORY_CONTROL 0x228a +#define regDME2_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig2_vpg_vpg_dispdec +// base address: 0x15ca0 +#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2268 +#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG2_VPG_GENERIC_PACKET_DATA 0x2269 +#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x226a +#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x226b +#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG2_VPG_GENERIC_STATUS 0x226c +#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG2_VPG_MEM_PWR 0x226d +#define regVPG2_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x226e +#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG2_VPG_ISRC1_2_DATA 0x226f +#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG2_VPG_MPEG_INFO0 0x2270 +#define regVPG2_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG2_VPG_MPEG_INFO1 0x2271 +#define regVPG2_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig3_dme_dme_dispdec +// base address: 0x16124 +#define regDME3_DME_CONTROL 0x2389 +#define regDME3_DME_CONTROL_BASE_IDX 2 +#define regDME3_DME_MEMORY_CONTROL 0x238a +#define regDME3_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig3_vpg_vpg_dispdec +// base address: 0x160a0 +#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2368 +#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG3_VPG_GENERIC_PACKET_DATA 0x2369 +#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x236a +#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x236b +#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG3_VPG_GENERIC_STATUS 0x236c +#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG3_VPG_MEM_PWR 0x236d +#define regVPG3_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x236e +#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG3_VPG_ISRC1_2_DATA 0x236f +#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG3_VPG_MPEG_INFO0 0x2370 +#define regVPG3_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG3_VPG_MPEG_INFO1 0x2371 +#define regVPG3_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig4_dme_dme_dispdec +// base address: 0x16524 +#define regDME4_DME_CONTROL 0x2489 +#define regDME4_DME_CONTROL_BASE_IDX 2 +#define regDME4_DME_MEMORY_CONTROL 0x248a +#define regDME4_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dig4_vpg_vpg_dispdec +// base address: 0x164a0 +#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2468 +#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG4_VPG_GENERIC_PACKET_DATA 0x2469 +#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x246a +#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x246b +#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG4_VPG_GENERIC_STATUS 0x246c +#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG4_VPG_MEM_PWR 0x246d +#define regVPG4_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x246e +#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG4_VPG_ISRC1_2_DATA 0x246f +#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG4_VPG_MPEG_INFO0 0x2470 +#define regVPG4_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG4_VPG_MPEG_INFO1 0x2471 +#define regVPG4_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dp_aux0_dispdec +// base address: 0x0 +#define regDP_AUX0_AUX_CONTROL 0x1f50 +#define regDP_AUX0_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_SW_CONTROL 0x1f51 +#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_ARB_CONTROL 0x1f52 +#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 +#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_SW_STATUS 0x1f54 +#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_LS_STATUS 0x1f55 +#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_SW_DATA 0x1f56 +#define regDP_AUX0_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX0_AUX_LS_DATA 0x1f57 +#define regDP_AUX0_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 +#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 +#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a +#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b +#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c +#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d +#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e +#define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f +#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 +#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 +#define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 +#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dp_aux1_dispdec +// base address: 0x70 +#define regDP_AUX1_AUX_CONTROL 0x1f6c +#define regDP_AUX1_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_SW_CONTROL 0x1f6d +#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_ARB_CONTROL 0x1f6e +#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f +#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_SW_STATUS 0x1f70 +#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_LS_STATUS 0x1f71 +#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_SW_DATA 0x1f72 +#define regDP_AUX1_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX1_AUX_LS_DATA 0x1f73 +#define regDP_AUX1_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 +#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 +#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 +#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 +#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a +#define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b +#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c +#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d +#define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 +#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dp_aux2_dispdec +// base address: 0xe0 +#define regDP_AUX2_AUX_CONTROL 0x1f88 +#define regDP_AUX2_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_SW_CONTROL 0x1f89 +#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_ARB_CONTROL 0x1f8a +#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b +#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_SW_STATUS 0x1f8c +#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_LS_STATUS 0x1f8d +#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_SW_DATA 0x1f8e +#define regDP_AUX2_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX2_AUX_LS_DATA 0x1f8f +#define regDP_AUX2_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 +#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 +#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 +#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 +#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96 +#define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 +#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 +#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 +#define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e +#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dp_aux3_dispdec +// base address: 0x150 +#define regDP_AUX3_AUX_CONTROL 0x1fa4 +#define regDP_AUX3_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_SW_CONTROL 0x1fa5 +#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_ARB_CONTROL 0x1fa6 +#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 +#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_SW_STATUS 0x1fa8 +#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_LS_STATUS 0x1fa9 +#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_SW_DATA 0x1faa +#define regDP_AUX3_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX3_AUX_LS_DATA 0x1fab +#define regDP_AUX3_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac +#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad +#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae +#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf +#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 +#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 +#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2 +#define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 +#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 +#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 +#define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba +#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dp_aux4_dispdec +// base address: 0x1c0 +#define regDP_AUX4_AUX_CONTROL 0x1fc0 +#define regDP_AUX4_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_SW_CONTROL 0x1fc1 +#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_ARB_CONTROL 0x1fc2 +#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 +#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_SW_STATUS 0x1fc4 +#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_LS_STATUS 0x1fc5 +#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_SW_DATA 0x1fc6 +#define regDP_AUX4_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX4_AUX_LS_DATA 0x1fc7 +#define regDP_AUX4_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 +#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 +#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca +#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb +#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc +#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd +#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce +#define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf +#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 +#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 +#define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6 +#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dout_i2c_dispdec +// base address: 0x0 +#define regDC_I2C_CONTROL 0x1e98 +#define regDC_I2C_CONTROL_BASE_IDX 2 +#define regDC_I2C_ARBITRATION 0x1e99 +#define regDC_I2C_ARBITRATION_BASE_IDX 2 +#define regDC_I2C_INTERRUPT_CONTROL 0x1e9a +#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDC_I2C_SW_STATUS 0x1e9b +#define regDC_I2C_SW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC1_HW_STATUS 0x1e9c +#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC2_HW_STATUS 0x1e9d +#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC3_HW_STATUS 0x1e9e +#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC4_HW_STATUS 0x1e9f +#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC5_HW_STATUS 0x1ea0 +#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC1_SPEED 0x1ea2 +#define regDC_I2C_DDC1_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC1_SETUP 0x1ea3 +#define regDC_I2C_DDC1_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC2_SPEED 0x1ea4 +#define regDC_I2C_DDC2_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC2_SETUP 0x1ea5 +#define regDC_I2C_DDC2_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC3_SPEED 0x1ea6 +#define regDC_I2C_DDC3_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC3_SETUP 0x1ea7 +#define regDC_I2C_DDC3_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC4_SPEED 0x1ea8 +#define regDC_I2C_DDC4_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC4_SETUP 0x1ea9 +#define regDC_I2C_DDC4_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC5_SPEED 0x1eaa +#define regDC_I2C_DDC5_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC5_SETUP 0x1eab +#define regDC_I2C_DDC5_SETUP_BASE_IDX 2 +#define regDC_I2C_TRANSACTION0 0x1eae +#define regDC_I2C_TRANSACTION0_BASE_IDX 2 +#define regDC_I2C_TRANSACTION1 0x1eaf +#define regDC_I2C_TRANSACTION1_BASE_IDX 2 +#define regDC_I2C_TRANSACTION2 0x1eb0 +#define regDC_I2C_TRANSACTION2_BASE_IDX 2 +#define regDC_I2C_TRANSACTION3 0x1eb1 +#define regDC_I2C_TRANSACTION3_BASE_IDX 2 +#define regDC_I2C_DATA 0x1eb2 +#define regDC_I2C_DATA_BASE_IDX 2 +#define regDC_I2C_EDID_DETECT_CTRL 0x1eb6 +#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 +#define regDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 +#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 + + +// addressBlock: dcn_dc_dio_dio_misc_dispdec +// base address: 0x0 +#define regDIO_SCRATCH0 0x1eca +#define regDIO_SCRATCH0_BASE_IDX 2 +#define regDIO_SCRATCH1 0x1ecb +#define regDIO_SCRATCH1_BASE_IDX 2 +#define regDIO_SCRATCH2 0x1ecc +#define regDIO_SCRATCH2_BASE_IDX 2 +#define regDIO_SCRATCH3 0x1ecd +#define regDIO_SCRATCH3_BASE_IDX 2 +#define regDIO_SCRATCH4 0x1ece +#define regDIO_SCRATCH4_BASE_IDX 2 +#define regDIO_SCRATCH5 0x1ecf +#define regDIO_SCRATCH5_BASE_IDX 2 +#define regDIO_SCRATCH6 0x1ed0 +#define regDIO_SCRATCH6_BASE_IDX 2 +#define regDIO_SCRATCH7 0x1ed1 +#define regDIO_SCRATCH7_BASE_IDX 2 +#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS 0x1ed3 +#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX 2 +#define regDIO_MEM_PWR_STATUS 0x1edd +#define regDIO_MEM_PWR_STATUS_BASE_IDX 2 +#define regDIO_MEM_PWR_CTRL 0x1ede +#define regDIO_MEM_PWR_CTRL_BASE_IDX 2 +#define regDIO_MEM_PWR_CTRL2 0x1edf +#define regDIO_MEM_PWR_CTRL2_BASE_IDX 2 +#define regDIO_CLK_CNTL 0x1ee0 +#define regDIO_CLK_CNTL_BASE_IDX 2 +#define regDIO_POWER_MANAGEMENT_CNTL 0x1ee4 +#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 +#define regDIG_SOFT_RESET 0x1eee +#define regDIG_SOFT_RESET_BASE_IDX 2 +#define regDIO_CLK_CNTL2 0x1ef2 +#define regDIO_CLK_CNTL2_BASE_IDX 2 +#define regDIO_CLK_CNTL3 0x1ef3 +#define regDIO_CLK_CNTL3_BASE_IDX 2 +#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff +#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 +#define regDIO_LINKA_CNTL 0x1f04 +#define regDIO_LINKA_CNTL_BASE_IDX 2 +#define regDIO_LINKB_CNTL 0x1f05 +#define regDIO_LINKB_CNTL_BASE_IDX 2 +#define regDIO_LINKC_CNTL 0x1f06 +#define regDIO_LINKC_CNTL_BASE_IDX 2 +#define regDIO_LINKD_CNTL 0x1f07 +#define regDIO_LINKD_CNTL_BASE_IDX 2 +#define regDIO_LINKE_CNTL 0x1f08 +#define regDIO_LINKE_CNTL_BASE_IDX 2 +#define regDIO_LINKF_CNTL 0x1f09 +#define regDIO_LINKF_CNTL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcio_dcio_dispdec +// base address: 0x0 +#define regDC_GENERICA 0x2868 +#define regDC_GENERICA_BASE_IDX 2 +#define regDC_GENERICB 0x2869 +#define regDC_GENERICB_BASE_IDX 2 +#define regDCIO_CLOCK_CNTL 0x286a +#define regDCIO_CLOCK_CNTL_BASE_IDX 2 +#define regDC_REF_CLK_CNTL 0x286b +#define regDC_REF_CLK_CNTL_BASE_IDX 2 +#define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e +#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 +#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 +#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 +#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 +#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regDCIO_WRCMD_DELAY 0x287e +#define regDCIO_WRCMD_DELAY_BASE_IDX 2 +#define regDC_PINSTRAPS 0x2880 +#define regDC_PINSTRAPS_BASE_IDX 2 +#define regDCIO_SPARE 0x2882 +#define regDCIO_SPARE_BASE_IDX 2 +#define regINTERCEPT_STATE 0x2884 +#define regINTERCEPT_STATE_BASE_IDX 2 +#define regDCIO_PATTERN_GEN_PAT 0x2886 +#define regDCIO_PATTERN_GEN_PAT_BASE_IDX 2 +#define regDCIO_PATTERN_GEN_EN 0x2887 +#define regDCIO_PATTERN_GEN_EN_BASE_IDX 2 +#define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b +#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 +#define regDCIO_GSL_GENLK_PAD_CNTL 0x288c +#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 +#define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d +#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 +#define regDCIO_SOFT_RESET 0x289e +#define regDCIO_SOFT_RESET_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcio_dcio_chip_dispdec +// base address: 0x0 +#define regDC_GPIO_GENERIC_MASK 0x28c8 +#define regDC_GPIO_GENERIC_MASK_BASE_IDX 2 +#define regDC_GPIO_GENERIC_A 0x28c9 +#define regDC_GPIO_GENERIC_A_BASE_IDX 2 +#define regDC_GPIO_GENERIC_EN 0x28ca +#define regDC_GPIO_GENERIC_EN_BASE_IDX 2 +#define regDC_GPIO_GENERIC_Y 0x28cb +#define regDC_GPIO_GENERIC_Y_BASE_IDX 2 +#define regDC_GPIO_DDC1_MASK 0x28d0 +#define regDC_GPIO_DDC1_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC1_A 0x28d1 +#define regDC_GPIO_DDC1_A_BASE_IDX 2 +#define regDC_GPIO_DDC1_EN 0x28d2 +#define regDC_GPIO_DDC1_EN_BASE_IDX 2 +#define regDC_GPIO_DDC1_Y 0x28d3 +#define regDC_GPIO_DDC1_Y_BASE_IDX 2 +#define regDC_GPIO_DDC2_MASK 0x28d4 +#define regDC_GPIO_DDC2_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC2_A 0x28d5 +#define regDC_GPIO_DDC2_A_BASE_IDX 2 +#define regDC_GPIO_DDC2_EN 0x28d6 +#define regDC_GPIO_DDC2_EN_BASE_IDX 2 +#define regDC_GPIO_DDC2_Y 0x28d7 +#define regDC_GPIO_DDC2_Y_BASE_IDX 2 +#define regDC_GPIO_DDC3_MASK 0x28d8 +#define regDC_GPIO_DDC3_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC3_A 0x28d9 +#define regDC_GPIO_DDC3_A_BASE_IDX 2 +#define regDC_GPIO_DDC3_EN 0x28da +#define regDC_GPIO_DDC3_EN_BASE_IDX 2 +#define regDC_GPIO_DDC3_Y 0x28db +#define regDC_GPIO_DDC3_Y_BASE_IDX 2 +#define regDC_GPIO_DDC4_MASK 0x28dc +#define regDC_GPIO_DDC4_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC4_A 0x28dd +#define regDC_GPIO_DDC4_A_BASE_IDX 2 +#define regDC_GPIO_DDC4_EN 0x28de +#define regDC_GPIO_DDC4_EN_BASE_IDX 2 +#define regDC_GPIO_DDC4_Y 0x28df +#define regDC_GPIO_DDC4_Y_BASE_IDX 2 +#define regDC_GPIO_DDC5_MASK 0x28e0 +#define regDC_GPIO_DDC5_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC5_A 0x28e1 +#define regDC_GPIO_DDC5_A_BASE_IDX 2 +#define regDC_GPIO_DDC5_EN 0x28e2 +#define regDC_GPIO_DDC5_EN_BASE_IDX 2 +#define regDC_GPIO_DDC5_Y 0x28e3 +#define regDC_GPIO_DDC5_Y_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_MASK 0x28e8 +#define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_A 0x28e9 +#define regDC_GPIO_DDCVGA_A_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_EN 0x28ea +#define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_Y 0x28eb +#define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 +#define regDC_GPIO_GENLK_MASK 0x28f0 +#define regDC_GPIO_GENLK_MASK_BASE_IDX 2 +#define regDC_GPIO_GENLK_A 0x28f1 +#define regDC_GPIO_GENLK_A_BASE_IDX 2 +#define regDC_GPIO_GENLK_EN 0x28f2 +#define regDC_GPIO_GENLK_EN_BASE_IDX 2 +#define regDC_GPIO_GENLK_Y 0x28f3 +#define regDC_GPIO_GENLK_Y_BASE_IDX 2 +#define regDC_GPIO_HPD_MASK 0x28f4 +#define regDC_GPIO_HPD_MASK_BASE_IDX 2 +#define regDC_GPIO_HPD_A 0x28f5 +#define regDC_GPIO_HPD_A_BASE_IDX 2 +#define regDC_GPIO_HPD_EN 0x28f6 +#define regDC_GPIO_HPD_EN_BASE_IDX 2 +#define regDC_GPIO_HPD_Y 0x28f7 +#define regDC_GPIO_HPD_Y_BASE_IDX 2 +#define regDC_GPIO_DRIVE_STRENGTH_S0 0x28f8 +#define regDC_GPIO_DRIVE_STRENGTH_S0_BASE_IDX 2 +#define regDC_GPIO_DRIVE_STRENGTH_S1 0x28f9 +#define regDC_GPIO_DRIVE_STRENGTH_S1_BASE_IDX 2 +#define regDC_GPIO_PWRSEQ0_EN 0x28fa +#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 +#define regDC_GPIO_PAD_STRENGTH_1 0x28fc +#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 +#define regDC_GPIO_PAD_STRENGTH_2 0x28fd +#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 +#define regPHY_AUX_CNTL 0x28ff +#define regPHY_AUX_CNTL_BASE_IDX 2 +#define regDC_GPIO_DRIVE_TXIMPSEL 0x2900 +#define regDC_GPIO_DRIVE_TXIMPSEL_BASE_IDX 2 +#define regDC_GPIO_TX12_EN 0x2915 +#define regDC_GPIO_TX12_EN_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_0 0x2916 +#define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_1 0x2917 +#define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_2 0x2918 +#define regDC_GPIO_AUX_CTRL_2_BASE_IDX 2 +#define regDC_GPIO_RXEN 0x2919 +#define regDC_GPIO_RXEN_BASE_IDX 2 +#define regDC_GPIO_PULLUPEN 0x291a +#define regDC_GPIO_PULLUPEN_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_3 0x291b +#define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_4 0x291c +#define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_5 0x291d +#define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 +#define regAUXI2C_PAD_ALL_PWR_OK 0x291e +#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcio_dcio_uniphy0_dispdec +// base address: 0x0 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x2928 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x2929 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x292a +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x292b +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x292c +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x292d +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x292e +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x292f +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2930 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2931 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2932 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2933 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x2934 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x2935 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x2936 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x2937 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x2938 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x2939 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x293a +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x293b +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x293c +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x293d +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x293e +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x293f +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2940 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2941 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2942 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2943 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x2944 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x2945 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x2946 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x2947 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x2948 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x2949 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x294a +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x294b +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x294c +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x294d +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x294e +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x294f +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2950 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2951 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2952 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2953 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x2954 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x2955 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x2956 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x2957 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x2958 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x2959 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x295a +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x295b +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x295c +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x295d +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x295e +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x295f +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2960 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2961 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcio_dcio_uniphy1_dispdec +// base address: 0x360 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcio_dcio_uniphy2_dispdec +// base address: 0x6c0 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcio_dcio_uniphy3_dispdec +// base address: 0xa20 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 + + +// addressBlock: dcn_dc_dcio_dcio_uniphy4_dispdec +// base address: 0xd80 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x2cb8 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x2cb9 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2cba +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2cbb +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2cbc +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2cbd +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2cbe +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2cbf +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2cc0 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2cc1 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 + + +// addressBlock: dcn_dc_pwrseq0_dispdec_pwrseq_dispdec +// base address: 0x0 +#define regDC_GPIO_PWRSEQ_EN 0x2f10 +#define regDC_GPIO_PWRSEQ_EN_BASE_IDX 2 +#define regDC_GPIO_PWRSEQ_CTRL 0x2f11 +#define regDC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 +#define regDC_GPIO_PWRSEQ_MASK 0x2f12 +#define regDC_GPIO_PWRSEQ_MASK_BASE_IDX 2 +#define regDC_GPIO_PWRSEQ_A_Y 0x2f13 +#define regDC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 +#define regPANEL_PWRSEQ_CNTL 0x2f14 +#define regPANEL_PWRSEQ_CNTL_BASE_IDX 2 +#define regPANEL_PWRSEQ_STATE 0x2f15 +#define regPANEL_PWRSEQ_STATE_BASE_IDX 2 +#define regPANEL_PWRSEQ_DELAY1 0x2f16 +#define regPANEL_PWRSEQ_DELAY1_BASE_IDX 2 +#define regPANEL_PWRSEQ_DELAY2 0x2f17 +#define regPANEL_PWRSEQ_DELAY2_BASE_IDX 2 +#define regPANEL_PWRSEQ_REF_DIV1 0x2f18 +#define regPANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 +#define regBL_PWM_CNTL 0x2f19 +#define regBL_PWM_CNTL_BASE_IDX 2 +#define regBL_PWM_CNTL2 0x2f1a +#define regBL_PWM_CNTL2_BASE_IDX 2 +#define regBL_PWM_PERIOD_CNTL 0x2f1b +#define regBL_PWM_PERIOD_CNTL_BASE_IDX 2 +#define regBL_PWM_GRP1_REG_LOCK 0x2f1c +#define regBL_PWM_GRP1_REG_LOCK_BASE_IDX 2 +#define regPANEL_PWRSEQ_REF_DIV2 0x2f1d +#define regPANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 +#define regPWRSEQ_SPARE 0x2f21 +#define regPWRSEQ_SPARE_BASE_IDX 2 + + +// addressBlock: dcn_dc_dsc0_dispdec_dscc_dispdec +// base address: 0x0 +#define regDSCC0_DSCC_CONFIG0 0x300a +#define regDSCC0_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC0_DSCC_CONFIG1 0x300b +#define regDSCC0_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC0_DSCC_STATUS 0x300c +#define regDSCC0_DSCC_STATUS_BASE_IDX 2 +#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d +#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG0 0x300e +#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG1 0x300f +#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG2 0x3010 +#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG3 0x3011 +#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG4 0x3012 +#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG5 0x3013 +#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG6 0x3014 +#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG7 0x3015 +#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG8 0x3016 +#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG9 0x3017 +#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG10 0x3018 +#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG11 0x3019 +#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG12 0x301a +#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG13 0x301b +#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG14 0x301c +#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG15 0x301d +#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG16 0x301e +#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG17 0x301f +#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG18 0x3020 +#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG19 0x3021 +#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG20 0x3022 +#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG21 0x3023 +#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG22 0x3024 +#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 +#define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC0_DSCC_MAX_ABS_ERROR0 0x302c +#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC0_DSCC_MAX_ABS_ERROR1 0x302d +#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e +#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f +#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 +#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 +#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dsc0_dispdec_dsccif_dispdec +// base address: 0x0 +#define regDSCCIF0_DSCCIF_CONFIG0 0x3005 +#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 +#define regDSCCIF0_DSCCIF_CONFIG1 0x3006 +#define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dcn_dc_dsc0_dispdec_dsc_top_dispdec +// base address: 0x0 +#define regDSC_TOP0_DSC_TOP_CONTROL 0x3000 +#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 +#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dsc1_dispdec_dscc_dispdec +// base address: 0x170 +#define regDSCC1_DSCC_CONFIG0 0x3066 +#define regDSCC1_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC1_DSCC_CONFIG1 0x3067 +#define regDSCC1_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC1_DSCC_STATUS 0x3068 +#define regDSCC1_DSCC_STATUS_BASE_IDX 2 +#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 +#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG0 0x306a +#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG1 0x306b +#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG2 0x306c +#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG3 0x306d +#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG4 0x306e +#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG5 0x306f +#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG6 0x3070 +#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG7 0x3071 +#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG8 0x3072 +#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG9 0x3073 +#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG10 0x3074 +#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG11 0x3075 +#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG12 0x3076 +#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG13 0x3077 +#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG14 0x3078 +#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG15 0x3079 +#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG16 0x307a +#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG17 0x307b +#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG18 0x307c +#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG19 0x307d +#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG20 0x307e +#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG21 0x307f +#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG22 0x3080 +#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 +#define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 +#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 +#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a +#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b +#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c +#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d +#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dsc1_dispdec_dsccif_dispdec +// base address: 0x170 +#define regDSCCIF1_DSCCIF_CONFIG0 0x3061 +#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 +#define regDSCCIF1_DSCCIF_CONFIG1 0x3062 +#define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dcn_dc_dsc1_dispdec_dsc_top_dispdec +// base address: 0x170 +#define regDSC_TOP1_DSC_TOP_CONTROL 0x305c +#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP1_DSC_DEBUG_CONTROL 0x305d +#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dsc2_dispdec_dscc_dispdec +// base address: 0x2e0 +#define regDSCC2_DSCC_CONFIG0 0x30c2 +#define regDSCC2_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC2_DSCC_CONFIG1 0x30c3 +#define regDSCC2_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC2_DSCC_STATUS 0x30c4 +#define regDSCC2_DSCC_STATUS_BASE_IDX 2 +#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5 +#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG0 0x30c6 +#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG1 0x30c7 +#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG2 0x30c8 +#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG3 0x30c9 +#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG4 0x30ca +#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG5 0x30cb +#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG6 0x30cc +#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG7 0x30cd +#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG8 0x30ce +#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG9 0x30cf +#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG10 0x30d0 +#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG11 0x30d1 +#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG12 0x30d2 +#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG13 0x30d3 +#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG14 0x30d4 +#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG15 0x30d5 +#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG16 0x30d6 +#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG17 0x30d7 +#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG18 0x30d8 +#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG19 0x30d9 +#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG20 0x30da +#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG21 0x30db +#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG22 0x30dc +#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd +#define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4 +#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5 +#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6 +#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7 +#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8 +#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9 +#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dsc2_dispdec_dsccif_dispdec +// base address: 0x2e0 +#define regDSCCIF2_DSCCIF_CONFIG0 0x30bd +#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 +#define regDSCCIF2_DSCCIF_CONFIG1 0x30be +#define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dcn_dc_dsc2_dispdec_dsc_top_dispdec +// base address: 0x2e0 +#define regDSC_TOP2_DSC_TOP_CONTROL 0x30b8 +#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 +#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dsc3_dispdec_dscc_dispdec +// base address: 0x450 +#define regDSCC3_DSCC_CONFIG0 0x311e +#define regDSCC3_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC3_DSCC_CONFIG1 0x311f +#define regDSCC3_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC3_DSCC_STATUS 0x3120 +#define regDSCC3_DSCC_STATUS_BASE_IDX 2 +#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS 0x3121 +#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG0 0x3122 +#define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG1 0x3123 +#define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG2 0x3124 +#define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG3 0x3125 +#define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG4 0x3126 +#define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG5 0x3127 +#define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG6 0x3128 +#define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG7 0x3129 +#define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG8 0x312a +#define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG9 0x312b +#define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG10 0x312c +#define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG11 0x312d +#define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG12 0x312e +#define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG13 0x312f +#define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG14 0x3130 +#define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG15 0x3131 +#define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG16 0x3132 +#define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG17 0x3133 +#define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG18 0x3134 +#define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG19 0x3135 +#define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG20 0x3136 +#define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG21 0x3137 +#define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG22 0x3138 +#define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC3_DSCC_MEM_POWER_CONTROL 0x3139 +#define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313a +#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x313b +#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x313c +#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x313d +#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x313e +#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x313f +#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC3_DSCC_MAX_ABS_ERROR0 0x3140 +#define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC3_DSCC_MAX_ABS_ERROR1 0x3141 +#define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x3142 +#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x3143 +#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3144 +#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3145 +#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3146 +#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3147 +#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3148 +#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149 +#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 + + +// addressBlock: dcn_dc_dsc3_dispdec_dsccif_dispdec +// base address: 0x450 +#define regDSCCIF3_DSCCIF_CONFIG0 0x3119 +#define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2 +#define regDSCCIF3_DSCCIF_CONFIG1 0x311a +#define regDSCCIF3_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dcn_dc_dsc3_dispdec_dsc_top_dispdec +// base address: 0x450 +#define regDSC_TOP3_DSC_TOP_CONTROL 0x3114 +#define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP3_DSC_DEBUG_CONTROL 0x3115 +#define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_hpo_top_dispdec +// base address: 0x2790c +#define regHPO_TOP_CLOCK_CONTROL 0x0e43 +#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 +#define regHPO_TOP_HW_CONTROL 0x0e4a +#define regHPO_TOP_HW_CONTROL_BASE_IDX 3 + + +// addressBlock: dcn_dc_hpo_dp_stream_mapper_dispdec +// base address: 0x27958 +#define regDP_STREAM_MAPPER_CONTROL0 0x0e56 +#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX 3 +#define regDP_STREAM_MAPPER_CONTROL1 0x0e57 +#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX 3 +#define regDP_STREAM_MAPPER_CONTROL2 0x0e58 +#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX 3 +#define regDP_STREAM_MAPPER_CONTROL3 0x0e59 +#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 + + +// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec +// base address: 0x2646c +#define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c +#define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x091d +#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_INFO0 0x091e +#define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_INFO1 0x091f +#define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX 3 +#define regAFMT5_AFMT_60958_0 0x0920 +#define regAFMT5_AFMT_60958_0_BASE_IDX 3 +#define regAFMT5_AFMT_60958_1 0x0921 +#define regAFMT5_AFMT_60958_1_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_CRC_CONTROL 0x0922 +#define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 3 +#define regAFMT5_AFMT_RAMP_CONTROL0 0x0923 +#define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX 3 +#define regAFMT5_AFMT_RAMP_CONTROL1 0x0924 +#define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX 3 +#define regAFMT5_AFMT_RAMP_CONTROL2 0x0925 +#define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX 3 +#define regAFMT5_AFMT_RAMP_CONTROL3 0x0926 +#define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX 3 +#define regAFMT5_AFMT_60958_2 0x0927 +#define regAFMT5_AFMT_60958_2_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_CRC_RESULT 0x0928 +#define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 3 +#define regAFMT5_AFMT_STATUS 0x0929 +#define regAFMT5_AFMT_STATUS_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL 0x092a +#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3 +#define regAFMT5_AFMT_INFOFRAME_CONTROL0 0x092b +#define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3 +#define regAFMT5_AFMT_INTERRUPT_STATUS 0x092c +#define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_SRC_CONTROL 0x092d +#define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3 +#define regAFMT5_AFMT_MEM_PWR 0x092f +#define regAFMT5_AFMT_MEM_PWR_BASE_IDX 3 + + +// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec +// base address: 0x264f0 +#define regDME5_DME_CONTROL 0x093c +#define regDME5_DME_CONTROL_BASE_IDX 3 +#define regDME5_DME_MEMORY_CONTROL 0x093d +#define regDME5_DME_MEMORY_CONTROL_BASE_IDX 3 + + +// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec +// base address: 0x264c4 +#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 +#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 +#define regVPG5_VPG_GENERIC_PACKET_DATA 0x0932 +#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 +#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 +#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 +#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 +#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 +#define regVPG5_VPG_GENERIC_STATUS 0x0935 +#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX 3 +#define regVPG5_VPG_MEM_PWR 0x0936 +#define regVPG5_VPG_MEM_PWR_BASE_IDX 3 +#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x0937 +#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3 +#define regVPG5_VPG_ISRC1_2_DATA 0x0938 +#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX 3 +#define regVPG5_VPG_MPEG_INFO0 0x0939 +#define regVPG5_VPG_MPEG_INFO0_BASE_IDX 3 +#define regVPG5_VPG_MPEG_INFO1 0x093a +#define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 + + +// addressBlock: dcn_dc_hpo_dp_stream_enc0_dispdec +// base address: 0x1ab8c +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x3624 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL 0x3625 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x3626 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x3627 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE 0x3628 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_stream_enc0_apg_apg_dispdec +// base address: 0x1abc0 +#define regAPG0_APG_CONTROL 0x3630 +#define regAPG0_APG_CONTROL_BASE_IDX 2 +#define regAPG0_APG_CONTROL2 0x3631 +#define regAPG0_APG_CONTROL2_BASE_IDX 2 +#define regAPG0_APG_DBG_GEN_CONTROL 0x3632 +#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG0_APG_PACKET_CONTROL 0x3633 +#define regAPG0_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG0_APG_AUDIO_CRC_CONTROL 0x363a +#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG0_APG_AUDIO_CRC_CONTROL2 0x363b +#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG0_APG_AUDIO_CRC_RESULT 0x363c +#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG0_APG_STATUS 0x3641 +#define regAPG0_APG_STATUS_BASE_IDX 2 +#define regAPG0_APG_STATUS2 0x3642 +#define regAPG0_APG_STATUS2_BASE_IDX 2 +#define regAPG0_APG_MEM_PWR 0x3644 +#define regAPG0_APG_MEM_PWR_BASE_IDX 2 +#define regAPG0_APG_SPARE 0x3646 +#define regAPG0_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_stream_enc0_dme_dme_dispdec +// base address: 0x1ac38 +#define regDME6_DME_CONTROL 0x364e +#define regDME6_DME_CONTROL_BASE_IDX 2 +#define regDME6_DME_MEMORY_CONTROL 0x364f +#define regDME6_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec +// base address: 0x1ac44 +#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3651 +#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG6_VPG_GENERIC_PACKET_DATA 0x3652 +#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x3653 +#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3654 +#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG6_VPG_GENERIC_STATUS 0x3655 +#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG6_VPG_MEM_PWR 0x3656 +#define regVPG6_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x3657 +#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG6_VPG_ISRC1_2_DATA 0x3658 +#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG6_VPG_MPEG_INFO0 0x3659 +#define regVPG6_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG6_VPG_MPEG_INFO1 0x365a +#define regVPG6_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_sym32_enc0_dispdec +// base address: 0x1ac74 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL 0x365d +#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL 0x365e +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x365f +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3660 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3661 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 0x3662 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 0x3663 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 0x3664 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 0x3665 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 0x3666 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 0x3667 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 0x3668 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 0x3669 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 0x366a +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b +#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x366c +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x366d +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x366e +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x366f +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3670 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3671 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3672 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3673 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3674 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3675 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x3676 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x3677 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3678 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3679 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x367a +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL 0x367b +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x367c +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x367d +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x367e +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL 0x3683 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL 0x3684 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3685 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3686 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 0x3688 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 0x3689 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS 0x368a +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL 0x368b +#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE 0x368c +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_stream_enc1_dispdec +// base address: 0x1aedc +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL 0x36f7 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x36f8 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL 0x36f9 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x36fa +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x36fb +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE 0x36fc +#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_stream_enc1_apg_apg_dispdec +// base address: 0x1af10 +#define regAPG1_APG_CONTROL 0x3704 +#define regAPG1_APG_CONTROL_BASE_IDX 2 +#define regAPG1_APG_CONTROL2 0x3705 +#define regAPG1_APG_CONTROL2_BASE_IDX 2 +#define regAPG1_APG_DBG_GEN_CONTROL 0x3706 +#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG1_APG_PACKET_CONTROL 0x3707 +#define regAPG1_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG1_APG_AUDIO_CRC_CONTROL 0x370e +#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG1_APG_AUDIO_CRC_CONTROL2 0x370f +#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG1_APG_AUDIO_CRC_RESULT 0x3710 +#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG1_APG_STATUS 0x3715 +#define regAPG1_APG_STATUS_BASE_IDX 2 +#define regAPG1_APG_STATUS2 0x3716 +#define regAPG1_APG_STATUS2_BASE_IDX 2 +#define regAPG1_APG_MEM_PWR 0x3718 +#define regAPG1_APG_MEM_PWR_BASE_IDX 2 +#define regAPG1_APG_SPARE 0x371a +#define regAPG1_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_stream_enc1_dme_dme_dispdec +// base address: 0x1af88 +#define regDME7_DME_CONTROL 0x3722 +#define regDME7_DME_CONTROL_BASE_IDX 2 +#define regDME7_DME_MEMORY_CONTROL 0x3723 +#define regDME7_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec +// base address: 0x1af94 +#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3725 +#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG7_VPG_GENERIC_PACKET_DATA 0x3726 +#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL 0x3727 +#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3728 +#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG7_VPG_GENERIC_STATUS 0x3729 +#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG7_VPG_MEM_PWR 0x372a +#define regVPG7_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL 0x372b +#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG7_VPG_ISRC1_2_DATA 0x372c +#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG7_VPG_MPEG_INFO0 0x372d +#define regVPG7_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG7_VPG_MPEG_INFO1 0x372e +#define regVPG7_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_sym32_enc1_dispdec +// base address: 0x1afc4 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL 0x3731 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3732 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3733 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3734 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3735 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 0x3736 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 0x3737 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 0x3738 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 0x3739 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 0x373a +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 0x373b +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 0x373c +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 0x373d +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 0x373e +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f +#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3740 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3741 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3742 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3743 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3744 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3745 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3746 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3747 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3748 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3749 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x374a +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x374b +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x374c +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x374d +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x374e +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL 0x374f +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3750 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3751 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3752 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL 0x3757 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL 0x3758 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3759 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x375a +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 0x375c +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 0x375d +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS 0x375e +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL 0x375f +#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE 0x3760 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_stream_enc2_dispdec +// base address: 0x1b22c +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL 0x37cb +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x37cc +#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL 0x37cd +#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x37ce +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x37cf +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE 0x37d0 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_stream_enc2_apg_apg_dispdec +// base address: 0x1b260 +#define regAPG2_APG_CONTROL 0x37d8 +#define regAPG2_APG_CONTROL_BASE_IDX 2 +#define regAPG2_APG_CONTROL2 0x37d9 +#define regAPG2_APG_CONTROL2_BASE_IDX 2 +#define regAPG2_APG_DBG_GEN_CONTROL 0x37da +#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG2_APG_PACKET_CONTROL 0x37db +#define regAPG2_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG2_APG_AUDIO_CRC_CONTROL 0x37e2 +#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG2_APG_AUDIO_CRC_CONTROL2 0x37e3 +#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG2_APG_AUDIO_CRC_RESULT 0x37e4 +#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG2_APG_STATUS 0x37e9 +#define regAPG2_APG_STATUS_BASE_IDX 2 +#define regAPG2_APG_STATUS2 0x37ea +#define regAPG2_APG_STATUS2_BASE_IDX 2 +#define regAPG2_APG_MEM_PWR 0x37ec +#define regAPG2_APG_MEM_PWR_BASE_IDX 2 +#define regAPG2_APG_SPARE 0x37ee +#define regAPG2_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_stream_enc2_dme_dme_dispdec +// base address: 0x1b2d8 +#define regDME8_DME_CONTROL 0x37f6 +#define regDME8_DME_CONTROL_BASE_IDX 2 +#define regDME8_DME_MEMORY_CONTROL 0x37f7 +#define regDME8_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec +// base address: 0x1b2e4 +#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL 0x37f9 +#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG8_VPG_GENERIC_PACKET_DATA 0x37fa +#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL 0x37fb +#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x37fc +#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG8_VPG_GENERIC_STATUS 0x37fd +#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG8_VPG_MEM_PWR 0x37fe +#define regVPG8_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL 0x37ff +#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG8_VPG_ISRC1_2_DATA 0x3800 +#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG8_VPG_MPEG_INFO0 0x3801 +#define regVPG8_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG8_VPG_MPEG_INFO1 0x3802 +#define regVPG8_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_sym32_enc2_dispdec +// base address: 0x1b314 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL 0x3805 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3806 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3807 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3808 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3809 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 0x380a +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 0x380b +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 0x380c +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 0x380d +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 0x380e +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 0x380f +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 0x3810 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 0x3811 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 0x3812 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3814 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3815 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3816 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3817 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3818 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3819 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x381a +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x381b +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x381c +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x381d +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x381e +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x381f +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3820 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3821 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x3822 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL 0x3823 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3824 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3825 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3826 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL 0x382b +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL 0x382c +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL 0x382d +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x382e +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 0x3830 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 0x3831 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS 0x3832 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3833 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE 0x3834 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_stream_enc3_dispdec +// base address: 0x1b57c +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL 0x389f +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x38a0 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL 0x38a1 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x38a2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x38a3 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE 0x38a4 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_stream_enc3_apg_apg_dispdec +// base address: 0x1b5b0 +#define regAPG3_APG_CONTROL 0x38ac +#define regAPG3_APG_CONTROL_BASE_IDX 2 +#define regAPG3_APG_CONTROL2 0x38ad +#define regAPG3_APG_CONTROL2_BASE_IDX 2 +#define regAPG3_APG_DBG_GEN_CONTROL 0x38ae +#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG3_APG_PACKET_CONTROL 0x38af +#define regAPG3_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG3_APG_AUDIO_CRC_CONTROL 0x38b6 +#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG3_APG_AUDIO_CRC_CONTROL2 0x38b7 +#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG3_APG_AUDIO_CRC_RESULT 0x38b8 +#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG3_APG_STATUS 0x38bd +#define regAPG3_APG_STATUS_BASE_IDX 2 +#define regAPG3_APG_STATUS2 0x38be +#define regAPG3_APG_STATUS2_BASE_IDX 2 +#define regAPG3_APG_MEM_PWR 0x38c0 +#define regAPG3_APG_MEM_PWR_BASE_IDX 2 +#define regAPG3_APG_SPARE 0x38c2 +#define regAPG3_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_stream_enc3_dme_dme_dispdec +// base address: 0x1b628 +#define regDME9_DME_CONTROL 0x38ca +#define regDME9_DME_CONTROL_BASE_IDX 2 +#define regDME9_DME_MEMORY_CONTROL 0x38cb +#define regDME9_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec +// base address: 0x1b634 +#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL 0x38cd +#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG9_VPG_GENERIC_PACKET_DATA 0x38ce +#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL 0x38cf +#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x38d0 +#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG9_VPG_GENERIC_STATUS 0x38d1 +#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG9_VPG_MEM_PWR 0x38d2 +#define regVPG9_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL 0x38d3 +#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG9_VPG_ISRC1_2_DATA 0x38d4 +#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG9_VPG_MPEG_INFO0 0x38d5 +#define regVPG9_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG9_VPG_MPEG_INFO1 0x38d6 +#define regVPG9_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_sym32_enc3_dispdec +// base address: 0x1b664 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL 0x38d9 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL 0x38da +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x38db +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x38dc +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x38dd +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 0x38de +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 0x38df +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 0x38e0 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 0x38e1 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 0x38e2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 0x38e3 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 0x38e4 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 0x38e5 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 0x38e6 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL 0x38e7 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x38e8 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x38e9 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x38ea +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x38eb +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x38ec +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x38ed +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x38ee +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x38ef +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x38f0 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x38f1 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x38f2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x38f3 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x38f4 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x38f5 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x38f6 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL 0x38f7 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x38f8 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x38f9 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x38fa +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL 0x38ff +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL 0x3900 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3901 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3902 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL 0x3903 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 0x3904 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 0x3905 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS 0x3906 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3907 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE 0x3908 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_link_enc0_dispdec +// base address: 0x1ad5c +#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL 0x3697 +#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE 0x3698 +#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_dphy_sym320_dispdec +// base address: 0x1ae00 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL 0x36c0 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS 0x36c1 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE 0x36c4 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 0x36c5 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 0x36c6 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 0x36c7 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 0x36c8 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 0x36cb +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 0x36cc +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 0x36cd +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 0x36ce +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 0x36d1 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 0x36d2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 0x36d3 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 0x36d4 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG 0x36d7 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 0x36d8 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 0x36d9 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 0x36da +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 0x36db +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE 0x36dc +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 0x36dd +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 0x36de +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 0x36df +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 0x36e0 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 0x36e1 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 0x36e2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 0x36e3 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 0x36e4 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 0x36e5 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 0x36e6 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 0x36e7 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS 0x36e8 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x36ea +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0 0x36eb +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1 0x36ec +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS 0x36ed +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT 0x36ee +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_link_enc1_dispdec +// base address: 0x1b0ac +#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL 0x376b +#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE 0x376c +#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dcn_dc_hpo_dp_dphy_sym321_dispdec +// base address: 0x1b150 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL 0x3794 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS 0x3795 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE 0x3798 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3799 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 0x379a +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 0x379b +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 0x379c +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 0x379f +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 0x37a0 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 0x37a1 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 0x37a2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 0x37a5 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 0x37a6 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 0x37a7 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 0x37a8 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG 0x37ab +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 0x37ac +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 0x37ad +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 0x37ae +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 0x37af +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE 0x37b0 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 0x37b1 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 0x37b2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 0x37b3 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 0x37b4 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 0x37b5 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 0x37b6 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 0x37b7 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 0x37b8 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 0x37b9 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 0x37ba +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 0x37bb +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS 0x37bc +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x37be +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0 0x37bf +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1 0x37c0 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS 0x37c1 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT 0x37c2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 + + +// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe0_dispdec +// base address: 0x0 +#define regRDPCSPIPE0_RDPCSPIPE_PHY_CNTL6 0x293b +#define regRDPCSPIPE0_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 + + +// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe1_dispdec +// base address: 0x360 +#define regRDPCSPIPE1_RDPCSPIPE_PHY_CNTL6 0x2a13 +#define regRDPCSPIPE1_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 + + +// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe2_dispdec +// base address: 0x6c0 +#define regRDPCSPIPE2_RDPCSPIPE_PHY_CNTL6 0x2aeb +#define regRDPCSPIPE2_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 + + +// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe3_dispdec +// base address: 0xa20 +#define regRDPCSPIPE3_RDPCSPIPE_PHY_CNTL6 0x2bc3 +#define regRDPCSPIPE3_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 + + +// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe4_dispdec +// base address: 0xd80 +#define regRDPCSPIPE4_RDPCSPIPE_PHY_CNTL6 0x2c9b +#define regRDPCSPIPE4_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 + + +// addressBlock: dcn_dc_hda_azcontroller_azdec +// base address: 0x0 +#define regCORB_WRITE_POINTER 0x0000 +#define regCORB_WRITE_POINTER_BASE_IDX 0 +#define regCORB_READ_POINTER 0x0000 +#define regCORB_READ_POINTER_BASE_IDX 0 +#define regCORB_CONTROL 0x0001 +#define regCORB_CONTROL_BASE_IDX 0 +#define regCORB_STATUS 0x0001 +#define regCORB_STATUS_BASE_IDX 0 +#define regCORB_SIZE 0x0001 +#define regCORB_SIZE_BASE_IDX 0 +#define regRIRB_LOWER_BASE_ADDRESS 0x0002 +#define regRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regRIRB_UPPER_BASE_ADDRESS 0x0003 +#define regRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regRIRB_WRITE_POINTER 0x0004 +#define regRIRB_WRITE_POINTER_BASE_IDX 0 +#define regRESPONSE_INTERRUPT_COUNT 0x0004 +#define regRESPONSE_INTERRUPT_COUNT_BASE_IDX 0 +#define regRIRB_CONTROL 0x0005 +#define regRIRB_CONTROL_BASE_IDX 0 +#define regRIRB_STATUS 0x0005 +#define regRIRB_STATUS_BASE_IDX 0 +#define regRIRB_SIZE 0x0005 +#define regRIRB_SIZE_BASE_IDX 0 +#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 +#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 +#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 +#define regIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 +#define regIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 +#define regIMMEDIATE_COMMAND_STATUS 0x0008 +#define regIMMEDIATE_COMMAND_STATUS_BASE_IDX 0 +#define regDMA_POSITION_LOWER_BASE_ADDRESS 0x000a +#define regDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regDMA_POSITION_UPPER_BASE_ADDRESS 0x000b +#define regDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regWALL_CLOCK_COUNTER_ALIAS 0x074c +#define regWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 + + +// addressBlock: dcn_dc_hda_azendpoint_azdec +// base address: 0x0 +#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 + + +// addressBlock: dcn_dc_hda_azinputendpoint_azdec +// base address: 0x0 +#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 +#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 +#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 +#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 + + +// addressBlock: dcn_dc_hda_azroot_azdec +// base address: 0x0 +#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 + + +// addressBlock: dcn_dc_hda_azstream0_azdec +// base address: 0x0 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dcn_dc_hda_azstream1_azdec +// base address: 0x20 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dcn_dc_hda_azstream2_azdec +// base address: 0x40 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dcn_dc_hda_azstream3_azdec +// base address: 0x60 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dcn_dc_hda_azstream4_azdec +// base address: 0x80 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dcn_dc_hda_azstream5_azdec +// base address: 0xa0 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dcn_dc_hda_azstream6_azdec +// base address: 0xc0 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dcn_dc_hda_azstream7_azdec +// base address: 0xe0 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: vga_vgaseqind +// base address: 0x0 +#define ixSEQ00 0x0000 +#define ixSEQ01 0x0001 +#define ixSEQ02 0x0002 +#define ixSEQ03 0x0003 +#define ixSEQ04 0x0004 + + +// addressBlock: vga_vgacrtind +// base address: 0x0 +#define ixCRT00 0x0000 +#define ixCRT01 0x0001 +#define ixCRT02 0x0002 +#define ixCRT03 0x0003 +#define ixCRT04 0x0004 +#define ixCRT05 0x0005 +#define ixCRT06 0x0006 +#define ixCRT07 0x0007 +#define ixCRT08 0x0008 +#define ixCRT09 0x0009 +#define ixCRT0A 0x000a +#define ixCRT0B 0x000b +#define ixCRT0C 0x000c +#define ixCRT0D 0x000d +#define ixCRT0E 0x000e +#define ixCRT0F 0x000f +#define ixCRT10 0x0010 +#define ixCRT11 0x0011 +#define ixCRT12 0x0012 +#define ixCRT13 0x0013 +#define ixCRT14 0x0014 +#define ixCRT15 0x0015 +#define ixCRT16 0x0016 +#define ixCRT17 0x0017 +#define ixCRT18 0x0018 +#define ixCRT1E 0x001e +#define ixCRT1F 0x001f +#define ixCRT22 0x0022 + + +// addressBlock: vga_vgagrphind +// base address: 0x0 +#define ixGRA00 0x0000 +#define ixGRA01 0x0001 +#define ixGRA02 0x0002 +#define ixGRA03 0x0003 +#define ixGRA04 0x0004 +#define ixGRA05 0x0005 +#define ixGRA06 0x0006 +#define ixGRA07 0x0007 +#define ixGRA08 0x0008 + + +// addressBlock: vga_vgaattrind +// base address: 0x0 +#define ixATTR00 0x0000 +#define ixATTR01 0x0001 +#define ixATTR02 0x0002 +#define ixATTR03 0x0003 +#define ixATTR04 0x0004 +#define ixATTR05 0x0005 +#define ixATTR06 0x0006 +#define ixATTR07 0x0007 +#define ixATTR08 0x0008 +#define ixATTR09 0x0009 +#define ixATTR0A 0x000a +#define ixATTR0B 0x000b +#define ixATTR0C 0x000c +#define ixATTR0D 0x000d +#define ixATTR0E 0x000e +#define ixATTR0F 0x000f +#define ixATTR10 0x0010 +#define ixATTR11 0x0011 +#define ixATTR12 0x0012 +#define ixATTR13 0x0013 +#define ixATTR14 0x0014 + + +// addressBlock: azendpoint_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e +#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e + + +// addressBlock: azendpoint_descriptorind +// base address: 0x0 +#define ixAUDIO_DESCRIPTOR0 0x0001 +#define ixAUDIO_DESCRIPTOR1 0x0002 +#define ixAUDIO_DESCRIPTOR2 0x0003 +#define ixAUDIO_DESCRIPTOR3 0x0004 +#define ixAUDIO_DESCRIPTOR4 0x0005 +#define ixAUDIO_DESCRIPTOR5 0x0006 +#define ixAUDIO_DESCRIPTOR6 0x0007 +#define ixAUDIO_DESCRIPTOR7 0x0008 +#define ixAUDIO_DESCRIPTOR8 0x0009 +#define ixAUDIO_DESCRIPTOR9 0x000a +#define ixAUDIO_DESCRIPTOR10 0x000b +#define ixAUDIO_DESCRIPTOR11 0x000c +#define ixAUDIO_DESCRIPTOR12 0x000d +#define ixAUDIO_DESCRIPTOR13 0x000e + + +// addressBlock: azendpoint_sinkinfoind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 +#define ixSINK_DESCRIPTION0 0x0005 +#define ixSINK_DESCRIPTION1 0x0006 +#define ixSINK_DESCRIPTION2 0x0007 +#define ixSINK_DESCRIPTION3 0x0008 +#define ixSINK_DESCRIPTION4 0x0009 +#define ixSINK_DESCRIPTION5 0x000a +#define ixSINK_DESCRIPTION6 0x000b +#define ixSINK_DESCRIPTION7 0x000c +#define ixSINK_DESCRIPTION8 0x000d +#define ixSINK_DESCRIPTION9 0x000e +#define ixSINK_DESCRIPTION10 0x000f +#define ixSINK_DESCRIPTION11 0x0010 +#define ixSINK_DESCRIPTION12 0x0011 +#define ixSINK_DESCRIPTION13 0x0012 +#define ixSINK_DESCRIPTION14 0x0013 +#define ixSINK_DESCRIPTION15 0x0014 +#define ixSINK_DESCRIPTION16 0x0015 +#define ixSINK_DESCRIPTION17 0x0016 + + +// addressBlock: azf0controller_azinputcrc0resultind +// base address: 0x0 +#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 +#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 +#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 +#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 +#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 +#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 +#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 +#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azinputcrc1resultind +// base address: 0x0 +#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 +#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 +#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 +#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 +#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 +#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 +#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 +#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azcrc0resultind +// base address: 0x0 +#define ixAZALIA_CRC0_CHANNEL0 0x0000 +#define ixAZALIA_CRC0_CHANNEL1 0x0001 +#define ixAZALIA_CRC0_CHANNEL2 0x0002 +#define ixAZALIA_CRC0_CHANNEL3 0x0003 +#define ixAZALIA_CRC0_CHANNEL4 0x0004 +#define ixAZALIA_CRC0_CHANNEL5 0x0005 +#define ixAZALIA_CRC0_CHANNEL6 0x0006 +#define ixAZALIA_CRC0_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azcrc1resultind +// base address: 0x0 +#define ixAZALIA_CRC1_CHANNEL0 0x0000 +#define ixAZALIA_CRC1_CHANNEL1 0x0001 +#define ixAZALIA_CRC1_CHANNEL2 0x0002 +#define ixAZALIA_CRC1_CHANNEL3 0x0003 +#define ixAZALIA_CRC1_CHANNEL4 0x0004 +#define ixAZALIA_CRC1_CHANNEL5 0x0005 +#define ixAZALIA_CRC1_CHANNEL6 0x0006 +#define ixAZALIA_CRC1_CHANNEL7 0x0007 + + +// addressBlock: azinputendpoint_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c + + +// addressBlock: azroot_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f + + +// addressBlock: azf0stream0_streamind +// base address: 0x0 +#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream1_streamind +// base address: 0x0 +#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream2_streamind +// base address: 0x0 +#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream3_streamind +// base address: 0x0 +#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream4_streamind +// base address: 0x0 +#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream5_streamind +// base address: 0x0 +#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream6_streamind +// base address: 0x0 +#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream7_streamind +// base address: 0x0 +#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream8_streamind +// base address: 0x0 +#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream9_streamind +// base address: 0x0 +#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream10_streamind +// base address: 0x0 +#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream11_streamind +// base address: 0x0 +#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream12_streamind +// base address: 0x0 +#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream13_streamind +// base address: 0x0 +#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream14_streamind +// base address: 0x0 +#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream15_streamind +// base address: 0x0 +#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0endpoint0_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint1_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint2_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint3_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint4_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint5_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint6_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint7_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0inputendpoint0_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint1_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint2_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint3_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint4_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint5_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint6_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint7_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: c20_phy_cr0_rdpcspipecrind +// base address: 0x0 +#define ixC20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS 0x10cc +#define ixC20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x12cc +#define ixC20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x14cc +#define ixC20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS 0x16cc +#define ixC20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK 0x2021 +#define ixC20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK 0x20c0 +#define ixC20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK 0x2221 +#define ixC20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK 0x22c0 +#define ixC20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK 0x2421 +#define ixC20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK 0x24c0 +#define ixC20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK 0x2621 +#define ixC20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK 0x26c0 +#define ixC20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x50cc +#define ixC20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK 0x6021 +#define ixC20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK 0x60c0 + + +// addressBlock: c20_phy_cr1_rdpcspipecrind +// base address: 0x0 +#define ixC20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS 0x10cc +#define ixC20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x12cc +#define ixC20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x14cc +#define ixC20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS 0x16cc +#define ixC20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK 0x2021 +#define ixC20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK 0x20c0 +#define ixC20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK 0x2221 +#define ixC20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK 0x22c0 +#define ixC20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK 0x2421 +#define ixC20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK 0x24c0 +#define ixC20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK 0x2621 +#define ixC20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK 0x26c0 +#define ixC20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x50cc +#define ixC20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK 0x6021 +#define ixC20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK 0x60c0 + + +// addressBlock: c20_phy_cr2_rdpcspipecrind +// base address: 0x0 +#define ixC20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS 0x10cc +#define ixC20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x12cc +#define ixC20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x14cc +#define ixC20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS 0x16cc +#define ixC20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK 0x2021 +#define ixC20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK 0x20c0 +#define ixC20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK 0x2221 +#define ixC20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK 0x22c0 +#define ixC20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK 0x2421 +#define ixC20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK 0x24c0 +#define ixC20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK 0x2621 +#define ixC20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK 0x26c0 +#define ixC20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x50cc +#define ixC20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK 0x6021 +#define ixC20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK 0x60c0 + + +// addressBlock: c20_phy_cr3_rdpcspipecrind +// base address: 0x0 +#define ixC20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS 0x10cc +#define ixC20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x12cc +#define ixC20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x14cc +#define ixC20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS 0x16cc +#define ixC20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK 0x2021 +#define ixC20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK 0x20c0 +#define ixC20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK 0x2221 +#define ixC20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK 0x22c0 +#define ixC20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK 0x2421 +#define ixC20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK 0x24c0 +#define ixC20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK 0x2621 +#define ixC20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK 0x26c0 +#define ixC20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x50cc +#define ixC20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK 0x6021 +#define ixC20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK 0x60c0 + + +// addressBlock: c20_phy_cr4_rdpcspipecrind +// base address: 0x0 +#define ixC20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS 0x10cc +#define ixC20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x12cc +#define ixC20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x14cc +#define ixC20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS 0x16cc +#define ixC20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK 0x2021 +#define ixC20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK 0x20c0 +#define ixC20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK 0x2221 +#define ixC20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK 0x22c0 +#define ixC20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK 0x2421 +#define ixC20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK 0x24c0 +#define ixC20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK 0x2621 +#define ixC20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK 0x26c0 +#define ixC20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x50cc +#define ixC20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK 0x6021 +#define ixC20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK 0x60c0 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h new file mode 100644 index 000000000000..d42f91560bb9 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h @@ -0,0 +1,222890 @@ + +/* + * Copyright (C) 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _dcn_3_2_0_SH_MASK_HEADER +#define _dcn_3_2_0_SH_MASK_HEADER + + +// addressBlock: dcn_dc_dccg_dccg_dfs_dispdec +//DENTIST_DISPCLK_CNTL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT 0x15 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT 0x16 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK 0x00200000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK 0x00400000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L + + +// addressBlock: dcn_dc_dccg_dccg_dispdec +//PHYPLLA_PIXCLK_RESYNC_CNTL +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x00000100L +//PHYPLLB_PIXCLK_RESYNC_CNTL +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK 0x00000100L +//PHYPLLC_PIXCLK_RESYNC_CNTL +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK 0x00000100L +//PHYPLLD_PIXCLK_RESYNC_CNTL +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK 0x00000100L +//DP_DTO_DBUF_EN +#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT 0x0 +#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT 0x1 +#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT 0x2 +#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT 0x3 +#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT 0x4 +#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT 0x5 +#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT 0x6 +#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT 0x7 +#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK 0x00000001L +#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK 0x00000002L +#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK 0x00000004L +#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK 0x00000008L +#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK 0x00000010L +#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK 0x00000020L +#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK 0x00000040L +#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK 0x00000080L +//DSCCLK3_DTO_PARAM +#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE__SHIFT 0x0 +#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO__SHIFT 0x10 +#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO_MASK 0x00FF0000L +//DPREFCLK_CGTT_BLK_CTRL_REG +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_GATE_DISABLE_CNTL4 +#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE_MASK 0x00020000L +//DPSTREAMCLK_CNTL +#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL__SHIFT 0x0 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN__SHIFT 0x3 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL__SHIFT 0x4 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN__SHIFT 0x7 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL__SHIFT 0x8 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN__SHIFT 0xb +#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL__SHIFT 0xc +#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN__SHIFT 0xf +#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL_MASK 0x00000007L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN_MASK 0x00000008L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL_MASK 0x00000070L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN_MASK 0x00000080L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL_MASK 0x00000700L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN_MASK 0x00000800L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL_MASK 0x00007000L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN_MASK 0x00008000L +//REFCLK_CGTT_BLK_CTRL_REG +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//PHYPLLE_PIXCLK_RESYNC_CNTL +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK 0x00000100L +//DCCG_GLOBAL_FGCG_REP_CNTL +#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS__SHIFT 0x0 +#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS_MASK 0x00000001L +//DCCG_DS_DTO_INCR +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0 +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xFFFFFFFFL +//DCCG_DS_DTO_MODULO +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0 +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xFFFFFFFFL +//DCCG_DS_CNTL +#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0 +#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT 0x4 +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8 +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9 +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10 +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18 +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19 +#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x00000001L +#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK 0x00000030L +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x00000100L +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x00000200L +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x00030000L +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x01000000L +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x02000000L +//DCCG_DS_HW_CAL_INTERVAL +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0 +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xFFFFFFFFL +//DPREFCLK_CNTL +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x00000007L +//DCE_VERSION +#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0 +#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8 +#define DCE_VERSION__MAJOR_VERSION_MASK 0x000000FFL +#define DCE_VERSION__MINOR_VERSION_MASK 0x0000FF00L +//DCCG_GTC_CNTL +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0 +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L +//DCCG_GTC_DTO_INCR +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0 +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xFFFFFFFFL +//DCCG_GTC_DTO_MODULO +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0 +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xFFFFFFFFL +//DCCG_GTC_CURRENT +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0 +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xFFFFFFFFL +//SYMCLK32_SE_CNTL +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL__SHIFT 0x0 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN__SHIFT 0x3 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL__SHIFT 0x4 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN__SHIFT 0x7 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL__SHIFT 0x8 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN__SHIFT 0xb +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL__SHIFT 0xc +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN__SHIFT 0xf +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL_MASK 0x00000007L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN_MASK 0x00000008L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL_MASK 0x00000070L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN_MASK 0x00000080L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL_MASK 0x00000700L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN_MASK 0x00000800L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL_MASK 0x00007000L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN_MASK 0x00008000L +//SYMCLK32_LE_CNTL +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL__SHIFT 0x0 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN__SHIFT 0x3 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL__SHIFT 0x4 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN__SHIFT 0x7 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL_MASK 0x00000007L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN_MASK 0x00000008L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL_MASK 0x00000070L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN_MASK 0x00000080L +//DTBCLK_P_CNTL +#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL__SHIFT 0x0 +#define DTBCLK_P_CNTL__DTBCLK_P0_EN__SHIFT 0x2 +#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL__SHIFT 0x3 +#define DTBCLK_P_CNTL__DTBCLK_P1_EN__SHIFT 0x5 +#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL__SHIFT 0x6 +#define DTBCLK_P_CNTL__DTBCLK_P2_EN__SHIFT 0x8 +#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL__SHIFT 0x9 +#define DTBCLK_P_CNTL__DTBCLK_P3_EN__SHIFT 0xb +#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL_MASK 0x00000003L +#define DTBCLK_P_CNTL__DTBCLK_P0_EN_MASK 0x00000004L +#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL_MASK 0x00000018L +#define DTBCLK_P_CNTL__DTBCLK_P1_EN_MASK 0x00000020L +#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL_MASK 0x000000C0L +#define DTBCLK_P_CNTL__DTBCLK_P2_EN_MASK 0x00000100L +#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL_MASK 0x00000600L +#define DTBCLK_P_CNTL__DTBCLK_P3_EN_MASK 0x00000800L +//DCCG_GATE_DISABLE_CNTL5 +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE__SHIFT 0x7 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE__SHIFT 0xd +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE_MASK 0x00000080L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE_MASK 0x00002000L +//DSCCLK0_DTO_PARAM +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT 0x0 +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT 0x10 +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK 0x00FF0000L +//DSCCLK1_DTO_PARAM +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT 0x0 +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT 0x10 +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK 0x00FF0000L +//DSCCLK2_DTO_PARAM +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT 0x0 +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT 0x10 +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK 0x00FF0000L +//OTG_PIXEL_RATE_DIV +#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK1__SHIFT 0x0 +#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK2__SHIFT 0x1 +#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK1__SHIFT 0x3 +#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK2__SHIFT 0x4 +#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK1__SHIFT 0x6 +#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK2__SHIFT 0x7 +#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK1__SHIFT 0x9 +#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK2__SHIFT 0xa +#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK1_MASK 0x00000001L +#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK2_MASK 0x00000006L +#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK1_MASK 0x00000008L +#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK2_MASK 0x00000030L +#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK1_MASK 0x00000040L +#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK2_MASK 0x00000180L +#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK1_MASK 0x00000200L +#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK2_MASK 0x00000C00L +//MILLISECOND_TIME_BASE_DIV +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001FFFFL +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +//DISPCLK_FREQ_CHANGE_CNTL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003FFFL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000F0000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0E000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L +//DC_MEM_GLOBAL_PWR_REQ_CNTL +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L +//DCCG_GATE_DISABLE_CNTL +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x00020000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x00040000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x00080000L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x08000000L +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000L +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000L +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000L +//DISPCLK_CGTT_BLK_CTRL_REG +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//SOCCLK_CGTT_BLK_CTRL_REG +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_CAC_STATUS +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xFFFFFFFFL +//MICROSECOND_TIME_BASE_DIV +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007FL +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007F00L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +//DCCG_GATE_DISABLE_CNTL2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE__SHIFT 0xd +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE__SHIFT 0x18 +#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE__SHIFT 0x19 +#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x00000020L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE_MASK 0x00002000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x00010000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x00020000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x00040000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x00080000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x00100000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x00200000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE_MASK 0x01000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE_MASK 0x02000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE_MASK 0x08000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE_MASK 0x10000000L +//SYMCLK_CGTT_BLK_CTRL_REG +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_DISP_CNTL_REG +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x00000100L +//OTG0_PIXEL_RATE_CNTL +#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE__SHIFT 0x3 +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 +#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS__SHIFT 0x6 +#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS__SHIFT 0x7 +#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT 0x8 +#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT 0x9 +#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL__SHIFT 0xc +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE_MASK 0x00000008L +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x00000020L +#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS_MASK 0x00000040L +#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS_MASK 0x00000080L +#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK 0x00000100L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK 0x00000200L +#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL_MASK 0x00003000L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO0_PHASE +#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 +#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xFFFFFFFFL +//DP_DTO0_MODULO +#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 +#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xFFFFFFFFL +//OTG0_PHYPLL_PIXEL_RATE_CNTL +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG1_PIXEL_RATE_CNTL +#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE__SHIFT 0x3 +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 +#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS__SHIFT 0x6 +#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS__SHIFT 0x7 +#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT 0x8 +#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT 0x9 +#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL__SHIFT 0xc +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE_MASK 0x00000008L +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x00000020L +#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS_MASK 0x00000040L +#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS_MASK 0x00000080L +#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK 0x00000100L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK 0x00000200L +#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL_MASK 0x00003000L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO1_PHASE +#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 +#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xFFFFFFFFL +//DP_DTO1_MODULO +#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 +#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xFFFFFFFFL +//OTG1_PHYPLL_PIXEL_RATE_CNTL +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG2_PIXEL_RATE_CNTL +#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE__SHIFT 0x3 +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4 +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5 +#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS__SHIFT 0x6 +#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS__SHIFT 0x7 +#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT 0x8 +#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT 0x9 +#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL__SHIFT 0xc +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE_MASK 0x00000008L +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x00000020L +#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS_MASK 0x00000040L +#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS_MASK 0x00000080L +#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK 0x00000100L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK 0x00000200L +#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL_MASK 0x00003000L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO2_PHASE +#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0 +#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xFFFFFFFFL +//DP_DTO2_MODULO +#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0 +#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xFFFFFFFFL +//OTG2_PHYPLL_PIXEL_RATE_CNTL +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG3_PIXEL_RATE_CNTL +#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE__SHIFT 0x3 +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4 +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5 +#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS__SHIFT 0x6 +#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS__SHIFT 0x7 +#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT 0x8 +#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT 0x9 +#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL__SHIFT 0xc +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE_MASK 0x00000008L +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x00000020L +#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS_MASK 0x00000040L +#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS_MASK 0x00000080L +#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK 0x00000100L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK 0x00000200L +#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL_MASK 0x00003000L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO3_PHASE +#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0 +#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xFFFFFFFFL +//DP_DTO3_MODULO +#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0 +#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xFFFFFFFFL +//OTG3_PHYPLL_PIXEL_RATE_CNTL +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//DPPCLK_CGTT_BLK_CTRL_REG +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DPPCLK0_DTO_PARAM +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT 0x0 +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT 0x10 +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK1_DTO_PARAM +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT 0x0 +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT 0x10 +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK2_DTO_PARAM +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT 0x0 +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT 0x10 +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK3_DTO_PARAM +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT 0x0 +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT 0x10 +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK 0x00FF0000L +//DCCG_CAC_STATUS2 +#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT 0x0 +#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK 0x0007FFFFL +//SYMCLKA_CLOCK_ENABLE +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKB_CLOCK_ENABLE +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKC_CLOCK_ENABLE +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKD_CLOCK_ENABLE +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKE_CLOCK_ENABLE +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x00000700L +//DCCG_SOFT_RESET +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 +#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 +#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10 +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11 +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12 +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13 +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14 +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15 +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L +#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L +#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x00000010L +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x00000100L +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x00001000L +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x00002000L +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x00004000L +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x00008000L +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x00010000L +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x00020000L +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x00040000L +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x00080000L +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x00100000L +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x00200000L +//DSCCLK_DTO_CTRL +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE__SHIFT 0x0 +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE__SHIFT 0x1 +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE__SHIFT 0x2 +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE__SHIFT 0x3 +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE__SHIFT 0x4 +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE__SHIFT 0x5 +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT 0x8 +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT 0x9 +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT 0xa +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT 0xb +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT 0xc +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT 0xd +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE_MASK 0x00000001L +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE_MASK 0x00000002L +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE_MASK 0x00000004L +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE_MASK 0x00000008L +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE_MASK 0x00000010L +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE_MASK 0x00000020L +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK 0x00000100L +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK 0x00000200L +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK 0x00000400L +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK 0x00000800L +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK 0x00001000L +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK 0x00002000L +//DCCG_AUDIO_DTO_SOURCE +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO__SHIFT 0x1d +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000070L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x00100000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x01000000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO_MASK 0x20000000L +//DCCG_AUDIO_DTO0_PHASE +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO0_MODULE +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO1_PHASE +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO1_MODULE +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG0_LATCH_VALUE +#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG1_LATCH_VALUE +#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG2_LATCH_VALUE +#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG3_LATCH_VALUE +#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG4_LATCH_VALUE +#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG5_LATCH_VALUE +#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK 0xFFFFFFFFL +//DPPCLK_DTO_CTRL +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE__SHIFT 0x0 +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT 0x1 +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE__SHIFT 0x4 +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT 0x5 +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE__SHIFT 0x8 +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT 0x9 +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE__SHIFT 0xc +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT 0xd +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE__SHIFT 0x10 +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT 0x11 +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE__SHIFT 0x14 +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT 0x15 +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE_MASK 0x00000001L +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK 0x00000002L +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE_MASK 0x00000010L +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK 0x00000020L +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE_MASK 0x00000100L +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK 0x00000200L +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE_MASK 0x00001000L +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK 0x00002000L +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE_MASK 0x00010000L +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK 0x00020000L +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE_MASK 0x00100000L +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK 0x00200000L +//DCCG_VSYNC_CNT_CTRL +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT 0x0 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT 0x2 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT 0x3 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT 0x4 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT 0x8 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT 0x10 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT 0x11 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT 0x12 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT 0x13 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT 0x14 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT 0x15 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT 0x18 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT 0x19 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT 0x1a +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT 0x1b +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT 0x1c +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT 0x1d +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK 0x00000001L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK 0x00000004L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK 0x00000008L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK 0x000000F0L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK 0x00000F00L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK 0x00010000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK 0x00020000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK 0x00040000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK 0x00080000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK 0x00100000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK 0x00200000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK 0x01000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK 0x02000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK 0x04000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK 0x08000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK 0x10000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK 0x20000000L +//DCCG_VSYNC_CNT_INT_CTRL +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT 0x0 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT 0x0 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT 0x1 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT 0x1 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT 0x2 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT 0x2 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT 0x3 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT 0x3 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT 0x4 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT 0x4 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT 0x5 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT 0x5 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT 0x8 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT 0x9 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT 0xa +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT 0xb +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT 0xc +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT 0xd +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK 0x00000001L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK 0x00000001L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK 0x00000002L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK 0x00000002L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK 0x00000004L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK 0x00000004L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK 0x00000008L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK 0x00000008L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK 0x00000010L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK 0x00000010L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK 0x00000020L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK 0x00000020L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK 0x00000100L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK 0x00000200L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK 0x00000400L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK 0x00000800L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK 0x00001000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK 0x00002000L +//FORCE_SYMCLK_DISABLE +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT 0x0 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT 0x1 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT 0x2 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT 0x3 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT 0x4 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT 0x5 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT 0x6 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK 0x00000001L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK 0x00000002L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK 0x00000004L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK 0x00000008L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK 0x00000010L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK 0x00000020L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK 0x00000040L +//DCCG_TEST_CLK_SEL +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL__SHIFT 0xe +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000001FFL +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00001000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL_MASK 0x0000C000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x01FF0000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000L +//DTBCLK_DTO0_PHASE +#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE__SHIFT 0x0 +#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE_MASK 0xFFFFFFFFL +//DTBCLK_DTO1_PHASE +#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE__SHIFT 0x0 +#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE_MASK 0xFFFFFFFFL +//DTBCLK_DTO2_PHASE +#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE__SHIFT 0x0 +#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE_MASK 0xFFFFFFFFL +//DTBCLK_DTO3_PHASE +#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE__SHIFT 0x0 +#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE_MASK 0xFFFFFFFFL +//DTBCLK_DTO0_MODULO +#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO__SHIFT 0x0 +#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO_MASK 0xFFFFFFFFL +//DTBCLK_DTO1_MODULO +#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO__SHIFT 0x0 +#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO_MASK 0xFFFFFFFFL +//DTBCLK_DTO2_MODULO +#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO__SHIFT 0x0 +#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO_MASK 0xFFFFFFFFL +//DTBCLK_DTO3_MODULO +#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO__SHIFT 0x0 +#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO_MASK 0xFFFFFFFFL +//HDMICHARCLK0_CLOCK_CNTL +#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN__SHIFT 0x0 +#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL__SHIFT 0x4 +#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN_MASK 0x00000001L +#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL_MASK 0x00000070L +//PHYASYMCLK_CLOCK_CNTL +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN__SHIFT 0x0 +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL__SHIFT 0x4 +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN_MASK 0x00000001L +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL_MASK 0x00000030L +//PHYBSYMCLK_CLOCK_CNTL +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN__SHIFT 0x0 +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL__SHIFT 0x4 +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN_MASK 0x00000001L +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL_MASK 0x00000030L +//PHYCSYMCLK_CLOCK_CNTL +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_EN__SHIFT 0x0 +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_SRC_SEL__SHIFT 0x4 +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_EN_MASK 0x00000001L +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_SRC_SEL_MASK 0x00000030L +//PHYDSYMCLK_CLOCK_CNTL +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_EN__SHIFT 0x0 +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_SRC_SEL__SHIFT 0x4 +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_EN_MASK 0x00000001L +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_SRC_SEL_MASK 0x00000030L +//PHYESYMCLK_CLOCK_CNTL +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN__SHIFT 0x0 +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL__SHIFT 0x4 +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN_MASK 0x00000001L +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL_MASK 0x00000030L +//HDMISTREAMCLK_CNTL +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL__SHIFT 0x0 +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN__SHIFT 0x3 +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_DTO_FORCE_DIS__SHIFT 0x4 +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL_MASK 0x00000007L +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN_MASK 0x00000008L +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_DTO_FORCE_DIS_MASK 0x00000010L +//DCCG_GATE_DISABLE_CNTL3 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE__SHIFT 0xd +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE__SHIFT 0xe +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE__SHIFT 0xf +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE__SHIFT 0x17 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE_MASK 0x00000020L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE_MASK 0x00002000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE_MASK 0x00004000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE_MASK 0x00008000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE_MASK 0x00100000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE_MASK 0x00200000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE_MASK 0x00800000L +//HDMISTREAMCLK0_DTO_PARAM +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE__SHIFT 0x0 +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO__SHIFT 0x8 +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN__SHIFT 0x10 +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE_MASK 0x000000FFL +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO_MASK 0x0000FF00L +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN_MASK 0x00010000L +//DCCG_AUDIO_DTBCLK_DTO_PHASE +#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTBCLK_DTO_MODULO +#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO__SHIFT 0x0 +#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO_MASK 0xFFFFFFFFL +//DTBCLK_DTO_DBUF_EN +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN__SHIFT 0x0 +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN__SHIFT 0x1 +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN__SHIFT 0x2 +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN__SHIFT 0x3 +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN_MASK 0x00000001L +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN_MASK 0x00000002L +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN_MASK 0x00000004L +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN_MASK 0x00000008L +//DMCUBCLK_CNTL +#define DMCUBCLK_CNTL__DMCUBCLK_SRC_SEL__SHIFT 0x0 +#define DMCUBCLK_CNTL__DMCUBCLK_SRC_SEL_MASK 0x00000003L + + + + +// addressBlock: dcn_dc_dmu_rbbmif_dispdec +//RBBMIF_TIMEOUT +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14 +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0x000FFFFFL +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xFFF00000L +//RBBMIF_STATUS +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0xFFFFFFFFL +//RBBMIF_STATUS_2 +#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT 0x0 +#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK 0x0000007FL +//RBBMIF_INT_STATUS +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT 0x2 +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK 0x0003FFFCL +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000L +//RBBMIF_TIMEOUT_DIS +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0 +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1 +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2 +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3 +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4 +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5 +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6 +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7 +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8 +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9 +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe +#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT 0xf +#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT 0x10 +#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT 0x11 +#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT 0x12 +#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT 0x13 +#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT 0x14 +#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT 0x15 +#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT 0x16 +#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT 0x17 +#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT 0x18 +#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT 0x19 +#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT 0x1a +#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT 0x1b +#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT 0x1c +#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT 0x1d +#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT 0x1e +#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT 0x1f +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x00000001L +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x00000002L +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x00000004L +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x00000008L +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x00000010L +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x00000020L +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x00000040L +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x00000080L +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x00000100L +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x00000200L +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x00000400L +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x00000800L +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x00001000L +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x00002000L +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x00004000L +#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK 0x00008000L +#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK 0x00010000L +#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK 0x00020000L +#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK 0x00040000L +#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK 0x00080000L +#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK 0x00100000L +#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK 0x00200000L +#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK 0x00400000L +#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK 0x00800000L +#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK 0x01000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK 0x02000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK 0x04000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK 0x08000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK 0x10000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK 0x20000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK 0x40000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK 0x80000000L +//RBBMIF_TIMEOUT_DIS_2 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT 0x0 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT 0x1 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT 0x2 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT 0x3 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT 0x4 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT 0x5 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS__SHIFT 0x6 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK 0x00000001L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK 0x00000002L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK 0x00000004L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK 0x00000008L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK 0x00000010L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK 0x00000020L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS_MASK 0x00000040L +//RBBMIF_STATUS_FLAG +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0 +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT 0x8 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT 0x9 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT 0x10 +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x00000003L +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x00000010L +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x00000020L +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x00000040L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK 0x00000100L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK 0x00000E00L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK 0xFFFF0000L + + +//DC_GPU_TIMER_START_POSITION_V_UPDATE +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_VSTARTUP +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK 0x00700000L +//DC_GPU_TIMER_READ +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xFFFFFFFFL +//DC_GPU_TIMER_READ_CNTL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000007FL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001C000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000E0000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L +//DISP_INTERRUPT_STATUS +#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE +#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE2 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE3 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE6 +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE7 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE8 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE9 +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE10 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE11 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE12 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE13 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE14 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE15 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE16 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE17 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE18 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE19 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE20 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE21 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE22 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK 0x80000000L +//DC_GPU_TIMER_START_POSITION_VREADY +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_FLIP +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT 0x18 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT 0x1c +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK 0x07000000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK 0x70000000L +//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_FLIP_AWAY +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT 0x18 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT 0x1c +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK 0x07000000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK 0x70000000L +//DISP_INTERRUPT_STATUS_CONTINUE23 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE24 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE25 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT_MASK 0x40000000L +//DCCG_INTERRUPT_DEST +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT 0x0 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT 0x1 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT 0x2 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT 0x3 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT 0x4 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT 0x5 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK 0x00000001L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK 0x00000002L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK 0x00000004L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK 0x00000008L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK 0x00000010L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK 0x00000020L +//DMU_INTERRUPT_DEST +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT 0x0 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT 0x1 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT 0x2 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT 0x3 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT 0x4 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST__SHIFT 0x5 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST__SHIFT 0x6 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST__SHIFT 0x7 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST__SHIFT 0x8 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST__SHIFT 0x9 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT 0xa +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT 0xb +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT 0xc +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT 0xd +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT 0xe +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT 0xf +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT 0x10 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT 0x11 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT 0x1a +#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1b +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK 0x00000001L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK 0x00000002L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK 0x00000004L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK 0x00000008L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK 0x00000010L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST_MASK 0x00000020L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST_MASK 0x00000040L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST_MASK 0x00000080L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST_MASK 0x00000100L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST_MASK 0x00000200L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK 0x00000400L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK 0x00000800L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK 0x00001000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK 0x00002000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK 0x00004000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK 0x00008000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK 0x00010000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK 0x00020000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK 0x04000000L +#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x08000000L +//DMU_INTERRUPT_DEST2 +#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST__SHIFT 0xc +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST__SHIFT 0xd +#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST_MASK 0x00001000L +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST_MASK 0x00002000L +//DCPG_INTERRUPT_DEST +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT 0x0 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT 0x1 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT 0x2 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT 0x3 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT 0x4 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT 0x5 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT 0x6 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT 0x7 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x10 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x11 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x12 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x13 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x14 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x15 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x16 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x17 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK 0x00000001L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK 0x00000002L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK 0x00000004L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK 0x00000008L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK 0x00000010L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK 0x00000020L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK 0x00000040L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK 0x00000080L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK 0x00010000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK 0x00020000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK 0x00040000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK 0x00080000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK 0x00100000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK 0x00200000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK 0x00400000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK 0x00800000L +//DCPG_INTERRUPT_DEST2 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT 0x0 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT 0x1 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT 0x2 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT 0x3 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT 0x4 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT 0x5 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x6 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x7 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x8 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x9 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT 0xa +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT 0xb +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK 0x00000001L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK 0x00000002L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK 0x00000004L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK 0x00000008L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK 0x00000010L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK 0x00000020L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000040L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000080L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000100L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000200L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000400L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000800L +//MMHUBBUB_INTERRUPT_DEST +#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST__SHIFT 0x0 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT 0x1 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT 0x2 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT 0x3 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT 0x4 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT 0x5 +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST__SHIFT 0x8 +#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST_MASK 0x00000001L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK 0x00000002L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK 0x00000004L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK 0x00000008L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK 0x00000010L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK 0x00000020L +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST_MASK 0x00000100L +//WB_INTERRUPT_DEST +#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0x1 +#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0x9 +#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0xb +#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000002L +#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000200L +#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000800L +//DCHUB_INTERRUPT_DEST +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x0 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x1 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x2 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x3 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x4 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x5 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x6 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x7 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x8 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x9 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0xa +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0xb +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x10 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x11 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x12 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x13 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x14 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x15 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x16 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x17 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x1a +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1b +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x1c +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x1d +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x1e +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1f +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000001L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000002L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000004L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000008L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000010L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000020L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000040L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000080L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000100L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000200L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000400L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000800L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00010000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK 0x00020000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00040000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00080000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00100000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK 0x00200000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00400000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00800000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK 0x02000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK 0x04000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x08000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK 0x10000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK 0x20000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK 0x40000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x80000000L +//DCHUB_PERFCOUNTER_INTERRUPT_DEST +//DCHUB_INTERRUPT_DEST2 +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x0 +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x1 +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x2 +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x3 +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x4 +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x5 +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x6 +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x7 +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x8 +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x9 +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xa +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xb +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST__SHIFT 0x1a +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000001L +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000002L +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000004L +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000008L +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000010L +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000020L +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000040L +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000080L +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000100L +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000200L +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000400L +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000800L +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x02000000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST_MASK 0x04000000L +//DPP_PERFCOUNTER_INTERRUPT_DEST +//MPC_INTERRUPT_DEST +#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT 0x0 +#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT 0x1 +#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT 0x2 +#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT 0x3 +#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT 0x4 +#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT 0x5 +#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT 0x6 +#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT 0x7 +#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK 0x00000001L +#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK 0x00000002L +#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK 0x00000004L +#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK 0x00000008L +#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK 0x00000010L +#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK 0x00000020L +#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK 0x00000040L +#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK 0x00000080L +//OPP_INTERRUPT_DEST +//OPTC_INTERRUPT_DEST +#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x18 +#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x19 +#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1a +#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1b +#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1c +#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1d +#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x01000000L +#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x02000000L +#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x04000000L +#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x08000000L +#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x10000000L +#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x20000000L +//OTG0_INTERRUPT_DEST +#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG1_INTERRUPT_DEST +#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG2_INTERRUPT_DEST +#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG3_INTERRUPT_DEST +#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG4_INTERRUPT_DEST +#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG5_INTERRUPT_DEST +#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//DIG_INTERRUPT_DEST +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x0 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x1 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x2 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x3 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x4 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x5 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x6 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x7 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0x8 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0x9 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xa +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xb +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xc +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xd +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xe +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xf +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000001L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000002L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000004L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000008L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000010L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000020L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000040L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000080L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000100L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000200L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000400L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000800L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00001000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00002000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00004000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00008000L +//I2C_DDC_HPD_INTERRUPT_DEST +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT 0x0 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT 0x1 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT 0x2 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT 0x3 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT 0x4 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT 0x5 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT 0x6 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT 0x7 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x10 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x11 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x12 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x13 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x14 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x15 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT 0x16 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK 0x00000001L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK 0x00000002L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK 0x00000004L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK 0x00000008L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK 0x00000010L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK 0x00000020L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK 0x00000040L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK 0x00000080L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK 0x00010000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK 0x00020000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK 0x00040000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK 0x00080000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK 0x00100000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK 0x00200000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK 0x00400000L +//DIO_INTERRUPT_DEST +#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST__SHIFT 0x4 +#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST_MASK 0x00000010L +//DCIO_INTERRUPT_DEST +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x0 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x1 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x2 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x3 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x4 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x5 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x6 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x10 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000001L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000002L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000004L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000008L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000010L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000020L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000040L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK 0x00010000L +//HPD_INTERRUPT_DEST +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT 0x0 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT 0x1 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT 0x2 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT 0x3 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT 0x4 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT 0x5 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT 0x8 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT 0x9 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT 0xa +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT 0xb +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT 0xc +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT 0xd +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK 0x00000001L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK 0x00000002L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK 0x00000004L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK 0x00000008L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK 0x00000010L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK 0x00000020L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK 0x00000100L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK 0x00000200L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK 0x00000400L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK 0x00000800L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK 0x00001000L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK 0x00002000L +//AZ_INTERRUPT_DEST +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x0 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x1 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x2 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x3 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x4 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x5 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x6 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x7 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT 0x8 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT 0x9 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT 0xa +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT 0xb +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT 0xc +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT 0xd +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT 0xe +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT 0xf +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT 0x10 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT 0x11 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT 0x12 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT 0x13 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT 0x14 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT 0x15 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT 0x16 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT 0x17 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000001L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000002L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000004L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000008L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000010L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000020L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000040L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000080L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK 0x00000100L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK 0x00000200L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK 0x00000400L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK 0x00000800L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK 0x00001000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK 0x00002000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK 0x00004000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK 0x00008000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK 0x00010000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK 0x00020000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK 0x00040000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK 0x00080000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK 0x00100000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK 0x00200000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK 0x00400000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK 0x00800000L +//AUX_INTERRUPT_DEST +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT 0x0 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT 0x1 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT 0x2 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT 0x3 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT 0x4 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT 0x5 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT 0x6 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT 0x7 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT 0x8 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT 0x9 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT 0xa +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT 0xb +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x10 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x11 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x12 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x13 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x14 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x15 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x16 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x17 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x18 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x19 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x1a +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x1b +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK 0x00000001L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK 0x00000002L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK 0x00000004L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK 0x00000008L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK 0x00000010L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK 0x00000020L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK 0x00000040L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK 0x00000080L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK 0x00000100L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK 0x00000200L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK 0x00000400L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK 0x00000800L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00010000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00020000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00040000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00080000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00100000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00200000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00400000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00800000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x01000000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x02000000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x04000000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x08000000L +//DSC_INTERRUPT_DEST +#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x0 +#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x1 +#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x4 +#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x5 +#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x8 +#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x9 +#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0xc +#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0xd +#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x10 +#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x11 +#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x14 +#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x15 +#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000001L +#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000002L +#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000010L +#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000020L +#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000100L +#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000200L +#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00001000L +#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00002000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00010000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00020000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00100000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00200000L +//HPO_INTERRUPT_DEST + + +//CC_DC_PIPE_DIS +#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x0 +#define CC_DC_PIPE_DIS__DC_FULL_DIS__SHIFT 0xc +#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT 0x10 +#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x000000FFL +#define CC_DC_PIPE_DIS__DC_FULL_DIS_MASK 0x00001000L +#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK 0x00010000L +//DMU_CLK_CNTL +#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT 0x0 +#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT 0x4 +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT 0x6 +#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT 0x8 +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT 0xa +#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK 0x0000000FL +#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK 0x00000010L +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK 0x00000040L +#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK 0x00000100L +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK 0x00000400L +//DMCUB_SMU_INTERRUPT_CNTL +#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT__SHIFT 0x0 +#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG__SHIFT 0x10 +#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT_MASK 0x00000001L +#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_MASK 0xFFFF0000L +//SMU_INTERRUPT_CONTROL +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x00000001L +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x00000010L +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xFFFF0000L +//DMU_MISC_ALLOW_DS_FORCE +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT 0x0 +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT 0x4 +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK 0x00000001L +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK 0x00000010L + + +//DOMAIN0_PG_CONFIG +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN0_PG_STATUS +#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN1_PG_CONFIG +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN1_PG_STATUS +#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN2_PG_CONFIG +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN2_PG_STATUS +#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN3_PG_CONFIG +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN3_PG_STATUS +#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN16_PG_CONFIG +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN16_PG_STATUS +#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN17_PG_CONFIG +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN17_PG_STATUS +#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN18_PG_CONFIG +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN18_PG_STATUS +#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN19_PG_CONFIG +#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN19_PG_STATUS +#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DCPG_INTERRUPT_STATUS +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK 0x00000040L +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L +//DCPG_INTERRUPT_STATUS_2 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED_MASK 0x00000040L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L +//DCPG_INTERRUPT_CONTROL_1 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT 0xc +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT 0xe +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK 0x00000001L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK 0x00000004L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK 0x00000008L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK 0x00000010L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK 0x00000040L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK 0x00000100L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK 0x00000400L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK 0x00001000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK 0x00004000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +//DCPG_INTERRUPT_CONTROL_3 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK__SHIFT 0xc +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK__SHIFT 0xe +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK_MASK 0x00000001L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK_MASK 0x00000004L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK 0x00000008L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK_MASK 0x00000010L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK_MASK 0x00000040L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK_MASK 0x00000100L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK_MASK 0x00000400L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK_MASK 0x00001000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK_MASK 0x00004000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +//DC_IP_REQUEST_CNTL +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0 +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x00000001L + + +// addressBlock: dcn_dc_dmu_dmcub_dispdec +//DMCUB_REGION0_OFFSET +#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT 0x8 +#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION0_OFFSET_HIGH +#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION1_OFFSET +#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT 0x8 +#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION1_OFFSET_HIGH +#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION2_OFFSET +#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT 0x8 +#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION2_OFFSET_HIGH +#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION4_OFFSET +#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT 0x8 +#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION4_OFFSET_HIGH +#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION5_OFFSET +#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT 0x8 +#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION5_OFFSET_HIGH +#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION6_OFFSET +#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT 0x8 +#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION6_OFFSET_HIGH +#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION7_OFFSET +#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT 0x8 +#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION7_OFFSET_HIGH +#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION0_TOP_ADDRESS +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT 0x1f +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK 0x80000000L +//DMCUB_REGION1_TOP_ADDRESS +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT 0x1f +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK 0x80000000L +//DMCUB_REGION2_TOP_ADDRESS +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT 0x1f +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK 0x80000000L +//DMCUB_REGION4_TOP_ADDRESS +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT 0x1f +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK 0x80000000L +//DMCUB_REGION5_TOP_ADDRESS +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT 0x1f +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK 0x80000000L +//DMCUB_REGION6_TOP_ADDRESS +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT 0x1f +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK 0x80000000L +//DMCUB_REGION7_TOP_ADDRESS +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT 0x1f +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW0_BASE_ADDRESS +#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW1_BASE_ADDRESS +#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW2_BASE_ADDRESS +#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW3_BASE_ADDRESS +#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW4_BASE_ADDRESS +#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW5_BASE_ADDRESS +#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW6_BASE_ADDRESS +#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW7_BASE_ADDRESS +#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW0_TOP_ADDRESS +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW1_TOP_ADDRESS +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW2_TOP_ADDRESS +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW3_TOP_ADDRESS +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW4_TOP_ADDRESS +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW5_TOP_ADDRESS +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW6_TOP_ADDRESS +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW7_TOP_ADDRESS +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW0_OFFSET +#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW0_OFFSET_HIGH +#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW1_OFFSET +#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW1_OFFSET_HIGH +#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW2_OFFSET +#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW2_OFFSET_HIGH +#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW3_OFFSET +#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW3_OFFSET_HIGH +#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW4_OFFSET +#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW4_OFFSET_HIGH +#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW5_OFFSET +#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW5_OFFSET_HIGH +#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW6_OFFSET +#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW6_OFFSET_HIGH +#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW7_OFFSET +#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW7_OFFSET_HIGH +#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_INTERRUPT_ENABLE +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT 0x0 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT 0x1 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT 0x2 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT 0x3 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT 0x4 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT 0x5 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT 0x6 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT 0x7 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT 0x8 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT 0x9 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT 0xa +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT 0xb +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT 0xc +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN__SHIFT 0xd +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN__SHIFT 0xe +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN__SHIFT 0xf +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN__SHIFT 0x10 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN__SHIFT 0x11 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT 0x12 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK 0x00000001L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK 0x00000002L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK 0x00000004L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK 0x00000008L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK 0x00000010L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK 0x00000020L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK 0x00000040L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK 0x00000080L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK 0x00000100L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK 0x00000200L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK 0x00000400L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK 0x00000800L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK 0x00001000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN_MASK 0x00002000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN_MASK 0x00004000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN_MASK 0x00008000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN_MASK 0x00010000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN_MASK 0x00020000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK 0x00040000L +//DMCUB_INTERRUPT_ACK +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT 0x0 +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT 0x1 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT 0x2 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT 0x3 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT 0x4 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT 0x5 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT 0x6 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT 0x7 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT 0x8 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT 0x9 +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT 0xa +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT 0xb +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT 0xc +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK__SHIFT 0xd +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK__SHIFT 0xe +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK__SHIFT 0xf +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK__SHIFT 0x10 +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK__SHIFT 0x11 +#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT 0x12 +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK 0x00000001L +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK 0x00000002L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK 0x00000004L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK 0x00000008L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK 0x00000010L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK 0x00000020L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK 0x00000040L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK 0x00000080L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK 0x00000100L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK 0x00000200L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK 0x00000400L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK 0x00000800L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK 0x00001000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK_MASK 0x00002000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK_MASK 0x00004000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK_MASK 0x00008000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK_MASK 0x00010000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK_MASK 0x00020000L +#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK 0x00040000L +//DMCUB_INTERRUPT_STATUS +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT 0x0 +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT 0x1 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT 0x2 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT 0x3 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT 0x4 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT 0x5 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT 0x6 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT 0x7 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT 0x8 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT 0x9 +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT 0xa +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT 0xb +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT 0xc +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT__SHIFT 0xd +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT__SHIFT 0xe +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT__SHIFT 0xf +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT__SHIFT 0x10 +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT__SHIFT 0x11 +#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT 0x12 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT 0x13 +#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT 0x14 +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK 0x00000001L +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK 0x00000002L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK 0x00000004L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK 0x00000008L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK 0x00000010L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK 0x00000020L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK 0x00000040L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK 0x00000080L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK 0x00000100L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK 0x00000200L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK 0x00000400L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK 0x00000800L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK 0x00001000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT_MASK 0x00002000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT_MASK 0x00004000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT_MASK 0x00008000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT_MASK 0x00010000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT_MASK 0x00020000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK 0x00040000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK 0x00080000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK 0x00100000L +//DMCUB_INTERRUPT_TYPE +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT 0x0 +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT 0x1 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT 0x2 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT 0x3 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT 0x4 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT 0x5 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT 0x6 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT 0x7 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT 0x8 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT 0x9 +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT 0xa +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT 0xb +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT 0xc +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE__SHIFT 0xd +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE__SHIFT 0xe +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE__SHIFT 0xf +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE__SHIFT 0x10 +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE__SHIFT 0x11 +#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT 0x12 +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK 0x00000001L +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK 0x00000002L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK 0x00000004L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK 0x00000008L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK 0x00000010L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK 0x00000020L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK 0x00000040L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK 0x00000080L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK 0x00000100L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK 0x00000200L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK 0x00000400L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK 0x00000800L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK 0x00001000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE_MASK 0x00002000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE_MASK 0x00004000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE_MASK 0x00008000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE_MASK 0x00010000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE_MASK 0x00020000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK 0x00040000L +//DMCUB_EXT_INTERRUPT_STATUS +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT 0x8 +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK 0x000000FFL +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK 0x0000FF00L +//DMCUB_EXT_INTERRUPT_CTXID +#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK 0x0FFFFFFFL +//DMCUB_EXT_INTERRUPT_ACK +#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK 0x00000001L +//DMCUB_INST_FETCH_FAULT_ADDR +#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_DATA_WRITE_FAULT_ADDR +#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_SEC_CNTL +#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL__SHIFT 0x0 +#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT 0x8 +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT 0x10 +#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT 0x11 +#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT 0x14 +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT 0x15 +#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT 0x18 +#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT 0x19 +#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL_MASK 0x00000007L +#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK 0x00003F00L +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK 0x00010000L +#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK 0x00020000L +#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK 0x00100000L +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK 0x00200000L +#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK 0x01000000L +#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK 0x02000000L +//DMCUB_MEM_CNTL +#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT 0x0 +#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT 0x4 +#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK 0x0000000FL +#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK 0x000000F0L +//DMCUB_INBOX0_BASE_ADDRESS +#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_SIZE +#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT 0x0 +#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_WPTR +#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT 0x0 +#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_RPTR +#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT 0x0 +#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_BASE_ADDRESS +#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_SIZE +#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT 0x0 +#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_WPTR +#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT 0x0 +#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_RPTR +#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT 0x0 +#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_BASE_ADDRESS +#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_SIZE +#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT 0x0 +#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_WPTR +#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT 0x0 +#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_RPTR +#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT 0x0 +#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_BASE_ADDRESS +#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_SIZE +#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT 0x0 +#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_WPTR +#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT 0x0 +#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_RPTR +#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT 0x0 +#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK 0xFFFFFFFFL +//DMCUB_TIMER_TRIGGER0 +#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT 0x0 +#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK 0xFFFFFFFFL +//DMCUB_TIMER_TRIGGER1 +#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT 0x0 +#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK 0xFFFFFFFFL +//DMCUB_TIMER_WINDOW +#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT 0x0 +#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK 0x00000007L +//DMCUB_SCRATCH0 +#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT 0x0 +#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH1 +#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT 0x0 +#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH2 +#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT 0x0 +#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH3 +#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT 0x0 +#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH4 +#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT 0x0 +#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH5 +#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT 0x0 +#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH6 +#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT 0x0 +#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH7 +#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT 0x0 +#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH8 +#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT 0x0 +#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH9 +#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT 0x0 +#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH10 +#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT 0x0 +#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH11 +#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT 0x0 +#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH12 +#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT 0x0 +#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH13 +#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT 0x0 +#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH14 +#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT 0x0 +#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH15 +#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT 0x0 +#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH16 +#define DMCUB_SCRATCH16__DMCUB_SCRATCH16__SHIFT 0x0 +#define DMCUB_SCRATCH16__DMCUB_SCRATCH16_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH17 +#define DMCUB_SCRATCH17__DMCUB_SCRATCH17__SHIFT 0x0 +#define DMCUB_SCRATCH17__DMCUB_SCRATCH17_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH18 +#define DMCUB_SCRATCH18__DMCUB_SCRATCH18__SHIFT 0x0 +#define DMCUB_SCRATCH18__DMCUB_SCRATCH18_MASK 0xFFFFFFFFL +//DMCUB_CNTL +#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT 0x0 +#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT 0x8 +#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT 0x10 +#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT 0x12 +#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT 0x13 +#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT 0x14 +#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK 0x000000FFL +#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK 0x00000100L +#define DMCUB_CNTL__DMCUB_ENABLE_MASK 0x00010000L +#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK 0x00040000L +#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK 0x00080000L +#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK 0x00100000L +//DMCUB_GPINT_DATAIN0 +#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN1 +#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAOUT +#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT 0x0 +#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK 0xFFFFFFFFL +//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR +#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_LS_WAKE_INT_ENABLE +#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT 0x0 +#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK 0xFFFFFFFFL +//DMCUB_MEM_PWR_CNTL +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT 0x1 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT 0x3 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT 0x4 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK 0x00000006L +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK 0x00000008L +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK 0x00000030L +//DMCUB_TIMER_CURRENT +#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT 0x0 +#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK 0xFFFFFFFFL +//DMCUB_PROC_ID +#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT 0x0 +#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK 0x0000FFFFL +//DMCUB_CNTL2 +#define DMCUB_CNTL2__DMCUB_SOFT_RESET__SHIFT 0x0 +#define DMCUB_CNTL2__DMCUB_SOFT_RESET_MASK 0x00000001L +//DMCUB_GPINT_DATAIN2 +#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN3 +#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN4 +#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN5 +#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN6 +#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6_MASK 0xFFFFFFFFL +//DMCUB_REGION3_TMR_AXI_SPACE +#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE__SHIFT 0x0 +#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE_MASK 0x07L +//DMCUB_SCRATCH19 +#define DMCUB_SCRATCH19__DMCUB_SCRATCH19__SHIFT 0x0 +#define DMCUB_SCRATCH19__DMCUB_SCRATCH19_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH20 +#define DMCUB_SCRATCH20__DMCUB_SCRATCH20__SHIFT 0x0 +#define DMCUB_SCRATCH20__DMCUB_SCRATCH20_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH21 +#define DMCUB_SCRATCH21__DMCUB_SCRATCH21__SHIFT 0x0 +#define DMCUB_SCRATCH21__DMCUB_SCRATCH21_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH22 +#define DMCUB_SCRATCH22__DMCUB_SCRATCH22__SHIFT 0x0 +#define DMCUB_SCRATCH22__DMCUB_SCRATCH22_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH23 +#define DMCUB_SCRATCH23__DMCUB_SCRATCH23__SHIFT 0x0 +#define DMCUB_SCRATCH23__DMCUB_SCRATCH23_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_wb0_dispdec_dwb_top_dispdec +//DWB_ENABLE_CLK_CTRL +#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE__SHIFT 0x0 +#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS__SHIFT 0x4 +#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS__SHIFT 0x8 +#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL__SHIFT 0xc +#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE_MASK 0x00000001L +#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS_MASK 0x00000010L +#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS_MASK 0x00000100L +#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL_MASK 0x00003000L +//DWB_MEM_PWR_CTRL +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE__SHIFT 0x8 +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS__SHIFT 0xa +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE__SHIFT 0xc +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE__SHIFT 0x10 +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS__SHIFT 0x12 +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE__SHIFT 0x14 +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE_MASK 0x00000300L +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS_MASK 0x00000400L +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE_MASK 0x00003000L +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE_MASK 0x00030000L +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS_MASK 0x00040000L +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE_MASK 0x00300000L +//FC_MODE_CTRL +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN__SHIFT 0x0 +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE__SHIFT 0x4 +#define FC_MODE_CTRL__FC_WINDOW_CROP_EN__SHIFT 0x8 +#define FC_MODE_CTRL__FC_EYE_SELECTION__SHIFT 0xc +#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY__SHIFT 0x10 +#define FC_MODE_CTRL__FC_NEW_CONTENT__SHIFT 0x14 +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT__SHIFT 0x1f +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_MASK 0x00000001L +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE_MASK 0x00000030L +#define FC_MODE_CTRL__FC_WINDOW_CROP_EN_MASK 0x00000100L +#define FC_MODE_CTRL__FC_EYE_SELECTION_MASK 0x00003000L +#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY_MASK 0x00010000L +#define FC_MODE_CTRL__FC_NEW_CONTENT_MASK 0x00100000L +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT_MASK 0x80000000L +//FC_FLOW_CTRL +#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT__SHIFT 0x0 +#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT_MASK 0x00000FFFL +//FC_WINDOW_START +#define FC_WINDOW_START__FC_WINDOW_START_X__SHIFT 0x0 +#define FC_WINDOW_START__FC_WINDOW_START_Y__SHIFT 0x10 +#define FC_WINDOW_START__FC_WINDOW_START_X_MASK 0x00001FFFL +#define FC_WINDOW_START__FC_WINDOW_START_Y_MASK 0x1FFF0000L +//FC_WINDOW_SIZE +#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH__SHIFT 0x0 +#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT__SHIFT 0x10 +#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH_MASK 0x00000FFFL +#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT_MASK 0x0FFF0000L +//FC_SOURCE_SIZE +#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH__SHIFT 0x0 +#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT__SHIFT 0x10 +#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH_MASK 0x00007FFFL +#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT_MASK 0x7FFF0000L +//DWB_UPDATE_CTRL +#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK__SHIFT 0x0 +#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING__SHIFT 0x4 +#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK_MASK 0x00000001L +#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING_MASK 0x00000010L +//DWB_CRC_CTRL +#define DWB_CRC_CTRL__DWB_CRC_EN__SHIFT 0x0 +#define DWB_CRC_CTRL__DWB_CRC_CONT_EN__SHIFT 0x4 +#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL__SHIFT 0x8 +#define DWB_CRC_CTRL__DWB_CRC_EN_MASK 0x00000001L +#define DWB_CRC_CTRL__DWB_CRC_CONT_EN_MASK 0x00000010L +#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL_MASK 0x00000300L +//DWB_CRC_MASK_R_G +#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK__SHIFT 0x0 +#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK__SHIFT 0x10 +#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK_MASK 0x0000FFFFL +#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK_MASK 0xFFFF0000L +//DWB_CRC_MASK_B_A +#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK__SHIFT 0x0 +#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK__SHIFT 0x10 +#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK_MASK 0x0000FFFFL +#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK_MASK 0xFFFF0000L +//DWB_CRC_VAL_R_G +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED__SHIFT 0x0 +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN__SHIFT 0x10 +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED_MASK 0x0000FFFFL +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN_MASK 0xFFFF0000L +//DWB_CRC_VAL_B_A +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE__SHIFT 0x0 +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A__SHIFT 0x10 +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE_MASK 0x0000FFFFL +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A_MASK 0xFFFF0000L +//DWB_OUT_CTRL +#define DWB_OUT_CTRL__OUT_FORMAT__SHIFT 0x0 +#define DWB_OUT_CTRL__OUT_DENORM__SHIFT 0x4 +#define DWB_OUT_CTRL__OUT_MAX__SHIFT 0x8 +#define DWB_OUT_CTRL__OUT_MIN__SHIFT 0x14 +#define DWB_OUT_CTRL__OUT_FORMAT_MASK 0x00000003L +#define DWB_OUT_CTRL__OUT_DENORM_MASK 0x00000030L +#define DWB_OUT_CTRL__OUT_MAX_MASK 0x0003FF00L +#define DWB_OUT_CTRL__OUT_MIN_MASK 0x3FF00000L +//DWB_MMHUBBUB_BACKPRESSURE_CNT_EN +#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__SHIFT 0x0 +#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN_MASK 0x00000001L +//DWB_MMHUBBUB_BACKPRESSURE_CNT +#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE__SHIFT 0x0 +#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE_MASK 0x0000FFFFL +//DWB_HOST_READ_CONTROL +#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL_MASK 0x000000FFL +//DWB_OVERFLOW_STATUS +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG__SHIFT 0x0 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK__SHIFT 0x8 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK__SHIFT 0xc +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG_MASK 0x00000001L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK_MASK 0x00000100L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK_MASK 0x00001000L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS_MASK 0x00010000L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE_MASK 0x00100000L +//DWB_OVERFLOW_COUNTER +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE__SHIFT 0x0 +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT__SHIFT 0x4 +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT__SHIFT 0x10 +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE_MASK 0x00000003L +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT_MASK 0x0000FFF0L +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT_MASK 0x0FFF0000L +//DWB_SOFT_RESET +#define DWB_SOFT_RESET__DWB_SOFT_RESET__SHIFT 0x0 +#define DWB_SOFT_RESET__DWB_SOFT_RESET_MASK 0x00000001L + + +// addressBlock: dcn_dc_wb0_dispdec_dwbcp_dispdec +//DWB_HDR_MULT_COEF +#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF__SHIFT 0x0 +#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF_MASK 0x0007FFFFL +//DWB_GAMUT_REMAP_MODE +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE__SHIFT 0x0 +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x18 +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_MASK 0x00000003L +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT_MASK 0x03000000L +//DWB_GAMUT_REMAP_COEF_FORMAT +#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//DWB_GAMUT_REMAPA_C11_C12 +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C13_C14 +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C21_C22 +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C23_C24 +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C31_C32 +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C33_C34 +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C11_C12 +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C13_C14 +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C21_C22 +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C23_C24 +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C31_C32 +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C33_C34 +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34_MASK 0xFFFF0000L +//DWB_OGAM_CONTROL +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE__SHIFT 0x0 +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT__SHIFT 0x4 +#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE__SHIFT 0x8 +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT__SHIFT 0x18 +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT__SHIFT 0x1c +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_MASK 0x00000003L +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_MASK 0x00000010L +#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE_MASK 0x00000100L +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT_MASK 0x03000000L +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT_MASK 0x10000000L +//DWB_OGAM_LUT_INDEX +#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX__SHIFT 0x0 +#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX_MASK 0x000001FFL +//DWB_OGAM_LUT_DATA +#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA__SHIFT 0x0 +#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA_MASK 0x0003FFFFL +//DWB_OGAM_LUT_CONTROL +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x4 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG__SHIFT 0x8 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL__SHIFT 0xc +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE__SHIFT 0x10 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000030L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG_MASK 0x00000100L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL_MASK 0x00001000L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE_MASK 0x00010000L +//DWB_OGAM_RAMA_START_CNTL_B +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//DWB_OGAM_RAMA_START_CNTL_G +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//DWB_OGAM_RAMA_START_CNTL_R +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//DWB_OGAM_RAMA_START_BASE_CNTL_B +#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_SLOPE_CNTL_B +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_BASE_CNTL_G +#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_SLOPE_CNTL_G +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_BASE_CNTL_R +#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_SLOPE_CNTL_R +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL1_B +#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL2_B +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//DWB_OGAM_RAMA_END_CNTL1_G +#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL2_G +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//DWB_OGAM_RAMA_END_CNTL1_R +#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL2_R +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//DWB_OGAM_RAMA_OFFSET_B +#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//DWB_OGAM_RAMA_OFFSET_G +#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//DWB_OGAM_RAMA_OFFSET_R +#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//DWB_OGAM_RAMA_REGION_0_1 +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_2_3 +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_4_5 +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_6_7 +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_8_9 +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_10_11 +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_12_13 +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_14_15 +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_16_17 +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_18_19 +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_20_21 +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_22_23 +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_24_25 +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_26_27 +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_28_29 +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_30_31 +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_32_33 +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_START_CNTL_B +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//DWB_OGAM_RAMB_START_CNTL_G +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//DWB_OGAM_RAMB_START_CNTL_R +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//DWB_OGAM_RAMB_START_BASE_CNTL_B +#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_SLOPE_CNTL_B +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_BASE_CNTL_G +#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_SLOPE_CNTL_G +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_BASE_CNTL_R +#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_SLOPE_CNTL_R +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL1_B +#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL2_B +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//DWB_OGAM_RAMB_END_CNTL1_G +#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL2_G +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//DWB_OGAM_RAMB_END_CNTL1_R +#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL2_R +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//DWB_OGAM_RAMB_OFFSET_B +#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//DWB_OGAM_RAMB_OFFSET_G +#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//DWB_OGAM_RAMB_OFFSET_R +#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//DWB_OGAM_RAMB_REGION_0_1 +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_2_3 +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_4_5 +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_6_7 +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_8_9 +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_10_11 +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_12_13 +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_14_15 +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_16_17 +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_18_19 +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_20_21 +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_22_23 +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_24_25 +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_26_27 +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_28_29 +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_30_31 +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_32_33 +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L + + +//VGA_MEM_WRITE_PAGE_ADDR +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L +//VGA_MEM_READ_PAGE_ADDR +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L +//VGA_RENDER_CONTROL +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0 +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5 +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7 +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8 +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10 +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18 +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19 +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001FL +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x02000000L +//VGA_SEQUENCER_RESET_CONTROL +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0 +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1 +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2 +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3 +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4 +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5 +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8 +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9 +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12 +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00FC0000L +//VGA_MODE_CONTROL +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0 +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4 +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8 +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10 +#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT 0x18 +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L +#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK 0x01000000L +//VGA_SURFACE_PITCH_SELECT +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L +//VGA_MEMORY_BASE_ADDRESS +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0 +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xFFFFFFFFL +//VGA_DISPBUF1_SURFACE_ADDR +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0 +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01FFFFFFL +//VGA_DISPBUF2_SURFACE_ADDR +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0 +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01FFFFFFL +//VGA_MEMORY_BASE_ADDRESS_HIGH +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0 +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x0000FFFFL +//VGA_HDP_CONTROL +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0 +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4 +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8 +#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10 +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18 +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L +#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L +//VGA_CACHE_CONTROL +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0 +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8 +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10 +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14 +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18 +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3F000000L +//D1VGA_CONTROL +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0 +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8 +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18 +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L +//D2VGA_CONTROL +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0 +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8 +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18 +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L +//VGA_STATUS +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0 +#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1 +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2 +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3 +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L +#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L +//VGA_INTERRUPT_CONTROL +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0 +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8 +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10 +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18 +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L +//VGA_STATUS_CLEAR +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0 +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8 +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10 +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18 +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L +//VGA_INTERRUPT_STATUS +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0 +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1 +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2 +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3 +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L +//VGA_MAIN_CONTROL +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0 +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3 +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5 +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8 +#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10 +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18 +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000E0L +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L +#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0x0000F000L +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L +//VGA_TEST_CONTROL +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18 +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L +//VGA_QOS_CTRL +#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT 0x0 +#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT 0x4 +#define VGA_QOS_CTRL__VGA_READ_QOS_MASK 0x0000000FL +#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK 0x000000F0L +//CRTC8_IDX +#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0 +#define CRTC8_IDX__VCRTC_IDX_MASK 0x3FL +//CRTC8_DATA +#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0 +#define CRTC8_DATA__VCRTC_DATA_MASK 0xFFL +//GENFC_WT +#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 +#define GENFC_WT__VSYNC_SEL_W_MASK 0x08L +//GENS1 +#define GENS1__NO_DISPLAY__SHIFT 0x0 +#define GENS1__VGA_VSTATUS__SHIFT 0x3 +#define GENS1__PIXEL_READ_BACK__SHIFT 0x4 +#define GENS1__NO_DISPLAY_MASK 0x01L +#define GENS1__VGA_VSTATUS_MASK 0x08L +#define GENS1__PIXEL_READ_BACK_MASK 0x30L +//ATTRDW +#define ATTRDW__ATTR_DATA__SHIFT 0x0 +#define ATTRDW__ATTR_DATA_MASK 0xFFL +//ATTRX +#define ATTRX__ATTR_IDX__SHIFT 0x0 +#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5 +#define ATTRX__ATTR_IDX_MASK 0x1FL +#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20L +//ATTRDR +#define ATTRDR__ATTR_DATA__SHIFT 0x0 +#define ATTRDR__ATTR_DATA_MASK 0xFFL +//GENMO_WT +#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0 +#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1 +#define GENMO_WT__VGA_CKSEL__SHIFT 0x2 +#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5 +#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6 +#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7 +#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x01L +#define GENMO_WT__VGA_RAM_EN_MASK 0x02L +#define GENMO_WT__VGA_CKSEL_MASK 0x0CL +#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20L +#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40L +#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80L +//GENS0 +#define GENS0__SENSE_SWITCH__SHIFT 0x4 +#define GENS0__CRT_INTR__SHIFT 0x7 +#define GENS0__SENSE_SWITCH_MASK 0x10L +#define GENS0__CRT_INTR_MASK 0x80L +//GENENB +#define GENENB__BLK_IO_BASE__SHIFT 0x0 +#define GENENB__BLK_IO_BASE_MASK 0xFFL +//SEQ8_IDX +#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0 +#define SEQ8_IDX__SEQ_IDX_MASK 0x07L +//SEQ8_DATA +#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0 +#define SEQ8_DATA__SEQ_DATA_MASK 0xFFL +//DAC_MASK +#define DAC_MASK__DAC_MASK__SHIFT 0x0 +#define DAC_MASK__DAC_MASK_MASK 0xFFL +//DAC_R_INDEX +#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0 +#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xFFL +//DAC_W_INDEX +#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0 +#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xFFL +//DAC_DATA +#define DAC_DATA__DAC_DATA__SHIFT 0x0 +#define DAC_DATA__DAC_DATA_MASK 0x3FL +//GENFC_RD +#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3 +#define GENFC_RD__VSYNC_SEL_R_MASK 0x08L +//GENMO_RD +#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0 +#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1 +#define GENMO_RD__VGA_CKSEL__SHIFT 0x2 +#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5 +#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 +#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7 +#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x01L +#define GENMO_RD__VGA_RAM_EN_MASK 0x02L +#define GENMO_RD__VGA_CKSEL_MASK 0x0CL +#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20L +#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40L +#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80L +//GRPH8_IDX +#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0 +#define GRPH8_IDX__GRPH_IDX_MASK 0x0FL +//GRPH8_DATA +#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0 +#define GRPH8_DATA__GRPH_DATA_MASK 0xFFL +//CRTC8_IDX_1 +#define CRTC8_IDX_1__VCRTC_IDX__SHIFT 0x0 +#define CRTC8_IDX_1__VCRTC_IDX_MASK 0x3FL +//CRTC8_DATA_1 +#define CRTC8_DATA_1__VCRTC_DATA__SHIFT 0x0 +#define CRTC8_DATA_1__VCRTC_DATA_MASK 0xFFL +//GENFC_WT_1 +#define GENFC_WT_1__VSYNC_SEL_W__SHIFT 0x3 +#define GENFC_WT_1__VSYNC_SEL_W_MASK 0x08L +//GENS1_1 +#define GENS1_1__NO_DISPLAY__SHIFT 0x0 +#define GENS1_1__VGA_VSTATUS__SHIFT 0x3 +#define GENS1_1__PIXEL_READ_BACK__SHIFT 0x4 +#define GENS1_1__NO_DISPLAY_MASK 0x01L +#define GENS1_1__VGA_VSTATUS_MASK 0x08L +#define GENS1_1__PIXEL_READ_BACK_MASK 0x30L +//D3VGA_CONTROL +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0 +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18 +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L +//D4VGA_CONTROL +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0 +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8 +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18 +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L +//D5VGA_CONTROL +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0 +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8 +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18 +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L +//D6VGA_CONTROL +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0 +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8 +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18 +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L +//VGA_SOURCE_SELECT +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L + + +// addressBlock: dcn_dc_mmhubbub_vgaif_dispdec +//MCIF_CONTROL +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L +//MCIF_WRITE_COMBINE_CONTROL +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0 +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000003FFL +//MCIF_PHASE0_OUTSTANDING_COUNTER +#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 +#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//MCIF_PHASE1_OUTSTANDING_COUNTER +#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 +#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//MCIF_PHASE2_OUTSTANDING_COUNTER +#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT 0x0 +#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL + + +// addressBlock: dcn_dc_mmhubbub_mcif_wb0_dispdec +//MCIF_WB_BUFMGR_SW_CONTROL +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L +//MCIF_WB_BUFMGR_STATUS +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L +//MCIF_WB_BUF_PITCH +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L +//MCIF_WB_BUF_1_STATUS +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_1_STATUS2 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK 0x00010000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK 0x00080000L +//MCIF_WB_BUF_2_STATUS +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_2_STATUS2 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK 0x00010000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK 0x00080000L +//MCIF_WB_BUF_3_STATUS +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_3_STATUS2 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK 0x00010000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK 0x00080000L +//MCIF_WB_BUF_4_STATUS +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_4_STATUS2 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK 0x00010000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK 0x00080000L +//MCIF_WB_ARBITRATION_CONTROL +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x14 +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFF00000L +//MCIF_WB_SCLK_CHANGE +#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0 +#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L +//MCIF_WB_TEST_DEBUG_INDEX +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//MCIF_WB_TEST_DEBUG_DATA +#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0 +#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_1_ADDR_Y +#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_1_ADDR_C +#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_2_ADDR_Y +#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_2_ADDR_C +#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_3_ADDR_Y +#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_3_ADDR_C +#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_4_ADDR_Y +#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_4_ADDR_C +#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUFMGR_VCE_CONTROL +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L +//MCIF_WB_NB_PSTATE_CONTROL +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1 +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L +//MCIF_WB_CLOCK_GATER_CONTROL +#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0 +#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L +//MCIF_WB_SELF_REFRESH_CONTROL +#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1 +#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L +//MULTI_LEVEL_QOS_CTRL +#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0 +#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL +//MCIF_WB_SECURITY_LEVEL +#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL__SHIFT 0x0 +#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE__SHIFT 0x4 +#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL_MASK 0x00000007L +#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE_MASK 0x00000070L +//MCIF_WB_BUF_LUMA_SIZE +#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0 +#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB_BUF_CHROMA_SIZE +#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0 +#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB_BUF_1_ADDR_Y_HIGH +#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_1_ADDR_C_HIGH +#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_2_ADDR_Y_HIGH +#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_2_ADDR_C_HIGH +#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_3_ADDR_Y_HIGH +#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_3_ADDR_C_HIGH +#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_4_ADDR_Y_HIGH +#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_4_ADDR_C_HIGH +#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_1_RESOLUTION +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_BUF_2_RESOLUTION +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_BUF_3_RESOLUTION +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_BUF_4_RESOLUTION +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_PSTATE_CHANGE_DURATION_VBI +#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT 0x0 +#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT 0x10 +#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI_MASK 0x0000FFFFL +#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI_MASK 0xFFFF0000L +//MCIF_WB_VMID_CONTROL +#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID__SHIFT 0x0 +#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID_MASK 0x0000000FL +//MCIF_WB_MIN_TTO +#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO__SHIFT 0x0 +#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO_MASK 0x0007FFFFL + + +//MCIF_WB_NB_PSTATE_LATENCY_WATERMARK +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0 +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x18 +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE__SHIFT 0x1f +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x001FFFFFL +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x07000000L +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE_MASK 0x80000000L +//MCIF_WB_WATERMARK +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0 +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x18 +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x001FFFFFL +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x07000000L +//MMHUBBUB_WARMUP_CONFIG +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS__SHIFT 0x10 +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID__SHIFT 0x14 +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS_MASK 0x000F0000L +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID_MASK 0x00F00000L +//MMHUBBUB_WARMUP_CONTROL_STATUS +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN__SHIFT 0x0 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN__SHIFT 0x4 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS__SHIFT 0x5 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK__SHIFT 0x6 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR__SHIFT 0x8 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN_MASK 0x00000001L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN_MASK 0x00000010L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS_MASK 0x00000020L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK_MASK 0x00000040L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR_MASK 0x03FFFF00L +//MMHUBBUB_WARMUP_BASE_ADDR_LOW +#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW__SHIFT 0x0 +#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW_MASK 0xFFFFFFFFL +//MMHUBBUB_WARMUP_BASE_ADDR_HIGH +#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH__SHIFT 0x0 +#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH_MASK 0x000007FFL +//MMHUBBUB_WARMUP_ADDR_REGION +#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION__SHIFT 0x0 +#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION_MASK 0x07FFFFFFL +//MMHUBBUB_MIN_TTO +#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO__SHIFT 0x0 +#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO_MASK 0x0007FFFFL +//MMHUBBUB_CTRL +#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE__SHIFT 0x0 +#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE_MASK 0x00000003L +//WBIF_SMU_WM_CONTROL +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL__SHIFT 0x14 +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ__SHIFT 0x16 +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL_MASK 0x00300000L +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ_MASK 0x00400000L +//WBIF0_MISC_CTRL +#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT 0x0 +#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT 0x10 +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT 0x18 +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT 0x19 +#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK 0x000003FFL +#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK 0x00010000L +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK 0x01000000L +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK 0x02000000L +//WBIF0_PHASE0_OUTSTANDING_COUNTER +#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 +#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//WBIF0_PHASE1_OUTSTANDING_COUNTER +#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 +#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//VGA_SRC_SPLIT_CNTL +#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT 0x0 +#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK 0x00000003L +//MMHUBBUB_MEM_PWR_STATUS +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT 0x0 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT 0x2 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT 0x4 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT 0x6 +#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x1f +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK 0x00000003L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK 0x0000000CL +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK 0x00000030L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK 0x000000C0L +#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x80000000L +//MMHUBBUB_MEM_PWR_CNTL +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x0 +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x1 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT 0x2 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT 0x4 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT 0x5 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT 0x7 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT 0x8 +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x00000001L +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x00000002L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK 0x0000000CL +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK 0x00000010L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK 0x00000060L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK 0x00000080L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK 0x00000100L +//MMHUBBUB_CLOCK_CNTL +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT 0x0 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT 0x5 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS__SHIFT 0x6 +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS__SHIFT 0x7 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0x8 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT 0x9 +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT 0xa +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS__SHIFT 0x11 +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK 0x00000020L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS_MASK 0x00000040L +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS_MASK 0x00000080L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000100L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK 0x00000200L +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK 0x00000400L +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS_MASK 0x00020000L +//MMHUBBUB_SOFT_RESET +#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0 +#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET__SHIFT 0x1 +#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT 0x2 +#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT 0x8 +#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L +#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET_MASK 0x00000002L +#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK 0x00000004L +#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK 0x00000100L +//DMU_IF_ERR_STATUS +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT 0x0 +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT 0x4 +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK 0x00000001L +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK 0x00000010L +//MMHUBBUB_CLIENT_UNIT_ID +#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID__SHIFT 0x0 +#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT 0x8 +#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID_MASK 0x0000003FL +#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK 0x00003F00L +//MMHUBBUB_WARMUP_VMID_CONTROL +#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID__SHIFT 0x0 +#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID_MASK 0x0000000FL + + +// addressBlock: dcn_dc_hda_azf0controller_dispdec +//AZALIA_CONTROLLER_CLOCK_GATING +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0 +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x00000001L +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x00000010L +//AZALIA_AUDIO_DTO +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000FFFFL +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xFFFF0000L +//AZALIA_AUDIO_DTO_CONTROL +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L +//AZALIA_SOCCLK_CONTROL +#define AZALIA_SOCCLK_CONTROL__DRM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT 0x0 +#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT 0x1 +#define AZALIA_SOCCLK_CONTROL__DRM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK 0x00000001L +#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK 0x00000002L +//AZALIA_UNDERFLOW_FILLER_SAMPLE +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0 +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xFFFFFFFFL +//AZALIA_DATA_DMA_CONTROL +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0x0000000CL +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0x000000C0L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L +//AZALIA_BDL_DMA_CONTROL +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0x0000000CL +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0x000000C0L +//AZALIA_RIRB_AND_DP_CONTROL +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x000001E0L +//AZALIA_CORB_DMA_CONTROL +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L +//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0 +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xFFFFFFFFL +//AZALIA_CYCLIC_BUFFER_SYNC +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0 +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L +//AZALIA_GLOBAL_CAPABILITIES +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L +//AZALIA_OUTPUT_PAYLOAD_CAPABILITY +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFF0000L +//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000FFL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0x00FF0000L +//AZALIA_INPUT_PAYLOAD_CAPABILITY +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFF0000L +//AZALIA_INPUT_CRC0_CONTROL0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC0_CONTROL1 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CONTROL2 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_INPUT_CRC0_CONTROL3 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC0_RESULT +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CONTROL0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC1_CONTROL1 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CONTROL2 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_INPUT_CRC1_CONTROL3 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC1_RESULT +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CONTROL0 +#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x00000001L +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L +//AZALIA_CRC0_CONTROL1 +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CONTROL2 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_CRC0_CONTROL3 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_CRC0_RESULT +#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CONTROL0 +#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x00000001L +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L +//AZALIA_CRC1_CONTROL1 +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CONTROL2 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_CRC1_CONTROL3 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_CRC1_RESULT +#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_MEM_PWR_CTRL +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x00000003L +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x00000004L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x00000018L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x00000020L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0x000000C0L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x00000100L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x00000600L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x00000800L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x00003000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x00004000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x00018000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x00020000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0x000C0000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x00100000L +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000L +//AZALIA_MEM_PWR_STATUS +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x00000003L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0x0000000CL +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x00000030L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0x000000C0L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x00000300L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0x00000C00L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x00003000L + + +// addressBlock: dcn_dc_hda_azf0root_dispdec +//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L +//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0 +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003FL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL +//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//AZALIA_F0_GTC_GROUP_OFFSET0 +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET1 +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET2 +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET3 +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET4 +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET5 +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET6 +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xFFFFFFFFL +//REG_DC_AUDIO_PORT_CONNECTIVITY +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT 0x0 +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK 0x00000007L +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK 0x00000007L +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L + + +// addressBlock: dcn_dc_hda_az_misc_dispdec +//AZ_CLOCK_CNTL +#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x0 +#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8 +#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x10 +#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT 0x18 +#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x00000001L +#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000100L +#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x00010000L +#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK 0x1F000000L + + +// addressBlock: dcn_dc_hda_azf0stream0_dispdec +//AZF0STREAM0_AZALIA_STREAM_INDEX +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM0_AZALIA_STREAM_DATA +#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0stream1_dispdec +//AZF0STREAM1_AZALIA_STREAM_INDEX +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM1_AZALIA_STREAM_DATA +#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0stream2_dispdec +//AZF0STREAM2_AZALIA_STREAM_INDEX +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM2_AZALIA_STREAM_DATA +#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0stream3_dispdec +//AZF0STREAM3_AZALIA_STREAM_INDEX +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM3_AZALIA_STREAM_DATA +#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0stream4_dispdec +//AZF0STREAM4_AZALIA_STREAM_INDEX +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM4_AZALIA_STREAM_DATA +#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0stream5_dispdec +//AZF0STREAM5_AZALIA_STREAM_INDEX +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM5_AZALIA_STREAM_DATA +#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0stream6_dispdec +//AZF0STREAM6_AZALIA_STREAM_INDEX +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM6_AZALIA_STREAM_DATA +#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0stream7_dispdec +//AZF0STREAM7_AZALIA_STREAM_INDEX +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM7_AZALIA_STREAM_DATA +#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0stream8_dispdec +//AZF0STREAM8_AZALIA_STREAM_INDEX +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM8_AZALIA_STREAM_DATA +#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0stream9_dispdec +//AZF0STREAM9_AZALIA_STREAM_INDEX +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM9_AZALIA_STREAM_DATA +#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0stream10_dispdec +//AZF0STREAM10_AZALIA_STREAM_INDEX +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM10_AZALIA_STREAM_DATA +#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0stream11_dispdec +//AZF0STREAM11_AZALIA_STREAM_INDEX +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM11_AZALIA_STREAM_DATA +#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0stream12_dispdec +//AZF0STREAM12_AZALIA_STREAM_INDEX +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM12_AZALIA_STREAM_DATA +#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0stream13_dispdec +//AZF0STREAM13_AZALIA_STREAM_INDEX +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM13_AZALIA_STREAM_DATA +#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0stream14_dispdec +//AZF0STREAM14_AZALIA_STREAM_INDEX +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM14_AZALIA_STREAM_DATA +#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0stream15_dispdec +//AZF0STREAM15_AZALIA_STREAM_INDEX +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM15_AZALIA_STREAM_DATA +#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0endpoint0_dispdec +//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0endpoint1_dispdec +//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0endpoint2_dispdec +//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0endpoint3_dispdec +//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0endpoint4_dispdec +//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0endpoint5_dispdec +//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0endpoint6_dispdec +//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0endpoint7_dispdec +//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0inputendpoint0_dispdec +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0inputendpoint1_dispdec +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0inputendpoint2_dispdec +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0inputendpoint3_dispdec +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0inputendpoint4_dispdec +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0inputendpoint5_dispdec +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0inputendpoint6_dispdec +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azf0inputendpoint7_dispdec +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_dchubbubl_hubbub_dispdec +//DCHUBBUB_ARB_DF_REQ_OUTSTAND +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT 0x0 +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT 0xa +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK 0x000003FFL +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK 0x000FFC00L +//DCHUBBUB_ARB_SAT_LEVEL +#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT 0x0 +#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK 0xFFFFFFFFL +//DCHUBBUB_ARB_QOS_FORCE +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT 0x0 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT 0x8 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST__SHIFT 0x9 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK 0x0000000FL +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK 0x00000100L +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST_MASK 0x00000200L +//DCHUBBUB_ARB_DRAM_STATE_CNTL +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT 0x0 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT 0x1 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST__SHIFT 0x2 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT 0x4 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT 0x5 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE__SHIFT 0x7 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE__SHIFT 0xc +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK 0x00000001L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK 0x00000002L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST_MASK 0x00000004L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK 0x00000010L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK 0x00000020L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE_MASK 0x00000080L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE_MASK 0x00001000L +//DCHUBBUB_ARB_USR_RETRAINING_CNTL +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING__SHIFT 0x1 +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE__SHIFT 0x8 +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE__SHIFT 0x9 +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST__SHIFT 0xa +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE__SHIFT 0xb +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST_MASK 0x00000001L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING_MASK 0x00000002L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE_MASK 0x00000100L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE_MASK 0x00000200L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST_MASK 0x00000400L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE_MASK 0x00000800L +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK 0x00003FFFL +//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK 0x000003FFL +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK 0x00003FFFL +//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK 0x000003FFL +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK 0x00003FFFL +//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_C +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK 0x000003FFL +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK 0x00003FFFL +//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_D +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK 0x000003FFL +//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT 0x0 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT 0x4 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT 0x5 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT 0x8 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE__SHIFT 0x18 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK 0x00000003L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK 0x00000010L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK 0x00000020L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK 0x00000100L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE_MASK 0x01000000L +//DCHUBBUB_ARB_MALL_CNTL +#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS__SHIFT 0x0 +#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE__SHIFT 0x4 +#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS_MASK 0x00000001L +#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE_MASK 0x00000010L +#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +//DCHUBBUB_ARB_TIMEOUT_ENABLE +#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT 0x0 +#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK 0x00000001L +//DCHUBBUB_GLOBAL_TIMER_CNTL +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT 0x0 +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT 0xc +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT 0x10 +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK 0x0000000FL +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK 0x00001000L +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK 0xFFFF0000L +//SURFACE_CHECK0_ADDRESS_LSB +#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK0_ADDRESS_MSB +#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK1_ADDRESS_LSB +#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK1_ADDRESS_MSB +#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK2_ADDRESS_LSB +#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK2_ADDRESS_MSB +#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK3_ADDRESS_LSB +#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK3_ADDRESS_MSB +#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK 0x80000000L +//VTG0_CONTROL +#define VTG0_CONTROL__VTG0_FP2__SHIFT 0x0 +#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT 0x10 +#define VTG0_CONTROL__VTG0_ENABLE__SHIFT 0x1f +#define VTG0_CONTROL__VTG0_FP2_MASK 0x00007FFFL +#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG0_CONTROL__VTG0_ENABLE_MASK 0x80000000L +//VTG1_CONTROL +#define VTG1_CONTROL__VTG1_FP2__SHIFT 0x0 +#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT 0x10 +#define VTG1_CONTROL__VTG1_ENABLE__SHIFT 0x1f +#define VTG1_CONTROL__VTG1_FP2_MASK 0x00007FFFL +#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG1_CONTROL__VTG1_ENABLE_MASK 0x80000000L +//VTG2_CONTROL +#define VTG2_CONTROL__VTG2_FP2__SHIFT 0x0 +#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT 0x10 +#define VTG2_CONTROL__VTG2_ENABLE__SHIFT 0x1f +#define VTG2_CONTROL__VTG2_FP2_MASK 0x00007FFFL +#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG2_CONTROL__VTG2_ENABLE_MASK 0x80000000L +//VTG3_CONTROL +#define VTG3_CONTROL__VTG3_FP2__SHIFT 0x0 +#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10 +#define VTG3_CONTROL__VTG3_ENABLE__SHIFT 0x1f +#define VTG3_CONTROL__VTG3_FP2_MASK 0x00007FFFL +#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG3_CONTROL__VTG3_ENABLE_MASK 0x80000000L +//DCHUBBUB_SOFT_RESET +#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT 0x0 +#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT 0x1 +#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT 0x4 +#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK 0x00000001L +#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK 0x00000002L +#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK 0x00000010L +//DCHUBBUB_CLOCK_CNTL +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT 0x0 +#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x5 +#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x6 +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS__SHIFT 0x7 +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL +#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000020L +#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000040L +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS_MASK 0x00000080L +//DCFCLK_CNTL +#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT 0x1f +#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK 0x80000000L +//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT 0x0 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN__SHIFT 0x1 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL__SHIFT 0x2 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT 0x3 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT 0x7 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT 0xa +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT 0xb +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK 0x00000001L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN_MASK 0x00000002L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL_MASK 0x00000004L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK 0x00000078L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK 0x00000380L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK 0x00000400L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK 0x007FF800L +//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT 0x0 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT 0x1 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT 0x4 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT 0xc +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT 0x13 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT 0x1f +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK 0x00000001L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK 0x0000000EL +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK 0x00000FF0L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK 0x00007000L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK 0x7FF80000L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK 0x80000000L +//DCHUBBUB_VLINE_SNAPSHOT +#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT 0x0 +#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK 0x00000001L +//DCHUBBUB_CTRL_STATUS +#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT 0x0 +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS__SHIFT 0x2 +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR__SHIFT 0x3 +#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE__SHIFT 0x1f +#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK 0x00000001L +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS_MASK 0x00000004L +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR_MASK 0x00000008L +#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE_MASK 0x80000000L +//DCHUBBUB_TIMEOUT_DETECTION_CTRL1 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT 0x6 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK 0x0000003FL +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK 0xFFFFFFC0L +//DCHUBBUB_TIMEOUT_DETECTION_CTRL2 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT 0x1b +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT 0x1c +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK 0x07FFFFFFL +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK 0x08000000L +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK 0x10000000L +//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT 0x1 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT 0x2 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT 0x3 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK 0x00000001L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK 0x00000002L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK 0x00000004L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK 0x000000F8L +//FMON_CTRL +#define FMON_CTRL__FMON_START__SHIFT 0x0 +#define FMON_CTRL__FMON_MODE__SHIFT 0x1 +#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT 0x4 +#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT 0x5 +#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT 0x6 +#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT 0x7 +#define FMON_CTRL__FMON_STATE__SHIFT 0x9 +#define FMON_CTRL__FMON_URG_FILTER__SHIFT 0xc +#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT 0xd +#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT 0x11 +#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT 0x16 +#define FMON_CTRL__FMON_SOF_SEL__SHIFT 0x1b +#define FMON_CTRL__FMON_START_MASK 0x00000001L +#define FMON_CTRL__FMON_MODE_MASK 0x00000006L +#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK 0x00000010L +#define FMON_CTRL__FMON_STATUS_IGNORE_MASK 0x00000020L +#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK 0x00000040L +#define FMON_CTRL__FMON_FILTER_UID_EN_MASK 0x00000180L +#define FMON_CTRL__FMON_STATE_MASK 0x00000600L +#define FMON_CTRL__FMON_URG_FILTER_MASK 0x00001000L +#define FMON_CTRL__FMON_URG_THRESHOLD_MASK 0x0001E000L +#define FMON_CTRL__FMON_FILTER_UID_1_MASK 0x003E0000L +#define FMON_CTRL__FMON_FILTER_UID_2_MASK 0x07C00000L +#define FMON_CTRL__FMON_SOF_SEL_MASK 0x38000000L + + +// addressBlock: dcn_dc_dchubbubl_hubbub_sdpif_dispdec +//DCHUBBUB_SDPIF_CFG0 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT 0x1 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT 0x3 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT 0x6 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT 0xa +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT 0xb +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT 0xc +#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT 0xd +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT 0xe +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT 0xf +#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT 0x19 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK 0x00000006L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK 0x00000038L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK 0x000003C0L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK 0x00000400L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK 0x00000800L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK 0x00001000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK 0x00002000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK 0x00004000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK 0x00008000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK 0x7E000000L +//DCHUBBUB_SDPIF_CFG1 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT 0x1 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT 0x2 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT 0x8 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING__SHIFT 0x9 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK 0x00000002L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK 0x00000004L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK 0x00000100L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING_MASK 0x00000200L +//DCHUBBUB_SDPIF_CFG2 +#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL__SHIFT 0x8 +#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT 0x10 +#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL_MASK 0x00000700L +#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK 0x01FF0000L +//VM_REQUEST_PHYSICAL +#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT 0x0 +#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT 0x3 +#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK 0x00000001L +#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK 0x00000008L +//DCHUBBUB_FORCE_IO_STATUS_0 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT 0x0 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT 0x1 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT 0x2 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT 0x3 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT 0x7 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT 0xa +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK 0x00000001L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK 0x00000002L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK 0x00000004L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK 0x00000078L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK 0x00000380L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK 0xFFFFFC00L +//DCHUBBUB_FORCE_IO_STATUS_1 +#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT 0x0 +#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK 0x001FFFFFL +//DCN_VM_FB_LOCATION_BASE +#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//DCN_VM_FB_LOCATION_TOP +#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//DCN_VM_FB_OFFSET +#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//DCN_VM_AGP_BOT +#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define DCN_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//DCN_VM_AGP_TOP +#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define DCN_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//DCN_VM_AGP_BASE +#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define DCN_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_START +#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK 0x000FFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_END +#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK 0x000FFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL +#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L +//DCHUBBUB_SDPIF_PIPE_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL__SHIFT 0x6 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL__SHIFT 0x9 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK 0x00000007L +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK 0x00000038L +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL_MASK 0x000001C0L +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL_MASK 0x00000E00L +//DCHUBBUB_SDPIF_PIPE_NOALLOC +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC__SHIFT 0x1 +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC__SHIFT 0x2 +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC_MASK 0x00000001L +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC_MASK 0x00000002L +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC_MASK 0x00000004L +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC_MASK 0x00000008L +//DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL__SHIFT 0x6 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL__SHIFT 0x9 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL_MASK 0x00000007L +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL_MASK 0x00000038L +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL_MASK 0x000001C0L +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL_MASK 0x00000E00L +//DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE2_DCCMETA_SEC_LVL__SHIFT 0x6 +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE3_DCCMETA_SEC_LVL__SHIFT 0x9 +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL_MASK 0x00000007L +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL_MASK 0x00000038L +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE2_DCCMETA_SEC_LVL_MASK 0x000001C0L +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE3_DCCMETA_SEC_LVL_MASK 0x00000E00L +//DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL__SHIFT 0x6 +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL__SHIFT 0x9 +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL_MASK 0x00000007L +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL_MASK 0x00000038L +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL_MASK 0x000001C0L +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL_MASK 0x00000E00L +//DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL__SHIFT 0x6 +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL__SHIFT 0x9 +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL_MASK 0x00000007L +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL_MASK 0x00000038L +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL_MASK 0x000001C0L +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL_MASK 0x00000E00L +//SDPIF_REQUEST_RATE_LIMIT +#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT__SHIFT 0x0 +#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT_MASK 0x00000FFFL +//DCHUBBUB_SDPIF_MEM_PWR_CTRL +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT 0x2 +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK 0x00000003L +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK 0x00000004L +//DCHUBBUB_SDPIF_MEM_PWR_STATUS +#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK 0x00000003L + + +// addressBlock: dcn_dc_dchubbubl_hubbub_ret_path_dispdec +//DCHUBBUB_RET_PATH_MEM_PWR_CTRL +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT 0x2 +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK 0x00000003L +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK 0x00000004L +//DCHUBBUB_RET_PATH_MEM_PWR_STATUS +#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK 0x00000003L +//DCHUBBUB_CRC_CTRL +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT 0x0 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT 0x1 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT 0x2 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT 0x3 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT 0x4 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT 0x6 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT 0x8 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT 0xc +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT 0x14 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK 0x00000001L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK 0x00000002L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK 0x00000004L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK 0x00000008L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK 0x00000030L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK 0x000000C0L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK 0x00000F00L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK 0x00001000L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK 0x00100000L +//DCHUBBUB_CRC0_VAL_R_G +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT 0x10 +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK 0x0000FFFFL +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK 0xFFFF0000L +//DCHUBBUB_CRC0_VAL_B_A +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT 0x10 +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK 0x0000FFFFL +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK 0xFFFF0000L +//DCHUBBUB_CRC1_VAL_R_G +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT 0x10 +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK 0x0000FFFFL +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK 0xFFFF0000L +//DCHUBBUB_CRC1_VAL_B_A +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT 0x10 +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK 0x0000FFFFL +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK 0xFFFF0000L +//DCHUBBUB_DCC_STAT_CNTL +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN__SHIFT 0x1 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE__SHIFT 0x2 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL__SHIFT 0x4 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT__SHIFT 0x10 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE_MASK 0x00000001L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN_MASK 0x00000002L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE_MASK 0x00000004L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL_MASK 0x000000F0L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT_MASK 0xFFFF0000L +//DCHUBBUB_DCC_STAT0 +#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ_MASK 0xFFFFFFFFL +//DCHUBBUB_DCC_STAT1 +#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ_MASK 0xFFFFFFFFL +//DCHUBBUB_DCC_STAT2 +#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ_MASK 0xFFFFFFFFL +//DCHUBBUB_COMPBUF_CTRL +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE__SHIFT 0x0 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE__SHIFT 0x10 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS__SHIFT 0x12 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR__SHIFT 0x13 +#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR__SHIFT 0x1f +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_MASK 0x0000001FL +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT_MASK 0x00001F00L +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE_MASK 0x00010000L +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS_MASK 0x00040000L +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR_MASK 0x00080000L +#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR_MASK 0x80000000L +//DCHUBBUB_DET0_CTRL +#define DCHUBBUB_DET0_CTRL__DET0_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET0_CTRL__DET0_SIZE_MASK 0x0000001FL +#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT_MASK 0x00001F00L +//DCHUBBUB_DET1_CTRL +#define DCHUBBUB_DET1_CTRL__DET1_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET1_CTRL__DET1_SIZE_MASK 0x0000001FL +#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT_MASK 0x00001F00L +//DCHUBBUB_DET2_CTRL +#define DCHUBBUB_DET2_CTRL__DET2_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET2_CTRL__DET2_SIZE_MASK 0x0000001FL +#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT_MASK 0x00001F00L +//DCHUBBUB_DET3_CTRL +#define DCHUBBUB_DET3_CTRL__DET3_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET3_CTRL__DET3_SIZE_MASK 0x0000001FL +#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT_MASK 0x00001F00L +//DCHUBBUB_MEM_PWR_MODE_CTRL +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE__SHIFT 0x0 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE__SHIFT 0x2 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE__SHIFT 0x4 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE__SHIFT 0x6 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE__SHIFT 0x8 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE__SHIFT 0xa +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x10 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE__SHIFT 0x12 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x14 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS__SHIFT 0x18 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS__SHIFT 0x19 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS__SHIFT 0x1a +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE_MASK 0x00000003L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE_MASK 0x0000000CL +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE_MASK 0x00000030L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE_MASK 0x000000C0L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE_MASK 0x00000300L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE_MASK 0x00000C00L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE_MASK 0x00030000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE_MASK 0x000C0000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00300000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS_MASK 0x01000000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS_MASK 0x02000000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS_MASK 0x04000000L +//COMPBUF_MEM_PWR_CTRL_1 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY__SHIFT 0x0 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY__SHIFT 0x8 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY__SHIFT 0x10 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY__SHIFT 0x18 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY_MASK 0x000000FFL +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY_MASK 0x0000FF00L +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY_MASK 0x00FF0000L +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY_MASK 0xFF000000L +//COMPBUF_MEM_PWR_CTRL_2 +#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY__SHIFT 0x0 +#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY_MASK 0x000000FFL +//DCHUBBUB_MEM_PWR_STATUS +#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE__SHIFT 0x2 +#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE__SHIFT 0x4 +#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE__SHIFT 0x6 +#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE__SHIFT 0x8 +#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE__SHIFT 0xa +#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE__SHIFT 0xc +#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE__SHIFT 0xe +#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE_MASK 0x00000003L +#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE_MASK 0x0000000CL +#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE_MASK 0x00000030L +#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE_MASK 0x000000C0L +#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE_MASK 0x00000300L +#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE_MASK 0x00000C00L +#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE_MASK 0x00003000L +#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE_MASK 0x0000C000L +//COMPBUF_RESERVED_SPACE +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B__SHIFT 0x0 +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS__SHIFT 0x10 +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK 0x00000FFFL +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS_MASK 0x0FFF0000L + + +// addressBlock: dcn_dc_dchubbubl_hubbub_vmrq_if_dispdec +//DCN_VM_CONTEXT0_CNTL +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_CNTL +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_CNTL +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_CNTL +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_CNTL +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_CNTL +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_CNTL +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_CNTL +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_CNTL +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_CNTL +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_CNTL +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_CNTL +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_CNTL +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_CNTL +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_CNTL +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_CNTL +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_DEFAULT_ADDR_MSB +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT 0x0 +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT 0x1c +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT 0x1d +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK 0x0000000FL +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK 0x10000000L +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK 0x20000000L +//DCN_VM_DEFAULT_ADDR_LSB +#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT 0x0 +#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//DCN_VM_FAULT_CNTL +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT 0x0 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT 0x1 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT 0x2 +#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT 0x8 +#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT 0x9 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK 0x00000001L +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK 0x00000002L +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK 0x00000004L +#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK 0x00000100L +#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK 0x00000200L +//DCN_VM_FAULT_STATUS +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT 0x0 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT 0x10 +#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID__SHIFT 0x14 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT 0x18 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT 0x1a +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT 0x1f +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK 0x0000FFFFL +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK 0x000F0000L +#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID_MASK 0x00F00000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK 0x03000000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK 0x3C000000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK 0x80000000L +//DCN_VM_FAULT_ADDR_MSB +#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT 0x0 +#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK 0x0000000FL +//DCN_VM_FAULT_ADDR_LSB +#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT 0x0 +#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_dcbubp0_dispdec_hubp_dispdec +//HUBP0_DCSURF_SURFACE_CONFIG +#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP0_DCSURF_ADDR_CONFIG +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP0_DCSURF_TILING_CONFIG +#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP0_DCSURF_PRI_VIEWPORT_START +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_START_C +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_START +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_START_C +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP0_DCHUBP_REQ_SIZE_CONFIG +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP0_DCHUBP_CNTL +#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP0_HUBP_CLK_CNTL +#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT 0x18 +#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK 0x01000000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP0_DCHUBP_VMPG_CONFIG +#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT 0x1 +#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT 0x2 +#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT 0x7 +#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK 0x00000002L +#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK 0x0000007CL +#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK 0x00000080L +//HUBP0_DCHUBP_MALL_CONFIG +#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT 0x0 +#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT 0x2 +#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK 0x00000003L +#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK 0x00000004L +//HUBP0_DCHUBP_MALL_SUB_VP +#define HUBP0_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT 0x0 +#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT 0x1 +#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT 0xf +#define HUBP0_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK 0x00000001L +#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK 0x00007FFEL +#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK 0x1FFF8000L +//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +//HUBP0_HUBP_MALL_STATUS +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT 0x0 +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT 0x1 +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT 0x2 +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT 0x3 +#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT 0x4 +#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT 0x6 +#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT 0x7 +#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT 0x8 +#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT 0x9 +#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT 0xa +#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT 0xb +#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT 0xc +#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT 0xd +#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT 0xe +#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT 0xf +#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT 0x10 +#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT 0x11 +#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT 0x12 +#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT 0x13 +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK 0x00000001L +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK 0x00000002L +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK 0x00000004L +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK 0x00000008L +#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE_MASK 0x00000010L +#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK 0x00000040L +#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK 0x00000080L +#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK 0x00000100L +#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK 0x00000200L +#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK 0x00000400L +#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK 0x00000800L +#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK 0x00001000L +#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK 0x00002000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK 0x00004000L +#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK 0x00008000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK 0x00010000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK 0x00020000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK 0x00040000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK 0x00080000L + + +// addressBlock: dcn_dc_dcbubp0_dispdec_hubpreq_dispdec +//HUBPREQ0_DCSURF_SURFACE_PITCH +#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ0_DCSURF_SURFACE_PITCH_C +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ0_VMID_SETTINGS_0 +#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SURFACE_CONTROL +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x2 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x5 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0xa +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xd +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x0000000CL +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00000060L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x00000C00L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x00006000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L +//HUBPREQ0_DCSURF_FLIP_CONTROL +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ0_DCSURF_FLIP_CONTROL2 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ0_DCSURF_SURFACE_INUSE +#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ0_DCSURF_SURFACE_INUSE_C +#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ0_DCN_EXPANSION_MODE +#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ0_DCN_TTU_QOS_WM +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ0_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ0_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_DMDATA_VM_CNTL +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ0_BLANK_OFFSET_0 +#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ0_BLANK_OFFSET_1 +#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ0_DST_DIMENSIONS +#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ0_DST_AFTER_SCALER +#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ0_PREFETCH_SETTINGS +#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ0_PREFETCH_SETTINGS_C +#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_0 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ0_VBLANK_PARAMETERS_1 +#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_2 +#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_3 +#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_4 +#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_0 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ0_FLIP_PARAMETERS_1 +#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_2 +#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_0 +#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_1 +#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_2 +#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_3 +#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_4 +#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_5 +#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_6 +#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_7 +#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ0_PER_LINE_DELIVERY_PRE +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ0_PER_LINE_DELIVERY +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ0_CURSOR_SETTINGS +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ0_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +//HUBPREQ0_VBLANK_PARAMETERS_5 +#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_6 +#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_3 +#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_4 +#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_5 +#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_6 +#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ0_UCLK_PSTATE_FORCE +#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT 0x0 +#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x1 +#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT 0x2 +#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x3 +#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK 0x00000001L +#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000002L +#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK 0x00000004L +#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000008L +//HUBPREQ0_HUBPREQ_STATUS_REG0 +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT 0x8 +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT 0x10 +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK 0x0000001FL +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK 0x00001F00L +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK 0x7FFF0000L +//HUBPREQ0_HUBPREQ_STATUS_REG1 +#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT 0x10 +#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK 0x00003FFFL +#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK 0x3FFF0000L +//HUBPREQ0_HUBPREQ_STATUS_REG2 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT 0x1 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT 0x3 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT 0x5 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT 0x8 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT 0x9 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT 0xa +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT 0xb +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT 0xc +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT 0xd +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT 0x10 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT 0x11 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT 0x12 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT 0x13 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT 0x14 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT 0x15 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT 0x1a +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT 0x1b +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT 0x1c +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT 0x1d +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT 0x1e +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT 0x1f +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK 0x00000001L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK 0x00000002L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK 0x00000004L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK 0x00000008L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK 0x00000010L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK 0x00000020L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK 0x00000100L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK 0x00000200L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK 0x00000400L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK 0x00000800L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK 0x00001000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK 0x00002000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK 0x00010000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK 0x00020000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK 0x00040000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK 0x00080000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK 0x00100000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK 0x00200000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK 0x04000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK 0x08000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK 0x10000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK 0x20000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK 0x40000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK 0x80000000L + + +// addressBlock: dcn_dc_dcbubp0_dispdec_hubpret_dispdec +//HUBPRET0_HUBPRET_CONTROL +#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00007FF0L +#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET0_HUBPRET_MEM_PWR_CTRL +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET0_HUBPRET_MEM_PWR_STATUS +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET0_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET0_HUBPRET_READ_LINE0 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE1 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_INTERRUPT +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET0_HUBPRET_READ_LINE_VALUE +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE_STATUS +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dcn_dc_dcbubp0_dispdec_cursor0_dispdec +//CURSOR0_0_CURSOR_CONTROL +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +//CURSOR0_0_CURSOR_SURFACE_ADDRESS +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_0_CURSOR_SIZE +#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_0_CURSOR_POSITION +#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_0_CURSOR_HOT_SPOT +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_0_CURSOR_STEREO_CONTROL +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_0_CURSOR_DST_OFFSET +#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_0_CURSOR_MEM_PWR_CTRL +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_0_CURSOR_MEM_PWR_STATUS +#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_0_DMDATA_ADDRESS_HIGH +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_0_DMDATA_ADDRESS_LOW +#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_0_DMDATA_CNTL +#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_0_DMDATA_QOS_CNTL +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_0_DMDATA_STATUS +#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_0_DMDATA_SW_CNTL +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_0_DMDATA_SW_DATA +#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_dcbubp1_dispdec_hubp_dispdec +//HUBP1_DCSURF_SURFACE_CONFIG +#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP1_DCSURF_ADDR_CONFIG +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP1_DCSURF_TILING_CONFIG +#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP1_DCSURF_PRI_VIEWPORT_START +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_START_C +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_START +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_START_C +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP1_DCHUBP_REQ_SIZE_CONFIG +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP1_DCHUBP_CNTL +#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP1_HUBP_CLK_CNTL +#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT 0x18 +#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK 0x01000000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP1_DCHUBP_VMPG_CONFIG +#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT 0x1 +#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT 0x2 +#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT 0x7 +#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK 0x00000002L +#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK 0x0000007CL +#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK 0x00000080L +//HUBP1_DCHUBP_MALL_CONFIG +#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT 0x0 +#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT 0x2 +#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK 0x00000003L +#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK 0x00000004L +//HUBP1_DCHUBP_MALL_SUB_VP +#define HUBP1_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT 0x0 +#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT 0x1 +#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT 0xf +#define HUBP1_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK 0x00000001L +#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK 0x00007FFEL +#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK 0x1FFF8000L +//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +//HUBP1_HUBP_MALL_STATUS +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT 0x0 +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT 0x1 +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT 0x2 +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT 0x3 +#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT 0x4 +#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT 0x6 +#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT 0x7 +#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT 0x8 +#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT 0x9 +#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT 0xa +#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT 0xb +#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT 0xc +#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT 0xd +#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT 0xe +#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT 0xf +#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT 0x10 +#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT 0x11 +#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT 0x12 +#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT 0x13 +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK 0x00000001L +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK 0x00000002L +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK 0x00000004L +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK 0x00000008L +#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE_MASK 0x00000010L +#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK 0x00000040L +#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK 0x00000080L +#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK 0x00000100L +#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK 0x00000200L +#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK 0x00000400L +#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK 0x00000800L +#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK 0x00001000L +#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK 0x00002000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK 0x00004000L +#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK 0x00008000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK 0x00010000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK 0x00020000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK 0x00040000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK 0x00080000L + + +// addressBlock: dcn_dc_dcbubp1_dispdec_hubpreq_dispdec +//HUBPREQ1_DCSURF_SURFACE_PITCH +#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ1_DCSURF_SURFACE_PITCH_C +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ1_VMID_SETTINGS_0 +#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SURFACE_CONTROL +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x2 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x5 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0xa +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xd +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x0000000CL +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00000060L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x00000C00L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x00006000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L +//HUBPREQ1_DCSURF_FLIP_CONTROL +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ1_DCSURF_FLIP_CONTROL2 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ1_DCSURF_SURFACE_INUSE +#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ1_DCSURF_SURFACE_INUSE_C +#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ1_DCN_EXPANSION_MODE +#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ1_DCN_TTU_QOS_WM +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ1_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ1_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_DMDATA_VM_CNTL +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ1_BLANK_OFFSET_0 +#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ1_BLANK_OFFSET_1 +#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ1_DST_DIMENSIONS +#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ1_DST_AFTER_SCALER +#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ1_PREFETCH_SETTINGS +#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ1_PREFETCH_SETTINGS_C +#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_0 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ1_VBLANK_PARAMETERS_1 +#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_2 +#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_3 +#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_4 +#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_0 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ1_FLIP_PARAMETERS_1 +#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_2 +#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_0 +#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_1 +#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_2 +#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_3 +#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_4 +#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_5 +#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_6 +#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_7 +#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ1_PER_LINE_DELIVERY_PRE +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ1_PER_LINE_DELIVERY +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ1_CURSOR_SETTINGS +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ1_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +//HUBPREQ1_VBLANK_PARAMETERS_5 +#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_6 +#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_3 +#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_4 +#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_5 +#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_6 +#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ1_UCLK_PSTATE_FORCE +#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT 0x0 +#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x1 +#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT 0x2 +#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x3 +#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK 0x00000001L +#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000002L +#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK 0x00000004L +#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000008L +//HUBPREQ1_HUBPREQ_STATUS_REG0 +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT 0x8 +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT 0x10 +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK 0x0000001FL +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK 0x00001F00L +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK 0x7FFF0000L +//HUBPREQ1_HUBPREQ_STATUS_REG1 +#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT 0x10 +#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK 0x00003FFFL +#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK 0x3FFF0000L +//HUBPREQ1_HUBPREQ_STATUS_REG2 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT 0x1 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT 0x3 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT 0x5 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT 0x8 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT 0x9 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT 0xa +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT 0xb +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT 0xc +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT 0xd +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT 0x10 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT 0x11 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT 0x12 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT 0x13 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT 0x14 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT 0x15 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT 0x1a +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT 0x1b +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT 0x1c +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT 0x1d +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT 0x1e +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT 0x1f +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK 0x00000001L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK 0x00000002L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK 0x00000004L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK 0x00000008L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK 0x00000010L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK 0x00000020L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK 0x00000100L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK 0x00000200L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK 0x00000400L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK 0x00000800L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK 0x00001000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK 0x00002000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK 0x00010000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK 0x00020000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK 0x00040000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK 0x00080000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK 0x00100000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK 0x00200000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK 0x04000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK 0x08000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK 0x10000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK 0x20000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK 0x40000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK 0x80000000L + + +// addressBlock: dcn_dc_dcbubp1_dispdec_hubpret_dispdec +//HUBPRET1_HUBPRET_CONTROL +#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00007FF0L +#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET1_HUBPRET_MEM_PWR_CTRL +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET1_HUBPRET_MEM_PWR_STATUS +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET1_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET1_HUBPRET_READ_LINE0 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE1 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_INTERRUPT +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET1_HUBPRET_READ_LINE_VALUE +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE_STATUS +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dcn_dc_dcbubp1_dispdec_cursor0_dispdec +//CURSOR0_1_CURSOR_CONTROL +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +//CURSOR0_1_CURSOR_SURFACE_ADDRESS +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_1_CURSOR_SIZE +#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_1_CURSOR_POSITION +#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_1_CURSOR_HOT_SPOT +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_1_CURSOR_STEREO_CONTROL +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_1_CURSOR_DST_OFFSET +#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_1_CURSOR_MEM_PWR_CTRL +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_1_CURSOR_MEM_PWR_STATUS +#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_1_DMDATA_ADDRESS_HIGH +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_1_DMDATA_ADDRESS_LOW +#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_1_DMDATA_CNTL +#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_1_DMDATA_QOS_CNTL +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_1_DMDATA_STATUS +#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_1_DMDATA_SW_CNTL +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_1_DMDATA_SW_DATA +#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_dcbubp2_dispdec_hubp_dispdec +//HUBP2_DCSURF_SURFACE_CONFIG +#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP2_DCSURF_ADDR_CONFIG +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP2_DCSURF_TILING_CONFIG +#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP2_DCSURF_PRI_VIEWPORT_START +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_START_C +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_START +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_START_C +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP2_DCHUBP_REQ_SIZE_CONFIG +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP2_DCHUBP_CNTL +#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP2_HUBP_CLK_CNTL +#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT 0x18 +#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK 0x01000000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP2_DCHUBP_VMPG_CONFIG +#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT 0x1 +#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT 0x2 +#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT 0x7 +#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK 0x00000002L +#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK 0x0000007CL +#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK 0x00000080L +//HUBP2_DCHUBP_MALL_CONFIG +#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT 0x0 +#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT 0x2 +#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK 0x00000003L +#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK 0x00000004L +//HUBP2_DCHUBP_MALL_SUB_VP +#define HUBP2_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT 0x0 +#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT 0x1 +#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT 0xf +#define HUBP2_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK 0x00000001L +#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK 0x00007FFEL +#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK 0x1FFF8000L +//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +//HUBP2_HUBP_MALL_STATUS +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT 0x0 +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT 0x1 +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT 0x2 +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT 0x3 +#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT 0x4 +#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT 0x6 +#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT 0x7 +#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT 0x8 +#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT 0x9 +#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT 0xa +#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT 0xb +#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT 0xc +#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT 0xd +#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT 0xe +#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT 0xf +#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT 0x10 +#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT 0x11 +#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT 0x12 +#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT 0x13 +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK 0x00000001L +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK 0x00000002L +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK 0x00000004L +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK 0x00000008L +#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE_MASK 0x00000010L +#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK 0x00000040L +#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK 0x00000080L +#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK 0x00000100L +#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK 0x00000200L +#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK 0x00000400L +#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK 0x00000800L +#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK 0x00001000L +#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK 0x00002000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK 0x00004000L +#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK 0x00008000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK 0x00010000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK 0x00020000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK 0x00040000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK 0x00080000L + + +// addressBlock: dcn_dc_dcbubp2_dispdec_hubpreq_dispdec +//HUBPREQ2_DCSURF_SURFACE_PITCH +#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ2_DCSURF_SURFACE_PITCH_C +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ2_VMID_SETTINGS_0 +#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SURFACE_CONTROL +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x2 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x5 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0xa +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xd +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x0000000CL +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00000060L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x00000C00L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x00006000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L +//HUBPREQ2_DCSURF_FLIP_CONTROL +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ2_DCSURF_FLIP_CONTROL2 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ2_DCSURF_SURFACE_INUSE +#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ2_DCSURF_SURFACE_INUSE_C +#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ2_DCN_EXPANSION_MODE +#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ2_DCN_TTU_QOS_WM +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ2_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ2_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_DMDATA_VM_CNTL +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ2_BLANK_OFFSET_0 +#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ2_BLANK_OFFSET_1 +#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ2_DST_DIMENSIONS +#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ2_DST_AFTER_SCALER +#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ2_PREFETCH_SETTINGS +#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ2_PREFETCH_SETTINGS_C +#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_0 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ2_VBLANK_PARAMETERS_1 +#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_2 +#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_3 +#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_4 +#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_0 +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ2_FLIP_PARAMETERS_1 +#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_2 +#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_0 +#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_1 +#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_2 +#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_3 +#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_4 +#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_5 +#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_6 +#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_7 +#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ2_PER_LINE_DELIVERY_PRE +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ2_PER_LINE_DELIVERY +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ2_CURSOR_SETTINGS +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ2_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +//HUBPREQ2_VBLANK_PARAMETERS_5 +#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_6 +#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_3 +#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_4 +#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_5 +#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_6 +#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ2_UCLK_PSTATE_FORCE +#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT 0x0 +#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x1 +#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT 0x2 +#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x3 +#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK 0x00000001L +#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000002L +#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK 0x00000004L +#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000008L +//HUBPREQ2_HUBPREQ_STATUS_REG0 +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT 0x8 +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT 0x10 +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK 0x0000001FL +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK 0x00001F00L +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK 0x7FFF0000L +//HUBPREQ2_HUBPREQ_STATUS_REG1 +#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT 0x10 +#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK 0x00003FFFL +#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK 0x3FFF0000L +//HUBPREQ2_HUBPREQ_STATUS_REG2 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT 0x1 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT 0x2 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT 0x3 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT 0x4 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT 0x5 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT 0x8 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT 0x9 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT 0xa +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT 0xb +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT 0xc +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT 0xd +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT 0x10 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT 0x11 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT 0x12 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT 0x13 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT 0x14 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT 0x15 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT 0x1a +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT 0x1b +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT 0x1c +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT 0x1d +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT 0x1e +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT 0x1f +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK 0x00000001L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK 0x00000002L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK 0x00000004L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK 0x00000008L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK 0x00000010L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK 0x00000020L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK 0x00000100L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK 0x00000200L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK 0x00000400L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK 0x00000800L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK 0x00001000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK 0x00002000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK 0x00010000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK 0x00020000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK 0x00040000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK 0x00080000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK 0x00100000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK 0x00200000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK 0x04000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK 0x08000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK 0x10000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK 0x20000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK 0x40000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK 0x80000000L + + +// addressBlock: dcn_dc_dcbubp2_dispdec_hubpret_dispdec +//HUBPRET2_HUBPRET_CONTROL +#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00007FF0L +#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET2_HUBPRET_MEM_PWR_CTRL +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET2_HUBPRET_MEM_PWR_STATUS +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET2_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET2_HUBPRET_READ_LINE0 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE1 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_INTERRUPT +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET2_HUBPRET_READ_LINE_VALUE +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE_STATUS +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dcn_dc_dcbubp2_dispdec_cursor0_dispdec +//CURSOR0_2_CURSOR_CONTROL +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +//CURSOR0_2_CURSOR_SURFACE_ADDRESS +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_2_CURSOR_SIZE +#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_2_CURSOR_POSITION +#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_2_CURSOR_HOT_SPOT +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_2_CURSOR_STEREO_CONTROL +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_2_CURSOR_DST_OFFSET +#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_2_CURSOR_MEM_PWR_CTRL +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_2_CURSOR_MEM_PWR_STATUS +#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_2_DMDATA_ADDRESS_HIGH +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_2_DMDATA_ADDRESS_LOW +#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_2_DMDATA_CNTL +#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_2_DMDATA_QOS_CNTL +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_2_DMDATA_STATUS +#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_2_DMDATA_SW_CNTL +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_2_DMDATA_SW_DATA +#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_dcbubp3_dispdec_hubp_dispdec +//HUBP3_DCSURF_SURFACE_CONFIG +#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP3_DCSURF_ADDR_CONFIG +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP3_DCSURF_TILING_CONFIG +#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP3_DCSURF_PRI_VIEWPORT_START +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_START_C +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_START +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_START_C +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP3_DCHUBP_REQ_SIZE_CONFIG +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP3_DCHUBP_CNTL +#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP3_HUBP_CLK_CNTL +#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT 0x18 +#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK 0x01000000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP3_DCHUBP_VMPG_CONFIG +#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT 0x1 +#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT 0x2 +#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT 0x7 +#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK 0x00000002L +#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK 0x0000007CL +#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK 0x00000080L +//HUBP3_DCHUBP_MALL_CONFIG +#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT 0x0 +#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT 0x2 +#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK 0x00000003L +#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK 0x00000004L +//HUBP3_DCHUBP_MALL_SUB_VP +#define HUBP3_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT 0x0 +#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT 0x1 +#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT 0xf +#define HUBP3_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK 0x00000001L +#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK 0x00007FFEL +#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK 0x1FFF8000L +//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +//HUBP3_HUBP_MALL_STATUS +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT 0x0 +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT 0x1 +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT 0x2 +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT 0x3 +#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT 0x4 +#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT 0x6 +#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT 0x7 +#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT 0x8 +#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT 0x9 +#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT 0xa +#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT 0xb +#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT 0xc +#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT 0xd +#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT 0xe +#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT 0xf +#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT 0x10 +#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT 0x11 +#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT 0x12 +#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT 0x13 +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK 0x00000001L +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK 0x00000002L +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK 0x00000004L +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK 0x00000008L +#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE_MASK 0x00000010L +#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK 0x00000040L +#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK 0x00000080L +#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK 0x00000100L +#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK 0x00000200L +#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK 0x00000400L +#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK 0x00000800L +#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK 0x00001000L +#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK 0x00002000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK 0x00004000L +#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK 0x00008000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK 0x00010000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK 0x00020000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK 0x00040000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK 0x00080000L + + +// addressBlock: dcn_dc_dcbubp3_dispdec_hubpreq_dispdec +//HUBPREQ3_DCSURF_SURFACE_PITCH +#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ3_DCSURF_SURFACE_PITCH_C +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ3_VMID_SETTINGS_0 +#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SURFACE_CONTROL +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x2 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x5 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0xa +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xd +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x0000000CL +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00000060L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x00000C00L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x00006000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L +//HUBPREQ3_DCSURF_FLIP_CONTROL +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ3_DCSURF_FLIP_CONTROL2 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ3_DCSURF_SURFACE_INUSE +#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ3_DCSURF_SURFACE_INUSE_C +#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ3_DCN_EXPANSION_MODE +#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ3_DCN_TTU_QOS_WM +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ3_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ3_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_DMDATA_VM_CNTL +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ3_BLANK_OFFSET_0 +#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ3_BLANK_OFFSET_1 +#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ3_DST_DIMENSIONS +#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ3_DST_AFTER_SCALER +#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ3_PREFETCH_SETTINGS +#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ3_PREFETCH_SETTINGS_C +#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_0 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ3_VBLANK_PARAMETERS_1 +#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_2 +#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_3 +#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_4 +#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_0 +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ3_FLIP_PARAMETERS_1 +#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_2 +#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_0 +#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_1 +#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_2 +#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_3 +#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_4 +#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_5 +#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_6 +#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_7 +#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ3_PER_LINE_DELIVERY_PRE +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ3_PER_LINE_DELIVERY +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ3_CURSOR_SETTINGS +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ3_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +//HUBPREQ3_VBLANK_PARAMETERS_5 +#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_6 +#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_3 +#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_4 +#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_5 +#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_6 +#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ3_UCLK_PSTATE_FORCE +#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT 0x0 +#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x1 +#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT 0x2 +#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x3 +#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK 0x00000001L +#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000002L +#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK 0x00000004L +#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000008L +//HUBPREQ3_HUBPREQ_STATUS_REG0 +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT 0x8 +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT 0x10 +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK 0x0000001FL +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK 0x00001F00L +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK 0x7FFF0000L +//HUBPREQ3_HUBPREQ_STATUS_REG1 +#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT 0x10 +#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK 0x00003FFFL +#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK 0x3FFF0000L +//HUBPREQ3_HUBPREQ_STATUS_REG2 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT 0x1 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT 0x2 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT 0x3 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT 0x4 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT 0x5 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT 0x8 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT 0x9 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT 0xa +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT 0xb +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT 0xc +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT 0xd +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT 0x10 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT 0x11 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT 0x12 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT 0x13 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT 0x14 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT 0x15 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT 0x1a +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT 0x1b +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT 0x1c +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT 0x1d +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT 0x1e +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT 0x1f +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK 0x00000001L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK 0x00000002L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK 0x00000004L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK 0x00000008L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK 0x00000010L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK 0x00000020L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK 0x00000100L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK 0x00000200L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK 0x00000400L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK 0x00000800L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK 0x00001000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK 0x00002000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK 0x00010000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK 0x00020000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK 0x00040000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK 0x00080000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK 0x00100000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK 0x00200000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK 0x04000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK 0x08000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK 0x10000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK 0x20000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK 0x40000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK 0x80000000L + + +// addressBlock: dcn_dc_dcbubp3_dispdec_hubpret_dispdec +//HUBPRET3_HUBPRET_CONTROL +#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00007FF0L +#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET3_HUBPRET_MEM_PWR_CTRL +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET3_HUBPRET_MEM_PWR_STATUS +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET3_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET3_HUBPRET_READ_LINE0 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE1 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_INTERRUPT +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET3_HUBPRET_READ_LINE_VALUE +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE_STATUS +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dcn_dc_dcbubp3_dispdec_cursor0_dispdec +//CURSOR0_3_CURSOR_CONTROL +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +//CURSOR0_3_CURSOR_SURFACE_ADDRESS +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_3_CURSOR_SIZE +#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_3_CURSOR_POSITION +#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_3_CURSOR_HOT_SPOT +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_3_CURSOR_STEREO_CONTROL +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_3_CURSOR_DST_OFFSET +#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_3_CURSOR_MEM_PWR_CTRL +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_3_CURSOR_MEM_PWR_STATUS +#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_3_DMDATA_ADDRESS_HIGH +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_3_DMDATA_ADDRESS_LOW +#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_3_DMDATA_CNTL +#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_3_DMDATA_QOS_CNTL +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_3_DMDATA_STATUS +#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_3_DMDATA_SW_CNTL +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_3_DMDATA_SW_DATA +#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_dpp0_dispdec_cnvc_cfg_dispdec +//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG0_FORMAT_CONTROL +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG0_FCNV_FP_BIAS_R +#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_BIAS_G +#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_BIAS_B +#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_R +#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_G +#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_B +#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG0_COLOR_KEYER_CONTROL +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG0_COLOR_KEYER_ALPHA +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_RED +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_GREEN +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_BLUE +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_ALPHA_2BIT_LUT +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L +//CNVC_CFG0_PRE_DEALPHA +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG0_PRE_CSC_MODE +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG0_PRE_CSC_C11_C12 +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C13_C14 +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C21_C22 +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C23_C24 +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C31_C32 +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C33_C34 +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C11_C12 +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C13_C14 +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C21_C22 +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C23_C24 +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C31_C32 +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C33_C34 +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG0_CNVC_COEF_FORMAT +#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG0_PRE_DEGAM +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG0_PRE_REALPHA +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dcn_dc_dpp0_dispdec_cnvc_cur_dispdec +//CNVC_CUR0_CURSOR0_CONTROL +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CNVC_CUR0_CURSOR0_COLOR0 +#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR0_CURSOR0_COLOR1 +#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR0_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dcn_dc_dpp0_dispdec_dscl_dispdec +//DSCL0_SCL_COEF_RAM_TAP_SELECT +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L +//DSCL0_SCL_COEF_RAM_TAP_DATA +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL0_SCL_MODE +#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL0_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL0_SCL_TAP_CONTROL +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL0_DSCL_CONTROL +#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL0_DSCL_2TAP_CONTROL +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL0_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL0_SCL_HORZ_FILTER_INIT +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL0_SCL_HORZ_FILTER_INIT_C +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL0_SCL_VERT_FILTER_INIT +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_INIT_BOT +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL0_SCL_VERT_FILTER_INIT_C +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL0_SCL_BLACK_COLOR +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL0_DSCL_UPDATE +#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL0_DSCL_AUTOCAL +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL0_OTG_H_BLANK +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL0_OTG_V_BLANK +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL0_RECOUT_START +#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL0_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL0_RECOUT_SIZE +#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL0_MPC_SIZE +#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL0_LB_DATA_FORMAT +#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL0_LB_MEMORY_CTRL +#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL0_LB_V_COUNTER +#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL0_DSCL_MEM_PWR_CTRL +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL0_DSCL_MEM_PWR_STATUS +#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL0_OBUF_CONTROL +#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL0_OBUF_MEM_PWR_CTRL +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dcn_dc_dpp0_dispdec_cm_dispdec +//CM0_CM_CONTROL +#define CM0_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM0_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM0_CM_POST_CSC_CONTROL +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM0_CM_POST_CSC_C11_C12 +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C13_C14 +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C21_C22 +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C23_C24 +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C31_C32 +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C33_C34 +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C11_C12 +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C13_C14 +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C21_C22 +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C23_C24 +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C31_C32 +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C33_C34 +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_CONTROL +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x2 +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK 0x0000000CL +//CM0_CM_GAMUT_REMAP_C11_C12 +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C13_C14 +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C21_C22 +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C23_C24 +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C31_C32 +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C33_C34 +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C11_C12 +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C13_C14 +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C21_C22 +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C23_C24 +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C31_C32 +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C33_C34 +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L +//CM0_CM_BIAS_CR_R +#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM0_CM_BIAS_Y_G_CB_B +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_CONTROL +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM0_CM_GAMCOR_LUT_INDEX +#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM0_CM_GAMCOR_LUT_DATA +#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_LUT_CONTROL +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM0_CM_GAMCOR_RAMA_START_CNTL_B +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMA_START_CNTL_G +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMA_START_CNTL_R +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMA_OFFSET_B +#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMA_OFFSET_G +#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMA_OFFSET_R +#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMA_REGION_0_1 +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_2_3 +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_4_5 +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_6_7 +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_8_9 +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_10_11 +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_12_13 +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_14_15 +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_16_17 +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_18_19 +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_20_21 +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_22_23 +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_24_25 +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_26_27 +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_28_29 +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_30_31 +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_32_33 +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_START_CNTL_B +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMB_START_CNTL_G +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMB_START_CNTL_R +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMB_OFFSET_B +#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMB_OFFSET_G +#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMB_OFFSET_R +#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMB_REGION_0_1 +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_2_3 +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_4_5 +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_6_7 +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_8_9 +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_10_11 +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_12_13 +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_14_15 +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_16_17 +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_18_19 +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_20_21 +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_22_23 +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_24_25 +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_26_27 +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_28_29 +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_30_31 +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_32_33 +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_HDR_MULT_COEF +#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM0_CM_MEM_PWR_CTRL +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +//CM0_CM_MEM_PWR_STATUS +#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +//CM0_CM_DEALPHA +#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM0_CM_COEF_FORMAT +#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L + + +// addressBlock: dcn_dc_dpp0_dispdec_dpp_top_dispdec +//DPP_TOP0_DPP_CONTROL +#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT 0x18 +#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK 0x01000000L +#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP0_DPP_SOFT_RESET +#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP0_DPP_CRC_VAL_R_G +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP0_DPP_CRC_VAL_B_A +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP0_DPP_CRC_CTRL +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xe +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x0000C000L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP0_HOST_READ_CONTROL +#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dcn_dc_dpp1_dispdec_cnvc_cfg_dispdec +//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG1_FORMAT_CONTROL +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG1_FCNV_FP_BIAS_R +#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_BIAS_G +#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_BIAS_B +#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_R +#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_G +#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_B +#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG1_COLOR_KEYER_CONTROL +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG1_COLOR_KEYER_ALPHA +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_RED +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_GREEN +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_BLUE +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_ALPHA_2BIT_LUT +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L +//CNVC_CFG1_PRE_DEALPHA +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG1_PRE_CSC_MODE +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG1_PRE_CSC_C11_C12 +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C13_C14 +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C21_C22 +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C23_C24 +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C31_C32 +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C33_C34 +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C11_C12 +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C13_C14 +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C21_C22 +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C23_C24 +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C31_C32 +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C33_C34 +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG1_CNVC_COEF_FORMAT +#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG1_PRE_DEGAM +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG1_PRE_REALPHA +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dcn_dc_dpp1_dispdec_cnvc_cur_dispdec +//CNVC_CUR1_CURSOR0_CONTROL +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CNVC_CUR1_CURSOR0_COLOR0 +#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR1_CURSOR0_COLOR1 +#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR1_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dcn_dc_dpp1_dispdec_dscl_dispdec +//DSCL1_SCL_COEF_RAM_TAP_SELECT +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L +//DSCL1_SCL_COEF_RAM_TAP_DATA +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL1_SCL_MODE +#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL1_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL1_SCL_TAP_CONTROL +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL1_DSCL_CONTROL +#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL1_DSCL_2TAP_CONTROL +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL1_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL1_SCL_HORZ_FILTER_INIT +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL1_SCL_HORZ_FILTER_INIT_C +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL1_SCL_VERT_FILTER_INIT +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_INIT_BOT +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL1_SCL_VERT_FILTER_INIT_C +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL1_SCL_BLACK_COLOR +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL1_DSCL_UPDATE +#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL1_DSCL_AUTOCAL +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL1_OTG_H_BLANK +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL1_OTG_V_BLANK +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL1_RECOUT_START +#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL1_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL1_RECOUT_SIZE +#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL1_MPC_SIZE +#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL1_LB_DATA_FORMAT +#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL1_LB_MEMORY_CTRL +#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL1_LB_V_COUNTER +#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL1_DSCL_MEM_PWR_CTRL +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL1_DSCL_MEM_PWR_STATUS +#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL1_OBUF_CONTROL +#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL1_OBUF_MEM_PWR_CTRL +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dcn_dc_dpp1_dispdec_cm_dispdec +//CM1_CM_CONTROL +#define CM1_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM1_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM1_CM_POST_CSC_CONTROL +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM1_CM_POST_CSC_C11_C12 +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C13_C14 +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C21_C22 +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C23_C24 +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C31_C32 +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C33_C34 +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C11_C12 +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C13_C14 +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C21_C22 +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C23_C24 +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C31_C32 +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C33_C34 +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_CONTROL +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x2 +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK 0x0000000CL +//CM1_CM_GAMUT_REMAP_C11_C12 +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C13_C14 +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C21_C22 +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C23_C24 +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C31_C32 +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C33_C34 +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C11_C12 +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C13_C14 +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C21_C22 +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C23_C24 +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C31_C32 +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C33_C34 +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L +//CM1_CM_BIAS_CR_R +#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM1_CM_BIAS_Y_G_CB_B +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_CONTROL +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM1_CM_GAMCOR_LUT_INDEX +#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM1_CM_GAMCOR_LUT_DATA +#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_LUT_CONTROL +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM1_CM_GAMCOR_RAMA_START_CNTL_B +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMA_START_CNTL_G +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMA_START_CNTL_R +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMA_OFFSET_B +#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMA_OFFSET_G +#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMA_OFFSET_R +#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMA_REGION_0_1 +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_2_3 +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_4_5 +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_6_7 +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_8_9 +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_10_11 +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_12_13 +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_14_15 +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_16_17 +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_18_19 +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_20_21 +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_22_23 +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_24_25 +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_26_27 +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_28_29 +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_30_31 +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_32_33 +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_START_CNTL_B +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMB_START_CNTL_G +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMB_START_CNTL_R +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMB_OFFSET_B +#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMB_OFFSET_G +#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMB_OFFSET_R +#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMB_REGION_0_1 +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_2_3 +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_4_5 +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_6_7 +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_8_9 +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_10_11 +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_12_13 +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_14_15 +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_16_17 +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_18_19 +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_20_21 +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_22_23 +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_24_25 +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_26_27 +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_28_29 +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_30_31 +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_32_33 +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_HDR_MULT_COEF +#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM1_CM_MEM_PWR_CTRL +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +//CM1_CM_MEM_PWR_STATUS +#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +//CM1_CM_DEALPHA +#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM1_CM_COEF_FORMAT +#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L + + +// addressBlock: dcn_dc_dpp1_dispdec_dpp_top_dispdec +//DPP_TOP1_DPP_CONTROL +#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT 0x18 +#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK 0x01000000L +#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP1_DPP_SOFT_RESET +#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP1_DPP_CRC_VAL_R_G +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP1_DPP_CRC_VAL_B_A +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP1_DPP_CRC_CTRL +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xe +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x0000C000L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP1_HOST_READ_CONTROL +#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dcn_dc_dpp2_dispdec_cnvc_cfg_dispdec +//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG2_FORMAT_CONTROL +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG2_FCNV_FP_BIAS_R +#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_BIAS_G +#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_BIAS_B +#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_SCALE_R +#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_SCALE_G +#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_SCALE_B +#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG2_COLOR_KEYER_CONTROL +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG2_COLOR_KEYER_ALPHA +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_RED +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_GREEN +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_BLUE +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_ALPHA_2BIT_LUT +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L +//CNVC_CFG2_PRE_DEALPHA +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG2_PRE_CSC_MODE +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG2_PRE_CSC_C11_C12 +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C13_C14 +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C21_C22 +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C23_C24 +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C31_C32 +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C33_C34 +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C11_C12 +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C13_C14 +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C21_C22 +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C23_C24 +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C31_C32 +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C33_C34 +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG2_CNVC_COEF_FORMAT +#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG2_PRE_DEGAM +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG2_PRE_REALPHA +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dcn_dc_dpp2_dispdec_cnvc_cur_dispdec +//CNVC_CUR2_CURSOR0_CONTROL +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CNVC_CUR2_CURSOR0_COLOR0 +#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR2_CURSOR0_COLOR1 +#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR2_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dcn_dc_dpp2_dispdec_dscl_dispdec +//DSCL2_SCL_COEF_RAM_TAP_SELECT +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L +//DSCL2_SCL_COEF_RAM_TAP_DATA +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL2_SCL_MODE +#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL2_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL2_SCL_TAP_CONTROL +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL2_DSCL_CONTROL +#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL2_DSCL_2TAP_CONTROL +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL2_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL2_SCL_HORZ_FILTER_INIT +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL2_SCL_HORZ_FILTER_INIT_C +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL2_SCL_VERT_FILTER_INIT +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_INIT_BOT +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL2_SCL_VERT_FILTER_INIT_C +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL2_SCL_BLACK_COLOR +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL2_DSCL_UPDATE +#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL2_DSCL_AUTOCAL +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL2_OTG_H_BLANK +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL2_OTG_V_BLANK +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL2_RECOUT_START +#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL2_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL2_RECOUT_SIZE +#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL2_MPC_SIZE +#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL2_LB_DATA_FORMAT +#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL2_LB_MEMORY_CTRL +#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL2_LB_V_COUNTER +#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL2_DSCL_MEM_PWR_CTRL +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL2_DSCL_MEM_PWR_STATUS +#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL2_OBUF_CONTROL +#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL2_OBUF_MEM_PWR_CTRL +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dcn_dc_dpp2_dispdec_cm_dispdec +//CM2_CM_CONTROL +#define CM2_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM2_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM2_CM_POST_CSC_CONTROL +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM2_CM_POST_CSC_C11_C12 +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C13_C14 +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C21_C22 +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C23_C24 +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C31_C32 +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C33_C34 +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C11_C12 +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C13_C14 +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C21_C22 +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C23_C24 +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C31_C32 +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C33_C34 +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_CONTROL +#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x2 +#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK 0x0000000CL +//CM2_CM_GAMUT_REMAP_C11_C12 +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C13_C14 +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C21_C22 +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C23_C24 +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C31_C32 +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C33_C34 +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C11_C12 +#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C13_C14 +#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C21_C22 +#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C23_C24 +#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C31_C32 +#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C33_C34 +#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L +//CM2_CM_BIAS_CR_R +#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM2_CM_BIAS_Y_G_CB_B +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_CONTROL +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM2_CM_GAMCOR_LUT_INDEX +#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM2_CM_GAMCOR_LUT_DATA +#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_LUT_CONTROL +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM2_CM_GAMCOR_RAMA_START_CNTL_B +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMA_START_CNTL_G +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMA_START_CNTL_R +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMA_OFFSET_B +#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMA_OFFSET_G +#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMA_OFFSET_R +#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMA_REGION_0_1 +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_2_3 +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_4_5 +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_6_7 +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_8_9 +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_10_11 +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_12_13 +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_14_15 +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_16_17 +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_18_19 +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_20_21 +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_22_23 +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_24_25 +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_26_27 +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_28_29 +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_30_31 +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_32_33 +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_START_CNTL_B +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMB_START_CNTL_G +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMB_START_CNTL_R +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMB_OFFSET_B +#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMB_OFFSET_G +#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMB_OFFSET_R +#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMB_REGION_0_1 +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_2_3 +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_4_5 +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_6_7 +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_8_9 +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_10_11 +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_12_13 +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_14_15 +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_16_17 +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_18_19 +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_20_21 +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_22_23 +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_24_25 +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_26_27 +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_28_29 +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_30_31 +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_32_33 +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_HDR_MULT_COEF +#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM2_CM_MEM_PWR_CTRL +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +//CM2_CM_MEM_PWR_STATUS +#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +//CM2_CM_DEALPHA +#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM2_CM_COEF_FORMAT +#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L + + +// addressBlock: dcn_dc_dpp2_dispdec_dpp_top_dispdec +//DPP_TOP2_DPP_CONTROL +#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT 0x18 +#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK 0x01000000L +#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP2_DPP_SOFT_RESET +#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP2_DPP_CRC_VAL_R_G +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP2_DPP_CRC_VAL_B_A +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP2_DPP_CRC_CTRL +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xe +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x0000C000L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP2_HOST_READ_CONTROL +#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dcn_dc_dpp3_dispdec_cnvc_cfg_dispdec +//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG3_FORMAT_CONTROL +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG3_FCNV_FP_BIAS_R +#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_BIAS_G +#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_BIAS_B +#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_SCALE_R +#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_SCALE_G +#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_SCALE_B +#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG3_COLOR_KEYER_CONTROL +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG3_COLOR_KEYER_ALPHA +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_RED +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_GREEN +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_BLUE +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_ALPHA_2BIT_LUT +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L +//CNVC_CFG3_PRE_DEALPHA +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG3_PRE_CSC_MODE +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG3_PRE_CSC_C11_C12 +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C13_C14 +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C21_C22 +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C23_C24 +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C31_C32 +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C33_C34 +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C11_C12 +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C13_C14 +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C21_C22 +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C23_C24 +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C31_C32 +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C33_C34 +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG3_CNVC_COEF_FORMAT +#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG3_PRE_DEGAM +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG3_PRE_REALPHA +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dcn_dc_dpp3_dispdec_cnvc_cur_dispdec +//CNVC_CUR3_CURSOR0_CONTROL +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CNVC_CUR3_CURSOR0_COLOR0 +#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR3_CURSOR0_COLOR1 +#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR3_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dcn_dc_dpp3_dispdec_dscl_dispdec +//DSCL3_SCL_COEF_RAM_TAP_SELECT +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L +//DSCL3_SCL_COEF_RAM_TAP_DATA +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL3_SCL_MODE +#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL3_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL3_SCL_TAP_CONTROL +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL3_DSCL_CONTROL +#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL3_DSCL_2TAP_CONTROL +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL3_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL3_SCL_HORZ_FILTER_INIT +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL3_SCL_HORZ_FILTER_INIT_C +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL3_SCL_VERT_FILTER_INIT +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_INIT_BOT +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL3_SCL_VERT_FILTER_INIT_C +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL3_SCL_BLACK_COLOR +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL3_DSCL_UPDATE +#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL3_DSCL_AUTOCAL +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL3_OTG_H_BLANK +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL3_OTG_V_BLANK +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL3_RECOUT_START +#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL3_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL3_RECOUT_SIZE +#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL3_MPC_SIZE +#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL3_LB_DATA_FORMAT +#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL3_LB_MEMORY_CTRL +#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL3_LB_V_COUNTER +#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL3_DSCL_MEM_PWR_CTRL +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL3_DSCL_MEM_PWR_STATUS +#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL3_OBUF_CONTROL +#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL3_OBUF_MEM_PWR_CTRL +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dcn_dc_dpp3_dispdec_cm_dispdec +//CM3_CM_CONTROL +#define CM3_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM3_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM3_CM_POST_CSC_CONTROL +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM3_CM_POST_CSC_C11_C12 +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C13_C14 +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C21_C22 +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C23_C24 +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C31_C32 +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C33_C34 +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C11_C12 +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C13_C14 +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C21_C22 +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C23_C24 +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C31_C32 +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C33_C34 +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_CONTROL +#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x2 +#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK 0x0000000CL +//CM3_CM_GAMUT_REMAP_C11_C12 +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C13_C14 +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C21_C22 +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C23_C24 +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C31_C32 +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C33_C34 +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C11_C12 +#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C13_C14 +#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C21_C22 +#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C23_C24 +#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C31_C32 +#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C33_C34 +#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L +//CM3_CM_BIAS_CR_R +#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM3_CM_BIAS_Y_G_CB_B +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_CONTROL +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM3_CM_GAMCOR_LUT_INDEX +#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM3_CM_GAMCOR_LUT_DATA +#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_LUT_CONTROL +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM3_CM_GAMCOR_RAMA_START_CNTL_B +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMA_START_CNTL_G +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMA_START_CNTL_R +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMA_OFFSET_B +#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMA_OFFSET_G +#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMA_OFFSET_R +#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMA_REGION_0_1 +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_2_3 +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_4_5 +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_6_7 +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_8_9 +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_10_11 +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_12_13 +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_14_15 +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_16_17 +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_18_19 +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_20_21 +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_22_23 +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_24_25 +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_26_27 +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_28_29 +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_30_31 +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_32_33 +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_START_CNTL_B +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMB_START_CNTL_G +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMB_START_CNTL_R +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMB_OFFSET_B +#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMB_OFFSET_G +#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMB_OFFSET_R +#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMB_REGION_0_1 +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_2_3 +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_4_5 +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_6_7 +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_8_9 +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_10_11 +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_12_13 +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_14_15 +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_16_17 +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_18_19 +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_20_21 +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_22_23 +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_24_25 +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_26_27 +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_28_29 +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_30_31 +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_32_33 +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_HDR_MULT_COEF +#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM3_CM_MEM_PWR_CTRL +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +//CM3_CM_MEM_PWR_STATUS +#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +//CM3_CM_DEALPHA +#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM3_CM_COEF_FORMAT +#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L + + +// addressBlock: dcn_dc_dpp3_dispdec_dpp_top_dispdec +//DPP_TOP3_DPP_CONTROL +#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT 0x18 +#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK 0x01000000L +#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP3_DPP_SOFT_RESET +#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP3_DPP_CRC_VAL_R_G +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP3_DPP_CRC_VAL_B_A +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP3_DPP_CRC_CTRL +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xe +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x0000C000L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP3_HOST_READ_CONTROL +#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dcn_dc_mpc_mpcc0_dispdec +//MPCC0_MPCC_TOP_SEL +#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC0_MPCC_BOT_SEL +#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC0_MPCC_OPP_ID +#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC0_MPCC_CONTROL +#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC0_MPCC_SM_CONTROL +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC0_MPCC_UPDATE_LOCK_SEL +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC0_MPCC_TOP_GAIN +#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC0_MPCC_BOT_GAIN_INSIDE +#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC0_MPCC_BOT_GAIN_OUTSIDE +#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL +#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 +#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 +#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L +#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L +//MPCC0_MPCC_BG_R_CR +#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC0_MPCC_BG_G_Y +#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC0_MPCC_BG_B_CB +#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC0_MPCC_MEM_PWR_CTRL +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC0_MPCC_STATUS +#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dcn_dc_mpc_mpcc1_dispdec +//MPCC1_MPCC_TOP_SEL +#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC1_MPCC_BOT_SEL +#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC1_MPCC_OPP_ID +#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC1_MPCC_CONTROL +#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC1_MPCC_SM_CONTROL +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC1_MPCC_UPDATE_LOCK_SEL +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC1_MPCC_TOP_GAIN +#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC1_MPCC_BOT_GAIN_INSIDE +#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC1_MPCC_BOT_GAIN_OUTSIDE +#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL +#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 +#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 +#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L +#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L +//MPCC1_MPCC_BG_R_CR +#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC1_MPCC_BG_G_Y +#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC1_MPCC_BG_B_CB +#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC1_MPCC_MEM_PWR_CTRL +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC1_MPCC_STATUS +#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dcn_dc_mpc_mpcc2_dispdec +//MPCC2_MPCC_TOP_SEL +#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC2_MPCC_BOT_SEL +#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC2_MPCC_OPP_ID +#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC2_MPCC_CONTROL +#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC2_MPCC_SM_CONTROL +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC2_MPCC_UPDATE_LOCK_SEL +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC2_MPCC_TOP_GAIN +#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC2_MPCC_BOT_GAIN_INSIDE +#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC2_MPCC_BOT_GAIN_OUTSIDE +#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL +#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 +#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 +#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L +#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L +//MPCC2_MPCC_BG_R_CR +#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC2_MPCC_BG_G_Y +#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC2_MPCC_BG_B_CB +#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC2_MPCC_MEM_PWR_CTRL +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC2_MPCC_STATUS +#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dcn_dc_mpc_mpcc3_dispdec +//MPCC3_MPCC_TOP_SEL +#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC3_MPCC_BOT_SEL +#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC3_MPCC_OPP_ID +#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC3_MPCC_CONTROL +#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC3_MPCC_SM_CONTROL +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC3_MPCC_UPDATE_LOCK_SEL +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC3_MPCC_TOP_GAIN +#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC3_MPCC_BOT_GAIN_INSIDE +#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC3_MPCC_BOT_GAIN_OUTSIDE +#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL +#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 +#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 +#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L +#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L +//MPCC3_MPCC_BG_R_CR +#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC3_MPCC_BG_G_Y +#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC3_MPCC_BG_B_CB +#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC3_MPCC_MEM_PWR_CTRL +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC3_MPCC_STATUS +#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dcn_dc_mpc_mpc_cfg_dispdec +//MPC_CLOCK_CONTROL +#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x1 +#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT 0x4 +#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00000002L +#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK 0x00000030L +//MPC_SOFT_RESET +#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT 0x0 +#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT 0x1 +#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT 0x2 +#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT 0x3 +#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT 0xa +#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT 0xb +#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT 0xc +#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT 0xd +#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT 0x14 +#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT 0x15 +#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT 0x16 +#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT 0x17 +#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x1f +#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK 0x00000001L +#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK 0x00000002L +#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK 0x00000004L +#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK 0x00000008L +#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK 0x00000400L +#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK 0x00000800L +#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK 0x00001000L +#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK 0x00002000L +#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK 0x00100000L +#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK 0x00200000L +#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK 0x00400000L +#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK 0x00800000L +#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK 0x80000000L +//MPC_CRC_CTRL +#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT 0x0 +#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT 0x4 +#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT 0x8 +#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT 0xa +#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT 0xc +#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT 0x18 +#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT 0x1e +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT 0x1f +#define MPC_CRC_CTRL__MPC_CRC_EN_MASK 0x00000001L +#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK 0x00000010L +#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK 0x00000300L +#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK 0x00000400L +#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK 0x00003000L +#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK 0x03000000L +#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK 0x40000000L +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK 0x80000000L +//MPC_CRC_SEL_CONTROL +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT 0x0 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT 0x4 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL__SHIFT 0x8 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT 0x10 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK 0x0000000FL +#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK 0x000000F0L +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL_MASK 0x00000300L +#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK 0xFFFF0000L +//MPC_CRC_RESULT_AR +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT 0x0 +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT 0x10 +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK 0x0000FFFFL +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK 0xFFFF0000L +//MPC_CRC_RESULT_GB +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT 0x0 +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT 0x10 +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK 0x0000FFFFL +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK 0xFFFF0000L +//MPC_CRC_RESULT_C +#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT 0x0 +#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK 0x0000FFFFL +//MPC_BYPASS_BG_AR +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT 0x0 +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT 0x10 +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK 0x0000FFFFL +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK 0xFFFF0000L +//MPC_BYPASS_BG_GB +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT 0x0 +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT 0x10 +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK 0x0000FFFFL +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK 0xFFFF0000L +//MPC_HOST_READ_CONTROL +#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL +//MPC_DPP_PENDING_STATUS +#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT 0x0 +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT 0x1 +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT 0x2 +#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT 0x4 +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT 0x5 +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT 0x6 +#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT 0x8 +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT 0x9 +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT 0xa +#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT 0xc +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT 0xd +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT 0xe +#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING_MASK 0x00000001L +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING_MASK 0x00000002L +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING_MASK 0x00000004L +#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING_MASK 0x00000010L +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING_MASK 0x00000020L +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING_MASK 0x00000040L +#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING_MASK 0x00000100L +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING_MASK 0x00000200L +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING_MASK 0x00000400L +#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING_MASK 0x00001000L +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING_MASK 0x00002000L +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING_MASK 0x00004000L +//MPC_PENDING_STATUS_MISC +#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT 0x0 +#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT 0x1 +#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT 0x2 +#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT 0x3 +#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING__SHIFT 0x8 +#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING__SHIFT 0x9 +#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING__SHIFT 0xa +#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING__SHIFT 0xb +#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING__SHIFT 0x10 +#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK 0x00000001L +#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK 0x00000002L +#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK 0x00000004L +#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK 0x00000008L +#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING_MASK 0x00000100L +#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING_MASK 0x00000200L +#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING_MASK 0x00000400L +#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING_MASK 0x00000800L +#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING_MASK 0x00010000L +//ADR_CFG_CUR_VUPDATE_LOCK_SET0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET0 +#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET0 +#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET0 +#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET0 +#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET1 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET1 +#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET1 +#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET1 +#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET1 +#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET2 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET2 +#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET2 +#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET2 +#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET2 +#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET3 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET3 +#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET3 +#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET3 +#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET3 +#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//MPC_DWB0_MUX +#define MPC_DWB0_MUX__MPC_DWB0_MUX__SHIFT 0x0 +#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS__SHIFT 0x4 +#define MPC_DWB0_MUX__MPC_DWB0_MUX_MASK 0x0000000FL +#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS_MASK 0x000000F0L + + +// addressBlock: dcn_dc_mpc_mpcc_ogam0_dispdec +//MPCC_OGAM0_MPCC_OGAM_CONTROL +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM0_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dcn_dc_mpc_mpcc_ogam1_dispdec +//MPCC_OGAM1_MPCC_OGAM_CONTROL +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM1_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dcn_dc_mpc_mpcc_ogam2_dispdec +//MPCC_OGAM2_MPCC_OGAM_CONTROL +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM2_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM2_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dcn_dc_mpc_mpcc_ogam3_dispdec +//MPCC_OGAM3_MPCC_OGAM_CONTROL +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM3_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM3_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dcn_dc_mpc_mpcc_mcm0_dispdec +//MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL +#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_3DLUT_MODE +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK 0x00000010L +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPCC_MCM0_MPCC_MCM_3DLUT_INDEX +#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL +//MPCC_MCM0_MPCC_MCM_3DLUT_DATA +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT 0x2 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK 0x00000004L +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L +//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL +//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L + + +// addressBlock: dcn_dc_mpc_mpcc_mcm1_dispdec +//MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL +#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_3DLUT_MODE +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK 0x00000010L +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPCC_MCM1_MPCC_MCM_3DLUT_INDEX +#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL +//MPCC_MCM1_MPCC_MCM_3DLUT_DATA +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT 0x2 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK 0x00000004L +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L +//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL +//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L + + +// addressBlock: dcn_dc_mpc_mpcc_mcm2_dispdec +//MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL +#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_3DLUT_MODE +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK 0x00000010L +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPCC_MCM2_MPCC_MCM_3DLUT_INDEX +#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL +//MPCC_MCM2_MPCC_MCM_3DLUT_DATA +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT 0x2 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK 0x00000004L +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L +//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL +//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L + + +// addressBlock: dcn_dc_mpc_mpcc_mcm3_dispdec +//MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL +#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_3DLUT_MODE +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK 0x00000010L +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPCC_MCM3_MPCC_MCM_3DLUT_INDEX +#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL +//MPCC_MCM3_MPCC_MCM_3DLUT_DATA +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT 0x2 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK 0x00000004L +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L +//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL +//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L + + +// addressBlock: dcn_dc_mpc_mpc_ocsc_dispdec +//MPC_OUT0_MUX +#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT0_DENORM_CONTROL +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT0_DENORM_CLAMP_G_Y +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT0_DENORM_CLAMP_B_CB +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT1_MUX +#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT1_DENORM_CONTROL +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT1_DENORM_CLAMP_G_Y +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT1_DENORM_CLAMP_B_CB +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT2_MUX +#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT2_DENORM_CONTROL +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT2_DENORM_CLAMP_G_Y +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT2_DENORM_CLAMP_B_CB +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT3_MUX +#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT3_DENORM_CONTROL +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT3_DENORM_CLAMP_G_Y +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT3_DENORM_CLAMP_B_CB +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT_CSC_COEF_FORMAT +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT 0x0 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT 0x1 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT 0x2 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT 0x3 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK 0x00000001L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK 0x00000002L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK 0x00000004L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK 0x00000008L +//MPC_OUT0_CSC_MODE +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT0_CSC_C11_C12_A +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C13_C14_A +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C21_C22_A +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C23_C24_A +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C31_C32_A +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C33_C34_A +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C11_C12_B +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C13_C14_B +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C21_C22_B +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C23_C24_B +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C31_C32_B +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C33_C34_B +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_MODE +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT1_CSC_C11_C12_A +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C13_C14_A +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C21_C22_A +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C23_C24_A +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C31_C32_A +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C33_C34_A +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C11_C12_B +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C13_C14_B +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C21_C22_B +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C23_C24_B +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C31_C32_B +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C33_C34_B +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_MODE +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT2_CSC_C11_C12_A +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C13_C14_A +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C21_C22_A +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C23_C24_A +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C31_C32_A +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C33_C34_A +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C11_C12_B +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C13_C14_B +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C21_C22_B +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C23_C24_B +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C31_C32_B +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C33_C34_B +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_MODE +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT3_CSC_C11_C12_A +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C13_C14_A +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C21_C22_A +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C23_C24_A +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C31_C32_A +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C33_C34_A +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C11_C12_B +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C13_C14_B +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C21_C22_B +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C23_C24_B +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C31_C32_B +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C33_C34_B +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dcn_dc_opp_abm0_dispdec +//ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_USER_LEVEL +#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_TARGET_ABM_LEVEL +#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM0_BL1_PWM_ABM_CNTL +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_BL1_PWM_GRP2_REG_LOCK +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//ABM0_DC_ABM1_CNTL +#define ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM0_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM0_DC_ABM1_IPCSC_COEFF_SEL +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_THRES_12 +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_THRES_34 +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_CNTL_MISC +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM0_DC_ABM1_HG_MISC_CTRL +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_LS_SUM_OF_LUMA +#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L +//ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L +//ABM0_DC_ABM1_LS_PIXEL_COUNT +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L +//ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM0_DC_ABM1_HG_SAMPLE_RATE +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_LS_SAMPLE_RATE +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_1 +#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_2 +#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_3 +#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_4 +#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_5 +#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_6 +#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_7 +#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_8 +#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_9 +#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_10 +#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_11 +#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_12 +#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_13 +#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_14 +#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_15 +#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_16 +#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_17 +#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_18 +#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_19 +#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_20 +#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_21 +#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_22 +#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_23 +#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_24 +#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_BL_MASTER_LOCK +#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dcn_dc_opp_abm1_dispdec +//ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_USER_LEVEL +#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_TARGET_ABM_LEVEL +#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM1_BL1_PWM_ABM_CNTL +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_BL1_PWM_GRP2_REG_LOCK +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//ABM1_DC_ABM1_CNTL +#define ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM1_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM1_DC_ABM1_IPCSC_COEFF_SEL +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_THRES_12 +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_THRES_34 +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_CNTL_MISC +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM1_DC_ABM1_HG_MISC_CTRL +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_LS_SUM_OF_LUMA +#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L +//ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L +//ABM1_DC_ABM1_LS_PIXEL_COUNT +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L +//ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM1_DC_ABM1_HG_SAMPLE_RATE +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_LS_SAMPLE_RATE +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_1 +#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_2 +#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_3 +#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_4 +#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_5 +#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_6 +#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_7 +#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_8 +#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_9 +#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_10 +#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_11 +#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_12 +#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_13 +#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_14 +#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_15 +#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_16 +#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_17 +#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_18 +#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_19 +#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_20 +#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_21 +#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_22 +#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_23 +#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_24 +#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_BL_MASTER_LOCK +#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dcn_dc_opp_abm2_dispdec +//ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_USER_LEVEL +#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_TARGET_ABM_LEVEL +#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM2_BL1_PWM_ABM_CNTL +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM2_BL1_PWM_GRP2_REG_LOCK +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//ABM2_DC_ABM1_CNTL +#define ABM2_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM2_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM2_DC_ABM1_IPCSC_COEFF_SEL +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_THRES_12 +#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL +#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L +#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_THRES_34 +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_CNTL_MISC +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM2_DC_ABM1_HG_MISC_CTRL +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_LS_SUM_OF_LUMA +#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L +//ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L +//ABM2_DC_ABM1_LS_PIXEL_COUNT +#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 +#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L +//ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM2_DC_ABM1_HG_SAMPLE_RATE +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_LS_SAMPLE_RATE +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_1 +#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_2 +#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_3 +#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_4 +#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_5 +#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_6 +#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_7 +#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_8 +#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_9 +#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_10 +#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_11 +#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_12 +#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_13 +#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_14 +#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_15 +#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_16 +#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_17 +#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_18 +#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_19 +#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_20 +#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_21 +#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_22 +#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_23 +#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_24 +#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_BL_MASTER_LOCK +#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dcn_dc_opp_abm3_dispdec +//ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_USER_LEVEL +#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_TARGET_ABM_LEVEL +#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM3_BL1_PWM_ABM_CNTL +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM3_BL1_PWM_GRP2_REG_LOCK +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//ABM3_DC_ABM1_CNTL +#define ABM3_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM3_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM3_DC_ABM1_IPCSC_COEFF_SEL +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_THRES_12 +#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL +#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L +#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_THRES_34 +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_CNTL_MISC +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM3_DC_ABM1_HG_MISC_CTRL +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_LS_SUM_OF_LUMA +#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L +//ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L +//ABM3_DC_ABM1_LS_PIXEL_COUNT +#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 +#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L +//ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM3_DC_ABM1_HG_SAMPLE_RATE +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_LS_SAMPLE_RATE +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_1 +#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_2 +#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_3 +#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_4 +#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_5 +#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_6 +#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_7 +#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_8 +#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_9 +#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_10 +#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_11 +#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_12 +#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_13 +#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_14 +#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_15 +#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_16 +#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_17 +#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_18 +#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_19 +#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_20 +#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_21 +#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_22 +#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_23 +#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_24 +#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_BL_MASTER_LOCK +#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dcn_dc_opp_dpg0_dispdec +//DPG0_DPG_CONTROL +#define DPG0_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG0_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG0_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG0_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG0_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG0_DPG_RAMP_CONTROL +#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG0_DPG_DIMENSIONS +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG0_DPG_COLOUR_R_CR +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG0_DPG_COLOUR_G_Y +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG0_DPG_COLOUR_B_CB +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG0_DPG_OFFSET_SEGMENT +#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG0_DPG_STATUS +#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dcn_dc_opp_fmt0_dispdec +//FMT0_FMT_CLAMP_COMPONENT_R +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_COMPONENT_G +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_COMPONENT_B +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT0_FMT_DYNAMIC_EXP_CNTL +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT0_FMT_CONTROL +#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT0_FMT_BIT_DEPTH_CONTROL +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT0_FMT_DITHER_RAND_R_SEED +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT0_FMT_DITHER_RAND_G_SEED +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT0_FMT_DITHER_RAND_B_SEED +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_CNTL +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT0_FMT_MAP420_MEMORY_CONTROL +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT0_FMT_422_CONTROL +#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dcn_dc_opp_oppbuf0_dispdec +//OPPBUF0_OPPBUF_CONTROL +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF0_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF0_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF0_OPPBUF_CONTROL1 +#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dcn_dc_opp_opp_pipe0_dispdec +//OPP_PIPE0_OPP_PIPE_CONTROL +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dcn_dc_opp_opp_pipe_crc0_dispdec +//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dcn_dc_opp_dpg1_dispdec +//DPG1_DPG_CONTROL +#define DPG1_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG1_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG1_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG1_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG1_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG1_DPG_RAMP_CONTROL +#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG1_DPG_DIMENSIONS +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG1_DPG_COLOUR_R_CR +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG1_DPG_COLOUR_G_Y +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG1_DPG_COLOUR_B_CB +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG1_DPG_OFFSET_SEGMENT +#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG1_DPG_STATUS +#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dcn_dc_opp_fmt1_dispdec +//FMT1_FMT_CLAMP_COMPONENT_R +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_COMPONENT_G +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_COMPONENT_B +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT1_FMT_DYNAMIC_EXP_CNTL +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT1_FMT_CONTROL +#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT1_FMT_BIT_DEPTH_CONTROL +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT1_FMT_DITHER_RAND_R_SEED +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT1_FMT_DITHER_RAND_G_SEED +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT1_FMT_DITHER_RAND_B_SEED +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_CNTL +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT1_FMT_MAP420_MEMORY_CONTROL +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT1_FMT_422_CONTROL +#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dcn_dc_opp_oppbuf1_dispdec +//OPPBUF1_OPPBUF_CONTROL +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF1_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF1_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF1_OPPBUF_CONTROL1 +#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dcn_dc_opp_opp_pipe1_dispdec +//OPP_PIPE1_OPP_PIPE_CONTROL +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dcn_dc_opp_opp_pipe_crc1_dispdec +//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dcn_dc_opp_dpg2_dispdec +//DPG2_DPG_CONTROL +#define DPG2_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG2_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG2_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG2_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG2_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG2_DPG_RAMP_CONTROL +#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG2_DPG_DIMENSIONS +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG2_DPG_COLOUR_R_CR +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG2_DPG_COLOUR_G_Y +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG2_DPG_COLOUR_B_CB +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG2_DPG_OFFSET_SEGMENT +#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG2_DPG_STATUS +#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dcn_dc_opp_fmt2_dispdec +//FMT2_FMT_CLAMP_COMPONENT_R +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_COMPONENT_G +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_COMPONENT_B +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT2_FMT_DYNAMIC_EXP_CNTL +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT2_FMT_CONTROL +#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT2_FMT_BIT_DEPTH_CONTROL +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT2_FMT_DITHER_RAND_R_SEED +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT2_FMT_DITHER_RAND_G_SEED +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT2_FMT_DITHER_RAND_B_SEED +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_CNTL +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT2_FMT_MAP420_MEMORY_CONTROL +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT2_FMT_422_CONTROL +#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dcn_dc_opp_oppbuf2_dispdec +//OPPBUF2_OPPBUF_CONTROL +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF2_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF2_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF2_OPPBUF_CONTROL1 +#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dcn_dc_opp_opp_pipe2_dispdec +//OPP_PIPE2_OPP_PIPE_CONTROL +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dcn_dc_opp_opp_pipe_crc2_dispdec +//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dcn_dc_opp_dpg3_dispdec +//DPG3_DPG_CONTROL +#define DPG3_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG3_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG3_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG3_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG3_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG3_DPG_RAMP_CONTROL +#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG3_DPG_DIMENSIONS +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG3_DPG_COLOUR_R_CR +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG3_DPG_COLOUR_G_Y +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG3_DPG_COLOUR_B_CB +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG3_DPG_OFFSET_SEGMENT +#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG3_DPG_STATUS +#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dcn_dc_opp_fmt3_dispdec +//FMT3_FMT_CLAMP_COMPONENT_R +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_COMPONENT_G +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_COMPONENT_B +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT3_FMT_DYNAMIC_EXP_CNTL +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT3_FMT_CONTROL +#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT3_FMT_BIT_DEPTH_CONTROL +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT3_FMT_DITHER_RAND_R_SEED +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT3_FMT_DITHER_RAND_G_SEED +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT3_FMT_DITHER_RAND_B_SEED +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_CNTL +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT3_FMT_MAP420_MEMORY_CONTROL +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT3_FMT_422_CONTROL +#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dcn_dc_opp_oppbuf3_dispdec +//OPPBUF3_OPPBUF_CONTROL +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF3_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF3_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF3_OPPBUF_CONTROL1 +#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dcn_dc_opp_opp_pipe3_dispdec +//OPP_PIPE3_OPP_PIPE_CONTROL +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dcn_dc_opp_opp_pipe_crc3_dispdec +//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dcn_dc_opp_dscrm0_dispdec +//DSCRM0_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dcn_dc_opp_dscrm1_dispdec +//DSCRM1_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dcn_dc_opp_dscrm2_dispdec +//DSCRM2_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dcn_dc_opp_dscrm3_dispdec +//DSCRM3_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dcn_dc_opp_opp_top_dispdec +//OPP_TOP_CLK_CONTROL +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT 0x4 +#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT 0x8 +#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT 0xc +#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT 0xd +#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON__SHIFT 0xe +#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON__SHIFT 0xf +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK 0x00000010L +#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK 0x00000F00L +#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK 0x00001000L +#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK 0x00002000L +#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON_MASK 0x00004000L +#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON_MASK 0x00008000L +//OPP_ABM_CONTROL +#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL__SHIFT 0x0 +#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL_MASK 0x00000007L + + +// addressBlock: dcn_dc_optc_odm0_dispdec +//ODM0_OPTC_INPUT_GLOBAL_CONTROL +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM0_OPTC_DATA_SOURCE_SELECT +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM0_OPTC_DATA_FORMAT_CONTROL +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM0_OPTC_BYTES_PER_PIXEL +#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM0_OPTC_WIDTH_CONTROL +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM0_OPTC_INPUT_CLOCK_CONTROL +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM0_OPTC_MEMORY_CONFIG +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM0_OPTC_INPUT_SPARE_REGISTER +#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_optc_odm1_dispdec +//ODM1_OPTC_INPUT_GLOBAL_CONTROL +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM1_OPTC_DATA_SOURCE_SELECT +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM1_OPTC_DATA_FORMAT_CONTROL +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM1_OPTC_BYTES_PER_PIXEL +#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM1_OPTC_WIDTH_CONTROL +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM1_OPTC_INPUT_CLOCK_CONTROL +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM1_OPTC_MEMORY_CONFIG +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM1_OPTC_INPUT_SPARE_REGISTER +#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_optc_odm2_dispdec +//ODM2_OPTC_INPUT_GLOBAL_CONTROL +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM2_OPTC_DATA_SOURCE_SELECT +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM2_OPTC_DATA_FORMAT_CONTROL +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM2_OPTC_BYTES_PER_PIXEL +#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM2_OPTC_WIDTH_CONTROL +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM2_OPTC_INPUT_CLOCK_CONTROL +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM2_OPTC_MEMORY_CONFIG +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM2_OPTC_INPUT_SPARE_REGISTER +#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_optc_odm3_dispdec +//ODM3_OPTC_INPUT_GLOBAL_CONTROL +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM3_OPTC_DATA_SOURCE_SELECT +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM3_OPTC_DATA_FORMAT_CONTROL +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM3_OPTC_BYTES_PER_PIXEL +#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM3_OPTC_WIDTH_CONTROL +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM3_OPTC_INPUT_CLOCK_CONTROL +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM3_OPTC_MEMORY_CONFIG +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM3_OPTC_INPUT_SPARE_REGISTER +#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_optc_otg0_dispdec +//OTG0_OTG_H_TOTAL +#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG0_OTG_H_BLANK_START_END +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG0_OTG_H_SYNC_A +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG0_OTG_H_SYNC_A_CNTL +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG0_OTG_H_TIMING_CNTL +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT 0x8 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT 0x10 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK 0x00000100L +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK 0x00030000L +//OTG0_OTG_V_TOTAL +#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MIN +#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MAX +#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MID +#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_CONTROL +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG0_OTG_V_TOTAL_INT_STATUS +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG0_OTG_VSYNC_NOM_INT_STATUS +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG0_OTG_V_BLANK_START_END +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG0_OTG_V_SYNC_A +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG0_OTG_V_SYNC_A_CNTL +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG0_OTG_TRIGA_CNTL +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG0_OTG_TRIGA_MANUAL_TRIG +#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG0_OTG_TRIGB_CNTL +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG0_OTG_TRIGB_MANUAL_TRIG +#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG0_OTG_FORCE_COUNT_NOW_CNTL +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG0_OTG_FLOW_CONTROL +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG0_OTG_STEREO_FORCE_NEXT_EYE +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG0_OTG_CONTROL +#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG0_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG0_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG0_OTG_INTERLACE_CONTROL +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG0_OTG_INTERLACE_STATUS +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG0_OTG_PIXEL_DATA_READBACK0 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG0_OTG_PIXEL_DATA_READBACK1 +#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG0_OTG_STATUS +#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG0_OTG_STATUS_POSITION +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG0_OTG_NOM_VERT_POSITION +#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG0_OTG_STATUS_FRAME_COUNT +#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG0_OTG_STATUS_VF_COUNT +#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG0_OTG_STATUS_HV_COUNT +#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG0_OTG_COUNT_CONTROL +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG0_OTG_COUNT_RESET +#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG0_OTG_VERT_SYNC_CONTROL +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG0_OTG_STEREO_STATUS +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG0_OTG_STEREO_CONTROL +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG0_OTG_SNAPSHOT_STATUS +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG0_OTG_SNAPSHOT_CONTROL +#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG0_OTG_SNAPSHOT_POSITION +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG0_OTG_SNAPSHOT_FRAME +#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG0_OTG_INTERRUPT_CONTROL +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG0_OTG_UPDATE_LOCK +#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG0_OTG_DOUBLE_BUFFER_CONTROL +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG0_OTG_MASTER_EN +#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_CRC_CNTL +#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT 0xa +#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK 0x00000400L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG0_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_DATA_RG +#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC0_DATA_B +#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_DATA_RG +#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC1_DATA_B +#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC2_DATA_RG +#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC2_DATA_B +#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC3_DATA_RG +#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC3_DATA_B +#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG0_OTG_STATIC_SCREEN_CONTROL +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG0_OTG_3D_STRUCTURE_CONTROL +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG0_OTG_GSL_VSYNC_GAP +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG0_OTG_MASTER_UPDATE_MODE +#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG0_OTG_CLOCK_CONTROL +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG0_OTG_VSTARTUP_PARAM +#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG0_OTG_VUPDATE_PARAM +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG0_OTG_VREADY_PARAM +#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG0_OTG_GLOBAL_SYNC_STATUS +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG0_OTG_MASTER_UPDATE_LOCK +#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG0_OTG_GSL_CONTROL +#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG0_OTG_GSL_WINDOW_X +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG0_OTG_GSL_WINDOW_Y +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG0_OTG_VUPDATE_KEEPOUT +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL0 +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL1 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL2 +#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL3 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG0_OTG_GLOBAL_CONTROL4 +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG0_OTG_TRIG_MANUAL_CONTROL +#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG0_OTG_MANUAL_FLOW_CONTROL +#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG0_OTG_DRR_TIMING_INT_STATUS +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG0_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG0_OTG_DRR_V_TOTAL_CHANGE +#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG0_OTG_DRR_TRIGGER_WINDOW +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG0_OTG_DRR_CONTROL +#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG0_OTG_M_CONST_DTO0 +#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG0_OTG_M_CONST_DTO1 +#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG0_OTG_REQUEST_CONTROL +#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG0_OTG_DSC_START_POSITION +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG0_OTG_PIPE_UPDATE_STATUS +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG0_OTG_SPARE_REGISTER +#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_optc_otg1_dispdec +//OTG1_OTG_H_TOTAL +#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG1_OTG_H_BLANK_START_END +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG1_OTG_H_SYNC_A +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG1_OTG_H_SYNC_A_CNTL +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG1_OTG_H_TIMING_CNTL +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT 0x8 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT 0x10 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK 0x00000100L +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK 0x00030000L +//OTG1_OTG_V_TOTAL +#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MIN +#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MAX +#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MID +#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_CONTROL +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG1_OTG_V_TOTAL_INT_STATUS +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG1_OTG_VSYNC_NOM_INT_STATUS +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG1_OTG_V_BLANK_START_END +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG1_OTG_V_SYNC_A +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG1_OTG_V_SYNC_A_CNTL +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG1_OTG_TRIGA_CNTL +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG1_OTG_TRIGA_MANUAL_TRIG +#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG1_OTG_TRIGB_CNTL +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG1_OTG_TRIGB_MANUAL_TRIG +#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG1_OTG_FORCE_COUNT_NOW_CNTL +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG1_OTG_FLOW_CONTROL +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG1_OTG_STEREO_FORCE_NEXT_EYE +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG1_OTG_CONTROL +#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG1_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG1_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG1_OTG_INTERLACE_CONTROL +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG1_OTG_INTERLACE_STATUS +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG1_OTG_PIXEL_DATA_READBACK0 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG1_OTG_PIXEL_DATA_READBACK1 +#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG1_OTG_STATUS +#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG1_OTG_STATUS_POSITION +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG1_OTG_NOM_VERT_POSITION +#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG1_OTG_STATUS_FRAME_COUNT +#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG1_OTG_STATUS_VF_COUNT +#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG1_OTG_STATUS_HV_COUNT +#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG1_OTG_COUNT_CONTROL +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG1_OTG_COUNT_RESET +#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG1_OTG_VERT_SYNC_CONTROL +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG1_OTG_STEREO_STATUS +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG1_OTG_STEREO_CONTROL +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG1_OTG_SNAPSHOT_STATUS +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG1_OTG_SNAPSHOT_CONTROL +#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG1_OTG_SNAPSHOT_POSITION +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG1_OTG_SNAPSHOT_FRAME +#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG1_OTG_INTERRUPT_CONTROL +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG1_OTG_UPDATE_LOCK +#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG1_OTG_DOUBLE_BUFFER_CONTROL +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG1_OTG_MASTER_EN +#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_CRC_CNTL +#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT 0xa +#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK 0x00000400L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG1_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_DATA_RG +#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC0_DATA_B +#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_DATA_RG +#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC1_DATA_B +#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC2_DATA_RG +#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC2_DATA_B +#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC3_DATA_RG +#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC3_DATA_B +#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG1_OTG_STATIC_SCREEN_CONTROL +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG1_OTG_3D_STRUCTURE_CONTROL +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG1_OTG_GSL_VSYNC_GAP +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG1_OTG_MASTER_UPDATE_MODE +#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG1_OTG_CLOCK_CONTROL +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG1_OTG_VSTARTUP_PARAM +#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG1_OTG_VUPDATE_PARAM +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG1_OTG_VREADY_PARAM +#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG1_OTG_GLOBAL_SYNC_STATUS +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG1_OTG_MASTER_UPDATE_LOCK +#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG1_OTG_GSL_CONTROL +#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG1_OTG_GSL_WINDOW_X +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG1_OTG_GSL_WINDOW_Y +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG1_OTG_VUPDATE_KEEPOUT +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL0 +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL1 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL2 +#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL3 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG1_OTG_GLOBAL_CONTROL4 +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG1_OTG_TRIG_MANUAL_CONTROL +#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG1_OTG_MANUAL_FLOW_CONTROL +#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG1_OTG_DRR_TIMING_INT_STATUS +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG1_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG1_OTG_DRR_V_TOTAL_CHANGE +#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG1_OTG_DRR_TRIGGER_WINDOW +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG1_OTG_DRR_CONTROL +#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG1_OTG_M_CONST_DTO0 +#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG1_OTG_M_CONST_DTO1 +#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG1_OTG_REQUEST_CONTROL +#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG1_OTG_DSC_START_POSITION +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG1_OTG_PIPE_UPDATE_STATUS +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG1_OTG_SPARE_REGISTER +#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_optc_otg2_dispdec +//OTG2_OTG_H_TOTAL +#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG2_OTG_H_BLANK_START_END +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG2_OTG_H_SYNC_A +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG2_OTG_H_SYNC_A_CNTL +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG2_OTG_H_TIMING_CNTL +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT 0x8 +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT 0x10 +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK 0x00000100L +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK 0x00030000L +//OTG2_OTG_V_TOTAL +#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MIN +#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MAX +#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MID +#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_CONTROL +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG2_OTG_V_TOTAL_INT_STATUS +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG2_OTG_VSYNC_NOM_INT_STATUS +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG2_OTG_V_BLANK_START_END +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG2_OTG_V_SYNC_A +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG2_OTG_V_SYNC_A_CNTL +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG2_OTG_TRIGA_CNTL +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG2_OTG_TRIGA_MANUAL_TRIG +#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG2_OTG_TRIGB_CNTL +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG2_OTG_TRIGB_MANUAL_TRIG +#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG2_OTG_FORCE_COUNT_NOW_CNTL +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG2_OTG_FLOW_CONTROL +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG2_OTG_STEREO_FORCE_NEXT_EYE +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG2_OTG_CONTROL +#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG2_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG2_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG2_OTG_INTERLACE_CONTROL +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG2_OTG_INTERLACE_STATUS +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG2_OTG_PIXEL_DATA_READBACK0 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG2_OTG_PIXEL_DATA_READBACK1 +#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG2_OTG_STATUS +#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG2_OTG_STATUS_POSITION +#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG2_OTG_NOM_VERT_POSITION +#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG2_OTG_STATUS_FRAME_COUNT +#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG2_OTG_STATUS_VF_COUNT +#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG2_OTG_STATUS_HV_COUNT +#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG2_OTG_COUNT_CONTROL +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG2_OTG_COUNT_RESET +#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG2_OTG_VERT_SYNC_CONTROL +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG2_OTG_STEREO_STATUS +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG2_OTG_STEREO_CONTROL +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG2_OTG_SNAPSHOT_STATUS +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG2_OTG_SNAPSHOT_CONTROL +#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG2_OTG_SNAPSHOT_POSITION +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG2_OTG_SNAPSHOT_FRAME +#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG2_OTG_INTERRUPT_CONTROL +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG2_OTG_UPDATE_LOCK +#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG2_OTG_DOUBLE_BUFFER_CONTROL +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG2_OTG_MASTER_EN +#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG2_OTG_CRC_CNTL +#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT 0xa +#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK 0x00000400L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG2_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_DATA_RG +#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC0_DATA_B +#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_DATA_RG +#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC1_DATA_B +#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC2_DATA_RG +#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC2_DATA_B +#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC3_DATA_RG +#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC3_DATA_B +#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG2_OTG_STATIC_SCREEN_CONTROL +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG2_OTG_3D_STRUCTURE_CONTROL +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG2_OTG_GSL_VSYNC_GAP +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG2_OTG_MASTER_UPDATE_MODE +#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG2_OTG_CLOCK_CONTROL +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG2_OTG_VSTARTUP_PARAM +#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG2_OTG_VUPDATE_PARAM +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG2_OTG_VREADY_PARAM +#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG2_OTG_GLOBAL_SYNC_STATUS +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG2_OTG_MASTER_UPDATE_LOCK +#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG2_OTG_GSL_CONTROL +#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG2_OTG_GSL_WINDOW_X +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG2_OTG_GSL_WINDOW_Y +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG2_OTG_VUPDATE_KEEPOUT +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL0 +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL1 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL2 +#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL3 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG2_OTG_GLOBAL_CONTROL4 +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG2_OTG_TRIG_MANUAL_CONTROL +#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG2_OTG_MANUAL_FLOW_CONTROL +#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG2_OTG_DRR_TIMING_INT_STATUS +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG2_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG2_OTG_DRR_V_TOTAL_CHANGE +#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG2_OTG_DRR_TRIGGER_WINDOW +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG2_OTG_DRR_CONTROL +#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG2_OTG_M_CONST_DTO0 +#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG2_OTG_M_CONST_DTO1 +#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG2_OTG_REQUEST_CONTROL +#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG2_OTG_DSC_START_POSITION +#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG2_OTG_PIPE_UPDATE_STATUS +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG2_OTG_SPARE_REGISTER +#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_optc_otg3_dispdec +//OTG3_OTG_H_TOTAL +#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG3_OTG_H_BLANK_START_END +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG3_OTG_H_SYNC_A +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG3_OTG_H_SYNC_A_CNTL +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG3_OTG_H_TIMING_CNTL +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT 0x8 +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT 0x10 +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK 0x00000100L +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK 0x00030000L +//OTG3_OTG_V_TOTAL +#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MIN +#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MAX +#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MID +#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_CONTROL +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG3_OTG_V_TOTAL_INT_STATUS +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG3_OTG_VSYNC_NOM_INT_STATUS +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG3_OTG_V_BLANK_START_END +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG3_OTG_V_SYNC_A +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG3_OTG_V_SYNC_A_CNTL +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG3_OTG_TRIGA_CNTL +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG3_OTG_TRIGA_MANUAL_TRIG +#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG3_OTG_TRIGB_CNTL +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG3_OTG_TRIGB_MANUAL_TRIG +#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG3_OTG_FORCE_COUNT_NOW_CNTL +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG3_OTG_FLOW_CONTROL +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG3_OTG_STEREO_FORCE_NEXT_EYE +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG3_OTG_CONTROL +#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG3_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG3_OTG_INTERLACE_CONTROL +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG3_OTG_INTERLACE_STATUS +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG3_OTG_PIXEL_DATA_READBACK0 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG3_OTG_PIXEL_DATA_READBACK1 +#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG3_OTG_STATUS +#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG3_OTG_STATUS_POSITION +#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG3_OTG_NOM_VERT_POSITION +#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG3_OTG_STATUS_FRAME_COUNT +#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG3_OTG_STATUS_VF_COUNT +#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG3_OTG_STATUS_HV_COUNT +#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG3_OTG_COUNT_CONTROL +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG3_OTG_COUNT_RESET +#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG3_OTG_VERT_SYNC_CONTROL +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG3_OTG_STEREO_STATUS +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG3_OTG_STEREO_CONTROL +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG3_OTG_SNAPSHOT_STATUS +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG3_OTG_SNAPSHOT_CONTROL +#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG3_OTG_SNAPSHOT_POSITION +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG3_OTG_SNAPSHOT_FRAME +#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG3_OTG_INTERRUPT_CONTROL +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG3_OTG_UPDATE_LOCK +#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG3_OTG_DOUBLE_BUFFER_CONTROL +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG3_OTG_MASTER_EN +#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG3_OTG_CRC_CNTL +#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT 0xa +#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK 0x00000400L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG3_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_DATA_RG +#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC0_DATA_B +#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_DATA_RG +#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC1_DATA_B +#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC2_DATA_RG +#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC2_DATA_B +#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC3_DATA_RG +#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC3_DATA_B +#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG3_OTG_STATIC_SCREEN_CONTROL +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG3_OTG_3D_STRUCTURE_CONTROL +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG3_OTG_GSL_VSYNC_GAP +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG3_OTG_MASTER_UPDATE_MODE +#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG3_OTG_CLOCK_CONTROL +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG3_OTG_VSTARTUP_PARAM +#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG3_OTG_VUPDATE_PARAM +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG3_OTG_VREADY_PARAM +#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG3_OTG_GLOBAL_SYNC_STATUS +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG3_OTG_MASTER_UPDATE_LOCK +#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG3_OTG_GSL_CONTROL +#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG3_OTG_GSL_WINDOW_X +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG3_OTG_GSL_WINDOW_Y +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG3_OTG_VUPDATE_KEEPOUT +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL0 +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL1 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL2 +#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL3 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG3_OTG_GLOBAL_CONTROL4 +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG3_OTG_TRIG_MANUAL_CONTROL +#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG3_OTG_MANUAL_FLOW_CONTROL +#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG3_OTG_DRR_TIMING_INT_STATUS +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG3_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG3_OTG_DRR_V_TOTAL_CHANGE +#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG3_OTG_DRR_TRIGGER_WINDOW +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG3_OTG_DRR_CONTROL +#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG3_OTG_M_CONST_DTO0 +#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG3_OTG_M_CONST_DTO1 +#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG3_OTG_REQUEST_CONTROL +#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG3_OTG_DSC_START_POSITION +#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG3_OTG_PIPE_UPDATE_STATUS +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG3_OTG_SPARE_REGISTER +#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_optc_optc_misc_dispdec +//GSL_SOURCE_SELECT +#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT 0x0 +#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT 0x4 +#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT 0x8 +#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT 0x10 +#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK 0x00000007L +#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK 0x00000070L +#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK 0x00000700L +#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK 0x00070000L +//OPTC_CLOCK_CONTROL +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT 0x1 +#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT 0x8 +#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS__SHIFT 0xf +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK 0x00000002L +#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK 0x00000F00L +#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS_MASK 0x00008000L +//ODM_MEM_PWR_CTRL +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT 0x0 +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT 0x2 +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT 0x4 +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT 0x6 +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT 0x8 +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT 0xa +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT 0xc +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT 0xe +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT 0x10 +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT 0x12 +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT 0x14 +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT 0x16 +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT 0x18 +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT 0x1a +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT 0x1c +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT 0x1e +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK 0x00000003L +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK 0x00000004L +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK 0x00000030L +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK 0x00000040L +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK 0x00000300L +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK 0x00000400L +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK 0x00003000L +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK 0x00004000L +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK 0x00030000L +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK 0x00040000L +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK 0x00300000L +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK 0x00400000L +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK 0x03000000L +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK 0x04000000L +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK 0x30000000L +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK 0x40000000L +//ODM_MEM_PWR_CTRL3 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT 0x0 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT 0x2 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK 0x00000003L +#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK 0x0000000CL +//ODM_MEM_PWR_STATUS +#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT 0x0 +#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT 0x2 +#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT 0x4 +#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT 0x6 +#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT 0x8 +#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT 0xa +#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT 0xc +#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT 0xe +#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK 0x00000003L +#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK 0x0000000CL +#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK 0x00000030L +#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK 0x000000C0L +#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK 0x00000300L +#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK 0x00000C00L +#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK 0x00003000L +#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK 0x0000C000L +//OPTC_MISC_SPARE_REGISTER +#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT 0x0 +#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK 0x000000FFL + + +// addressBlock: dcn_dc_dio_hpd0_dispdec +//HPD0_DC_HPD_INT_STATUS +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD0_DC_HPD_INT_CONTROL +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD0_DC_HPD_CONTROL +#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD0_DC_HPD_FAST_TRAIN_CNTL +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD0_DC_HPD_TOGGLE_FILT_CNTL +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dcn_dc_dio_hpd1_dispdec +//HPD1_DC_HPD_INT_STATUS +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD1_DC_HPD_INT_CONTROL +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD1_DC_HPD_CONTROL +#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD1_DC_HPD_FAST_TRAIN_CNTL +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD1_DC_HPD_TOGGLE_FILT_CNTL +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dcn_dc_dio_hpd2_dispdec +//HPD2_DC_HPD_INT_STATUS +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD2_DC_HPD_INT_CONTROL +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD2_DC_HPD_CONTROL +#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD2_DC_HPD_FAST_TRAIN_CNTL +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD2_DC_HPD_TOGGLE_FILT_CNTL +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dcn_dc_dio_hpd3_dispdec +//HPD3_DC_HPD_INT_STATUS +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD3_DC_HPD_INT_CONTROL +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD3_DC_HPD_CONTROL +#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD3_DC_HPD_FAST_TRAIN_CNTL +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD3_DC_HPD_TOGGLE_FILT_CNTL +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dcn_dc_dio_hpd4_dispdec +//HPD4_DC_HPD_INT_STATUS +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD4_DC_HPD_INT_CONTROL +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD4_DC_HPD_CONTROL +#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD4_DC_HPD_FAST_TRAIN_CNTL +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD4_DC_HPD_TOGGLE_FILT_CNTL +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dcn_dc_dio_dp0_dispdec +//DP0_DP_LINK_CNTL +#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP0_DP_PIXEL_FORMAT +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT 0x1e +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK 0x40000000L +//DP0_DP_MSA_COLORIMETRY +#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP0_DP_CONFIG +#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP0_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP0_DP_VID_STREAM_CNTL +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP0_DP_STEER_FIFO +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP0_DP_STEER_FIFO__DP_TU_SIZE__SHIFT 0x18 +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP0_DP_STEER_FIFO__DP_TU_SIZE_MASK 0x3F000000L +//DP0_DP_MSA_MISC +#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP0_DP_DPHY_INTERNAL_CTRL +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP0_DP_VID_TIMING +#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP0_DP_VID_N +#define DP0_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP0_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP0_DP_VID_M +#define DP0_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP0_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP0_DP_LINK_FRAMING_CNTL +#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP0_DP_HBR2_EYE_PATTERN +#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP0_DP_VID_MSA_VBID +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP0_DP_VID_INTERRUPT_CNTL +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP0_DP_DPHY_CNTL +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP0_DP_DPHY_TRAINING_PATTERN_SEL +#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP0_DP_DPHY_SYM0 +#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP0_DP_DPHY_SYM1 +#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP0_DP_DPHY_SYM2 +#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP0_DP_DPHY_8B10B_CNTL +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP0_DP_DPHY_PRBS_CNTL +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP0_DP_DPHY_SCRAM_CNTL +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP0_DP_DPHY_CRC_EN +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP0_DP_DPHY_CRC_CNTL +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP0_DP_DPHY_CRC_RESULT +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP0_DP_DPHY_CRC_MST_CNTL +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP0_DP_DPHY_CRC_MST_STATUS +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP0_DP_DPHY_FAST_TRAINING +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP0_DP_DPHY_FAST_TRAINING_STATUS +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP0_DP_SEC_CNTL +#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP0_DP_SEC_CNTL1 +#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING1 +#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING2 +#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING3 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING4 +#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP0_DP_SEC_AUD_N +#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_N_READBACK +#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_M +#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_M_READBACK +#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP0_DP_SEC_TIMESTAMP +#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP0_DP_SEC_PACKET_CNTL +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP0_DP_MSE_RATE_CNTL +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP0_DP_MSE_RATE_UPDATE +#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP0_DP_MSE_SAT0 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP0_DP_MSE_SAT1 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP0_DP_MSE_SAT2 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP0_DP_MSE_SAT_UPDATE +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP0_DP_MSE_LINK_TIMING +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP0_DP_MSE_MISC_CNTL +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP0_DP_DPHY_BS_SR_SWAP_CNTL +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP0_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP0_DP_MSE_SAT0_STATUS +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP0_DP_MSE_SAT1_STATUS +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP0_DP_MSE_SAT2_STATUS +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP0_DP_DPIA_SPARE +#define DP0_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT 0x0 +#define DP0_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK 0x00000003L +//DP0_DP_MSA_TIMING_PARAM1 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP0_DP_MSA_TIMING_PARAM2 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP0_DP_MSA_TIMING_PARAM3 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP0_DP_MSA_TIMING_PARAM4 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP0_DP_MSO_CNTL +#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP0_DP_MSO_CNTL1 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP0_DP_DSC_CNTL +#define DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000001L +//DP0_DP_SEC_CNTL2 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP0_DP_SEC_CNTL3 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL4 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL5 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL6 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP0_DP_SEC_CNTL7 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP0_DP_DB_CNTL +#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP0_DP_MSA_VBID_MISC +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_METADATA_TRANSMISSION +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP0_DP_ALPM_CNTL +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP8_CNTL +#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP9_CNTL +#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP10_CNTL +#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP11_CNTL +#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP_EN_DB_STATUS +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP0_DP_AUXLESS_ALPM_CNTL1 +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +//DP0_DP_AUXLESS_ALPM_CNTL2 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT 0x8 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0xf +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT 0x10 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x16 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x17 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT 0x18 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK 0x00003F00L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00008000L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK 0x000F0000L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00400000L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00800000L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK 0xFF000000L +//DP0_DP_AUXLESS_ALPM_CNTL3 +#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_AUXLESS_ALPM_CNTL4 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x0 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x8 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x9 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0xa +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0xb +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x0000007FL +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000100L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000200L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000400L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000800L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP0_DP_AUXLESS_ALPM_CNTL5 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L + + +// addressBlock: dcn_dc_dio_dig0_dispdec +//DIG0_DIG_FE_CNTL +#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG0_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT 0xf +#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG0_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK 0x00008000L +#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG0_DIG_OUTPUT_CRC_CNTL +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG0_DIG_OUTPUT_CRC_RESULT +#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG0_DIG_CLOCK_PATTERN +#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG0_DIG_TEST_PATTERN +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG0_DIG_RANDOM_PATTERN_SEED +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG0_DIG_FIFO_CTRL0 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x7 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT 0x8 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x0000007CL +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000080L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK 0x00000100L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG0_DIG_FIFO_CTRL1 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG0_HDMI_METADATA_PACKET_CONTROL +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_CONTROL +#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG0_HDMI_STATUS +#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG0_HDMI_AUDIO_PACKET_CONTROL +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG0_HDMI_ACR_PACKET_CONTROL +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG0_HDMI_VBI_PACKET_CONTROL +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG0_HDMI_INFOFRAME_CONTROL0 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG0_HDMI_INFOFRAME_CONTROL1 +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG0_HDMI_GC +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG0_HDMI_DB_CONTROL +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG0_HDMI_ACR_32_0 +#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_32_1 +#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_44_0 +#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_44_1 +#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_48_0 +#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_48_1 +#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_STATUS_0 +#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_STATUS_1 +#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG0_AFMT_CNTL +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG0_DIG_BE_CNTL +#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG0_DIG_BE_EN_CNTL +#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG0_TMDS_CNTL +#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG0_TMDS_CONTROL_CHAR +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG0_TMDS_CONTROL0_FEEDBACK +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG0_TMDS_STEREOSYNC_CTL_SEL +#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG0_TMDS_CTL_BITS +#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG0_TMDS_DCBALANCER_CONTROL +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG0_TMDS_SYNC_DCBALANCE_CHAR +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG0_TMDS_CTL0_1_GEN_CNTL +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG0_TMDS_CTL2_3_GEN_CNTL +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG0_DIG_VERSION +#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG0_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG0_FORCE_DIG_DISABLE +#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dcn_dc_dio_dp1_dispdec +//DP1_DP_LINK_CNTL +#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP1_DP_PIXEL_FORMAT +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT 0x1e +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK 0x40000000L +//DP1_DP_MSA_COLORIMETRY +#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP1_DP_CONFIG +#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP1_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP1_DP_VID_STREAM_CNTL +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP1_DP_STEER_FIFO +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP1_DP_STEER_FIFO__DP_TU_SIZE__SHIFT 0x18 +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP1_DP_STEER_FIFO__DP_TU_SIZE_MASK 0x3F000000L +//DP1_DP_MSA_MISC +#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP1_DP_DPHY_INTERNAL_CTRL +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP1_DP_VID_TIMING +#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP1_DP_VID_N +#define DP1_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP1_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP1_DP_VID_M +#define DP1_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP1_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP1_DP_LINK_FRAMING_CNTL +#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP1_DP_HBR2_EYE_PATTERN +#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP1_DP_VID_MSA_VBID +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP1_DP_VID_INTERRUPT_CNTL +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP1_DP_DPHY_CNTL +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP1_DP_DPHY_TRAINING_PATTERN_SEL +#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP1_DP_DPHY_SYM0 +#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP1_DP_DPHY_SYM1 +#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP1_DP_DPHY_SYM2 +#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP1_DP_DPHY_8B10B_CNTL +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP1_DP_DPHY_PRBS_CNTL +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP1_DP_DPHY_SCRAM_CNTL +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP1_DP_DPHY_CRC_EN +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP1_DP_DPHY_CRC_CNTL +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP1_DP_DPHY_CRC_RESULT +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP1_DP_DPHY_CRC_MST_CNTL +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP1_DP_DPHY_CRC_MST_STATUS +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP1_DP_DPHY_FAST_TRAINING +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP1_DP_DPHY_FAST_TRAINING_STATUS +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP1_DP_SEC_CNTL +#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP1_DP_SEC_CNTL1 +#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING1 +#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING2 +#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING3 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING4 +#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP1_DP_SEC_AUD_N +#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_N_READBACK +#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_M +#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_M_READBACK +#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP1_DP_SEC_TIMESTAMP +#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP1_DP_SEC_PACKET_CNTL +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP1_DP_MSE_RATE_CNTL +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP1_DP_MSE_RATE_UPDATE +#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP1_DP_MSE_SAT0 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP1_DP_MSE_SAT1 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP1_DP_MSE_SAT2 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP1_DP_MSE_SAT_UPDATE +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP1_DP_MSE_LINK_TIMING +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP1_DP_MSE_MISC_CNTL +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP1_DP_DPHY_BS_SR_SWAP_CNTL +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP1_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP1_DP_MSE_SAT0_STATUS +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP1_DP_MSE_SAT1_STATUS +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP1_DP_MSE_SAT2_STATUS +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP1_DP_DPIA_SPARE +#define DP1_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT 0x0 +#define DP1_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK 0x00000003L +//DP1_DP_MSA_TIMING_PARAM1 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP1_DP_MSA_TIMING_PARAM2 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP1_DP_MSA_TIMING_PARAM3 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP1_DP_MSA_TIMING_PARAM4 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP1_DP_MSO_CNTL +#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP1_DP_MSO_CNTL1 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP1_DP_DSC_CNTL +#define DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000001L +//DP1_DP_SEC_CNTL2 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP1_DP_SEC_CNTL3 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL4 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL5 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL6 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP1_DP_SEC_CNTL7 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP1_DP_DB_CNTL +#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP1_DP_MSA_VBID_MISC +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_METADATA_TRANSMISSION +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP1_DP_ALPM_CNTL +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP8_CNTL +#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP9_CNTL +#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP10_CNTL +#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP11_CNTL +#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP_EN_DB_STATUS +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP1_DP_AUXLESS_ALPM_CNTL1 +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +//DP1_DP_AUXLESS_ALPM_CNTL2 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT 0x8 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0xf +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT 0x10 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x16 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x17 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT 0x18 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK 0x00003F00L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00008000L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK 0x000F0000L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00400000L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00800000L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK 0xFF000000L +//DP1_DP_AUXLESS_ALPM_CNTL3 +#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_AUXLESS_ALPM_CNTL4 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x0 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x8 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x9 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0xa +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0xb +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x0000007FL +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000100L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000200L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000400L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000800L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP1_DP_AUXLESS_ALPM_CNTL5 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L + + +// addressBlock: dcn_dc_dio_dig1_dispdec +//DIG1_DIG_FE_CNTL +#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG1_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT 0xf +#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG1_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK 0x00008000L +#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG1_DIG_OUTPUT_CRC_CNTL +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG1_DIG_OUTPUT_CRC_RESULT +#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG1_DIG_CLOCK_PATTERN +#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG1_DIG_TEST_PATTERN +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG1_DIG_RANDOM_PATTERN_SEED +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG1_DIG_FIFO_CTRL0 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x7 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT 0x8 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x0000007CL +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000080L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK 0x00000100L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG1_DIG_FIFO_CTRL1 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG1_HDMI_METADATA_PACKET_CONTROL +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_CONTROL +#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG1_HDMI_STATUS +#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG1_HDMI_AUDIO_PACKET_CONTROL +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG1_HDMI_ACR_PACKET_CONTROL +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG1_HDMI_VBI_PACKET_CONTROL +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG1_HDMI_INFOFRAME_CONTROL0 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG1_HDMI_INFOFRAME_CONTROL1 +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG1_HDMI_GC +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG1_HDMI_DB_CONTROL +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG1_HDMI_ACR_32_0 +#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_32_1 +#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_44_0 +#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_44_1 +#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_48_0 +#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_48_1 +#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_STATUS_0 +#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_STATUS_1 +#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG1_AFMT_CNTL +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG1_DIG_BE_CNTL +#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG1_DIG_BE_EN_CNTL +#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG1_TMDS_CNTL +#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG1_TMDS_CONTROL_CHAR +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG1_TMDS_CONTROL0_FEEDBACK +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG1_TMDS_STEREOSYNC_CTL_SEL +#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG1_TMDS_CTL_BITS +#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG1_TMDS_DCBALANCER_CONTROL +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG1_TMDS_SYNC_DCBALANCE_CHAR +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG1_TMDS_CTL0_1_GEN_CNTL +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG1_TMDS_CTL2_3_GEN_CNTL +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG1_DIG_VERSION +#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG1_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG1_FORCE_DIG_DISABLE +#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dcn_dc_dio_dp2_dispdec +//DP2_DP_LINK_CNTL +#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP2_DP_PIXEL_FORMAT +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT 0x1e +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK 0x40000000L +//DP2_DP_MSA_COLORIMETRY +#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP2_DP_CONFIG +#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP2_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP2_DP_VID_STREAM_CNTL +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP2_DP_STEER_FIFO +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP2_DP_STEER_FIFO__DP_TU_SIZE__SHIFT 0x18 +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP2_DP_STEER_FIFO__DP_TU_SIZE_MASK 0x3F000000L +//DP2_DP_MSA_MISC +#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP2_DP_DPHY_INTERNAL_CTRL +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP2_DP_VID_TIMING +#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP2_DP_VID_N +#define DP2_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP2_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP2_DP_VID_M +#define DP2_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP2_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP2_DP_LINK_FRAMING_CNTL +#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP2_DP_HBR2_EYE_PATTERN +#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP2_DP_VID_MSA_VBID +#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP2_DP_VID_INTERRUPT_CNTL +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP2_DP_DPHY_CNTL +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP2_DP_DPHY_TRAINING_PATTERN_SEL +#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP2_DP_DPHY_SYM0 +#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP2_DP_DPHY_SYM1 +#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP2_DP_DPHY_SYM2 +#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP2_DP_DPHY_8B10B_CNTL +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP2_DP_DPHY_PRBS_CNTL +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP2_DP_DPHY_SCRAM_CNTL +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP2_DP_DPHY_CRC_EN +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP2_DP_DPHY_CRC_CNTL +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP2_DP_DPHY_CRC_RESULT +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP2_DP_DPHY_CRC_MST_CNTL +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP2_DP_DPHY_CRC_MST_STATUS +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP2_DP_DPHY_FAST_TRAINING +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP2_DP_DPHY_FAST_TRAINING_STATUS +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP2_DP_SEC_CNTL +#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP2_DP_SEC_CNTL1 +#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING1 +#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING2 +#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING3 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING4 +#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP2_DP_SEC_AUD_N +#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_N_READBACK +#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_M +#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_M_READBACK +#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP2_DP_SEC_TIMESTAMP +#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP2_DP_SEC_PACKET_CNTL +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP2_DP_MSE_RATE_CNTL +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP2_DP_MSE_RATE_UPDATE +#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP2_DP_MSE_SAT0 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP2_DP_MSE_SAT1 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP2_DP_MSE_SAT2 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP2_DP_MSE_SAT_UPDATE +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP2_DP_MSE_LINK_TIMING +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP2_DP_MSE_MISC_CNTL +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP2_DP_DPHY_BS_SR_SWAP_CNTL +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP2_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP2_DP_MSE_SAT0_STATUS +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP2_DP_MSE_SAT1_STATUS +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP2_DP_MSE_SAT2_STATUS +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP2_DP_DPIA_SPARE +#define DP2_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT 0x0 +#define DP2_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK 0x00000003L +//DP2_DP_MSA_TIMING_PARAM1 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP2_DP_MSA_TIMING_PARAM2 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP2_DP_MSA_TIMING_PARAM3 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP2_DP_MSA_TIMING_PARAM4 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP2_DP_MSO_CNTL +#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP2_DP_MSO_CNTL1 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP2_DP_DSC_CNTL +#define DP2_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP2_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000001L +//DP2_DP_SEC_CNTL2 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP2_DP_SEC_CNTL3 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL4 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL5 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL6 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP2_DP_SEC_CNTL7 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP2_DP_DB_CNTL +#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP2_DP_MSA_VBID_MISC +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_METADATA_TRANSMISSION +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP2_DP_ALPM_CNTL +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP8_CNTL +#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP9_CNTL +#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP10_CNTL +#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP11_CNTL +#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP_EN_DB_STATUS +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP2_DP_AUXLESS_ALPM_CNTL1 +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +//DP2_DP_AUXLESS_ALPM_CNTL2 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT 0x8 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0xf +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT 0x10 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x16 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x17 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT 0x18 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK 0x00003F00L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00008000L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK 0x000F0000L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00400000L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00800000L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK 0xFF000000L +//DP2_DP_AUXLESS_ALPM_CNTL3 +#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_AUXLESS_ALPM_CNTL4 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x0 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x8 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x9 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0xa +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0xb +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x0000007FL +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000100L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000200L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000400L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000800L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP2_DP_AUXLESS_ALPM_CNTL5 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L + + +// addressBlock: dcn_dc_dio_dig2_dispdec +//DIG2_DIG_FE_CNTL +#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG2_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT 0xf +#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG2_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK 0x00008000L +#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG2_DIG_OUTPUT_CRC_CNTL +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG2_DIG_OUTPUT_CRC_RESULT +#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG2_DIG_CLOCK_PATTERN +#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG2_DIG_TEST_PATTERN +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG2_DIG_RANDOM_PATTERN_SEED +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG2_DIG_FIFO_CTRL0 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x7 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT 0x8 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x0000007CL +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000080L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK 0x00000100L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG2_DIG_FIFO_CTRL1 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG2_HDMI_METADATA_PACKET_CONTROL +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_CONTROL +#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG2_HDMI_STATUS +#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG2_HDMI_AUDIO_PACKET_CONTROL +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG2_HDMI_ACR_PACKET_CONTROL +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG2_HDMI_VBI_PACKET_CONTROL +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG2_HDMI_INFOFRAME_CONTROL0 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG2_HDMI_INFOFRAME_CONTROL1 +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG2_HDMI_GC +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG2_HDMI_DB_CONTROL +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG2_HDMI_ACR_32_0 +#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_32_1 +#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_44_0 +#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_44_1 +#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_48_0 +#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_48_1 +#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_STATUS_0 +#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_STATUS_1 +#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG2_AFMT_CNTL +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG2_DIG_BE_CNTL +#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG2_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG2_DIG_BE_EN_CNTL +#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG2_TMDS_CNTL +#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG2_TMDS_CONTROL_CHAR +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG2_TMDS_CONTROL0_FEEDBACK +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG2_TMDS_STEREOSYNC_CTL_SEL +#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG2_TMDS_CTL_BITS +#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG2_TMDS_DCBALANCER_CONTROL +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG2_TMDS_SYNC_DCBALANCE_CHAR +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG2_TMDS_CTL0_1_GEN_CNTL +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG2_TMDS_CTL2_3_GEN_CNTL +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG2_DIG_VERSION +#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG2_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG2_FORCE_DIG_DISABLE +#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dcn_dc_dio_dp3_dispdec +//DP3_DP_LINK_CNTL +#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP3_DP_PIXEL_FORMAT +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT 0x1e +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK 0x40000000L +//DP3_DP_MSA_COLORIMETRY +#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP3_DP_CONFIG +#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP3_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP3_DP_VID_STREAM_CNTL +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP3_DP_STEER_FIFO +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP3_DP_STEER_FIFO__DP_TU_SIZE__SHIFT 0x18 +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP3_DP_STEER_FIFO__DP_TU_SIZE_MASK 0x3F000000L +//DP3_DP_MSA_MISC +#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP3_DP_DPHY_INTERNAL_CTRL +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP3_DP_VID_TIMING +#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP3_DP_VID_N +#define DP3_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP3_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP3_DP_VID_M +#define DP3_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP3_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP3_DP_LINK_FRAMING_CNTL +#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP3_DP_HBR2_EYE_PATTERN +#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP3_DP_VID_MSA_VBID +#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP3_DP_VID_INTERRUPT_CNTL +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP3_DP_DPHY_CNTL +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP3_DP_DPHY_TRAINING_PATTERN_SEL +#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP3_DP_DPHY_SYM0 +#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP3_DP_DPHY_SYM1 +#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP3_DP_DPHY_SYM2 +#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP3_DP_DPHY_8B10B_CNTL +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP3_DP_DPHY_PRBS_CNTL +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP3_DP_DPHY_SCRAM_CNTL +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP3_DP_DPHY_CRC_EN +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP3_DP_DPHY_CRC_CNTL +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP3_DP_DPHY_CRC_RESULT +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP3_DP_DPHY_CRC_MST_CNTL +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP3_DP_DPHY_CRC_MST_STATUS +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP3_DP_DPHY_FAST_TRAINING +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP3_DP_DPHY_FAST_TRAINING_STATUS +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP3_DP_SEC_CNTL +#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP3_DP_SEC_CNTL1 +#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING1 +#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING2 +#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING3 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING4 +#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP3_DP_SEC_AUD_N +#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_N_READBACK +#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_M +#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_M_READBACK +#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP3_DP_SEC_TIMESTAMP +#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP3_DP_SEC_PACKET_CNTL +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP3_DP_MSE_RATE_CNTL +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP3_DP_MSE_RATE_UPDATE +#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP3_DP_MSE_SAT0 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP3_DP_MSE_SAT1 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP3_DP_MSE_SAT2 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP3_DP_MSE_SAT_UPDATE +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP3_DP_MSE_LINK_TIMING +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP3_DP_MSE_MISC_CNTL +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP3_DP_DPHY_BS_SR_SWAP_CNTL +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP3_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP3_DP_MSE_SAT0_STATUS +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP3_DP_MSE_SAT1_STATUS +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP3_DP_MSE_SAT2_STATUS +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP3_DP_DPIA_SPARE +#define DP3_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT 0x0 +#define DP3_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK 0x00000003L +//DP3_DP_MSA_TIMING_PARAM1 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP3_DP_MSA_TIMING_PARAM2 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP3_DP_MSA_TIMING_PARAM3 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP3_DP_MSA_TIMING_PARAM4 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP3_DP_MSO_CNTL +#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP3_DP_MSO_CNTL1 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP3_DP_DSC_CNTL +#define DP3_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP3_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000001L +//DP3_DP_SEC_CNTL2 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP3_DP_SEC_CNTL3 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL4 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL5 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL6 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP3_DP_SEC_CNTL7 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP3_DP_DB_CNTL +#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP3_DP_MSA_VBID_MISC +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_METADATA_TRANSMISSION +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP3_DP_ALPM_CNTL +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP8_CNTL +#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP9_CNTL +#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP10_CNTL +#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP11_CNTL +#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP_EN_DB_STATUS +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP3_DP_AUXLESS_ALPM_CNTL1 +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +//DP3_DP_AUXLESS_ALPM_CNTL2 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT 0x8 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0xf +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT 0x10 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x16 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x17 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT 0x18 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK 0x00003F00L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00008000L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK 0x000F0000L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00400000L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00800000L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK 0xFF000000L +//DP3_DP_AUXLESS_ALPM_CNTL3 +#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_AUXLESS_ALPM_CNTL4 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x0 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x8 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x9 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0xa +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0xb +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x0000007FL +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000100L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000200L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000400L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000800L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP3_DP_AUXLESS_ALPM_CNTL5 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L + + +// addressBlock: dcn_dc_dio_dig3_dispdec +//DIG3_DIG_FE_CNTL +#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG3_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT 0xf +#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG3_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK 0x00008000L +#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG3_DIG_OUTPUT_CRC_CNTL +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG3_DIG_OUTPUT_CRC_RESULT +#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG3_DIG_CLOCK_PATTERN +#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG3_DIG_TEST_PATTERN +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG3_DIG_RANDOM_PATTERN_SEED +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG3_DIG_FIFO_CTRL0 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x7 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT 0x8 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x0000007CL +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000080L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK 0x00000100L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG3_DIG_FIFO_CTRL1 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG3_HDMI_METADATA_PACKET_CONTROL +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_CONTROL +#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG3_HDMI_STATUS +#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG3_HDMI_AUDIO_PACKET_CONTROL +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG3_HDMI_ACR_PACKET_CONTROL +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG3_HDMI_VBI_PACKET_CONTROL +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG3_HDMI_INFOFRAME_CONTROL0 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG3_HDMI_INFOFRAME_CONTROL1 +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG3_HDMI_GC +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG3_HDMI_DB_CONTROL +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG3_HDMI_ACR_32_0 +#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_32_1 +#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_44_0 +#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_44_1 +#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_48_0 +#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_48_1 +#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_STATUS_0 +#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_STATUS_1 +#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG3_AFMT_CNTL +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG3_DIG_BE_CNTL +#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG3_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG3_DIG_BE_EN_CNTL +#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG3_TMDS_CNTL +#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG3_TMDS_CONTROL_CHAR +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG3_TMDS_CONTROL0_FEEDBACK +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG3_TMDS_STEREOSYNC_CTL_SEL +#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG3_TMDS_CTL_BITS +#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG3_TMDS_DCBALANCER_CONTROL +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG3_TMDS_SYNC_DCBALANCE_CHAR +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG3_TMDS_CTL0_1_GEN_CNTL +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG3_TMDS_CTL2_3_GEN_CNTL +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG3_DIG_VERSION +#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG3_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG3_FORCE_DIG_DISABLE +#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dcn_dc_dio_dp4_dispdec +//DP4_DP_LINK_CNTL +#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP4_DP_PIXEL_FORMAT +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT 0x1e +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK 0x40000000L +//DP4_DP_MSA_COLORIMETRY +#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP4_DP_CONFIG +#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP4_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP4_DP_VID_STREAM_CNTL +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP4_DP_STEER_FIFO +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP4_DP_STEER_FIFO__DP_TU_SIZE__SHIFT 0x18 +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP4_DP_STEER_FIFO__DP_TU_SIZE_MASK 0x3F000000L +//DP4_DP_MSA_MISC +#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP4_DP_DPHY_INTERNAL_CTRL +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP4_DP_VID_TIMING +#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP4_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP4_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP4_DP_VID_N +#define DP4_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP4_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP4_DP_VID_M +#define DP4_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP4_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP4_DP_LINK_FRAMING_CNTL +#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP4_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP4_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP4_DP_HBR2_EYE_PATTERN +#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP4_DP_VID_MSA_VBID +#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP4_DP_VID_INTERRUPT_CNTL +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP4_DP_DPHY_CNTL +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP4_DP_DPHY_TRAINING_PATTERN_SEL +#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP4_DP_DPHY_SYM0 +#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP4_DP_DPHY_SYM1 +#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP4_DP_DPHY_SYM2 +#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP4_DP_DPHY_8B10B_CNTL +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP4_DP_DPHY_PRBS_CNTL +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP4_DP_DPHY_SCRAM_CNTL +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP4_DP_DPHY_CRC_EN +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP4_DP_DPHY_CRC_CNTL +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP4_DP_DPHY_CRC_RESULT +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP4_DP_DPHY_CRC_MST_CNTL +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP4_DP_DPHY_CRC_MST_STATUS +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP4_DP_DPHY_FAST_TRAINING +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP4_DP_DPHY_FAST_TRAINING_STATUS +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP4_DP_SEC_CNTL +#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP4_DP_SEC_CNTL1 +#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING1 +#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING2 +#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING3 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING4 +#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP4_DP_SEC_AUD_N +#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_N_READBACK +#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_M +#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_M_READBACK +#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP4_DP_SEC_TIMESTAMP +#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP4_DP_SEC_PACKET_CNTL +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP4_DP_MSE_RATE_CNTL +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP4_DP_MSE_RATE_UPDATE +#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP4_DP_MSE_SAT0 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP4_DP_MSE_SAT1 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP4_DP_MSE_SAT2 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP4_DP_MSE_SAT_UPDATE +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP4_DP_MSE_LINK_TIMING +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP4_DP_MSE_MISC_CNTL +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP4_DP_DPHY_BS_SR_SWAP_CNTL +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP4_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP4_DP_MSE_SAT0_STATUS +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP4_DP_MSE_SAT1_STATUS +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP4_DP_MSE_SAT2_STATUS +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP4_DP_DPIA_SPARE +#define DP4_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT 0x0 +#define DP4_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK 0x00000003L +//DP4_DP_MSA_TIMING_PARAM1 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP4_DP_MSA_TIMING_PARAM2 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP4_DP_MSA_TIMING_PARAM3 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP4_DP_MSA_TIMING_PARAM4 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP4_DP_MSO_CNTL +#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP4_DP_MSO_CNTL1 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP4_DP_DSC_CNTL +#define DP4_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP4_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000001L +//DP4_DP_SEC_CNTL2 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP4_DP_SEC_CNTL3 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL4 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL5 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL6 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP4_DP_SEC_CNTL7 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP4_DP_DB_CNTL +#define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP4_DP_MSA_VBID_MISC +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_METADATA_TRANSMISSION +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP4_DP_ALPM_CNTL +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP4_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP4_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP8_CNTL +#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP9_CNTL +#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP10_CNTL +#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP11_CNTL +#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP_EN_DB_STATUS +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP4_DP_AUXLESS_ALPM_CNTL1 +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +//DP4_DP_AUXLESS_ALPM_CNTL2 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT 0x8 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0xf +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT 0x10 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x16 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x17 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT 0x18 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK 0x00003F00L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00008000L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK 0x000F0000L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00400000L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00800000L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK 0xFF000000L +//DP4_DP_AUXLESS_ALPM_CNTL3 +#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_AUXLESS_ALPM_CNTL4 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x0 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x8 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x9 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0xa +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0xb +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x0000007FL +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000100L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000200L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000400L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000800L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP4_DP_AUXLESS_ALPM_CNTL5 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L + + +// addressBlock: dcn_dc_dio_dig4_dispdec +//DIG4_DIG_FE_CNTL +#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG4_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT 0xf +#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG4_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK 0x00008000L +#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG4_DIG_OUTPUT_CRC_CNTL +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG4_DIG_OUTPUT_CRC_RESULT +#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG4_DIG_CLOCK_PATTERN +#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG4_DIG_TEST_PATTERN +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG4_DIG_RANDOM_PATTERN_SEED +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG4_DIG_FIFO_CTRL0 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x7 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT 0x8 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x0000007CL +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000080L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK 0x00000100L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG4_DIG_FIFO_CTRL1 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG4_HDMI_METADATA_PACKET_CONTROL +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_CONTROL +#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG4_HDMI_STATUS +#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG4_HDMI_AUDIO_PACKET_CONTROL +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG4_HDMI_ACR_PACKET_CONTROL +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG4_HDMI_VBI_PACKET_CONTROL +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG4_HDMI_INFOFRAME_CONTROL0 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG4_HDMI_INFOFRAME_CONTROL1 +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG4_HDMI_GC +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG4_HDMI_DB_CONTROL +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG4_HDMI_ACR_32_0 +#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_32_1 +#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_44_0 +#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_44_1 +#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_48_0 +#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_48_1 +#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_STATUS_0 +#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_STATUS_1 +#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG4_AFMT_CNTL +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG4_DIG_BE_CNTL +#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG4_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG4_DIG_BE_EN_CNTL +#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG4_TMDS_CNTL +#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG4_TMDS_CONTROL_CHAR +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG4_TMDS_CONTROL0_FEEDBACK +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG4_TMDS_STEREOSYNC_CTL_SEL +#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG4_TMDS_CTL_BITS +#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG4_TMDS_DCBALANCER_CONTROL +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG4_TMDS_SYNC_DCBALANCE_CHAR +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG4_TMDS_CTL0_1_GEN_CNTL +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG4_TMDS_CTL2_3_GEN_CNTL +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG4_DIG_VERSION +#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG4_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG4_FORCE_DIG_DISABLE +#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dcn_dc_dio_dig0_afmt_afmt_dispdec +//AFMT0_AFMT_VBI_PACKET_CONTROL +#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT0_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT0_AFMT_AUDIO_INFO0 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT0_AFMT_AUDIO_INFO1 +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT0_AFMT_60958_0 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT0_AFMT_60958_1 +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT0_AFMT_AUDIO_CRC_CONTROL +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT0_AFMT_RAMP_CONTROL0 +#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT0_AFMT_RAMP_CONTROL1 +#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT0_AFMT_RAMP_CONTROL2 +#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT0_AFMT_RAMP_CONTROL3 +#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT0_AFMT_60958_2 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT0_AFMT_AUDIO_CRC_RESULT +#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT0_AFMT_STATUS +#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT0_AFMT_AUDIO_PACKET_CONTROL +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT0_AFMT_INFOFRAME_CONTROL0 +#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT0_AFMT_INTERRUPT_STATUS +//AFMT0_AFMT_AUDIO_SRC_CONTROL +#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT0_AFMT_MEM_PWR +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dcn_dc_dio_dig1_afmt_afmt_dispdec +//AFMT1_AFMT_VBI_PACKET_CONTROL +#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT1_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT1_AFMT_AUDIO_INFO0 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT1_AFMT_AUDIO_INFO1 +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT1_AFMT_60958_0 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT1_AFMT_60958_1 +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT1_AFMT_AUDIO_CRC_CONTROL +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT1_AFMT_RAMP_CONTROL0 +#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT1_AFMT_RAMP_CONTROL1 +#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT1_AFMT_RAMP_CONTROL2 +#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT1_AFMT_RAMP_CONTROL3 +#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT1_AFMT_60958_2 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT1_AFMT_AUDIO_CRC_RESULT +#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT1_AFMT_STATUS +#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT1_AFMT_AUDIO_PACKET_CONTROL +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT1_AFMT_INFOFRAME_CONTROL0 +#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT1_AFMT_INTERRUPT_STATUS +//AFMT1_AFMT_AUDIO_SRC_CONTROL +#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT1_AFMT_MEM_PWR +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dcn_dc_dio_dig2_afmt_afmt_dispdec +//AFMT2_AFMT_VBI_PACKET_CONTROL +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT2_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT2_AFMT_AUDIO_INFO0 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT2_AFMT_AUDIO_INFO1 +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT2_AFMT_60958_0 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT2_AFMT_60958_1 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT2_AFMT_AUDIO_CRC_CONTROL +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT2_AFMT_RAMP_CONTROL0 +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT2_AFMT_RAMP_CONTROL1 +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT2_AFMT_RAMP_CONTROL2 +#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT2_AFMT_RAMP_CONTROL3 +#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT2_AFMT_60958_2 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT2_AFMT_AUDIO_CRC_RESULT +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT2_AFMT_STATUS +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT2_AFMT_AUDIO_PACKET_CONTROL +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT2_AFMT_INFOFRAME_CONTROL0 +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT2_AFMT_INTERRUPT_STATUS +//AFMT2_AFMT_AUDIO_SRC_CONTROL +#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT2_AFMT_MEM_PWR +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dcn_dc_dio_dig3_afmt_afmt_dispdec +//AFMT3_AFMT_VBI_PACKET_CONTROL +#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT3_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT3_AFMT_AUDIO_INFO0 +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT3_AFMT_AUDIO_INFO1 +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT3_AFMT_60958_0 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT3_AFMT_60958_1 +#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT3_AFMT_AUDIO_CRC_CONTROL +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT3_AFMT_RAMP_CONTROL0 +#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT3_AFMT_RAMP_CONTROL1 +#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT3_AFMT_RAMP_CONTROL2 +#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT3_AFMT_RAMP_CONTROL3 +#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT3_AFMT_60958_2 +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT3_AFMT_AUDIO_CRC_RESULT +#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT3_AFMT_STATUS +#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT3_AFMT_AUDIO_PACKET_CONTROL +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT3_AFMT_INFOFRAME_CONTROL0 +#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT3_AFMT_INTERRUPT_STATUS +//AFMT3_AFMT_AUDIO_SRC_CONTROL +#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT3_AFMT_MEM_PWR +#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dcn_dc_dio_dig4_afmt_afmt_dispdec +//AFMT4_AFMT_VBI_PACKET_CONTROL +#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT4_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT4_AFMT_AUDIO_INFO0 +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT4_AFMT_AUDIO_INFO1 +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT4_AFMT_60958_0 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT4_AFMT_60958_1 +#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT4_AFMT_AUDIO_CRC_CONTROL +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT4_AFMT_RAMP_CONTROL0 +#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT4_AFMT_RAMP_CONTROL1 +#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT4_AFMT_RAMP_CONTROL2 +#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT4_AFMT_RAMP_CONTROL3 +#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT4_AFMT_60958_2 +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT4_AFMT_AUDIO_CRC_RESULT +#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT4_AFMT_STATUS +#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT4_AFMT_AUDIO_PACKET_CONTROL +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT4_AFMT_INFOFRAME_CONTROL0 +#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT4_AFMT_INTERRUPT_STATUS +//AFMT4_AFMT_AUDIO_SRC_CONTROL +#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT4_AFMT_MEM_PWR +#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dcn_dc_dio_dig0_dme_dme_dispdec +//DME0_DME_CONTROL +#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME0_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME0_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME0_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME0_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME0_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME0_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME0_DME_MEMORY_CONTROL +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dcn_dc_dio_dig0_vpg_vpg_dispdec +//VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG0_VPG_GENERIC_PACKET_DATA +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG0_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG0_VPG_GENERIC_STATUS +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG0_VPG_MEM_PWR +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG0_VPG_ISRC1_2_ACCESS_CTRL +#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG0_VPG_ISRC1_2_DATA +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG0_VPG_MPEG_INFO0 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG0_VPG_MPEG_INFO1 +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dcn_dc_dio_dig1_dme_dme_dispdec +//DME1_DME_CONTROL +#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME1_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME1_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME1_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME1_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME1_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME1_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME1_DME_MEMORY_CONTROL +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dcn_dc_dio_dig1_vpg_vpg_dispdec +//VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG1_VPG_GENERIC_PACKET_DATA +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG1_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG1_VPG_GENERIC_STATUS +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG1_VPG_MEM_PWR +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG1_VPG_ISRC1_2_ACCESS_CTRL +#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG1_VPG_ISRC1_2_DATA +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG1_VPG_MPEG_INFO0 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG1_VPG_MPEG_INFO1 +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dcn_dc_dio_dig2_dme_dme_dispdec +//DME2_DME_CONTROL +#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME2_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME2_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME2_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME2_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME2_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME2_DME_MEMORY_CONTROL +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dcn_dc_dio_dig2_vpg_vpg_dispdec +//VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG2_VPG_GENERIC_PACKET_DATA +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG2_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG2_VPG_GENERIC_STATUS +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG2_VPG_MEM_PWR +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG2_VPG_ISRC1_2_ACCESS_CTRL +#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG2_VPG_ISRC1_2_DATA +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG2_VPG_MPEG_INFO0 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG2_VPG_MPEG_INFO1 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dcn_dc_dio_dig3_dme_dme_dispdec +//DME3_DME_CONTROL +#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME3_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME3_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME3_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME3_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME3_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME3_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME3_DME_MEMORY_CONTROL +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dcn_dc_dio_dig3_vpg_vpg_dispdec +//VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG3_VPG_GENERIC_PACKET_DATA +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG3_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG3_VPG_GENERIC_STATUS +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG3_VPG_MEM_PWR +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG3_VPG_ISRC1_2_ACCESS_CTRL +#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG3_VPG_ISRC1_2_DATA +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG3_VPG_MPEG_INFO0 +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG3_VPG_MPEG_INFO1 +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dcn_dc_dio_dig4_dme_dme_dispdec +//DME4_DME_CONTROL +#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME4_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME4_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME4_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME4_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME4_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME4_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME4_DME_MEMORY_CONTROL +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dcn_dc_dio_dig4_vpg_vpg_dispdec +//VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG4_VPG_GENERIC_PACKET_DATA +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG4_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG4_VPG_GENERIC_STATUS +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG4_VPG_MEM_PWR +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG4_VPG_ISRC1_2_ACCESS_CTRL +#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG4_VPG_ISRC1_2_DATA +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG4_VPG_MPEG_INFO0 +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG4_VPG_MPEG_INFO1 +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dcn_dc_dio_dp_aux0_dispdec +//DP_AUX0_AUX_CONTROL +#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX0_AUX_SW_CONTROL +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX0_AUX_ARB_CONTROL +#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX0_AUX_INTERRUPT_CONTROL +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX0_AUX_SW_STATUS +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX0_AUX_LS_STATUS +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX0_AUX_SW_DATA +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX0_AUX_LS_DATA +#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX0_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX0_AUX_DPHY_TX_CONTROL +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX0_AUX_DPHY_RX_CONTROL0 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX0_AUX_DPHY_RX_CONTROL1 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX0_AUX_DPHY_TX_STATUS +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX0_AUX_DPHY_RX_STATUS +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX0_AUX_GTC_SYNC_CONTROL +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX0_AUX_GTC_SYNC_STATUS +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX0_AUX_PHY_WAKE_CNTL +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dcn_dc_dio_dp_aux1_dispdec +//DP_AUX1_AUX_CONTROL +#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX1_AUX_SW_CONTROL +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX1_AUX_ARB_CONTROL +#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX1_AUX_INTERRUPT_CONTROL +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX1_AUX_SW_STATUS +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX1_AUX_LS_STATUS +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX1_AUX_SW_DATA +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX1_AUX_LS_DATA +#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX1_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX1_AUX_DPHY_TX_CONTROL +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX1_AUX_DPHY_RX_CONTROL0 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX1_AUX_DPHY_RX_CONTROL1 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX1_AUX_DPHY_TX_STATUS +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX1_AUX_DPHY_RX_STATUS +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX1_AUX_GTC_SYNC_CONTROL +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX1_AUX_GTC_SYNC_STATUS +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX1_AUX_PHY_WAKE_CNTL +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dcn_dc_dio_dp_aux2_dispdec +//DP_AUX2_AUX_CONTROL +#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX2_AUX_SW_CONTROL +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX2_AUX_ARB_CONTROL +#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX2_AUX_INTERRUPT_CONTROL +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX2_AUX_SW_STATUS +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX2_AUX_LS_STATUS +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX2_AUX_SW_DATA +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX2_AUX_LS_DATA +#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX2_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX2_AUX_DPHY_TX_CONTROL +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX2_AUX_DPHY_RX_CONTROL0 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX2_AUX_DPHY_RX_CONTROL1 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX2_AUX_DPHY_TX_STATUS +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX2_AUX_DPHY_RX_STATUS +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX2_AUX_GTC_SYNC_CONTROL +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX2_AUX_GTC_SYNC_STATUS +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX2_AUX_PHY_WAKE_CNTL +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dcn_dc_dio_dp_aux3_dispdec +//DP_AUX3_AUX_CONTROL +#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX3_AUX_SW_CONTROL +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX3_AUX_ARB_CONTROL +#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX3_AUX_INTERRUPT_CONTROL +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX3_AUX_SW_STATUS +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX3_AUX_LS_STATUS +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX3_AUX_SW_DATA +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX3_AUX_LS_DATA +#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX3_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX3_AUX_DPHY_TX_CONTROL +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX3_AUX_DPHY_RX_CONTROL0 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX3_AUX_DPHY_RX_CONTROL1 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX3_AUX_DPHY_TX_STATUS +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX3_AUX_DPHY_RX_STATUS +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX3_AUX_GTC_SYNC_CONTROL +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX3_AUX_GTC_SYNC_STATUS +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX3_AUX_PHY_WAKE_CNTL +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dcn_dc_dio_dp_aux4_dispdec +//DP_AUX4_AUX_CONTROL +#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX4_AUX_SW_CONTROL +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX4_AUX_ARB_CONTROL +#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX4_AUX_INTERRUPT_CONTROL +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX4_AUX_SW_STATUS +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX4_AUX_LS_STATUS +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX4_AUX_SW_DATA +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX4_AUX_LS_DATA +#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX4_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX4_AUX_DPHY_TX_CONTROL +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX4_AUX_DPHY_RX_CONTROL0 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX4_AUX_DPHY_RX_CONTROL1 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX4_AUX_DPHY_TX_STATUS +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX4_AUX_DPHY_RX_STATUS +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX4_AUX_GTC_SYNC_CONTROL +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX4_AUX_GTC_SYNC_STATUS +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX4_AUX_PHY_WAKE_CNTL +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dcn_dc_dio_dout_i2c_dispdec +//DC_I2C_CONTROL +#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3 +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14 +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f +#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000L +//DC_I2C_ARBITRATION +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0 +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19 +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L +//DC_I2C_INTERRUPT_CONTROL +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L +//DC_I2C_SW_STATUS +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L +//DC_I2C_DDC1_HW_STATUS +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC2_HW_STATUS +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC3_HW_STATUS +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC4_HW_STATUS +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC5_HW_STATUS +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC1_SPEED +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC1_SETUP +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC2_SPEED +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC2_SETUP +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC3_SPEED +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC3_SETUP +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC4_SPEED +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC4_SETUP +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC5_SPEED +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC5_SETUP +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_TRANSACTION0 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8 +#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L +#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x03FF0000L +//DC_I2C_TRANSACTION1 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8 +#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L +#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x03FF0000L +//DC_I2C_TRANSACTION2 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8 +#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L +#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x03FF0000L +//DC_I2C_TRANSACTION3 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8 +#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L +#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x03FF0000L +//DC_I2C_DATA +#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0 +#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8 +#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f +#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L +#define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000FF00L +#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x03FF0000L +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L +//DC_I2C_EDID_DETECT_CTRL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000FFFFL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00F00000L +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L +//DC_I2C_READ_REQUEST_INTERRUPT +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x00000001L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x00000002L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x00000004L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x00000008L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x00000010L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x00000020L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x00000040L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x00000080L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x00000100L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x00000200L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x00000400L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x00000800L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x00001000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x00002000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x00004000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x00008000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x00010000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x00020000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x00040000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x00080000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x00100000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x00200000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x00400000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x00800000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x01000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x02000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x04000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x08000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000L + + +// addressBlock: dcn_dc_dio_dio_misc_dispdec +//DIO_SCRATCH0 +#define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT 0x0 +#define DIO_SCRATCH0__DIO_SCRATCH0_MASK 0xFFFFFFFFL +//DIO_SCRATCH1 +#define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT 0x0 +#define DIO_SCRATCH1__DIO_SCRATCH1_MASK 0xFFFFFFFFL +//DIO_SCRATCH2 +#define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT 0x0 +#define DIO_SCRATCH2__DIO_SCRATCH2_MASK 0xFFFFFFFFL +//DIO_SCRATCH3 +#define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT 0x0 +#define DIO_SCRATCH3__DIO_SCRATCH3_MASK 0xFFFFFFFFL +//DIO_SCRATCH4 +#define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT 0x0 +#define DIO_SCRATCH4__DIO_SCRATCH4_MASK 0xFFFFFFFFL +//DIO_SCRATCH5 +#define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT 0x0 +#define DIO_SCRATCH5__DIO_SCRATCH5_MASK 0xFFFFFFFFL +//DIO_SCRATCH6 +#define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT 0x0 +#define DIO_SCRATCH6__DIO_SCRATCH6_MASK 0xFFFFFFFFL +//DIO_SCRATCH7 +#define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT 0x0 +#define DIO_SCRATCH7__DIO_SCRATCH7_MASK 0xFFFFFFFFL +//DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x0 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x1 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x3 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x4 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x5 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x6 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000001L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000002L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000008L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000010L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000020L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000040L +//DIO_MEM_PWR_STATUS +#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0 +#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3 +#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4 +#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5 +#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6 +#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7 +#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8 +#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9 +#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x00000001L +#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x00000008L +#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x00000010L +#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x00000020L +#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x00000040L +#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x00000080L +#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x00000100L +#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x00000200L +//DIO_MEM_PWR_CTRL +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0 +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1 +#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4 +#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5 +#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6 +#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7 +#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8 +#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9 +#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000001L +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x00000002L +#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x00000010L +#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x00000020L +#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x00000040L +#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x00000080L +#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x00000100L +#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x00000200L +#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x00000400L +//DIO_MEM_PWR_CTRL2 +#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT 0x18 +#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT 0x19 +#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT 0x1a +#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT 0x1b +#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT 0x1c +#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT 0x1d +#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT 0x1e +#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK 0x01000000L +#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK 0x02000000L +#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK 0x04000000L +#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK 0x08000000L +#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK 0x10000000L +#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK 0x20000000L +#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK 0x40000000L +//DIO_CLK_CNTL +#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS__SHIFT 0x5 +#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18 +#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19 +#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a +#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b +#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c +#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d +#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e +#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS_MASK 0x00000020L +#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x01000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x02000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x04000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x08000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000L +//DIO_POWER_MANAGEMENT_CNTL +#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0 +#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8 +#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L +#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L +//DIG_SOFT_RESET +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0 +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1 +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4 +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5 +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8 +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9 +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10 +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11 +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14 +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15 +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18 +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19 +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x01000000L +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x02000000L +//DIO_CLK_CNTL2 +#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT 0x0 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT 0x7 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT 0x8 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT 0x9 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT 0xb +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT 0xc +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT 0xd +#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT 0x11 +#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT 0x12 +#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT 0x13 +#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT 0x14 +#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT 0x15 +#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT 0x16 +#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT 0x17 +#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS__SHIFT 0x18 +#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS__SHIFT 0x19 +#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS__SHIFT 0x1a +#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS__SHIFT 0x1b +#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS__SHIFT 0x1c +#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS__SHIFT 0x1d +#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS__SHIFT 0x1e +#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK 0x0000007FL +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK 0x00000080L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK 0x00000100L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK 0x00000200L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK 0x00000800L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK 0x00001000L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK 0x00002000L +#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK 0x00020000L +#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK 0x00040000L +#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK 0x00080000L +#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK 0x00100000L +#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK 0x00200000L +#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK 0x00400000L +#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK 0x00800000L +#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS_MASK 0x01000000L +#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS_MASK 0x02000000L +#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS_MASK 0x04000000L +#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS_MASK 0x08000000L +#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS_MASK 0x10000000L +#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS_MASK 0x20000000L +#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS_MASK 0x40000000L +//DIO_CLK_CNTL3 +#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT 0x0 +#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT 0x1 +#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT 0x2 +#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT 0x3 +#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT 0x4 +#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT 0x5 +#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT 0x6 +#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT 0xb +#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT 0xc +#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT 0xd +#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT 0xe +#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT 0xf +#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT 0x10 +#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK 0x00000001L +#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK 0x00000002L +#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK 0x00000004L +#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK 0x00000008L +#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK 0x00000010L +#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK 0x00000020L +#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK 0x00000040L +#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK 0x00000800L +#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK 0x00001000L +#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK 0x00002000L +#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK 0x00004000L +#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK 0x00008000L +#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK 0x00010000L +//DIO_HDMI_RXSTATUS_TIMER_CONTROL +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT 0x0 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT 0x4 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT 0x8 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT 0xc +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT 0x10 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK 0x00000001L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK 0x00000010L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK 0x00000100L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK 0x00001000L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK 0x0FFF0000L +//DIO_LINKA_CNTL +#define DIO_LINKA_CNTL__ENC_TYPE_SEL__SHIFT 0x0 +#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define DIO_LINKA_CNTL__ENC_TYPE_SEL_MASK 0x00000003L +#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL_MASK 0x00000700L +//DIO_LINKB_CNTL +#define DIO_LINKB_CNTL__ENC_TYPE_SEL__SHIFT 0x0 +#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define DIO_LINKB_CNTL__ENC_TYPE_SEL_MASK 0x00000003L +#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL_MASK 0x00000700L +//DIO_LINKC_CNTL +#define DIO_LINKC_CNTL__ENC_TYPE_SEL__SHIFT 0x0 +#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define DIO_LINKC_CNTL__ENC_TYPE_SEL_MASK 0x00000003L +#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL_MASK 0x00000700L +//DIO_LINKD_CNTL +#define DIO_LINKD_CNTL__ENC_TYPE_SEL__SHIFT 0x0 +#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define DIO_LINKD_CNTL__ENC_TYPE_SEL_MASK 0x00000003L +#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL_MASK 0x00000700L +//DIO_LINKE_CNTL +#define DIO_LINKE_CNTL__ENC_TYPE_SEL__SHIFT 0x0 +#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define DIO_LINKE_CNTL__ENC_TYPE_SEL_MASK 0x00000003L +#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL_MASK 0x00000700L +//DIO_LINKF_CNTL +#define DIO_LINKF_CNTL__ENC_TYPE_SEL__SHIFT 0x0 +#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define DIO_LINKF_CNTL__ENC_TYPE_SEL_MASK 0x00000003L +#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL_MASK 0x00000700L + + +// addressBlock: dcn_dc_dcio_dcio_dispdec +//DC_GENERICA +#define DC_GENERICA__GENERICA_EN__SHIFT 0x0 +#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7 +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_GENERICA__GENERICA_EN_MASK 0x00000001L +#define DC_GENERICA__GENERICA_SEL_MASK 0x00000F80L +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L +//DC_GENERICB +#define DC_GENERICB__GENERICB_EN__SHIFT 0x0 +#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_GENERICB__GENERICB_EN_MASK 0x00000001L +#define DC_GENERICB__GENERICB_SEL_MASK 0x00000F00L +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L +//DCIO_CLOCK_CNTL +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0 +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5 +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x0000001FL +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x00000020L +//DC_REF_CLK_CNTL +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L +//UNIPHYA_CHANNEL_XBAR_CNTL +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//UNIPHYB_CHANNEL_XBAR_CNTL +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//UNIPHYC_CHANNEL_XBAR_CNTL +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//UNIPHYD_CHANNEL_XBAR_CNTL +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//UNIPHYE_CHANNEL_XBAR_CNTL +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//DCIO_WRCMD_DELAY +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x18 +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xFF000000L +//DC_PINSTRAPS +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10 +#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11 +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x00002000L +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000C000L +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x00010000L +#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0x000E0000L +//DCIO_SPARE +#define DCIO_SPARE__DCIO_SPARE__SHIFT 0x0 +#define DCIO_SPARE__DCIO_SPARE_MASK 0xFFFFFFFFL +//INTERCEPT_STATE +#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT 0x0 +#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE__SHIFT 0x1 +#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE__SHIFT 0x4 +#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE__SHIFT 0x5 +#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE__SHIFT 0x6 +#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE__SHIFT 0x7 +#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE__SHIFT 0x8 +#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE__SHIFT 0x9 +#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE__SHIFT 0xa +#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK 0x00000001L +#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE_MASK 0x00000002L +#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE_MASK 0x00000010L +#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE_MASK 0x00000020L +#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE_MASK 0x00000040L +#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE_MASK 0x00000080L +#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE_MASK 0x00000100L +#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE_MASK 0x00000200L +#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE_MASK 0x00000400L +//DCIO_PATTERN_GEN_PAT +#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT__SHIFT 0x0 +#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT_MASK 0xFFFFFFFFL +//DCIO_PATTERN_GEN_EN +#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN__SHIFT 0x0 +#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN_MASK 0x00000001L +//DCIO_BL_PWM_FRAME_START_DISP_SEL +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT 0x0 +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL__SHIFT 0x4 +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK 0x00000007L +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL_MASK 0x00000070L +//DCIO_GSL_GENLK_PAD_CNTL +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT 0x4 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT 0x14 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK 0x00000030L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK 0x00300000L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L +//DCIO_GSL_SWAPLOCK_PAD_CNTL +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT 0x4 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT 0x14 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK 0x00000030L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK 0x00300000L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L +//DCIO_SOFT_RESET +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0 +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x1 +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x2 +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x3 +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x4 +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0x5 +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0x6 +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x8 +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x9 +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0xa +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0xb +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0xc +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xd +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xe +#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT 0x10 +#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET__SHIFT 0x11 +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x00000001L +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x00000002L +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x00000004L +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x00000008L +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x00000010L +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x00000020L +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x00000040L +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000100L +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000200L +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000400L +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000800L +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00001000L +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00002000L +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x00004000L +#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK 0x00010000L +#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET_MASK 0x00020000L + + +// addressBlock: dcn_dc_dcio_dcio_chip_dispdec +//DC_GPIO_GENERIC_MASK +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN__SHIFT 0x1c +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x0000000CL +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x000000C0L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000C00L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x0000C000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x000C0000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00C00000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x0C000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN_MASK 0xF0000000L +//DC_GPIO_GENERIC_A +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L +//DC_GPIO_GENERIC_EN +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L +//DC_GPIO_GENERIC_Y +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L +//DC_GPIO_DDC1_MASK +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 +#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L +#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC1_A +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L +//DC_GPIO_DDC1_EN +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC1_Y +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC2_MASK +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 +#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L +#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC2_A +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L +//DC_GPIO_DDC2_EN +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC2_Y +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC3_MASK +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 +#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L +#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC3_A +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L +//DC_GPIO_DDC3_EN +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC3_Y +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC4_MASK +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 +#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L +#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC4_A +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L +//DC_GPIO_DDC4_EN +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC4_Y +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC5_MASK +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 +#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L +#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC5_A +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L +//DC_GPIO_DDC5_EN +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC5_Y +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L +//DC_GPIO_DDCVGA_MASK +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY__SHIFT 0x4 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10 +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY_MASK 0x00000010L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xF0000000L +//DC_GPIO_DDCVGA_A +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L +//DC_GPIO_DDCVGA_EN +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L +//DC_GPIO_DDCVGA_Y +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L +//DC_GPIO_GENLK_MASK +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x4 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xc +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x14 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1c +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000030L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00003000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00300000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x30000000L +//DC_GPIO_GENLK_A +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L +//DC_GPIO_GENLK_EN +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L +//DC_GPIO_GENLK_Y +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L +//DC_GPIO_HPD_MASK +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x000000C0L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000C00L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x000C0000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00C00000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x0C000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0xC0000000L +//DC_GPIO_HPD_A +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0 +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8 +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10 +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18 +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L +//DC_GPIO_HPD_EN +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0 +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1 +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2 +#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5 +#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8 +#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9 +#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10 +#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11 +#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14 +#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15 +#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18 +#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19 +#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c +#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d +#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x00000002L +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x00000004L +#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x00000020L +#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x00000040L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L +#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x00000200L +#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x00000400L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L +#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x00020000L +#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x00040000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x00100000L +#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x00200000L +#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x00400000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x01000000L +#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x02000000L +#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x04000000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L +#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000L +#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000L +//DC_GPIO_HPD_Y +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L +//DC_GPIO_DRIVE_STRENGTH_S0 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICA_S0__SHIFT 0x0 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICB_S0__SHIFT 0x1 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICC_S0__SHIFT 0x2 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICD_S0__SHIFT 0x3 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICE_S0__SHIFT 0x4 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICF_S0__SHIFT 0x5 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICG_S0__SHIFT 0x6 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_CLK_S0__SHIFT 0x8 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_VSYNC_S0__SHIFT 0x9 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_A_S0__SHIFT 0xa +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_B_S0__SHIFT 0xb +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICA_S0_MASK 0x00000001L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICB_S0_MASK 0x00000002L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICC_S0_MASK 0x00000004L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICD_S0_MASK 0x00000008L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICE_S0_MASK 0x00000010L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICF_S0_MASK 0x00000020L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICG_S0_MASK 0x00000040L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_CLK_S0_MASK 0x00000100L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_VSYNC_S0_MASK 0x00000200L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_A_S0_MASK 0x00000400L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_B_S0_MASK 0x00000800L +//DC_GPIO_DRIVE_STRENGTH_S1 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICA_S1__SHIFT 0x0 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICB_S1__SHIFT 0x1 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICC_S1__SHIFT 0x2 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICD_S1__SHIFT 0x3 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICE_S1__SHIFT 0x4 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICF_S1__SHIFT 0x5 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICG_S1__SHIFT 0x6 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_CLK_S1__SHIFT 0x8 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_VSYNC_S1__SHIFT 0x9 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_A_S1__SHIFT 0xa +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_B_S1__SHIFT 0xb +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICA_S1_MASK 0x00000001L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICB_S1_MASK 0x00000002L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICC_S1_MASK 0x00000004L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICD_S1_MASK 0x00000008L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICE_S1_MASK 0x00000010L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICF_S1_MASK 0x00000020L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICG_S1_MASK 0x00000040L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_CLK_S1_MASK 0x00000100L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_VSYNC_S1_MASK 0x00000200L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_A_S1_MASK 0x00000400L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_B_S1_MASK 0x00000800L +//DC_GPIO_PWRSEQ0_EN +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT 0x14 +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT 0x15 +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT 0x19 +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT 0x1a +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1d +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK 0x00100000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK 0x00E00000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK 0x02000000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK 0x1C000000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x20000000L +//DC_GPIO_PAD_STRENGTH_1 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10 +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000FL +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000F0L +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0x000F0000L +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0x00F00000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0F000000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xF0000000L +//DC_GPIO_PAD_STRENGTH_2 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000FL +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000F0L +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x00000700L +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x00007000L +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xC0000000L +//PHY_AUX_CNTL +#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0x9 +#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT 0xa +#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT 0xc +#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT 0xe +#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT 0x10 +#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT 0x12 +#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT 0x14 +#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00000200L +#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK 0x00000C00L +#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK 0x00003000L +#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK 0x0000C000L +#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK 0x00030000L +#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK 0x000C0000L +#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK 0x00300000L +//DC_GPIO_DRIVE_TXIMPSEL +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICA_TXIMPSEL__SHIFT 0x0 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICB_TXIMPSEL__SHIFT 0x1 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICC_TXIMPSEL__SHIFT 0x2 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICD_TXIMPSEL__SHIFT 0x3 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICE_TXIMPSEL__SHIFT 0x4 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICF_TXIMPSEL__SHIFT 0x5 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICG_TXIMPSEL__SHIFT 0x6 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_CLK_TXIMPSEL__SHIFT 0x8 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_VSYNC_TXIMPSEL__SHIFT 0x9 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_A_TXIMPSEL__SHIFT 0xa +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_B_TXIMPSEL__SHIFT 0xb +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD1_TXIMPSEL__SHIFT 0xc +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD2_TXIMPSEL__SHIFT 0xd +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD3_TXIMPSEL__SHIFT 0xe +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD4_TXIMPSEL__SHIFT 0xf +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD5_TXIMPSEL__SHIFT 0x10 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD6_TXIMPSEL__SHIFT 0x11 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICA_TXIMPSEL_MASK 0x00000001L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICB_TXIMPSEL_MASK 0x00000002L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICC_TXIMPSEL_MASK 0x00000004L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICD_TXIMPSEL_MASK 0x00000008L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICE_TXIMPSEL_MASK 0x00000010L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICF_TXIMPSEL_MASK 0x00000020L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICG_TXIMPSEL_MASK 0x00000040L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_CLK_TXIMPSEL_MASK 0x00000100L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_VSYNC_TXIMPSEL_MASK 0x00000200L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_A_TXIMPSEL_MASK 0x00000400L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_B_TXIMPSEL_MASK 0x00000800L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD1_TXIMPSEL_MASK 0x00001000L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD2_TXIMPSEL_MASK 0x00002000L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD3_TXIMPSEL_MASK 0x00004000L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD4_TXIMPSEL_MASK 0x00008000L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD5_TXIMPSEL_MASK 0x00010000L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD6_TXIMPSEL_MASK 0x00020000L +//DC_GPIO_TX12_EN +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT 0x3 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT 0x4 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT 0x5 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT 0x6 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT 0x7 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT 0x8 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT 0x9 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK 0x00000008L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK 0x00000010L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK 0x00000020L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK 0x00000040L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK 0x00000080L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK 0x00000100L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK 0x00000200L +//DC_GPIO_AUX_CTRL_0 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT 0x15 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK 0x000000C0L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK 0x00000300L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK 0x00000C00L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK 0x00003000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK 0x00200000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK 0x00C00000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK 0xC0000000L +//DC_GPIO_AUX_CTRL_1 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT 0x1 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT 0x3 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT 0x7 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT 0xb +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK 0x00000001L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK 0x00000002L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK 0x00000004L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK 0x00000008L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK 0x00000010L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK 0x00000020L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK 0x00000040L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK 0x00000080L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK 0x00001800L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK 0x0000C000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK 0x00030000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK 0x000C0000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK 0x00300000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK 0xC0000000L +//DC_GPIO_AUX_CTRL_2 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK 0x00004000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK 0x40000000L +//DC_GPIO_RXEN +#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT 0x0 +#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT 0x1 +#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT 0x2 +#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT 0x3 +#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT 0x4 +#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT 0x5 +#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT 0x6 +#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT 0x8 +#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT 0x9 +#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT 0xa +#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT 0xb +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT 0xc +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT 0xd +#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT 0xe +#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT 0xf +#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT 0x10 +#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT 0x11 +#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT 0x12 +#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT 0x13 +#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK 0x00000001L +#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK 0x00000002L +#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK 0x00000004L +#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK 0x00000008L +#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK 0x00000010L +#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK 0x00000020L +#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK 0x00000040L +#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK 0x00000100L +#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK 0x00000200L +#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK 0x00000400L +#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK 0x00000800L +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK 0x00001000L +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK 0x00002000L +#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK 0x00004000L +#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK 0x00008000L +#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK 0x00010000L +#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK 0x00020000L +#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK 0x00040000L +#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK 0x00080000L +//DC_GPIO_PULLUPEN +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT 0x0 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT 0x1 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT 0x2 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT 0x3 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT 0x4 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT 0x5 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT 0x6 +#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT 0x8 +#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT 0x9 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT 0xe +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT 0xf +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT 0x10 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT 0x11 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT 0x12 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT 0x13 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK 0x00000001L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK 0x00000002L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK 0x00000004L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK 0x00000008L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK 0x00000010L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK 0x00000020L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK 0x00000040L +#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK 0x00000100L +#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK 0x00000200L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK 0x00004000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK 0x00008000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK 0x00010000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK 0x00020000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK 0x00040000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK 0x00080000L +//DC_GPIO_AUX_CTRL_3 +#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT 0x1 +#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT 0x3 +#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT 0xb +#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK 0x00000001L +#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK 0x00000002L +#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK 0x00000004L +#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK 0x00000008L +#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK 0x00000010L +#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK 0x00000020L +#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK 0x00000800L +#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK 0x00030000L +#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK 0x000C0000L +#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK 0x00300000L +#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK 0x00C00000L +#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK 0x03000000L +#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK 0x0C000000L +//DC_GPIO_AUX_CTRL_4 +#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK 0x0000000FL +#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK 0x000000F0L +#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK 0x00000F00L +#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK 0x0000F000L +#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK 0x000F0000L +#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK 0x00F00000L +//DC_GPIO_AUX_CTRL_5 +#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT 0xf +#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT 0x15 +#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT 0x17 +#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK 0x000000C0L +#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK 0x00000300L +#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK 0x00000C00L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK 0x00004000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK 0x00008000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK 0x00200000L +#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK 0x00400000L +#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK 0x00800000L +#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK 0x20000000L +//AUXI2C_PAD_ALL_PWR_OK +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT 0x0 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT 0x1 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT 0x2 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT 0x3 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT 0x4 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT 0x5 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK 0x00000001L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK 0x00000002L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK 0x00000004L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK 0x00000008L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK 0x00000010L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK 0x00000020L + + +// addressBlock: dcn_dc_dcio_dcio_uniphy0_dispdec +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_dcio_dcio_uniphy1_dispdec +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_dcio_dcio_uniphy2_dispdec +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_dcio_dcio_uniphy3_dispdec +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_dcio_dcio_uniphy4_dispdec +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_pwrseq0_dispdec_pwrseq_dispdec +//DC_GPIO_PWRSEQ_EN +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00010000L +//DC_GPIO_PWRSEQ_CTRL +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL__SHIFT 0x1 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL__SHIFT 0x2 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT 0x3 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT 0x4 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT 0x5 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT 0x6 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT 0x7 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1__SHIFT 0x14 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1__SHIFT 0x15 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1__SHIFT 0x16 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL_MASK 0x00000002L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL_MASK 0x00000004L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK 0x00000008L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK 0x00000010L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK 0x00000020L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK 0x00000040L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK 0x00000080L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1_MASK 0x00100000L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1_MASK 0x00200000L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1_MASK 0x00400000L +//DC_GPIO_PWRSEQ_MASK +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT 0x4 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT 0x6 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x14 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x16 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK 0x00000010L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK 0x000000C0L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x0000C000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00100000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x00C00000L +//DC_GPIO_PWRSEQ_A_Y +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT 0x1 +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT 0x9 +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT 0x11 +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK 0x00000002L +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK 0x00000200L +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK 0x00020000L +//PANEL_PWRSEQ_CNTL +#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT 0x0 +#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT 0x4 +#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT 0x8 +#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT 0x9 +#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT 0xa +#define PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT 0x10 +#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT 0x11 +#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT 0x12 +#define PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT 0x18 +#define PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT 0x19 +#define PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT 0x1a +#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK 0x00000001L +#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK 0x00000010L +#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK 0x00000100L +#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK 0x00000200L +#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK 0x00000400L +#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK 0x00010000L +#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK 0x00020000L +#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK 0x00040000L +#define PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK 0x01000000L +#define PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK 0x02000000L +#define PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK 0x04000000L +//PANEL_PWRSEQ_STATE +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT 0x1 +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT 0x2 +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT 0x3 +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT 0x4 +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT 0x8 +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK 0x00000002L +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK 0x00000004L +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK 0x00000008L +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK 0x00000010L +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK 0x00000F00L +//PANEL_PWRSEQ_DELAY1 +#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT 0x0 +#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT 0x8 +#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT 0x10 +#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT 0x18 +#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK 0x000000FFL +#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK 0x0000FF00L +#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK 0x00FF0000L +#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK 0xFF000000L +//PANEL_PWRSEQ_DELAY2 +#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT 0x0 +#define PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT 0x8 +#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT 0x10 +#define PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT 0x18 +#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK 0x000000FFL +#define PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK 0x0000FF00L +#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK 0x00FF0000L +#define PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK 0x01000000L +//PANEL_PWRSEQ_REF_DIV1 +#define PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT 0x0 +#define PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT 0x10 +#define PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK 0x00000FFFL +#define PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK 0xFFFF0000L +//BL_PWM_CNTL +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 +#define BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT 0x13 +#define BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT 0x14 +#define BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x15 +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e +#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000FFFFL +#define BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK 0x00080000L +#define BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK 0x00100000L +#define BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x00200000L +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L +#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L +//BL_PWM_CNTL2 +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT 0x1f +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000FFFFL +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000L +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK 0x80000000L +//BL_PWM_PERIOD_CNTL +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000FFFFL +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000F0000L +//BL_PWM_GRP1_REG_LOCK +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//PANEL_PWRSEQ_REF_DIV2 +#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT 0x0 +#define PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT 0x8 +#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT 0x10 +#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK 0x0000007FL +#define PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK 0x00007F00L +#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK 0x00010000L +//PWRSEQ_SPARE +#define PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT 0x0 +#define PWRSEQ_SPARE__PWRSEQ_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_dsc0_dispdec_dscc_dispdec +//DSCC0_DSCC_CONFIG0 +#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC0_DSCC_CONFIG1 +#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC0_DSCC_STATUS +#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC0_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT 0xc +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT 0x1c +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK 0x00001000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK 0x10000000L +//DSCC0_DSCC_PPS_CONFIG0 +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC0_DSCC_PPS_CONFIG1 +#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG2 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG3 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG4 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG5 +#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG6 +#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC0_DSCC_PPS_CONFIG7 +#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG8 +#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG9 +#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG10 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG11 +#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC0_DSCC_PPS_CONFIG12 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG13 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG14 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG15 +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG16 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG17 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG18 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG19 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG20 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG21 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG22 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC0_DSCC_MEM_POWER_CONTROL +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_MAX_ABS_ERROR0 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC0_DSCC_MAX_ABS_ERROR1 +#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL + + +// addressBlock: dcn_dc_dsc0_dispdec_dsccif_dispdec +//DSCCIF0_DSCCIF_CONFIG0 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF0_DSCCIF_CONFIG1 +#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dcn_dc_dsc0_dispdec_dsc_top_dispdec +//DSC_TOP0_DSC_TOP_CONTROL +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +//DSC_TOP0_DSC_DEBUG_CONTROL +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L + + +// addressBlock: dcn_dc_dsc1_dispdec_dscc_dispdec +//DSCC1_DSCC_CONFIG0 +#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC1_DSCC_CONFIG1 +#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC1_DSCC_STATUS +#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC1_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT 0xc +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT 0x1c +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK 0x00001000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK 0x10000000L +//DSCC1_DSCC_PPS_CONFIG0 +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC1_DSCC_PPS_CONFIG1 +#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG2 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG3 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG4 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG5 +#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG6 +#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC1_DSCC_PPS_CONFIG7 +#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG8 +#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG9 +#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG10 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG11 +#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC1_DSCC_PPS_CONFIG12 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG13 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG14 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG15 +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG16 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG17 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG18 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG19 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG20 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG21 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG22 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC1_DSCC_MEM_POWER_CONTROL +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_MAX_ABS_ERROR0 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC1_DSCC_MAX_ABS_ERROR1 +#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL + + +// addressBlock: dcn_dc_dsc1_dispdec_dsccif_dispdec +//DSCCIF1_DSCCIF_CONFIG0 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF1_DSCCIF_CONFIG1 +#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dcn_dc_dsc1_dispdec_dsc_top_dispdec +//DSC_TOP1_DSC_TOP_CONTROL +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L + + +// addressBlock: dcn_dc_dsc2_dispdec_dscc_dispdec +//DSCC2_DSCC_CONFIG0 +#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC2_DSCC_CONFIG1 +#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC2_DSCC_STATUS +#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC2_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT 0xc +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT 0x1c +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK 0x00001000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK 0x10000000L +//DSCC2_DSCC_PPS_CONFIG0 +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC2_DSCC_PPS_CONFIG1 +#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG2 +#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG3 +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG4 +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG5 +#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG6 +#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC2_DSCC_PPS_CONFIG7 +#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG8 +#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG9 +#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG10 +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG11 +#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC2_DSCC_PPS_CONFIG12 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC2_DSCC_PPS_CONFIG13 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC2_DSCC_PPS_CONFIG14 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC2_DSCC_PPS_CONFIG15 +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG16 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG17 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG18 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG19 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG20 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG21 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG22 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC2_DSCC_MEM_POWER_CONTROL +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_MAX_ABS_ERROR0 +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC2_DSCC_MAX_ABS_ERROR1 +#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL + + +// addressBlock: dcn_dc_dsc2_dispdec_dsccif_dispdec +//DSCCIF2_DSCCIF_CONFIG0 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF2_DSCCIF_CONFIG1 +#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dcn_dc_dsc2_dispdec_dsc_top_dispdec +//DSC_TOP2_DSC_TOP_CONTROL +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L + + +// addressBlock: dcn_dc_dsc3_dispdec_dscc_dispdec +//DSCC3_DSCC_CONFIG0 +#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC3_DSCC_CONFIG1 +#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC3_DSCC_STATUS +#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC3_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT 0xc +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT 0x1c +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK 0x00001000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK 0x10000000L +//DSCC3_DSCC_PPS_CONFIG0 +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC3_DSCC_PPS_CONFIG1 +#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG2 +#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG3 +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG4 +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG5 +#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG6 +#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC3_DSCC_PPS_CONFIG7 +#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG8 +#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG9 +#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG10 +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG11 +#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC3_DSCC_PPS_CONFIG12 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC3_DSCC_PPS_CONFIG13 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC3_DSCC_PPS_CONFIG14 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC3_DSCC_PPS_CONFIG15 +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG16 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG17 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG18 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG19 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG20 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG21 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG22 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC3_DSCC_MEM_POWER_CONTROL +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_MAX_ABS_ERROR0 +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC3_DSCC_MAX_ABS_ERROR1 +#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL + + +// addressBlock: dcn_dc_dsc3_dispdec_dsccif_dispdec +//DSCCIF3_DSCCIF_CONFIG0 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF3_DSCCIF_CONFIG1 +#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dcn_dc_dsc3_dispdec_dsc_top_dispdec +//DSC_TOP3_DSC_TOP_CONTROL +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L + + +// addressBlock: dcn_dc_hpo_hpo_top_dispdec +//HPO_TOP_CLOCK_CONTROL +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT 0x1 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT 0x4 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT 0x5 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT 0x8 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS__SHIFT 0x9 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT 0xc +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS__SHIFT 0xd +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS__SHIFT 0x10 +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS__SHIFT 0x11 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS__SHIFT 0x12 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS__SHIFT 0x13 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS__SHIFT 0x14 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS__SHIFT 0x15 +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT 0x18 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK 0x00000002L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK 0x00000010L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK 0x00000020L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK 0x00000100L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS_MASK 0x00000200L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK 0x00001000L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS_MASK 0x00002000L +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS_MASK 0x00010000L +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS_MASK 0x00020000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS_MASK 0x00040000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS_MASK 0x00080000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS_MASK 0x00100000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS_MASK 0x00200000L +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK 0xFF000000L +//HPO_TOP_HW_CONTROL +#define HPO_TOP_HW_CONTROL__HPO_IO_EN__SHIFT 0x0 +#define HPO_TOP_HW_CONTROL__HPO_IO_EN_MASK 0x00000001L + + +// addressBlock: dcn_dc_hpo_dp_stream_mapper_dispdec +//DP_STREAM_MAPPER_CONTROL0 +#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET_MASK 0x00000007L +//DP_STREAM_MAPPER_CONTROL1 +#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET_MASK 0x00000007L +//DP_STREAM_MAPPER_CONTROL2 +#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET_MASK 0x00000007L +//DP_STREAM_MAPPER_CONTROL3 +#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET_MASK 0x00000007L + + +// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec +//AFMT5_AFMT_VBI_PACKET_CONTROL +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT5_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT5_AFMT_AUDIO_INFO0 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT5_AFMT_AUDIO_INFO1 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT5_AFMT_60958_0 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT5_AFMT_60958_1 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT5_AFMT_AUDIO_CRC_CONTROL +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT5_AFMT_RAMP_CONTROL0 +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT5_AFMT_RAMP_CONTROL1 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT5_AFMT_RAMP_CONTROL2 +#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT5_AFMT_RAMP_CONTROL3 +#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT5_AFMT_60958_2 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT5_AFMT_AUDIO_CRC_RESULT +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT5_AFMT_STATUS +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT5_AFMT_AUDIO_PACKET_CONTROL +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT5_AFMT_INFOFRAME_CONTROL0 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT5_AFMT_INTERRUPT_STATUS +//AFMT5_AFMT_AUDIO_SRC_CONTROL +#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT5_AFMT_MEM_PWR +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec +//DME5_DME_CONTROL +#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME5_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME5_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME5_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME5_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME5_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME5_DME_MEMORY_CONTROL +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec +//VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG5_VPG_GENERIC_PACKET_DATA +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG5_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG5_VPG_GENERIC_STATUS +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG5_VPG_MEM_PWR +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG5_VPG_ISRC1_2_ACCESS_CTRL +#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG5_VPG_ISRC1_2_DATA +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG5_VPG_MPEG_INFO0 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG5_VPG_MPEG_INFO1 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dcn_dc_hpo_dp_stream_enc0_dispdec +//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +//DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00001F00L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC0_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hpo_dp_stream_enc0_apg_apg_dispdec +//APG0_APG_CONTROL +#define APG0_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG0_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG0_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG0_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG0_APG_CONTROL2 +#define APG0_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG0_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG0_APG_DBG_GEN_CONTROL +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG0_APG_PACKET_CONTROL +#define APG0_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT 0x0 +#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT 0x1 +#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG0_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK 0x00000001L +#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK 0x00000002L +#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG0_APG_AUDIO_CRC_CONTROL +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG0_APG_AUDIO_CRC_CONTROL2 +#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG0_APG_AUDIO_CRC_RESULT +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG0_APG_STATUS +#define APG0_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG0_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG0_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG0_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG0_APG_STATUS2 +#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG0_APG_MEM_PWR +#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG0_APG_SPARE +#define APG0_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG0_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hpo_dp_stream_enc0_dme_dme_dispdec +//DME6_DME_CONTROL +#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME6_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME6_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME6_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME6_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME6_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME6_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME6_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME6_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME6_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME6_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME6_DME_MEMORY_CONTROL +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dcn_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec +//VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG6_VPG_GENERIC_PACKET_DATA +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG6_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG6_VPG_GENERIC_STATUS +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG6_VPG_MEM_PWR +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG6_VPG_ISRC1_2_ACCESS_CTRL +#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG6_VPG_ISRC1_2_DATA +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG6_VPG_MPEG_INFO0 +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG6_VPG_MPEG_INFO1 +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dcn_dc_hpo_dp_sym32_enc0_dispdec +//DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK 0x0000FFFFL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK 0x0000FFFFL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +//DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hpo_dp_stream_enc1_dispdec +//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +//DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00001F00L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC1_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hpo_dp_stream_enc1_apg_apg_dispdec +//APG1_APG_CONTROL +#define APG1_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG1_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG1_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG1_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG1_APG_CONTROL2 +#define APG1_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG1_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG1_APG_DBG_GEN_CONTROL +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG1_APG_PACKET_CONTROL +#define APG1_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT 0x0 +#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT 0x1 +#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG1_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK 0x00000001L +#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK 0x00000002L +#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG1_APG_AUDIO_CRC_CONTROL +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG1_APG_AUDIO_CRC_CONTROL2 +#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG1_APG_AUDIO_CRC_RESULT +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG1_APG_STATUS +#define APG1_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG1_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG1_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG1_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG1_APG_STATUS2 +#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG1_APG_MEM_PWR +#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG1_APG_SPARE +#define APG1_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG1_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hpo_dp_stream_enc1_dme_dme_dispdec +//DME7_DME_CONTROL +#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME7_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME7_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME7_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME7_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME7_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME7_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME7_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME7_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME7_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME7_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME7_DME_MEMORY_CONTROL +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dcn_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec +//VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG7_VPG_GENERIC_PACKET_DATA +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG7_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG7_VPG_GENERIC_STATUS +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG7_VPG_MEM_PWR +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG7_VPG_ISRC1_2_ACCESS_CTRL +#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG7_VPG_ISRC1_2_DATA +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG7_VPG_MPEG_INFO0 +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG7_VPG_MPEG_INFO1 +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dcn_dc_hpo_dp_sym32_enc1_dispdec +//DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK 0x0000FFFFL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK 0x0000FFFFL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +//DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hpo_dp_stream_enc2_dispdec +//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +//DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00001F00L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC2_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hpo_dp_stream_enc2_apg_apg_dispdec +//APG2_APG_CONTROL +#define APG2_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG2_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG2_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG2_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG2_APG_CONTROL2 +#define APG2_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG2_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG2_APG_DBG_GEN_CONTROL +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG2_APG_PACKET_CONTROL +#define APG2_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT 0x0 +#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT 0x1 +#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG2_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK 0x00000001L +#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK 0x00000002L +#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG2_APG_AUDIO_CRC_CONTROL +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG2_APG_AUDIO_CRC_CONTROL2 +#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG2_APG_AUDIO_CRC_RESULT +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG2_APG_STATUS +#define APG2_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG2_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG2_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG2_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG2_APG_STATUS2 +#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG2_APG_MEM_PWR +#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG2_APG_SPARE +#define APG2_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG2_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hpo_dp_stream_enc2_dme_dme_dispdec +//DME8_DME_CONTROL +#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME8_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME8_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME8_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME8_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME8_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME8_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME8_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME8_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME8_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME8_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME8_DME_MEMORY_CONTROL +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dcn_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec +//VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG8_VPG_GENERIC_PACKET_DATA +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG8_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG8_VPG_GENERIC_STATUS +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG8_VPG_MEM_PWR +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG8_VPG_ISRC1_2_ACCESS_CTRL +#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG8_VPG_ISRC1_2_DATA +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG8_VPG_MPEG_INFO0 +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG8_VPG_MPEG_INFO1 +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dcn_dc_hpo_dp_sym32_enc2_dispdec +//DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK 0x0000FFFFL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK 0x0000FFFFL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +//DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hpo_dp_stream_enc3_dispdec +//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +//DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00001F00L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC3_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hpo_dp_stream_enc3_apg_apg_dispdec +//APG3_APG_CONTROL +#define APG3_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG3_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG3_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG3_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG3_APG_CONTROL2 +#define APG3_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG3_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG3_APG_DBG_GEN_CONTROL +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG3_APG_PACKET_CONTROL +#define APG3_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT 0x0 +#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT 0x1 +#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG3_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK 0x00000001L +#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK 0x00000002L +#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG3_APG_AUDIO_CRC_CONTROL +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG3_APG_AUDIO_CRC_CONTROL2 +#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG3_APG_AUDIO_CRC_RESULT +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG3_APG_STATUS +#define APG3_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG3_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG3_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG3_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG3_APG_STATUS2 +#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG3_APG_MEM_PWR +#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG3_APG_SPARE +#define APG3_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG3_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hpo_dp_stream_enc3_dme_dme_dispdec +//DME9_DME_CONTROL +#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME9_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME9_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME9_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME9_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME9_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME9_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME9_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME9_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME9_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME9_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME9_DME_MEMORY_CONTROL +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dcn_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec +//VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG9_VPG_GENERIC_PACKET_DATA +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG9_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG9_VPG_GENERIC_STATUS +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG9_VPG_MEM_PWR +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG9_VPG_ISRC1_2_ACCESS_CTRL +#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG9_VPG_ISRC1_2_DATA +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG9_VPG_MPEG_INFO0 +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG9_VPG_MPEG_INFO1 +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dcn_dc_hpo_dp_sym32_enc3_dispdec +//DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK 0x0000FFFFL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK 0x0000FFFFL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +//DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hpo_dp_link_enc0_dispdec +//DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x4 +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK 0x00000010L +//DP_LINK_ENC0_DP_LINK_ENC_SPARE +#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hpo_dp_dphy_sym320_dispdec +//DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE_MASK 0x00000030L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK 0x00000300L +//DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT 0xc +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT 0x10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK 0x00000030L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK 0x00001000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK 0x00030000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK 0x00000003L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT 0xc +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT 0x10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT 0x14 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT 0x18 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT 0x1c +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK 0x00000070L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK 0x00000700L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK 0x00007000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK 0x00070000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK 0x00700000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK 0x07000000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK 0x70000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK 0x000000FFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT 0x2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT 0x3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT 0x6 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT 0x7 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK 0x00000004L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK 0x00000008L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK 0x00000040L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK 0x00000080L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK 0x00000100L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT 0x2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT 0xa +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT 0xc +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT 0x10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT 0x12 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT 0x14 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT 0x18 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT 0x1a +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT 0x1c +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK 0x00000003L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK 0x00000004L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK 0x000000F0L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK 0x00000300L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK 0x00000400L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK 0x0000F000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK 0x00030000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK 0x00040000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK 0x00F00000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK 0x03000000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK 0x04000000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK 0xF0000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT 0x6 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT 0x10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT 0x11 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT 0x14 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT 0x15 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK 0x00000030L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK 0x000000C0L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK 0x00003F00L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK 0x00010000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK 0x000E0000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK 0x00100000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK 0x00600000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK 0x00FFFF00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hpo_dp_link_enc1_dispdec +//DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x4 +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK 0x00000010L +//DP_LINK_ENC1_DP_LINK_ENC_SPARE +#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hpo_dp_dphy_sym321_dispdec +//DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE_MASK 0x00000030L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK 0x00000300L +//DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT 0xc +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT 0x10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK 0x00000030L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK 0x00001000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK 0x00030000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK 0x00000003L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT 0xc +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT 0x10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT 0x14 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT 0x18 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT 0x1c +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK 0x00000070L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK 0x00000700L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK 0x00007000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK 0x00070000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK 0x00700000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK 0x07000000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK 0x70000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK 0x000000FFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT 0x2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT 0x3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT 0x6 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT 0x7 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK 0x00000004L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK 0x00000008L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK 0x00000040L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK 0x00000080L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK 0x00000100L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT 0x2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT 0xa +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT 0xc +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT 0x10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT 0x12 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT 0x14 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT 0x18 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT 0x1a +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT 0x1c +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK 0x00000003L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK 0x00000004L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK 0x000000F0L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK 0x00000300L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK 0x00000400L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK 0x0000F000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK 0x00030000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK 0x00040000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK 0x00F00000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK 0x03000000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK 0x04000000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK 0xF0000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT 0x6 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT 0x10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT 0x11 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT 0x14 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT 0x15 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK 0x00000030L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK 0x000000C0L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK 0x00003F00L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK 0x00010000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK 0x000E0000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK 0x00100000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK 0x00600000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK 0x00FFFF00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe0_dispdec +//RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6 +#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 +#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 +#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 +#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L +#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L +#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L + + +// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe1_dispdec +//RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6 +#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 +#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 +#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 +#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L +#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L +#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L + + +// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe2_dispdec +//RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6 +#define RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 +#define RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 +#define RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 +#define RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L +#define RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L +#define RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L + + +// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe3_dispdec +//RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6 +#define RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 +#define RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 +#define RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 +#define RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L +#define RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L +#define RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L + + +// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe4_dispdec +//RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6 +#define RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 +#define RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 +#define RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 +#define RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L +#define RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L +#define RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L + + +// addressBlock: dcn_dc_hda_azcontroller_azdec +//CORB_WRITE_POINTER +#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 +#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL +//CORB_READ_POINTER +#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 +#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf +#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL +#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L +//CORB_CONTROL +#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 +#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 +#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L +#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L +//CORB_STATUS +#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 +#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x01L +//CORB_SIZE +#define CORB_SIZE__CORB_SIZE__SHIFT 0x0 +#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 +#define CORB_SIZE__CORB_SIZE_MASK 0x0003L +#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0x00F0L +//RIRB_LOWER_BASE_ADDRESS +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//RIRB_UPPER_BASE_ADDRESS +#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//RIRB_WRITE_POINTER +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0x00FFL +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000L +//RESPONSE_INTERRUPT_COUNT +#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 +#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0x00FFL +//RIRB_CONTROL +#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 +#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 +#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 +#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x01L +#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x02L +#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x04L +//RIRB_STATUS +#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 +#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 +#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x01L +#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x04L +//RIRB_SIZE +#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 +#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 +#define RIRB_SIZE__RIRB_SIZE_MASK 0x0003L +#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0x00F0L +//IMMEDIATE_COMMAND_OUTPUT_INTERFACE +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0x0FFFFFFFL +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xF0000000L +//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0000FFFFL +//IMMEDIATE_RESPONSE_INPUT_INTERFACE +#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 +#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xFFFFFFFFL +//IMMEDIATE_COMMAND_STATUS +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x00000001L +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x00000002L +//DMA_POSITION_LOWER_BASE_ADDRESS +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x00000001L +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007EL +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//DMA_POSITION_UPPER_BASE_ADDRESS +#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//WALL_CLOCK_COUNTER_ALIAS +#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 +#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azendpoint_azdec +//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dcn_dc_hda_azinputendpoint_azdec +//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dcn_dc_hda_azroot_azdec +//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dcn_dc_hda_azstream0_azdec +//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azstream1_azdec +//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azstream2_azdec +//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azstream3_azdec +//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azstream4_azdec +//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azstream5_azdec +//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azstream6_azdec +//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dcn_dc_hda_azstream7_azdec +//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: vga_vgaseqind +//SEQ00 +#define SEQ00__SEQ_RST0B__SHIFT 0x0 +#define SEQ00__SEQ_RST1B__SHIFT 0x1 +#define SEQ00__SEQ_RST0B_MASK 0x01L +#define SEQ00__SEQ_RST1B_MASK 0x02L +//SEQ01 +#define SEQ01__SEQ_DOT8__SHIFT 0x0 +#define SEQ01__SEQ_SHIFT2__SHIFT 0x2 +#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3 +#define SEQ01__SEQ_SHIFT4__SHIFT 0x4 +#define SEQ01__SEQ_MAXBW__SHIFT 0x5 +#define SEQ01__SEQ_DOT8_MASK 0x01L +#define SEQ01__SEQ_SHIFT2_MASK 0x04L +#define SEQ01__SEQ_PCLKBY2_MASK 0x08L +#define SEQ01__SEQ_SHIFT4_MASK 0x10L +#define SEQ01__SEQ_MAXBW_MASK 0x20L +//SEQ02 +#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0 +#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1 +#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2 +#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3 +#define SEQ02__SEQ_MAP0_EN_MASK 0x01L +#define SEQ02__SEQ_MAP1_EN_MASK 0x02L +#define SEQ02__SEQ_MAP2_EN_MASK 0x04L +#define SEQ02__SEQ_MAP3_EN_MASK 0x08L +//SEQ03 +#define SEQ03__SEQ_FONT_B1__SHIFT 0x0 +#define SEQ03__SEQ_FONT_B2__SHIFT 0x1 +#define SEQ03__SEQ_FONT_A1__SHIFT 0x2 +#define SEQ03__SEQ_FONT_A2__SHIFT 0x3 +#define SEQ03__SEQ_FONT_B0__SHIFT 0x4 +#define SEQ03__SEQ_FONT_A0__SHIFT 0x5 +#define SEQ03__SEQ_FONT_B1_MASK 0x01L +#define SEQ03__SEQ_FONT_B2_MASK 0x02L +#define SEQ03__SEQ_FONT_A1_MASK 0x04L +#define SEQ03__SEQ_FONT_A2_MASK 0x08L +#define SEQ03__SEQ_FONT_B0_MASK 0x10L +#define SEQ03__SEQ_FONT_A0_MASK 0x20L +//SEQ04 +#define SEQ04__SEQ_256K__SHIFT 0x1 +#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2 +#define SEQ04__SEQ_CHAIN__SHIFT 0x3 +#define SEQ04__SEQ_256K_MASK 0x02L +#define SEQ04__SEQ_ODDEVEN_MASK 0x04L +#define SEQ04__SEQ_CHAIN_MASK 0x08L + + +// addressBlock: vga_vgacrtind +//CRT00 +#define CRT00__H_TOTAL__SHIFT 0x0 +#define CRT00__H_TOTAL_MASK 0xFFL +//CRT01 +#define CRT01__H_DISP_END__SHIFT 0x0 +#define CRT01__H_DISP_END_MASK 0xFFL +//CRT02 +#define CRT02__H_BLANK_START__SHIFT 0x0 +#define CRT02__H_BLANK_START_MASK 0xFFL +//CRT03 +#define CRT03__H_BLANK_END__SHIFT 0x0 +#define CRT03__H_DE_SKEW__SHIFT 0x5 +#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7 +#define CRT03__H_BLANK_END_MASK 0x1FL +#define CRT03__H_DE_SKEW_MASK 0x60L +#define CRT03__CR10CR11_R_DIS_B_MASK 0x80L +//CRT04 +#define CRT04__H_SYNC_START__SHIFT 0x0 +#define CRT04__H_SYNC_START_MASK 0xFFL +//CRT05 +#define CRT05__H_SYNC_END__SHIFT 0x0 +#define CRT05__H_SYNC_SKEW__SHIFT 0x5 +#define CRT05__H_BLANK_END_B5__SHIFT 0x7 +#define CRT05__H_SYNC_END_MASK 0x1FL +#define CRT05__H_SYNC_SKEW_MASK 0x60L +#define CRT05__H_BLANK_END_B5_MASK 0x80L +//CRT06 +#define CRT06__V_TOTAL__SHIFT 0x0 +#define CRT06__V_TOTAL_MASK 0xFFL +//CRT07 +#define CRT07__V_TOTAL_B8__SHIFT 0x0 +#define CRT07__V_DISP_END_B8__SHIFT 0x1 +#define CRT07__V_SYNC_START_B8__SHIFT 0x2 +#define CRT07__V_BLANK_START_B8__SHIFT 0x3 +#define CRT07__LINE_CMP_B8__SHIFT 0x4 +#define CRT07__V_TOTAL_B9__SHIFT 0x5 +#define CRT07__V_DISP_END_B9__SHIFT 0x6 +#define CRT07__V_SYNC_START_B9__SHIFT 0x7 +#define CRT07__V_TOTAL_B8_MASK 0x01L +#define CRT07__V_DISP_END_B8_MASK 0x02L +#define CRT07__V_SYNC_START_B8_MASK 0x04L +#define CRT07__V_BLANK_START_B8_MASK 0x08L +#define CRT07__LINE_CMP_B8_MASK 0x10L +#define CRT07__V_TOTAL_B9_MASK 0x20L +#define CRT07__V_DISP_END_B9_MASK 0x40L +#define CRT07__V_SYNC_START_B9_MASK 0x80L +//CRT08 +#define CRT08__ROW_SCAN_START__SHIFT 0x0 +#define CRT08__BYTE_PAN__SHIFT 0x5 +#define CRT08__ROW_SCAN_START_MASK 0x1FL +#define CRT08__BYTE_PAN_MASK 0x60L +//CRT09 +#define CRT09__MAX_ROW_SCAN__SHIFT 0x0 +#define CRT09__V_BLANK_START_B9__SHIFT 0x5 +#define CRT09__LINE_CMP_B9__SHIFT 0x6 +#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7 +#define CRT09__MAX_ROW_SCAN_MASK 0x1FL +#define CRT09__V_BLANK_START_B9_MASK 0x20L +#define CRT09__LINE_CMP_B9_MASK 0x40L +#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80L +//CRT0A +#define CRT0A__CURSOR_START__SHIFT 0x0 +#define CRT0A__CURSOR_DISABLE__SHIFT 0x5 +#define CRT0A__CURSOR_START_MASK 0x1FL +#define CRT0A__CURSOR_DISABLE_MASK 0x20L +//CRT0B +#define CRT0B__CURSOR_END__SHIFT 0x0 +#define CRT0B__CURSOR_SKEW__SHIFT 0x5 +#define CRT0B__CURSOR_END_MASK 0x1FL +#define CRT0B__CURSOR_SKEW_MASK 0x60L +//CRT0C +#define CRT0C__DISP_START__SHIFT 0x0 +#define CRT0C__DISP_START_MASK 0xFFL +//CRT0D +#define CRT0D__DISP_START__SHIFT 0x0 +#define CRT0D__DISP_START_MASK 0xFFL +//CRT0E +#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0 +#define CRT0E__CURSOR_LOC_HI_MASK 0xFFL +//CRT0F +#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0 +#define CRT0F__CURSOR_LOC_LO_MASK 0xFFL +//CRT10 +#define CRT10__V_SYNC_START__SHIFT 0x0 +#define CRT10__V_SYNC_START_MASK 0xFFL +//CRT11 +#define CRT11__V_SYNC_END__SHIFT 0x0 +#define CRT11__V_INTR_CLR__SHIFT 0x4 +#define CRT11__V_INTR_EN__SHIFT 0x5 +#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6 +#define CRT11__C0T7_WR_ONLY__SHIFT 0x7 +#define CRT11__V_SYNC_END_MASK 0x0FL +#define CRT11__V_INTR_CLR_MASK 0x10L +#define CRT11__V_INTR_EN_MASK 0x20L +#define CRT11__SEL5_REFRESH_CYC_MASK 0x40L +#define CRT11__C0T7_WR_ONLY_MASK 0x80L +//CRT12 +#define CRT12__V_DISP_END__SHIFT 0x0 +#define CRT12__V_DISP_END_MASK 0xFFL +//CRT13 +#define CRT13__DISP_PITCH__SHIFT 0x0 +#define CRT13__DISP_PITCH_MASK 0xFFL +//CRT14 +#define CRT14__UNDRLN_LOC__SHIFT 0x0 +#define CRT14__ADDR_CNT_BY4__SHIFT 0x5 +#define CRT14__DOUBLE_WORD__SHIFT 0x6 +#define CRT14__UNDRLN_LOC_MASK 0x1FL +#define CRT14__ADDR_CNT_BY4_MASK 0x20L +#define CRT14__DOUBLE_WORD_MASK 0x40L +//CRT15 +#define CRT15__V_BLANK_START__SHIFT 0x0 +#define CRT15__V_BLANK_START_MASK 0xFFL +//CRT16 +#define CRT16__V_BLANK_END__SHIFT 0x0 +#define CRT16__V_BLANK_END_MASK 0xFFL +//CRT17 +#define CRT17__RA0_AS_A13B__SHIFT 0x0 +#define CRT17__RA1_AS_A14B__SHIFT 0x1 +#define CRT17__VCOUNT_BY2__SHIFT 0x2 +#define CRT17__ADDR_CNT_BY2__SHIFT 0x3 +#define CRT17__WRAP_A15TOA0__SHIFT 0x5 +#define CRT17__BYTE_MODE__SHIFT 0x6 +#define CRT17__CRTC_SYNC_EN__SHIFT 0x7 +#define CRT17__RA0_AS_A13B_MASK 0x01L +#define CRT17__RA1_AS_A14B_MASK 0x02L +#define CRT17__VCOUNT_BY2_MASK 0x04L +#define CRT17__ADDR_CNT_BY2_MASK 0x08L +#define CRT17__WRAP_A15TOA0_MASK 0x20L +#define CRT17__BYTE_MODE_MASK 0x40L +#define CRT17__CRTC_SYNC_EN_MASK 0x80L +//CRT18 +#define CRT18__LINE_CMP__SHIFT 0x0 +#define CRT18__LINE_CMP_MASK 0xFFL +//CRT1E +#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1 +#define CRT1E__GRPH_DEC_RD1_MASK 0x02L +//CRT1F +#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0 +#define CRT1F__GRPH_DEC_RD0_MASK 0xFFL +//CRT22 +#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0 +#define CRT22__GRPH_LATCH_DATA_MASK 0xFFL + + +// addressBlock: vga_vgagrphind +//GRA00 +#define GRA00__GRPH_SET_RESET0__SHIFT 0x0 +#define GRA00__GRPH_SET_RESET1__SHIFT 0x1 +#define GRA00__GRPH_SET_RESET2__SHIFT 0x2 +#define GRA00__GRPH_SET_RESET3__SHIFT 0x3 +#define GRA00__GRPH_SET_RESET0_MASK 0x01L +#define GRA00__GRPH_SET_RESET1_MASK 0x02L +#define GRA00__GRPH_SET_RESET2_MASK 0x04L +#define GRA00__GRPH_SET_RESET3_MASK 0x08L +//GRA01 +#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0 +#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1 +#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2 +#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3 +#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x01L +#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x02L +#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x04L +#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x08L +//GRA02 +#define GRA02__GRPH_CCOMP__SHIFT 0x0 +#define GRA02__GRPH_CCOMP_MASK 0x0FL +//GRA03 +#define GRA03__GRPH_ROTATE__SHIFT 0x0 +#define GRA03__GRPH_FN_SEL__SHIFT 0x3 +#define GRA03__GRPH_ROTATE_MASK 0x07L +#define GRA03__GRPH_FN_SEL_MASK 0x18L +//GRA04 +#define GRA04__GRPH_RMAP__SHIFT 0x0 +#define GRA04__GRPH_RMAP_MASK 0x03L +//GRA05 +#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0 +#define GRA05__GRPH_READ1__SHIFT 0x3 +#define GRA05__CGA_ODDEVEN__SHIFT 0x4 +#define GRA05__GRPH_OES__SHIFT 0x5 +#define GRA05__GRPH_PACK__SHIFT 0x6 +#define GRA05__GRPH_WRITE_MODE_MASK 0x03L +#define GRA05__GRPH_READ1_MASK 0x08L +#define GRA05__CGA_ODDEVEN_MASK 0x10L +#define GRA05__GRPH_OES_MASK 0x20L +#define GRA05__GRPH_PACK_MASK 0x40L +//GRA06 +#define GRA06__GRPH_GRAPHICS__SHIFT 0x0 +#define GRA06__GRPH_ODDEVEN__SHIFT 0x1 +#define GRA06__GRPH_ADRSEL__SHIFT 0x2 +#define GRA06__GRPH_GRAPHICS_MASK 0x01L +#define GRA06__GRPH_ODDEVEN_MASK 0x02L +#define GRA06__GRPH_ADRSEL_MASK 0x0CL +//GRA07 +#define GRA07__GRPH_XCARE0__SHIFT 0x0 +#define GRA07__GRPH_XCARE1__SHIFT 0x1 +#define GRA07__GRPH_XCARE2__SHIFT 0x2 +#define GRA07__GRPH_XCARE3__SHIFT 0x3 +#define GRA07__GRPH_XCARE0_MASK 0x01L +#define GRA07__GRPH_XCARE1_MASK 0x02L +#define GRA07__GRPH_XCARE2_MASK 0x04L +#define GRA07__GRPH_XCARE3_MASK 0x08L +//GRA08 +#define GRA08__GRPH_BMSK__SHIFT 0x0 +#define GRA08__GRPH_BMSK_MASK 0xFFL + + +// addressBlock: vga_vgaattrind +//ATTR00 +#define ATTR00__ATTR_PAL__SHIFT 0x0 +#define ATTR00__ATTR_PAL_MASK 0x3FL +//ATTR01 +#define ATTR01__ATTR_PAL__SHIFT 0x0 +#define ATTR01__ATTR_PAL_MASK 0x3FL +//ATTR02 +#define ATTR02__ATTR_PAL__SHIFT 0x0 +#define ATTR02__ATTR_PAL_MASK 0x3FL +//ATTR03 +#define ATTR03__ATTR_PAL__SHIFT 0x0 +#define ATTR03__ATTR_PAL_MASK 0x3FL +//ATTR04 +#define ATTR04__ATTR_PAL__SHIFT 0x0 +#define ATTR04__ATTR_PAL_MASK 0x3FL +//ATTR05 +#define ATTR05__ATTR_PAL__SHIFT 0x0 +#define ATTR05__ATTR_PAL_MASK 0x3FL +//ATTR06 +#define ATTR06__ATTR_PAL__SHIFT 0x0 +#define ATTR06__ATTR_PAL_MASK 0x3FL +//ATTR07 +#define ATTR07__ATTR_PAL__SHIFT 0x0 +#define ATTR07__ATTR_PAL_MASK 0x3FL +//ATTR08 +#define ATTR08__ATTR_PAL__SHIFT 0x0 +#define ATTR08__ATTR_PAL_MASK 0x3FL +//ATTR09 +#define ATTR09__ATTR_PAL__SHIFT 0x0 +#define ATTR09__ATTR_PAL_MASK 0x3FL +//ATTR0A +#define ATTR0A__ATTR_PAL__SHIFT 0x0 +#define ATTR0A__ATTR_PAL_MASK 0x3FL +//ATTR0B +#define ATTR0B__ATTR_PAL__SHIFT 0x0 +#define ATTR0B__ATTR_PAL_MASK 0x3FL +//ATTR0C +#define ATTR0C__ATTR_PAL__SHIFT 0x0 +#define ATTR0C__ATTR_PAL_MASK 0x3FL +//ATTR0D +#define ATTR0D__ATTR_PAL__SHIFT 0x0 +#define ATTR0D__ATTR_PAL_MASK 0x3FL +//ATTR0E +#define ATTR0E__ATTR_PAL__SHIFT 0x0 +#define ATTR0E__ATTR_PAL_MASK 0x3FL +//ATTR0F +#define ATTR0F__ATTR_PAL__SHIFT 0x0 +#define ATTR0F__ATTR_PAL_MASK 0x3FL +//ATTR10 +#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0 +#define ATTR10__ATTR_MONO_EN__SHIFT 0x1 +#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2 +#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3 +#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5 +#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6 +#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7 +#define ATTR10__ATTR_GRPH_MODE_MASK 0x01L +#define ATTR10__ATTR_MONO_EN_MASK 0x02L +#define ATTR10__ATTR_LGRPH_EN_MASK 0x04L +#define ATTR10__ATTR_BLINK_EN_MASK 0x08L +#define ATTR10__ATTR_PANTOPONLY_MASK 0x20L +#define ATTR10__ATTR_PCLKBY2_MASK 0x40L +#define ATTR10__ATTR_CSEL_EN_MASK 0x80L +//ATTR11 +#define ATTR11__ATTR_OVSC__SHIFT 0x0 +#define ATTR11__ATTR_OVSC_MASK 0xFFL +//ATTR12 +#define ATTR12__ATTR_MAP_EN__SHIFT 0x0 +#define ATTR12__ATTR_VSMUX__SHIFT 0x4 +#define ATTR12__ATTR_MAP_EN_MASK 0x0FL +#define ATTR12__ATTR_VSMUX_MASK 0x30L +//ATTR13 +#define ATTR13__ATTR_PPAN__SHIFT 0x0 +#define ATTR13__ATTR_PPAN_MASK 0x0FL +//ATTR14 +#define ATTR14__ATTR_CSEL1__SHIFT 0x0 +#define ATTR14__ATTR_CSEL2__SHIFT 0x2 +#define ATTR14__ATTR_CSEL1_MASK 0x03L +#define ATTR14__ATTR_CSEL2_MASK 0x0CL + + +// addressBlock: azendpoint_f2codecind +//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007FL +//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000FC00L +//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x00000003L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZALIA_F2_CODEC_PIN_CONTROL_HBR +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xFFFFFFFFL + + +// addressBlock: azendpoint_descriptorind +//AUDIO_DESCRIPTOR0 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR1 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR2 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR3 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR4 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR5 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR6 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR7 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR8 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR9 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR10 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR11 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR12 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR13 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L + + +// addressBlock: azendpoint_sinkinfoind +//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000FFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000FFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xFFFFFFFFL +//SINK_DESCRIPTION0 +#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION1 +#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION2 +#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION3 +#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION4 +#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION5 +#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION6 +#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION7 +#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION8 +#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION9 +#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION10 +#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION11 +#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION12 +#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION13 +#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION14 +#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION15 +#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION16 +#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION17 +#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000FFL + + +// addressBlock: azf0controller_azinputcrc0resultind +//AZALIA_INPUT_CRC0_CHANNEL0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL1 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL2 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL3 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL4 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL5 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL6 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL7 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azinputcrc1resultind +//AZALIA_INPUT_CRC1_CHANNEL0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL1 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL2 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL3 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL4 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL5 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL6 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL7 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azcrc0resultind +//AZALIA_CRC0_CHANNEL0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL1 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL2 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL3 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL4 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL5 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL6 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL7 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azcrc1resultind +//AZALIA_CRC1_CHANNEL0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL1 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL2 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL3 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL4 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL5 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL6 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL7 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azinputendpoint_f2codecind +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L + + +// addressBlock: azroot_f2codecind +//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L + + +// addressBlock: azf0stream0_streamind +//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream1_streamind +//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream2_streamind +//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream3_streamind +//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream4_streamind +//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream5_streamind +//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream6_streamind +//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream7_streamind +//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream8_streamind +//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream9_streamind +//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream10_streamind +//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream11_streamind +//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream12_streamind +//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream13_streamind +//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream14_streamind +//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream15_streamind +//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0endpoint0_endpointind +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint1_endpointind +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint2_endpointind +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint3_endpointind +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint4_endpointind +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint5_endpointind +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint6_endpointind +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint7_endpointind +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0inputendpoint0_inputendpointind +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint1_inputendpointind +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint2_inputendpointind +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint3_inputendpointind +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint4_inputendpointind +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint5_inputendpointind +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint6_inputendpointind +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint7_inputendpointind +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: c20_phy_cr0_rdpcspipecrind +//C20_PHY_CR0_SUP_DIG_IDCODE_LO +#define C20_PHY_CR0_SUP_DIG_IDCODE_LO__VAL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_IDCODE_LO__VAL_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_IDCODE_HI +#define C20_PHY_CR0_SUP_DIG_IDCODE_HI__VAL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_IDCODE_HI__VAL_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0 +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_MASK 0x01C0L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1 +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_MASK 0x0003L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_MASK 0x0018L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN +#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN +#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN +#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x0003L +#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_MASK 0x0038L +#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV_MASK 0x001CL +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL_MASK 0x0060L +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK 0x0E00L +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS_MASK 0x4000L +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1 +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD_MASK 0x3000L +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_OVRD_IN +#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN +#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK 0x03E0L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_1 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_2 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_3 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_4 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_5 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_6 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV_MASK 0x001CL +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL_MASK 0x0060L +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK 0x0700L +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_MASK 0x007FL +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_MASK 0x7F00L +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_MASK 0x007FL +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_MASK 0x7F00L +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_MASK 0x0003L +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_MASK 0x0018L +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK 0x03E0L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_2 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_3 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_4 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_5 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_6 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_MASK 0x7C00L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN +#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x001FL +#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x01C0L +#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV_MASK 0x000EL +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV_MASK 0x0030L +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0380L +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD_MASK 0x3000L +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_1 +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_ASIC_IN +#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN +#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK 0x00F8L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_1 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_2 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_3 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_4 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_5 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_6 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV_MASK 0x000EL +#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV_MASK 0x0030L +#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK 0x01C0L +#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS_MASK 0x007FL +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_MASK 0x3F80L +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS_MASK 0x007FL +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_MASK 0x3F80L +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I_MASK 0x0003L +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO_MASK 0x000CL +#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK 0x00F8L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_2 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_3 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_4 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_5 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_6 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN +#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN +#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x0600L +#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK 0x3800L +#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_ASIC_IN_0 +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__PHY_RESET__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_USE_PAD__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__TEST_BURNIN__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RTUNE_REQ__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RES_REQ_IN__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RES_ACK_IN__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__BG_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_RANGE__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__PHY_RESET_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_USE_PAD_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__TEST_BURNIN_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RTUNE_REQ_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RES_REQ_IN_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RES_ACK_IN_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__BG_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_RANGE_MASK 0x3800L +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE_MASK 0x4000L +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_ASIC_IN_1 +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__SUP_MISC__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__SUP_MISC_MASK 0x00FFL +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL_MASK 0x0C00L +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL_MASK 0x3000L +#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_ASIC_OUT_0 +#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__MPLLA_STATE__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RTUNE_ACK__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__DTB_OUT__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__MPLLA_STATE_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RTUNE_ACK_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__DTB_OUT_MASK 0x00C0L +#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN +#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x001FL +#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00E0L +#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET_MASK 0x3E00L +#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN +#define C20_PHY_CR0_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR0_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN +#define C20_PHY_CR0_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR0_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL_MASK 0x01F0L +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE_MASK 0x007CL +#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG +#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK 0x0038L +#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_SUP_DIG_RTUNE_STAT +#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__STAT__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RTUNE_STATE__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__STAT_MASK 0x03FFL +#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RTUNE_STATE_MASK 0x1C00L +#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE_MASK 0x6000L +#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_RTUNE_RX_SET_VAL +#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x003FL +#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL +#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x03FFL +#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL +#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x03FFL +#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_RTUNE_RX_STAT +#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x003FL +#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_STAT +#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x03FFL +#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_STAT +#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x03FFL +#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_0 +#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG_MASK 0x03FFL +#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_1 +#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN_MASK 0x03FFL +#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_RTUNE_FAST_FLAGS +#define C20_PHY_CR0_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK 0x01FFL +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK 0x01FFL +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK 0x00FFL +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 +#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK 0x001FL +#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE_MASK 0x000CL +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE_MASK 0x0030L +#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT_MASK 0x000FL +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE_MASK 0x7F80L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK 0x03E0L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE_MASK 0x3C00L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME_MASK 0x03FFL +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME_MASK 0x3C00L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME_MASK 0x07FFL +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME_MASK 0xF800L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME_MASK 0x001FL +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME_MASK 0x03E0L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME_MASK 0x007FL +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME_MASK 0x0F80L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL_MASK 0x0F00L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP_MASK 0x0300L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG_MASK 0x0C00L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0_MASK 0x00FFL +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0_MASK 0xFF00L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1_MASK 0x00FFL +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1_MASK 0xFF00L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2_MASK 0x00FFL +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2_MASK 0xFF00L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3_MASK 0x00FFL +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3_MASK 0xFF00L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME_MASK 0x03FFL +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME_MASK 0x07FFL +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME_MASK 0x03FFL +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME_MASK 0x03FFL +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME_MASK 0x007FL +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_FRAC_OUT +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_SSC_RAMP +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE_MASK 0x007CL +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK 0x03E0L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC_MASK 0x4000L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME_MASK 0x00FFL +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME_MASK 0x3F00L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME_MASK 0x00FFL +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME_MASK 0xFF00L +//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME_MASK 0x003FL +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME_MASK 0x0FC0L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME_MASK 0x003FL +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME_MASK 0x0FC0L +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS_MASK 0x001FL +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME_MASK 0x007FL +#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_FRAC_OUT +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_SSC_RAMP +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT_MASK 0x01F0L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL_MASK 0x0030L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE_MASK 0x3000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT +#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_MASK 0x000CL +#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE_MASK 0x0180L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE_MASK 0x7E00L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL_MASK 0x0006L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL_MASK 0x0018L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC_MASK 0x003FL +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT_MASK 0xFFC0L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK 0x4000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC_MASK 0x003FL +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT_MASK 0xFFC0L +//C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT +#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x000CL +#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x3FF0L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_MASK 0x00FFL +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_MASK 0x1E00L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST_MASK 0x0060L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST_MASK 0x1800L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST_MASK 0x0003L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX_MASK 0x000CL +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0_MASK 0x0030L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6_MASK 0x00C0L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0_MASK 0x7F00L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5_MASK 0x0060L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN_MASK 0x0F00L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN_MASK 0xF000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE_MASK 0x0003L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE_MASK 0x000CL +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM_MASK 0x0030L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR_MASK 0x00C0L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9_MASK 0x7E00L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0_MASK 0x007FL +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF_MASK 0x0180L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR_MASK 0x7E00L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL_MASK 0x00C0L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET_MASK 0x4000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16_MASK 0x003FL +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22_MASK 0x3F80L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW_MASK 0x0FF8L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG_MASK 0x6000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0_MASK 0x00FFL +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV_MASK 0x000CL +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6_MASK 0x00C0L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV_MASK 0x4000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP_MASK 0x1F00L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13_MASK 0x6000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE__SHIFT 0xf +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ_MASK 0x0006L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED_MASK 0x00F0L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H_MASK 0x0600L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP_MASK 0x4000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE_MASK 0x8000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_MASK 0x001CL +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5_MASK 0x00E0L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8_MASK 0x0F00L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN__SHIFT 0x5 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF_MASK 0x0004L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS_MASK 0x0008L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH_MASK 0x0010L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN_MASK 0x0020L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING_MASK 0x0600L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK_MASK 0x2000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED__SHIFT 0x7 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X__SHIFT 0x9 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N__SHIFT 0xb +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER__SHIFT 0xd +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR_MASK 0x000CL +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2_MASK 0x0030L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP_MASK 0x0040L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_MASK 0x0080L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2_MASK 0x0100L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X_MASK 0x0200L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD_MASK 0x0400L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N_MASK 0x0800L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC_MASK 0x1000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER_MASK 0xE000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF__SHIFT 0x3 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH__SHIFT 0xa +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF_MASK 0x0007L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF_MASK 0x0038L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL_MASK 0x00C0L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0_MASK 0x0300L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH_MASK 0x0C00L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2_MASK 0x3000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG__SHIFT 0x1 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC__SHIFT 0x2 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL__SHIFT 0x4 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP__SHIFT 0x6 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK__SHIFT 0x8 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN__SHIFT 0xc +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST__SHIFT 0xe +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0_MASK 0x0001L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG_MASK 0x0002L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC_MASK 0x000CL +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL_MASK 0x0030L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP_MASK 0x00C0L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK_MASK 0x0F00L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN_MASK 0x3000L +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST_MASK 0xC000L +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_CMN_CTL +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWCMN_DIG_CMN_CLK_GATE_CTL +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE__SHIFT 0x4 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE__SHIFT 0x8 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE__SHIFT 0xc +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_MASK 0x0010L +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_MASK 0x0100L +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_MASK 0x0400L +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE_MASK 0x1000L +#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME__SHIFT 0x6 +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME_MASK 0x003FL +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME_MASK 0x03C0L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_CTRL +#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE_MASK 0x000FL +#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ADDR +#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ADDR__ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ADDR__ADDR_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_DATA +#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_DATA__DATA__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_DATA__DATA_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_FLAGS +#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ACCUM +#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ACCUM__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ACCUM__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_MPLL_IN +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE_MASK 0x0004L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWCMN_DIG_FW_PWRUP_DONE +#define C20_PHY_CR0_RAWCMN_DIG_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWCMN_DIG_STATIC_CONFIG_STATUS +#define C20_PHY_CR0_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS +#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL__SHIFT 0x7 +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL_MASK 0x0003L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL_MASK 0x0180L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWCMN_DIG_CONFIG_MASTER_VERSION +#define C20_PHY_CR0_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0 +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID__SHIFT 0x8 +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID_MASK 0x0100L +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1 +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID__SHIFT 0x8 +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID_MASK 0x0100L +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2 +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID__SHIFT 0x8 +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID_MASK 0x0100L +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3 +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID__SHIFT 0x8 +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID_MASK 0x0100L +#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL +#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0 +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1 +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2 +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0 +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL__SHIFT 0x8 +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC_MASK 0x00FFL +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL_MASK 0x0700L +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1 +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET__SHIFT 0x5 +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL_MASK 0x001FL +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET_MASK 0x3FE0L +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2 +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET__SHIFT 0x5 +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET_MASK 0x001FL +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET_MASK 0x3FE0L +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_3 +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN__SHIFT 0xf +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN_MASK 0x8000L +//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV__SHIFT 0x8 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV__SHIFT 0xb +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS__SHIFT 0xd +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD__SHIFT 0xe +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER_MASK 0x00FFL +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV_MASK 0x0700L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV_MASK 0x1800L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS_MASK 0x2000L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD_MASK 0xC000L +//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_2 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_3 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_4 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_5 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT 0x4 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT 0x9 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL__SHIFT 0xd +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB_MASK 0x000FL +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK 0x01F0L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD_MASK 0x0200L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV_MASK 0x1C00L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL_MASK 0x2000L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_7 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_8 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_9 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV__SHIFT 0xd +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV_MASK 0xE000L +//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV__SHIFT 0x8 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER_MASK 0x00FFL +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV_MASK 0x0300L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE_MASK 0x7C00L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP__SHIFT 0x7 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO__SHIFT 0xe +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT_MASK 0x007FL +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP_MASK 0x3F80L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO_MASK 0xC000L +//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS__SHIFT 0x7 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I__SHIFT 0xe +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS_MASK 0x007FL +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS_MASK 0x3F80L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I_MASK 0xC000L +//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_4 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_5 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT 0x4 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT 0x9 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB_MASK 0x000FL +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK 0x01F0L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD_MASK 0x0200L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV_MASK 0x1C00L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_7 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_8 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_9 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV__SHIFT 0x3 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV_MASK 0x0007L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV_MASK 0x0018L +#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0__SHIFT 0xc +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0_MASK 0x0FFFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0_MASK 0x1000L +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1__SHIFT 0xc +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1_MASK 0x0FFFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1_MASK 0x1000L +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2__SHIFT 0xc +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2_MASK 0x0FFFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2_MASK 0x1000L +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3__SHIFT 0xc +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3_MASK 0x0FFFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3_MASK 0x1000L +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_DONE +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0__SHIFT 0xc +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0_MASK 0x0FFFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0_MASK 0x1000L +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1__SHIFT 0xc +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1_MASK 0x0FFFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1_MASK 0x1000L +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2__SHIFT 0xc +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2_MASK 0x0FFFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2_MASK 0x1000L +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3__SHIFT 0xc +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3_MASK 0x0FFFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3_MASK 0x1000L +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_DONE +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE_MASK 0x0FFFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE_MASK 0x0FFFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_IN_RECAL +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_IN_RECAL +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO_MASK 0x0004L +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL__SHIFT 0x4 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK__SHIFT 0x5 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL_MASK 0x0010L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK_MASK 0x0020L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ__SHIFT 0x3 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ_MASK 0x0008L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL +#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL +#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS +#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS +#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK 0x003FL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK 0x03FFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0_MASK 0x03FFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK 0x003FL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK 0x03FFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1_MASK 0x03FFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK 0x003FL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK 0x03FFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2_MASK 0x03FFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_3 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK 0x003FL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK 0x03FFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3_MASK 0x03FFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_4 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK 0x003FL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK 0x03FFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4_MASK 0x03FFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_5 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK 0x003FL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK 0x03FFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5_MASK 0x03FFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_6 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK 0x003FL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK 0x03FFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6_MASK 0x03FFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_7 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK 0x003FL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK 0x03FFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7_MASK 0x03FFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL_MASK 0x000CL +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL_MASK 0x0060L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS__SHIFT 0x3 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE_MASK 0x0004L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS_MASK 0x0018L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OUT +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_0__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_0__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_1__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_1__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_AON_RAW_VERSION +#define C20_PHY_CR0_RAWCMN_DIG_AON_RAW_VERSION__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RAW_VERSION__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL_MASK 0x0004L +#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_EOF_ADDR +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_BOC_ADDR +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN_MASK 0xFF00L +//C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK__SHIFT 0x1 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE__SHIFT 0x5 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE__SHIFT 0x6 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ__SHIFT 0x7 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ__SHIFT 0x8 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL__SHIFT 0x9 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT__SHIFT 0xa +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT__SHIFT 0xb +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL__SHIFT 0xc +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF__SHIFT 0xd +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW__SHIFT 0xe +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK_MASK 0x0002L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE_MASK 0x0020L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE_MASK 0x0040L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ_MASK 0x0080L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ_MASK 0x0100L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL_MASK 0x0200L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT_MASK 0x0400L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT_MASK 0x0800L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL_MASK 0x1000L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF_MASK 0x2000L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW_MASK 0x4000L +#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWCMN_DIG_AON_METADATA_LOCATION +#define C20_PHY_CR0_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION_MASK 0x7FFFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_MASK 0x7FFFL +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE0_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE0_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL +#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR0_LANE0_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR0_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL +#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL +#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE0_DIG_RX_LBERT_ERR +#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ +#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE1_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE1_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL +#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR0_LANE1_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR0_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL +#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL +#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE1_DIG_RX_LBERT_ERR +#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ +#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE2_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE2_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL +#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR0_LANE2_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR0_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL +#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL +#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE2_DIG_RX_LBERT_ERR +#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ +#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE3_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE3_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL +#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR0_LANE3_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR0_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL +#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL +#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE3_DIG_RX_LBERT_ERR +#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ +#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_SUP +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE0_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_SUP +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE1_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_SUP +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE2_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_SUP +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANE3_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_DONE +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CODE +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_TX_IN_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_RTRIM +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_DONE +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CODE +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_TX_IN_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_RTRIM +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_DONE +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CODE +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_TX_IN_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_RTRIM +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_DONE +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CODE +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_TX_IN_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_RTRIM +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANEX_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANEX_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL +#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR0_LANEX_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR0_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL +#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL +#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANEX_DIG_RX_LBERT_ERR +#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ +#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_SUP +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEX_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_DONE +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CODE +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_TX_IN_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_RTRIM +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL + + +// addressBlock: c20_phy_lane0_pipe0_rdpcspipemsgbusind +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK 0x01L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK 0x02L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK 0x04L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK 0x08L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK 0x10L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK 0x7FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK 0x80L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK 0xFFL +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK 0x01L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK 0x02L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK 0x01L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK 0x02L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK 0x04L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK 0xF8L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK 0x01L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK 0x02L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK 0x01L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK 0xFEL +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK 0x01L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK 0x1EL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK 0x20L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK 0x40L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK 0x80L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK 0x03L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK 0x03L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK 0xFFL +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK 0x01L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK 0x02L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK 0x04L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK 0xF8L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK 0x3FL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x03L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x0CL +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x30L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK 0x10L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK 0x01L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK 0x02L +#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK 0xFCL + + +// addressBlock: c20_phy_lane1_pipe0_rdpcspipemsgbusind +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK 0x01L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK 0x02L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK 0x04L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK 0x08L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK 0x10L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK 0x7FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK 0x80L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK 0xFFL +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK 0x01L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK 0x02L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK 0x01L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK 0x02L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK 0x04L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK 0xF8L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK 0x01L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK 0x02L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK 0x01L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK 0xFEL +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK 0x01L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK 0x1EL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK 0x20L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK 0x40L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK 0x80L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK 0x03L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK 0x03L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK 0xFFL +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK 0x01L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK 0x02L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK 0x04L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK 0xF8L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK 0x3FL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x03L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x0CL +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x30L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK 0x10L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK 0x01L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK 0x02L +#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK 0xFCL + + +// addressBlock: c20_phy_cr1_rdpcspipecrind +//C20_PHY_CR1_SUP_DIG_IDCODE_LO +#define C20_PHY_CR1_SUP_DIG_IDCODE_LO__VAL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_IDCODE_LO__VAL_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_IDCODE_HI +#define C20_PHY_CR1_SUP_DIG_IDCODE_HI__VAL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_IDCODE_HI__VAL_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0 +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_MASK 0x01C0L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1 +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_MASK 0x0003L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_MASK 0x0018L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN +#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN +#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN +#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x0003L +#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_MASK 0x0038L +#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV_MASK 0x001CL +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL_MASK 0x0060L +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK 0x0E00L +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS_MASK 0x4000L +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1 +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD_MASK 0x3000L +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_OVRD_IN +#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN +#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK 0x03E0L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_1 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_2 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_3 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_4 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_5 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_6 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV_MASK 0x001CL +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL_MASK 0x0060L +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK 0x0700L +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_MASK 0x007FL +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_MASK 0x7F00L +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_MASK 0x007FL +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_MASK 0x7F00L +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_MASK 0x0003L +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_MASK 0x0018L +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK 0x03E0L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_2 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_3 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_4 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_5 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_6 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_MASK 0x7C00L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN +#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x001FL +#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x01C0L +#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV_MASK 0x000EL +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV_MASK 0x0030L +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0380L +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD_MASK 0x3000L +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_1 +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_ASIC_IN +#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN +#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK 0x00F8L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_1 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_2 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_3 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_4 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_5 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_6 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV_MASK 0x000EL +#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV_MASK 0x0030L +#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK 0x01C0L +#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS_MASK 0x007FL +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_MASK 0x3F80L +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS_MASK 0x007FL +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_MASK 0x3F80L +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I_MASK 0x0003L +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO_MASK 0x000CL +#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK 0x00F8L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_2 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_3 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_4 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_5 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_6 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN +#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN +#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x0600L +#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK 0x3800L +#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_ASIC_IN_0 +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__PHY_RESET__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_USE_PAD__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__TEST_BURNIN__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RTUNE_REQ__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RES_REQ_IN__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RES_ACK_IN__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__BG_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_RANGE__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__PHY_RESET_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_USE_PAD_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__TEST_BURNIN_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RTUNE_REQ_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RES_REQ_IN_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RES_ACK_IN_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__BG_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_RANGE_MASK 0x3800L +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE_MASK 0x4000L +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_ASIC_IN_1 +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__SUP_MISC__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__SUP_MISC_MASK 0x00FFL +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL_MASK 0x0C00L +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL_MASK 0x3000L +#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_ASIC_OUT_0 +#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__MPLLA_STATE__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RTUNE_ACK__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__DTB_OUT__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__MPLLA_STATE_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RTUNE_ACK_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__DTB_OUT_MASK 0x00C0L +#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN +#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x001FL +#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00E0L +#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET_MASK 0x3E00L +#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN +#define C20_PHY_CR1_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR1_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN +#define C20_PHY_CR1_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR1_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL_MASK 0x01F0L +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE_MASK 0x007CL +#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG +#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK 0x0038L +#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_SUP_DIG_RTUNE_STAT +#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__STAT__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RTUNE_STATE__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__STAT_MASK 0x03FFL +#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RTUNE_STATE_MASK 0x1C00L +#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE_MASK 0x6000L +#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_RTUNE_RX_SET_VAL +#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x003FL +#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL +#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x03FFL +#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL +#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x03FFL +#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_RTUNE_RX_STAT +#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x003FL +#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_STAT +#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x03FFL +#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_STAT +#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x03FFL +#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_0 +#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG_MASK 0x03FFL +#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_1 +#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN_MASK 0x03FFL +#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_RTUNE_FAST_FLAGS +#define C20_PHY_CR1_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK 0x01FFL +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK 0x01FFL +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK 0x00FFL +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 +#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK 0x001FL +#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE_MASK 0x000CL +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE_MASK 0x0030L +#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT_MASK 0x000FL +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE_MASK 0x7F80L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK 0x03E0L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE_MASK 0x3C00L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME_MASK 0x03FFL +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME_MASK 0x3C00L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME_MASK 0x07FFL +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME_MASK 0xF800L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME_MASK 0x001FL +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME_MASK 0x03E0L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME_MASK 0x007FL +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME_MASK 0x0F80L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL_MASK 0x0F00L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP_MASK 0x0300L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG_MASK 0x0C00L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0_MASK 0x00FFL +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0_MASK 0xFF00L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1_MASK 0x00FFL +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1_MASK 0xFF00L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2_MASK 0x00FFL +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2_MASK 0xFF00L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3_MASK 0x00FFL +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3_MASK 0xFF00L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME_MASK 0x03FFL +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME_MASK 0x07FFL +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME_MASK 0x03FFL +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME_MASK 0x03FFL +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME_MASK 0x007FL +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_FRAC_OUT +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_SSC_RAMP +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE_MASK 0x007CL +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK 0x03E0L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC_MASK 0x4000L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME_MASK 0x00FFL +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME_MASK 0x3F00L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME_MASK 0x00FFL +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME_MASK 0xFF00L +//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME_MASK 0x003FL +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME_MASK 0x0FC0L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME_MASK 0x003FL +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME_MASK 0x0FC0L +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS_MASK 0x001FL +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME_MASK 0x007FL +#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_FRAC_OUT +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_SSC_RAMP +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT_MASK 0x01F0L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL_MASK 0x0030L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE_MASK 0x3000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT +#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_MASK 0x000CL +#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE_MASK 0x0180L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE_MASK 0x7E00L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL_MASK 0x0006L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL_MASK 0x0018L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC_MASK 0x003FL +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT_MASK 0xFFC0L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK 0x4000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC_MASK 0x003FL +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT_MASK 0xFFC0L +//C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT +#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x000CL +#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x3FF0L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_MASK 0x00FFL +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_MASK 0x1E00L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST_MASK 0x0060L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST_MASK 0x1800L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST_MASK 0x0003L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX_MASK 0x000CL +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0_MASK 0x0030L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6_MASK 0x00C0L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0_MASK 0x7F00L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5_MASK 0x0060L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN_MASK 0x0F00L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN_MASK 0xF000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE_MASK 0x0003L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE_MASK 0x000CL +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM_MASK 0x0030L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR_MASK 0x00C0L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9_MASK 0x7E00L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0_MASK 0x007FL +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF_MASK 0x0180L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR_MASK 0x7E00L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL_MASK 0x00C0L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET_MASK 0x4000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16_MASK 0x003FL +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22_MASK 0x3F80L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW_MASK 0x0FF8L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG_MASK 0x6000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0_MASK 0x00FFL +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV_MASK 0x000CL +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6_MASK 0x00C0L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV_MASK 0x4000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP_MASK 0x1F00L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13_MASK 0x6000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE__SHIFT 0xf +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ_MASK 0x0006L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED_MASK 0x00F0L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H_MASK 0x0600L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP_MASK 0x4000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE_MASK 0x8000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_MASK 0x001CL +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5_MASK 0x00E0L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8_MASK 0x0F00L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN__SHIFT 0x5 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF_MASK 0x0004L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS_MASK 0x0008L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH_MASK 0x0010L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN_MASK 0x0020L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING_MASK 0x0600L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK_MASK 0x2000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED__SHIFT 0x7 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X__SHIFT 0x9 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N__SHIFT 0xb +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER__SHIFT 0xd +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR_MASK 0x000CL +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2_MASK 0x0030L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP_MASK 0x0040L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_MASK 0x0080L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2_MASK 0x0100L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X_MASK 0x0200L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD_MASK 0x0400L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N_MASK 0x0800L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC_MASK 0x1000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER_MASK 0xE000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF__SHIFT 0x3 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH__SHIFT 0xa +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF_MASK 0x0007L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF_MASK 0x0038L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL_MASK 0x00C0L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0_MASK 0x0300L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH_MASK 0x0C00L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2_MASK 0x3000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG__SHIFT 0x1 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC__SHIFT 0x2 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL__SHIFT 0x4 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP__SHIFT 0x6 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK__SHIFT 0x8 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN__SHIFT 0xc +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST__SHIFT 0xe +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0_MASK 0x0001L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG_MASK 0x0002L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC_MASK 0x000CL +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL_MASK 0x0030L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP_MASK 0x00C0L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK_MASK 0x0F00L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN_MASK 0x3000L +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST_MASK 0xC000L +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_CMN_CTL +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWCMN_DIG_CMN_CLK_GATE_CTL +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE__SHIFT 0x4 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE__SHIFT 0x8 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE__SHIFT 0xc +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_MASK 0x0010L +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_MASK 0x0100L +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_MASK 0x0400L +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE_MASK 0x1000L +#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME__SHIFT 0x6 +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME_MASK 0x003FL +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME_MASK 0x03C0L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_CTRL +#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE_MASK 0x000FL +#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ADDR +#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ADDR__ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ADDR__ADDR_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_DATA +#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_DATA__DATA__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_DATA__DATA_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_FLAGS +#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ACCUM +#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ACCUM__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ACCUM__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_MPLL_IN +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE_MASK 0x0004L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWCMN_DIG_FW_PWRUP_DONE +#define C20_PHY_CR1_RAWCMN_DIG_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWCMN_DIG_STATIC_CONFIG_STATUS +#define C20_PHY_CR1_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS +#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL__SHIFT 0x7 +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL_MASK 0x0003L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL_MASK 0x0180L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWCMN_DIG_CONFIG_MASTER_VERSION +#define C20_PHY_CR1_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0 +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID__SHIFT 0x8 +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID_MASK 0x0100L +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1 +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID__SHIFT 0x8 +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID_MASK 0x0100L +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2 +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID__SHIFT 0x8 +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID_MASK 0x0100L +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3 +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID__SHIFT 0x8 +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID_MASK 0x0100L +#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL +#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0 +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1 +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2 +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0 +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL__SHIFT 0x8 +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC_MASK 0x00FFL +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL_MASK 0x0700L +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1 +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET__SHIFT 0x5 +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL_MASK 0x001FL +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET_MASK 0x3FE0L +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2 +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET__SHIFT 0x5 +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET_MASK 0x001FL +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET_MASK 0x3FE0L +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_3 +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN__SHIFT 0xf +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN_MASK 0x8000L +//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV__SHIFT 0x8 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV__SHIFT 0xb +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS__SHIFT 0xd +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD__SHIFT 0xe +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER_MASK 0x00FFL +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV_MASK 0x0700L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV_MASK 0x1800L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS_MASK 0x2000L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD_MASK 0xC000L +//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_2 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_3 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_4 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_5 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT 0x4 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT 0x9 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL__SHIFT 0xd +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB_MASK 0x000FL +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK 0x01F0L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD_MASK 0x0200L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV_MASK 0x1C00L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL_MASK 0x2000L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_7 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_8 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_9 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV__SHIFT 0xd +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV_MASK 0xE000L +//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV__SHIFT 0x8 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER_MASK 0x00FFL +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV_MASK 0x0300L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE_MASK 0x7C00L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP__SHIFT 0x7 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO__SHIFT 0xe +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT_MASK 0x007FL +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP_MASK 0x3F80L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO_MASK 0xC000L +//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS__SHIFT 0x7 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I__SHIFT 0xe +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS_MASK 0x007FL +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS_MASK 0x3F80L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I_MASK 0xC000L +//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_4 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_5 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT 0x4 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT 0x9 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB_MASK 0x000FL +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK 0x01F0L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD_MASK 0x0200L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV_MASK 0x1C00L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_7 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_8 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_9 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV__SHIFT 0x3 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV_MASK 0x0007L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV_MASK 0x0018L +#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0__SHIFT 0xc +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0_MASK 0x0FFFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0_MASK 0x1000L +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1__SHIFT 0xc +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1_MASK 0x0FFFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1_MASK 0x1000L +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2__SHIFT 0xc +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2_MASK 0x0FFFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2_MASK 0x1000L +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3__SHIFT 0xc +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3_MASK 0x0FFFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3_MASK 0x1000L +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_DONE +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0__SHIFT 0xc +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0_MASK 0x0FFFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0_MASK 0x1000L +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1__SHIFT 0xc +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1_MASK 0x0FFFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1_MASK 0x1000L +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2__SHIFT 0xc +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2_MASK 0x0FFFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2_MASK 0x1000L +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3__SHIFT 0xc +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3_MASK 0x0FFFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3_MASK 0x1000L +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_DONE +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE_MASK 0x0FFFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE_MASK 0x0FFFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_IN_RECAL +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_IN_RECAL +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO_MASK 0x0004L +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL__SHIFT 0x4 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK__SHIFT 0x5 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL_MASK 0x0010L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK_MASK 0x0020L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ__SHIFT 0x3 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ_MASK 0x0008L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL +#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL +#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS +#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS +#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK 0x003FL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK 0x03FFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0_MASK 0x03FFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK 0x003FL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK 0x03FFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1_MASK 0x03FFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK 0x003FL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK 0x03FFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2_MASK 0x03FFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_3 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK 0x003FL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK 0x03FFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3_MASK 0x03FFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_4 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK 0x003FL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK 0x03FFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4_MASK 0x03FFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_5 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK 0x003FL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK 0x03FFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5_MASK 0x03FFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_6 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK 0x003FL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK 0x03FFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6_MASK 0x03FFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_7 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK 0x003FL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK 0x03FFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7_MASK 0x03FFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL_MASK 0x000CL +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL_MASK 0x0060L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS__SHIFT 0x3 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE_MASK 0x0004L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS_MASK 0x0018L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OUT +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_0__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_0__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_1__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_1__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_AON_RAW_VERSION +#define C20_PHY_CR1_RAWCMN_DIG_AON_RAW_VERSION__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RAW_VERSION__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL_MASK 0x0004L +#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_EOF_ADDR +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_BOC_ADDR +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN_MASK 0xFF00L +//C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK__SHIFT 0x1 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE__SHIFT 0x5 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE__SHIFT 0x6 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ__SHIFT 0x7 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ__SHIFT 0x8 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL__SHIFT 0x9 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT__SHIFT 0xa +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT__SHIFT 0xb +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL__SHIFT 0xc +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF__SHIFT 0xd +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW__SHIFT 0xe +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK_MASK 0x0002L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE_MASK 0x0020L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE_MASK 0x0040L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ_MASK 0x0080L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ_MASK 0x0100L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL_MASK 0x0200L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT_MASK 0x0400L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT_MASK 0x0800L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL_MASK 0x1000L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF_MASK 0x2000L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW_MASK 0x4000L +#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWCMN_DIG_AON_METADATA_LOCATION +#define C20_PHY_CR1_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION_MASK 0x7FFFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_MASK 0x7FFFL +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE0_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE0_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL +#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR1_LANE0_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR1_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL +#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL +#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE0_DIG_RX_LBERT_ERR +#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ +#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE1_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE1_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL +#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR1_LANE1_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR1_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL +#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL +#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE1_DIG_RX_LBERT_ERR +#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ +#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE2_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE2_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL +#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR1_LANE2_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR1_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL +#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL +#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE2_DIG_RX_LBERT_ERR +#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ +#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE3_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE3_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL +#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR1_LANE3_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR1_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL +#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL +#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE3_DIG_RX_LBERT_ERR +#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ +#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_SUP +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE0_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_SUP +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE1_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_SUP +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE2_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_SUP +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANE3_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_DONE +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CODE +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_TX_IN_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_RTRIM +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_DONE +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CODE +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_TX_IN_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_RTRIM +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_DONE +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CODE +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_TX_IN_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_RTRIM +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_DONE +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CODE +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_TX_IN_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_RTRIM +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANEX_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANEX_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL +#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR1_LANEX_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR1_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL +#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL +#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANEX_DIG_RX_LBERT_ERR +#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ +#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_SUP +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEX_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_DONE +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CODE +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_TX_IN_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_RTRIM +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL + + +// addressBlock: c20_phy_lane0_pipe1_rdpcspipemsgbusind +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK 0x01L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK 0x02L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK 0x04L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK 0x08L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK 0x10L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK 0x7FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK 0x80L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK 0xFFL +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK 0x01L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK 0x02L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK 0x01L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK 0x02L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK 0x04L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK 0xF8L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK 0x01L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK 0x02L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK 0x01L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK 0xFEL +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK 0x01L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK 0x1EL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK 0x20L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK 0x40L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK 0x80L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK 0x03L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK 0x03L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK 0xFFL +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK 0x01L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK 0x02L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK 0x04L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK 0xF8L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK 0x3FL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x03L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x0CL +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x30L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK 0x10L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK 0x01L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK 0x02L +#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK 0xFCL + + +// addressBlock: c20_phy_lane1_pipe1_rdpcspipemsgbusind +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK 0x01L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK 0x02L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK 0x04L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK 0x08L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK 0x10L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK 0x7FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK 0x80L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK 0xFFL +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK 0x01L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK 0x02L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK 0x01L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK 0x02L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK 0x04L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK 0xF8L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK 0x01L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK 0x02L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK 0x01L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK 0xFEL +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK 0x01L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK 0x1EL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK 0x20L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK 0x40L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK 0x80L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK 0x03L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK 0x03L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK 0xFFL +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK 0x01L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK 0x02L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK 0x04L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK 0xF8L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK 0x3FL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x03L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x0CL +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x30L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK 0x10L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK 0x01L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK 0x02L +#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK 0xFCL + + +// addressBlock: c20_phy_cr2_rdpcspipecrind +//C20_PHY_CR2_SUP_DIG_IDCODE_LO +#define C20_PHY_CR2_SUP_DIG_IDCODE_LO__VAL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_IDCODE_LO__VAL_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_IDCODE_HI +#define C20_PHY_CR2_SUP_DIG_IDCODE_HI__VAL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_IDCODE_HI__VAL_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0 +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_MASK 0x01C0L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1 +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_MASK 0x0003L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_MASK 0x0018L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN +#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN +#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN +#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x0003L +#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_MASK 0x0038L +#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV_MASK 0x001CL +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL_MASK 0x0060L +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK 0x0E00L +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS_MASK 0x4000L +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1 +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD_MASK 0x3000L +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_MPLLA_BW_LOW_OVRD_IN +#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN +#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK 0x03E0L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_1 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_2 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_3 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_4 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_5 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_6 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV_MASK 0x001CL +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL_MASK 0x0060L +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK 0x0700L +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_MASK 0x007FL +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_MASK 0x7F00L +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_MASK 0x007FL +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_MASK 0x7F00L +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_MASK 0x0003L +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_MASK 0x0018L +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK 0x03E0L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_2 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_3 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_4 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_5 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_6 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_MASK 0x7C00L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN +#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x001FL +#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x01C0L +#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV_MASK 0x000EL +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV_MASK 0x0030L +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0380L +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD_MASK 0x3000L +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_1 +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_SUP_DIG_MPLLA_BW_LOW_ASIC_IN +#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN +#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK 0x00F8L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_1 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_2 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_3 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_4 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_5 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_6 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV_MASK 0x000EL +#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV_MASK 0x0030L +#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK 0x01C0L +#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS_MASK 0x007FL +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_MASK 0x3F80L +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS_MASK 0x007FL +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_MASK 0x3F80L +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I_MASK 0x0003L +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO_MASK 0x000CL +#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK 0x00F8L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_2 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_3 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_4 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_5 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_6 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN +#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN +#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x0600L +#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK 0x3800L +#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_ASIC_IN_0 +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__PHY_RESET__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_USE_PAD__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__TEST_BURNIN__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RTUNE_REQ__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RES_REQ_IN__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RES_ACK_IN__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__BG_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_RANGE__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__PHY_RESET_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_USE_PAD_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__TEST_BURNIN_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RTUNE_REQ_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RES_REQ_IN_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RES_ACK_IN_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__BG_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_RANGE_MASK 0x3800L +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE_MASK 0x4000L +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_ASIC_IN_1 +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__SUP_MISC__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__SUP_MISC_MASK 0x00FFL +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL_MASK 0x0C00L +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL_MASK 0x3000L +#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_ASIC_OUT_0 +#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__MPLLA_STATE__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RTUNE_ACK__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__DTB_OUT__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__MPLLA_STATE_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RTUNE_ACK_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__DTB_OUT_MASK 0x00C0L +#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN +#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x001FL +#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00E0L +#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET_MASK 0x3E00L +#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN +#define C20_PHY_CR2_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR2_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN +#define C20_PHY_CR2_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR2_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL_MASK 0x01F0L +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE_MASK 0x007CL +#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG +#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK 0x0038L +#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_SUP_DIG_RTUNE_STAT +#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__STAT__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__RTUNE_STATE__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__STAT_MASK 0x03FFL +#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__RTUNE_STATE_MASK 0x1C00L +#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE_MASK 0x6000L +#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_RTUNE_RX_SET_VAL +#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x003FL +#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL +#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x03FFL +#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL +#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x03FFL +#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_RTUNE_RX_STAT +#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x003FL +#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_STAT +#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x03FFL +#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_STAT +#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x03FFL +#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_0 +#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG_MASK 0x03FFL +#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_1 +#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN_MASK 0x03FFL +#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_RTUNE_FAST_FLAGS +#define C20_PHY_CR2_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK 0x01FFL +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK 0x01FFL +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK 0x00FFL +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 +#define C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK 0x001FL +#define C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE_MASK 0x000CL +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE_MASK 0x0030L +#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT_MASK 0x000FL +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE_MASK 0x7F80L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK 0x03E0L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE_MASK 0x3C00L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME_MASK 0x03FFL +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME_MASK 0x3C00L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME_MASK 0x07FFL +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME_MASK 0xF800L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME_MASK 0x001FL +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME_MASK 0x03E0L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME_MASK 0x007FL +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME_MASK 0x0F80L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL_MASK 0x0F00L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP_MASK 0x0300L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG_MASK 0x0C00L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0_MASK 0x00FFL +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0_MASK 0xFF00L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1_MASK 0x00FFL +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1_MASK 0xFF00L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2_MASK 0x00FFL +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2_MASK 0xFF00L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3_MASK 0x00FFL +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3_MASK 0xFF00L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME_MASK 0x03FFL +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME_MASK 0x07FFL +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME_MASK 0x03FFL +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME_MASK 0x03FFL +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME_MASK 0x007FL +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_FRAC_OUT +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_SSC_RAMP +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE_MASK 0x007CL +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK 0x03E0L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC_MASK 0x4000L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME_MASK 0x00FFL +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME_MASK 0x3F00L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME_MASK 0x00FFL +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME_MASK 0xFF00L +//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME_MASK 0x003FL +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME_MASK 0x0FC0L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME_MASK 0x003FL +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME_MASK 0x0FC0L +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS_MASK 0x001FL +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME_MASK 0x007FL +#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_FRAC_OUT +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_SSC_RAMP +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT_MASK 0x01F0L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL_MASK 0x0030L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE_MASK 0x3000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT +#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_MASK 0x000CL +#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE_MASK 0x0180L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE_MASK 0x7E00L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL_MASK 0x0006L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL_MASK 0x0018L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC_MASK 0x003FL +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT_MASK 0xFFC0L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK 0x4000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC_MASK 0x003FL +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT_MASK 0xFFC0L +//C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT +#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x000CL +#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x3FF0L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_MASK 0x00FFL +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_MASK 0x1E00L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST_MASK 0x0060L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST_MASK 0x1800L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST_MASK 0x0003L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX_MASK 0x000CL +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0_MASK 0x0030L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6_MASK 0x00C0L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0_MASK 0x7F00L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5_MASK 0x0060L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN_MASK 0x0F00L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN_MASK 0xF000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE_MASK 0x0003L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE_MASK 0x000CL +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM_MASK 0x0030L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR_MASK 0x00C0L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9_MASK 0x7E00L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0_MASK 0x007FL +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF_MASK 0x0180L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR_MASK 0x7E00L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL_MASK 0x00C0L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET_MASK 0x4000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16_MASK 0x003FL +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22_MASK 0x3F80L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW_MASK 0x0FF8L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG_MASK 0x6000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0_MASK 0x00FFL +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV_MASK 0x000CL +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6_MASK 0x00C0L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV_MASK 0x4000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP_MASK 0x1F00L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13_MASK 0x6000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE__SHIFT 0xf +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ_MASK 0x0006L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED_MASK 0x00F0L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H_MASK 0x0600L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP_MASK 0x4000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE_MASK 0x8000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_MASK 0x001CL +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5_MASK 0x00E0L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8_MASK 0x0F00L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN__SHIFT 0x5 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF_MASK 0x0004L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS_MASK 0x0008L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH_MASK 0x0010L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN_MASK 0x0020L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING_MASK 0x0600L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK_MASK 0x2000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED__SHIFT 0x7 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X__SHIFT 0x9 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N__SHIFT 0xb +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER__SHIFT 0xd +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR_MASK 0x000CL +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2_MASK 0x0030L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP_MASK 0x0040L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_MASK 0x0080L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2_MASK 0x0100L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X_MASK 0x0200L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD_MASK 0x0400L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N_MASK 0x0800L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC_MASK 0x1000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER_MASK 0xE000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF__SHIFT 0x3 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH__SHIFT 0xa +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF_MASK 0x0007L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF_MASK 0x0038L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL_MASK 0x00C0L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0_MASK 0x0300L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH_MASK 0x0C00L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2_MASK 0x3000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG__SHIFT 0x1 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC__SHIFT 0x2 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL__SHIFT 0x4 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP__SHIFT 0x6 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK__SHIFT 0x8 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN__SHIFT 0xc +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST__SHIFT 0xe +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0_MASK 0x0001L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG_MASK 0x0002L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC_MASK 0x000CL +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL_MASK 0x0030L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP_MASK 0x00C0L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK_MASK 0x0F00L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN_MASK 0x3000L +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST_MASK 0xC000L +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_CMN_CTL +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWCMN_DIG_CMN_CLK_GATE_CTL +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE__SHIFT 0x4 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE__SHIFT 0x8 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE__SHIFT 0xc +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_MASK 0x0010L +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_MASK 0x0100L +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_MASK 0x0400L +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE_MASK 0x1000L +#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME__SHIFT 0x6 +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME_MASK 0x003FL +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME_MASK 0x03C0L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_CTRL +#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE_MASK 0x000FL +#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_ADDR +#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_ADDR__ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_ADDR__ADDR_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_DATA +#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_DATA__DATA__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_DATA__DATA_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_FLAGS +#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_ACCUM +#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_ACCUM__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_ACCUM__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_MPLL_IN +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE_MASK 0x0004L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWCMN_DIG_FW_PWRUP_DONE +#define C20_PHY_CR2_RAWCMN_DIG_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWCMN_DIG_STATIC_CONFIG_STATUS +#define C20_PHY_CR2_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS +#define C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL__SHIFT 0x7 +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL_MASK 0x0003L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL_MASK 0x0180L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWCMN_DIG_CONFIG_MASTER_VERSION +#define C20_PHY_CR2_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0 +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID__SHIFT 0x8 +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID_MASK 0x0100L +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1 +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID__SHIFT 0x8 +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID_MASK 0x0100L +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2 +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID__SHIFT 0x8 +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID_MASK 0x0100L +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3 +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID__SHIFT 0x8 +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID_MASK 0x0100L +#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL +#define C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0 +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1 +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2 +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0 +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL__SHIFT 0x8 +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC_MASK 0x00FFL +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL_MASK 0x0700L +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1 +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET__SHIFT 0x5 +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL_MASK 0x001FL +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET_MASK 0x3FE0L +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2 +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET__SHIFT 0x5 +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET_MASK 0x001FL +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET_MASK 0x3FE0L +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_3 +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN__SHIFT 0xf +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN_MASK 0x8000L +//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV__SHIFT 0x8 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV__SHIFT 0xb +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS__SHIFT 0xd +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD__SHIFT 0xe +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER_MASK 0x00FFL +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV_MASK 0x0700L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV_MASK 0x1800L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS_MASK 0x2000L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD_MASK 0xC000L +//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_2 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_3 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_4 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_5 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT 0x4 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT 0x9 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL__SHIFT 0xd +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB_MASK 0x000FL +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK 0x01F0L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD_MASK 0x0200L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV_MASK 0x1C00L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL_MASK 0x2000L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_7 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_8 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_9 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV__SHIFT 0xd +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV_MASK 0xE000L +//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV__SHIFT 0x8 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER_MASK 0x00FFL +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV_MASK 0x0300L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE_MASK 0x7C00L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP__SHIFT 0x7 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO__SHIFT 0xe +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT_MASK 0x007FL +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP_MASK 0x3F80L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO_MASK 0xC000L +//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS__SHIFT 0x7 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I__SHIFT 0xe +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS_MASK 0x007FL +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS_MASK 0x3F80L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I_MASK 0xC000L +//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_4 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_5 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT 0x4 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT 0x9 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB_MASK 0x000FL +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK 0x01F0L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD_MASK 0x0200L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV_MASK 0x1C00L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_7 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_8 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_9 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV__SHIFT 0x3 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV_MASK 0x0007L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV_MASK 0x0018L +#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0__SHIFT 0xc +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0_MASK 0x0FFFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0_MASK 0x1000L +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1__SHIFT 0xc +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1_MASK 0x0FFFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1_MASK 0x1000L +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2__SHIFT 0xc +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2_MASK 0x0FFFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2_MASK 0x1000L +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3__SHIFT 0xc +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3_MASK 0x0FFFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3_MASK 0x1000L +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_DONE +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0__SHIFT 0xc +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0_MASK 0x0FFFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0_MASK 0x1000L +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1__SHIFT 0xc +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1_MASK 0x0FFFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1_MASK 0x1000L +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2__SHIFT 0xc +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2_MASK 0x0FFFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2_MASK 0x1000L +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3__SHIFT 0xc +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3_MASK 0x0FFFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3_MASK 0x1000L +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_DONE +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE_MASK 0x0FFFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE_MASK 0x0FFFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_IN_RECAL +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_IN_RECAL +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO_MASK 0x0004L +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL__SHIFT 0x4 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK__SHIFT 0x5 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL_MASK 0x0010L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK_MASK 0x0020L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ__SHIFT 0x3 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ_MASK 0x0008L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL +#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL +#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS +#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS +#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK 0x003FL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK 0x03FFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0_MASK 0x03FFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK 0x003FL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK 0x03FFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1_MASK 0x03FFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK 0x003FL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK 0x03FFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2_MASK 0x03FFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_3 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK 0x003FL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK 0x03FFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3_MASK 0x03FFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_4 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK 0x003FL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK 0x03FFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4_MASK 0x03FFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_5 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK 0x003FL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK 0x03FFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5_MASK 0x03FFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_6 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK 0x003FL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK 0x03FFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6_MASK 0x03FFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_7 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK 0x003FL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK 0x03FFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7_MASK 0x03FFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL_MASK 0x000CL +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL_MASK 0x0060L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS__SHIFT 0x3 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE_MASK 0x0004L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS_MASK 0x0018L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OUT +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWCMN_DIG_AON_FW_VERSION_0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_FW_VERSION_0__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_FW_VERSION_0__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_AON_FW_VERSION_1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_FW_VERSION_1__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_FW_VERSION_1__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_AON_RAW_VERSION +#define C20_PHY_CR2_RAWCMN_DIG_AON_RAW_VERSION__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RAW_VERSION__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL_MASK 0x0004L +#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_EOF_ADDR +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_BOC_ADDR +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN_MASK 0xFF00L +//C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK__SHIFT 0x1 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE__SHIFT 0x5 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE__SHIFT 0x6 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ__SHIFT 0x7 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ__SHIFT 0x8 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL__SHIFT 0x9 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT__SHIFT 0xa +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT__SHIFT 0xb +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL__SHIFT 0xc +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF__SHIFT 0xd +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW__SHIFT 0xe +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK_MASK 0x0002L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE_MASK 0x0020L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE_MASK 0x0040L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ_MASK 0x0080L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ_MASK 0x0100L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL_MASK 0x0200L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT_MASK 0x0400L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT_MASK 0x0800L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL_MASK 0x1000L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF_MASK 0x2000L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW_MASK 0x4000L +#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWCMN_DIG_AON_METADATA_LOCATION +#define C20_PHY_CR2_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION_MASK 0x7FFFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_MASK 0x7FFFL +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE0_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE0_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL +#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR2_LANE0_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR2_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL +#define C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL +#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE0_DIG_RX_LBERT_ERR +#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ +#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE1_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE1_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL +#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR2_LANE1_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR2_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL +#define C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL +#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE1_DIG_RX_LBERT_ERR +#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ +#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE2_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE2_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL +#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR2_LANE2_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR2_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL +#define C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL +#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE2_DIG_RX_LBERT_ERR +#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ +#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE3_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE3_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL +#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR2_LANE3_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR2_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL +#define C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL +#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE3_DIG_RX_LBERT_ERR +#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ +#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_SUP +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE0_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_SUP +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE1_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_SUP +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE2_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_SUP +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANE3_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_DONE +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CODE +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_TX_IN_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_RTRIM +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_DONE +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CODE +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_TX_IN_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_RTRIM +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_DONE +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CODE +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_TX_IN_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_RTRIM +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_DONE +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CODE +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_TX_IN_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_RTRIM +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANEX_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANEX_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL +#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR2_LANEX_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR2_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL +#define C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL +#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANEX_DIG_RX_LBERT_ERR +#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ +#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_SUP +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEX_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_DONE +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CODE +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_TX_IN_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_RTRIM +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL + + +// addressBlock: c20_phy_lane0_pipe2_rdpcspipemsgbusind +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK 0x01L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK 0x02L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK 0x04L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK 0x08L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK 0x10L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK 0x7FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK 0x80L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK 0xFFL +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK 0x01L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK 0x02L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK 0x01L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK 0x02L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK 0x04L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK 0xF8L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK 0x01L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK 0x02L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK 0x01L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK 0xFEL +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK 0x01L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK 0x1EL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK 0x20L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK 0x40L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK 0x80L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK 0x03L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK 0x03L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK 0xFFL +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK 0x01L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK 0x02L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK 0x04L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK 0xF8L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK 0x3FL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x03L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x0CL +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x30L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK 0x10L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK 0x01L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK 0x02L +#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK 0xFCL + + +// addressBlock: c20_phy_lane1_pipe2_rdpcspipemsgbusind +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK 0x01L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK 0x02L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK 0x04L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK 0x08L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK 0x10L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK 0x7FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK 0x80L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK 0xFFL +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK 0x01L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK 0x02L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK 0x01L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK 0x02L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK 0x04L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK 0xF8L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK 0x01L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK 0x02L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK 0x01L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK 0xFEL +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK 0x01L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK 0x1EL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK 0x20L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK 0x40L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK 0x80L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK 0x03L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK 0x03L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK 0xFFL +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK 0x01L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK 0x02L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK 0x04L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK 0xF8L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK 0x3FL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x03L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x0CL +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x30L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK 0x10L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK 0x01L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK 0x02L +#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK 0xFCL + + +// addressBlock: c20_phy_cr3_rdpcspipecrind +//C20_PHY_CR3_SUP_DIG_IDCODE_LO +#define C20_PHY_CR3_SUP_DIG_IDCODE_LO__VAL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_IDCODE_LO__VAL_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_IDCODE_HI +#define C20_PHY_CR3_SUP_DIG_IDCODE_HI__VAL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_IDCODE_HI__VAL_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0 +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_MASK 0x01C0L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1 +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_MASK 0x0003L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_MASK 0x0018L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN +#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN +#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN +#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x0003L +#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_MASK 0x0038L +#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV_MASK 0x001CL +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL_MASK 0x0060L +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK 0x0E00L +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS_MASK 0x4000L +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1 +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD_MASK 0x3000L +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_MPLLA_BW_LOW_OVRD_IN +#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN +#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK 0x03E0L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_1 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_2 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_3 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_4 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_5 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_6 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV_MASK 0x001CL +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL_MASK 0x0060L +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK 0x0700L +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_MASK 0x007FL +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_MASK 0x7F00L +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_MASK 0x007FL +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_MASK 0x7F00L +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_MASK 0x0003L +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_MASK 0x0018L +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK 0x03E0L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_2 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_3 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_4 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_5 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_6 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_MASK 0x7C00L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN +#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x001FL +#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x01C0L +#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV_MASK 0x000EL +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV_MASK 0x0030L +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0380L +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD_MASK 0x3000L +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_1 +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_SUP_DIG_MPLLA_BW_LOW_ASIC_IN +#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN +#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK 0x00F8L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_1 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_2 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_3 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_4 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_5 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_6 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV_MASK 0x000EL +#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV_MASK 0x0030L +#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK 0x01C0L +#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS_MASK 0x007FL +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_MASK 0x3F80L +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS_MASK 0x007FL +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_MASK 0x3F80L +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I_MASK 0x0003L +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO_MASK 0x000CL +#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK 0x00F8L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_2 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_3 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_4 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_5 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_6 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN +#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN +#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x0600L +#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK 0x3800L +#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_ASIC_IN_0 +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__PHY_RESET__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_USE_PAD__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__TEST_BURNIN__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RTUNE_REQ__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RES_REQ_IN__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RES_ACK_IN__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__BG_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_RANGE__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__PHY_RESET_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_USE_PAD_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__TEST_BURNIN_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RTUNE_REQ_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RES_REQ_IN_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RES_ACK_IN_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__BG_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_RANGE_MASK 0x3800L +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE_MASK 0x4000L +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_ASIC_IN_1 +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__SUP_MISC__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__SUP_MISC_MASK 0x00FFL +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL_MASK 0x0C00L +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL_MASK 0x3000L +#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_ASIC_OUT_0 +#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__MPLLA_STATE__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RTUNE_ACK__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__DTB_OUT__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__MPLLA_STATE_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RTUNE_ACK_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__DTB_OUT_MASK 0x00C0L +#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN +#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x001FL +#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00E0L +#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET_MASK 0x3E00L +#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN +#define C20_PHY_CR3_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR3_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN +#define C20_PHY_CR3_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR3_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL_MASK 0x01F0L +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE_MASK 0x007CL +#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG +#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK 0x0038L +#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_SUP_DIG_RTUNE_STAT +#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__STAT__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__RTUNE_STATE__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__STAT_MASK 0x03FFL +#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__RTUNE_STATE_MASK 0x1C00L +#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE_MASK 0x6000L +#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_RTUNE_RX_SET_VAL +#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x003FL +#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL +#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x03FFL +#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL +#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x03FFL +#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_RTUNE_RX_STAT +#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x003FL +#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_STAT +#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x03FFL +#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_STAT +#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x03FFL +#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_0 +#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG_MASK 0x03FFL +#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_1 +#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN_MASK 0x03FFL +#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_RTUNE_FAST_FLAGS +#define C20_PHY_CR3_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK 0x01FFL +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK 0x01FFL +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK 0x00FFL +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 +#define C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK 0x001FL +#define C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE_MASK 0x000CL +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE_MASK 0x0030L +#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT_MASK 0x000FL +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE_MASK 0x7F80L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK 0x03E0L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE_MASK 0x3C00L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME_MASK 0x03FFL +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME_MASK 0x3C00L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME_MASK 0x07FFL +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME_MASK 0xF800L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME_MASK 0x001FL +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME_MASK 0x03E0L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME_MASK 0x007FL +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME_MASK 0x0F80L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL_MASK 0x0F00L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP_MASK 0x0300L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG_MASK 0x0C00L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0_MASK 0x00FFL +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0_MASK 0xFF00L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1_MASK 0x00FFL +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1_MASK 0xFF00L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2_MASK 0x00FFL +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2_MASK 0xFF00L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3_MASK 0x00FFL +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3_MASK 0xFF00L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME_MASK 0x03FFL +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME_MASK 0x07FFL +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME_MASK 0x03FFL +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME_MASK 0x03FFL +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME_MASK 0x007FL +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_FRAC_OUT +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_SSC_RAMP +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE_MASK 0x007CL +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK 0x03E0L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC_MASK 0x4000L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME_MASK 0x00FFL +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME_MASK 0x3F00L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME_MASK 0x00FFL +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME_MASK 0xFF00L +//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME_MASK 0x003FL +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME_MASK 0x0FC0L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME_MASK 0x003FL +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME_MASK 0x0FC0L +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS_MASK 0x001FL +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME_MASK 0x007FL +#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_FRAC_OUT +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_SSC_RAMP +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT_MASK 0x01F0L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL_MASK 0x0030L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE_MASK 0x3000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT +#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_MASK 0x000CL +#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE_MASK 0x0180L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE_MASK 0x7E00L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL_MASK 0x0006L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL_MASK 0x0018L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC_MASK 0x003FL +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT_MASK 0xFFC0L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK 0x4000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC_MASK 0x003FL +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT_MASK 0xFFC0L +//C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT +#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x000CL +#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x3FF0L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_MASK 0x00FFL +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_MASK 0x1E00L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST_MASK 0x0060L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST_MASK 0x1800L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST_MASK 0x0003L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX_MASK 0x000CL +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0_MASK 0x0030L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6_MASK 0x00C0L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0_MASK 0x7F00L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5_MASK 0x0060L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN_MASK 0x0F00L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN_MASK 0xF000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE_MASK 0x0003L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE_MASK 0x000CL +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM_MASK 0x0030L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR_MASK 0x00C0L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9_MASK 0x7E00L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0_MASK 0x007FL +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF_MASK 0x0180L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR_MASK 0x7E00L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL_MASK 0x00C0L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET_MASK 0x4000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16_MASK 0x003FL +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22_MASK 0x3F80L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW_MASK 0x0FF8L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG_MASK 0x6000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0_MASK 0x00FFL +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV_MASK 0x000CL +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6_MASK 0x00C0L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV_MASK 0x4000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP_MASK 0x1F00L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13_MASK 0x6000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE__SHIFT 0xf +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ_MASK 0x0006L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED_MASK 0x00F0L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H_MASK 0x0600L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP_MASK 0x4000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE_MASK 0x8000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_MASK 0x001CL +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5_MASK 0x00E0L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8_MASK 0x0F00L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN__SHIFT 0x5 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF_MASK 0x0004L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS_MASK 0x0008L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH_MASK 0x0010L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN_MASK 0x0020L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING_MASK 0x0600L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK_MASK 0x2000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED__SHIFT 0x7 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X__SHIFT 0x9 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N__SHIFT 0xb +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER__SHIFT 0xd +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR_MASK 0x000CL +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2_MASK 0x0030L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP_MASK 0x0040L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_MASK 0x0080L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2_MASK 0x0100L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X_MASK 0x0200L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD_MASK 0x0400L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N_MASK 0x0800L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC_MASK 0x1000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER_MASK 0xE000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF__SHIFT 0x3 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH__SHIFT 0xa +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF_MASK 0x0007L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF_MASK 0x0038L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL_MASK 0x00C0L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0_MASK 0x0300L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH_MASK 0x0C00L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2_MASK 0x3000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG__SHIFT 0x1 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC__SHIFT 0x2 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL__SHIFT 0x4 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP__SHIFT 0x6 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK__SHIFT 0x8 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN__SHIFT 0xc +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST__SHIFT 0xe +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0_MASK 0x0001L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG_MASK 0x0002L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC_MASK 0x000CL +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL_MASK 0x0030L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP_MASK 0x00C0L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK_MASK 0x0F00L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN_MASK 0x3000L +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST_MASK 0xC000L +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_CMN_CTL +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWCMN_DIG_CMN_CLK_GATE_CTL +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE__SHIFT 0x4 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE__SHIFT 0x8 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE__SHIFT 0xc +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_MASK 0x0010L +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_MASK 0x0100L +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_MASK 0x0400L +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE_MASK 0x1000L +#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME__SHIFT 0x6 +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME_MASK 0x003FL +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME_MASK 0x03C0L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_CTRL +#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE_MASK 0x000FL +#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_ADDR +#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_ADDR__ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_ADDR__ADDR_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_DATA +#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_DATA__DATA__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_DATA__DATA_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_FLAGS +#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_ACCUM +#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_ACCUM__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_ACCUM__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_MPLL_IN +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE_MASK 0x0004L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWCMN_DIG_FW_PWRUP_DONE +#define C20_PHY_CR3_RAWCMN_DIG_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWCMN_DIG_STATIC_CONFIG_STATUS +#define C20_PHY_CR3_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS +#define C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL__SHIFT 0x7 +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL_MASK 0x0003L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL_MASK 0x0180L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWCMN_DIG_CONFIG_MASTER_VERSION +#define C20_PHY_CR3_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0 +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID__SHIFT 0x8 +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID_MASK 0x0100L +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1 +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID__SHIFT 0x8 +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID_MASK 0x0100L +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2 +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID__SHIFT 0x8 +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID_MASK 0x0100L +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3 +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID__SHIFT 0x8 +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID_MASK 0x0100L +#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL +#define C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0 +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1 +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2 +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0 +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL__SHIFT 0x8 +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC_MASK 0x00FFL +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL_MASK 0x0700L +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1 +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET__SHIFT 0x5 +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL_MASK 0x001FL +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET_MASK 0x3FE0L +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2 +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET__SHIFT 0x5 +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET_MASK 0x001FL +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET_MASK 0x3FE0L +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_3 +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN__SHIFT 0xf +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN_MASK 0x8000L +//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV__SHIFT 0x8 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV__SHIFT 0xb +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS__SHIFT 0xd +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD__SHIFT 0xe +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER_MASK 0x00FFL +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV_MASK 0x0700L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV_MASK 0x1800L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS_MASK 0x2000L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD_MASK 0xC000L +//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_2 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_3 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_4 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_5 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT 0x4 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT 0x9 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL__SHIFT 0xd +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB_MASK 0x000FL +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK 0x01F0L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD_MASK 0x0200L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV_MASK 0x1C00L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL_MASK 0x2000L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_7 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_8 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_9 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV__SHIFT 0xd +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV_MASK 0xE000L +//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV__SHIFT 0x8 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER_MASK 0x00FFL +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV_MASK 0x0300L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE_MASK 0x7C00L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP__SHIFT 0x7 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO__SHIFT 0xe +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT_MASK 0x007FL +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP_MASK 0x3F80L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO_MASK 0xC000L +//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS__SHIFT 0x7 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I__SHIFT 0xe +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS_MASK 0x007FL +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS_MASK 0x3F80L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I_MASK 0xC000L +//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_4 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_5 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT 0x4 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT 0x9 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB_MASK 0x000FL +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK 0x01F0L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD_MASK 0x0200L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV_MASK 0x1C00L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_7 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_8 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_9 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV__SHIFT 0x3 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV_MASK 0x0007L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV_MASK 0x0018L +#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0__SHIFT 0xc +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0_MASK 0x0FFFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0_MASK 0x1000L +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1__SHIFT 0xc +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1_MASK 0x0FFFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1_MASK 0x1000L +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2__SHIFT 0xc +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2_MASK 0x0FFFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2_MASK 0x1000L +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3__SHIFT 0xc +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3_MASK 0x0FFFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3_MASK 0x1000L +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_DONE +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0__SHIFT 0xc +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0_MASK 0x0FFFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0_MASK 0x1000L +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1__SHIFT 0xc +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1_MASK 0x0FFFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1_MASK 0x1000L +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2__SHIFT 0xc +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2_MASK 0x0FFFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2_MASK 0x1000L +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3__SHIFT 0xc +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3_MASK 0x0FFFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3_MASK 0x1000L +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_DONE +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE_MASK 0x0FFFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE_MASK 0x0FFFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_IN_RECAL +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_IN_RECAL +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO_MASK 0x0004L +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL__SHIFT 0x4 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK__SHIFT 0x5 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL_MASK 0x0010L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK_MASK 0x0020L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ__SHIFT 0x3 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ_MASK 0x0008L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL +#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL +#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS +#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS +#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK 0x003FL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK 0x03FFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0_MASK 0x03FFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK 0x003FL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK 0x03FFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1_MASK 0x03FFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK 0x003FL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK 0x03FFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2_MASK 0x03FFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_3 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK 0x003FL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK 0x03FFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3_MASK 0x03FFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_4 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK 0x003FL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK 0x03FFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4_MASK 0x03FFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_5 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK 0x003FL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK 0x03FFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5_MASK 0x03FFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_6 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK 0x003FL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK 0x03FFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6_MASK 0x03FFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_7 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK 0x003FL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK 0x03FFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7_MASK 0x03FFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL_MASK 0x000CL +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL_MASK 0x0060L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS__SHIFT 0x3 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE_MASK 0x0004L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS_MASK 0x0018L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OUT +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWCMN_DIG_AON_FW_VERSION_0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_FW_VERSION_0__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_FW_VERSION_0__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_AON_FW_VERSION_1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_FW_VERSION_1__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_FW_VERSION_1__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_AON_RAW_VERSION +#define C20_PHY_CR3_RAWCMN_DIG_AON_RAW_VERSION__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RAW_VERSION__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL_MASK 0x0004L +#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_EOF_ADDR +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_BOC_ADDR +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN_MASK 0xFF00L +//C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK__SHIFT 0x1 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE__SHIFT 0x5 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE__SHIFT 0x6 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ__SHIFT 0x7 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ__SHIFT 0x8 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL__SHIFT 0x9 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT__SHIFT 0xa +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT__SHIFT 0xb +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL__SHIFT 0xc +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF__SHIFT 0xd +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW__SHIFT 0xe +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK_MASK 0x0002L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE_MASK 0x0020L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE_MASK 0x0040L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ_MASK 0x0080L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ_MASK 0x0100L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL_MASK 0x0200L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT_MASK 0x0400L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT_MASK 0x0800L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL_MASK 0x1000L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF_MASK 0x2000L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW_MASK 0x4000L +#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWCMN_DIG_AON_METADATA_LOCATION +#define C20_PHY_CR3_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION_MASK 0x7FFFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_MASK 0x7FFFL +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE0_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE0_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL +#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR3_LANE0_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR3_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL +#define C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL +#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE0_DIG_RX_LBERT_ERR +#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ +#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE1_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE1_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL +#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR3_LANE1_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR3_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL +#define C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL +#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE1_DIG_RX_LBERT_ERR +#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ +#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE2_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE2_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL +#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR3_LANE2_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR3_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL +#define C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL +#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE2_DIG_RX_LBERT_ERR +#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ +#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE3_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE3_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL +#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR3_LANE3_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR3_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL +#define C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL +#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE3_DIG_RX_LBERT_ERR +#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ +#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_SUP +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE0_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_SUP +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE1_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_SUP +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE2_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_SUP +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANE3_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_DONE +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CODE +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_TX_IN_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_RTRIM +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_DONE +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CODE +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_TX_IN_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_RTRIM +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_DONE +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CODE +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_TX_IN_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_RTRIM +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_DONE +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CODE +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_TX_IN_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_RTRIM +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANEX_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANEX_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL +#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR3_LANEX_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR3_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL +#define C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL +#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANEX_DIG_RX_LBERT_ERR +#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ +#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_SUP +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEX_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_DONE +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CODE +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_TX_IN_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_RTRIM +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL + + +// addressBlock: c20_phy_lane0_pipe3_rdpcspipemsgbusind +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK 0x01L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK 0x02L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK 0x04L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK 0x08L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK 0x10L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK 0x7FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK 0x80L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK 0xFFL +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK 0x01L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK 0x02L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK 0x01L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK 0x02L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK 0x04L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK 0xF8L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK 0x01L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK 0x02L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK 0x01L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK 0xFEL +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK 0x01L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK 0x1EL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK 0x20L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK 0x40L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK 0x80L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK 0x03L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK 0x03L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK 0xFFL +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK 0x01L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK 0x02L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK 0x04L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK 0xF8L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK 0x3FL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x03L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x0CL +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x30L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK 0x10L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK 0x01L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK 0x02L +#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK 0xFCL + + +// addressBlock: c20_phy_lane1_pipe3_rdpcspipemsgbusind +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK 0x01L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK 0x02L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK 0x04L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK 0x08L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK 0x10L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK 0x7FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK 0x80L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK 0xFFL +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK 0x01L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK 0x02L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK 0x01L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK 0x02L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK 0x04L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK 0xF8L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK 0x01L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK 0x02L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK 0x01L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK 0xFEL +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK 0x01L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK 0x1EL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK 0x20L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK 0x40L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK 0x80L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK 0x03L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK 0x03L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK 0xFFL +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK 0x01L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK 0x02L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK 0x04L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK 0xF8L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK 0x3FL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x03L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x0CL +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x30L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK 0x10L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK 0x01L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK 0x02L +#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK 0xFCL + + +// addressBlock: c20_phy_cr4_rdpcspipecrind +//C20_PHY_CR4_SUP_DIG_IDCODE_LO +#define C20_PHY_CR4_SUP_DIG_IDCODE_LO__VAL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_IDCODE_LO__VAL_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_IDCODE_HI +#define C20_PHY_CR4_SUP_DIG_IDCODE_HI__VAL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_IDCODE_HI__VAL_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0 +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_MASK 0x01C0L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1 +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_MASK 0x0003L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_MASK 0x0018L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN +#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN +#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN +#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x0003L +#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_MASK 0x0038L +#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV_MASK 0x001CL +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL_MASK 0x0060L +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK 0x0E00L +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS_MASK 0x4000L +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1 +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD_MASK 0x3000L +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_MPLLA_BW_LOW_OVRD_IN +#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN +#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK 0x03E0L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_1 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_2 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_3 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_4 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_5 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_6 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV_MASK 0x001CL +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL_MASK 0x0060L +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK 0x0700L +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_MASK 0x007FL +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_MASK 0x7F00L +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_MASK 0x007FL +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_MASK 0x7F00L +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_MASK 0x0003L +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_MASK 0x0018L +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK 0x03E0L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_2 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_3 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_4 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_5 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_6 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_MASK 0x7C00L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN +#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x001FL +#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x01C0L +#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV_MASK 0x000EL +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV_MASK 0x0030L +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0380L +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD_MASK 0x3000L +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_1 +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_SUP_DIG_MPLLA_BW_LOW_ASIC_IN +#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN +#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK 0x00F8L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_1 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_2 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_3 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_4 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_5 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_6 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV_MASK 0x000EL +#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV_MASK 0x0030L +#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK 0x01C0L +#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS_MASK 0x007FL +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_MASK 0x3F80L +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS_MASK 0x007FL +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_MASK 0x3F80L +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I_MASK 0x0003L +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO_MASK 0x000CL +#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK 0x00F8L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_2 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16_MASK 0x000FL +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_3 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_4 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_5 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_6 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN +#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN +#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0x01FEL +#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x0600L +#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK 0x3800L +#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_ASIC_IN_0 +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__PHY_RESET__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_USE_PAD__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__TEST_BURNIN__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RTUNE_REQ__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RES_REQ_IN__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RES_ACK_IN__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__BG_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_RANGE__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__PHY_RESET_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_USE_PAD_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__TEST_BURNIN_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RTUNE_REQ_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RES_REQ_IN_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RES_ACK_IN_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__BG_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_RANGE_MASK 0x3800L +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE_MASK 0x4000L +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_ASIC_IN_1 +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__SUP_MISC__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__SUP_MISC_MASK 0x00FFL +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL_MASK 0x0C00L +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL_MASK 0x3000L +#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_ASIC_OUT_0 +#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__MPLLA_STATE__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RTUNE_ACK__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__DTB_OUT__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__MPLLA_STATE_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RTUNE_ACK_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__DTB_OUT_MASK 0x00C0L +#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN +#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x001FL +#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00E0L +#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET_MASK 0x3E00L +#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN +#define C20_PHY_CR4_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR4_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN +#define C20_PHY_CR4_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET_MASK 0x01FFL +#define C20_PHY_CR4_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL_MASK 0x01F0L +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE_MASK 0x007CL +#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG +#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK 0x0038L +#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_SUP_DIG_RTUNE_STAT +#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__STAT__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__RTUNE_STATE__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__STAT_MASK 0x03FFL +#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__RTUNE_STATE_MASK 0x1C00L +#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE_MASK 0x6000L +#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_RTUNE_RX_SET_VAL +#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x003FL +#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL +#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x03FFL +#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL +#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x03FFL +#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_RTUNE_RX_STAT +#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x003FL +#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_STAT +#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x03FFL +#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_STAT +#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x03FFL +#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_0 +#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG_MASK 0x03FFL +#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_1 +#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN_MASK 0x03FFL +#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_RTUNE_FAST_FLAGS +#define C20_PHY_CR4_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK 0x01FFL +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK 0x01FFL +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK 0x00FFL +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 +#define C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK 0x001FL +#define C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE_MASK 0x000CL +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE_MASK 0x0030L +#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT_MASK 0x000FL +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE_MASK 0x7F80L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK 0x03E0L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE_MASK 0x3C00L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME_MASK 0x03FFL +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME_MASK 0x3C00L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME_MASK 0x07FFL +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME_MASK 0xF800L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME_MASK 0x001FL +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME_MASK 0x03E0L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME_MASK 0x007FL +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME_MASK 0x0F80L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL_MASK 0x0F00L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP_MASK 0x0300L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG_MASK 0x0C00L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0_MASK 0x00FFL +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0_MASK 0xFF00L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1_MASK 0x00FFL +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1_MASK 0xFF00L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2_MASK 0x00FFL +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2_MASK 0xFF00L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3_MASK 0x00FFL +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3_MASK 0xFF00L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME_MASK 0x03FFL +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME_MASK 0x07FFL +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME_MASK 0x03FFL +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME_MASK 0x03FFL +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME_MASK 0x007FL +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_FRAC_OUT +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_SSC_RAMP +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE_MASK 0x007CL +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK 0x03E0L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC_MASK 0x4000L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME_MASK 0x00FFL +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME_MASK 0x3F00L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME_MASK 0x00FFL +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME_MASK 0xFF00L +//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME_MASK 0x003FL +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME_MASK 0x0FC0L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME_MASK 0x003FL +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME_MASK 0x0FC0L +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS_MASK 0x001FL +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME_MASK 0x007FL +#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_FRAC_OUT +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_SSC_RAMP +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK 0x7FFFL +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT_MASK 0x01F0L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL_MASK 0x0030L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE_MASK 0x3000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT +#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_MASK 0x000CL +#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE_MASK 0x0180L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE_MASK 0x7E00L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL_MASK 0x0006L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL_MASK 0x0018L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC_MASK 0x003FL +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT_MASK 0xFFC0L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK 0x4000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC_MASK 0x003FL +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT_MASK 0xFFC0L +//C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT +#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x000CL +#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x3FF0L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_MASK 0x00FFL +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_MASK 0x1E00L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST_MASK 0x0060L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST_MASK 0x1800L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST_MASK 0x0003L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX_MASK 0x000CL +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0_MASK 0x0030L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6_MASK 0x00C0L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0_MASK 0x7F00L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5_MASK 0x0060L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN_MASK 0x0F00L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN_MASK 0xF000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE_MASK 0x0003L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE_MASK 0x000CL +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM_MASK 0x0030L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR_MASK 0x00C0L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9_MASK 0x7E00L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0_MASK 0x007FL +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF_MASK 0x0180L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR_MASK 0x7E00L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL_MASK 0x00C0L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET_MASK 0x4000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16_MASK 0x003FL +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22_MASK 0x3F80L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW_MASK 0x0FF8L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG_MASK 0x6000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0_MASK 0x00FFL +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV_MASK 0x000CL +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6_MASK 0x00C0L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV_MASK 0x4000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP_MASK 0x1F00L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13_MASK 0x6000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE__SHIFT 0xf +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ_MASK 0x0006L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED_MASK 0x00F0L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H_MASK 0x0600L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP_MASK 0x4000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE_MASK 0x8000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_MASK 0x001CL +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5_MASK 0x00E0L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8_MASK 0x0F00L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN__SHIFT 0x5 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF_MASK 0x0004L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS_MASK 0x0008L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH_MASK 0x0010L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN_MASK 0x0020L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING_MASK 0x0600L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK_MASK 0x2000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED__SHIFT 0x7 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X__SHIFT 0x9 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N__SHIFT 0xb +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER__SHIFT 0xd +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR_MASK 0x000CL +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2_MASK 0x0030L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP_MASK 0x0040L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_MASK 0x0080L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2_MASK 0x0100L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X_MASK 0x0200L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD_MASK 0x0400L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N_MASK 0x0800L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC_MASK 0x1000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER_MASK 0xE000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF__SHIFT 0x3 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH__SHIFT 0xa +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF_MASK 0x0007L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF_MASK 0x0038L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL_MASK 0x00C0L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0_MASK 0x0300L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH_MASK 0x0C00L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2_MASK 0x3000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG__SHIFT 0x1 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC__SHIFT 0x2 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL__SHIFT 0x4 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP__SHIFT 0x6 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK__SHIFT 0x8 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN__SHIFT 0xc +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST__SHIFT 0xe +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0_MASK 0x0001L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG_MASK 0x0002L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC_MASK 0x000CL +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL_MASK 0x0030L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP_MASK 0x00C0L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK_MASK 0x0F00L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN_MASK 0x3000L +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST_MASK 0xC000L +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_CMN_CTL +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWCMN_DIG_CMN_CLK_GATE_CTL +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE__SHIFT 0x4 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE__SHIFT 0x8 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE__SHIFT 0xc +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_MASK 0x0010L +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_MASK 0x0100L +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_MASK 0x0400L +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE_MASK 0x1000L +#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME__SHIFT 0x6 +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME_MASK 0x003FL +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME_MASK 0x03C0L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_CTRL +#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE_MASK 0x000FL +#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_ADDR +#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_ADDR__ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_ADDR__ADDR_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_DATA +#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_DATA__DATA__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_DATA__DATA_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_FLAGS +#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_ACCUM +#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_ACCUM__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_ACCUM__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_MPLL_IN +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE_MASK 0x0004L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWCMN_DIG_FW_PWRUP_DONE +#define C20_PHY_CR4_RAWCMN_DIG_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWCMN_DIG_STATIC_CONFIG_STATUS +#define C20_PHY_CR4_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS +#define C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL__SHIFT 0x7 +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL_MASK 0x0003L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL_MASK 0x0180L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWCMN_DIG_CONFIG_MASTER_VERSION +#define C20_PHY_CR4_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0 +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID__SHIFT 0x8 +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID_MASK 0x0100L +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1 +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID__SHIFT 0x8 +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID_MASK 0x0100L +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2 +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID__SHIFT 0x8 +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID_MASK 0x0100L +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3 +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID__SHIFT 0x8 +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID_MASK 0x0100L +#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL +#define C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0 +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1 +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2 +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0 +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL__SHIFT 0x8 +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC_MASK 0x00FFL +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL_MASK 0x0700L +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1 +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET__SHIFT 0x5 +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL_MASK 0x001FL +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET_MASK 0x3FE0L +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2 +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET__SHIFT 0x5 +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET_MASK 0x001FL +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET_MASK 0x3FE0L +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_3 +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN__SHIFT 0xf +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN_MASK 0x8000L +//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV__SHIFT 0x8 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV__SHIFT 0xb +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS__SHIFT 0xd +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD__SHIFT 0xe +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER_MASK 0x00FFL +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV_MASK 0x0700L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV_MASK 0x1800L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS_MASK 0x2000L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD_MASK 0xC000L +//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_2 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_3 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_4 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_5 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT 0x4 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT 0x9 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL__SHIFT 0xd +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB_MASK 0x000FL +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK 0x01F0L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD_MASK 0x0200L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV_MASK 0x1C00L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL_MASK 0x2000L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_7 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_8 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_9 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV__SHIFT 0xd +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER_MASK 0x0FFFL +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV_MASK 0xE000L +//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV__SHIFT 0x8 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER_MASK 0x00FFL +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV_MASK 0x0300L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE_MASK 0x7C00L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP__SHIFT 0x7 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO__SHIFT 0xe +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT_MASK 0x007FL +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP_MASK 0x3F80L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO_MASK 0xC000L +//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS__SHIFT 0x7 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I__SHIFT 0xe +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS_MASK 0x007FL +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS_MASK 0x3F80L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I_MASK 0xC000L +//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_4 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_5 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT 0x4 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT 0x9 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB_MASK 0x000FL +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK 0x01F0L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD_MASK 0x0200L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV_MASK 0x1C00L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_7 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_8 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_9 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV__SHIFT 0x3 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV_MASK 0x0007L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV_MASK 0x0018L +#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0__SHIFT 0xc +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0_MASK 0x0FFFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0_MASK 0x1000L +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1__SHIFT 0xc +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1_MASK 0x0FFFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1_MASK 0x1000L +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2__SHIFT 0xc +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2_MASK 0x0FFFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2_MASK 0x1000L +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3__SHIFT 0xc +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3_MASK 0x0FFFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3_MASK 0x1000L +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_DONE +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0__SHIFT 0xc +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0_MASK 0x0FFFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0_MASK 0x1000L +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1__SHIFT 0xc +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1_MASK 0x0FFFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1_MASK 0x1000L +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2__SHIFT 0xc +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2_MASK 0x0FFFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2_MASK 0x1000L +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3__SHIFT 0xc +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3_MASK 0x0FFFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3_MASK 0x1000L +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_DONE +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE_MASK 0x0FFFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE_MASK 0x0FFFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_IN_RECAL +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_IN_RECAL +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO_MASK 0x0004L +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL__SHIFT 0x4 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK__SHIFT 0x5 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL_MASK 0x0010L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK_MASK 0x0020L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ__SHIFT 0x3 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ_MASK 0x0008L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL +#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL +#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS +#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS +#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK 0x003FL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK 0x03FFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0_MASK 0x03FFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK 0x003FL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK 0x03FFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1_MASK 0x03FFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK 0x003FL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK 0x03FFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2_MASK 0x03FFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_3 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK 0x003FL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK 0x03FFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3_MASK 0x03FFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_4 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK 0x003FL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK 0x03FFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4_MASK 0x03FFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_5 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK 0x003FL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK 0x03FFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5_MASK 0x03FFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_6 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK 0x003FL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK 0x03FFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6_MASK 0x03FFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_7 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK 0x003FL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK 0x03FFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7_MASK 0x03FFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL_MASK 0x000CL +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL_MASK 0x0060L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS__SHIFT 0x3 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE_MASK 0x0004L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS_MASK 0x0018L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OUT +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWCMN_DIG_AON_FW_VERSION_0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_FW_VERSION_0__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_FW_VERSION_0__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_AON_FW_VERSION_1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_FW_VERSION_1__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_FW_VERSION_1__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_AON_RAW_VERSION +#define C20_PHY_CR4_RAWCMN_DIG_AON_RAW_VERSION__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RAW_VERSION__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL_MASK 0x0004L +#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_EOF_ADDR +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_BOC_ADDR +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN_MASK 0xFF00L +//C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK__SHIFT 0x1 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE__SHIFT 0x5 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE__SHIFT 0x6 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ__SHIFT 0x7 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ__SHIFT 0x8 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL__SHIFT 0x9 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT__SHIFT 0xa +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT__SHIFT 0xb +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL__SHIFT 0xc +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF__SHIFT 0xd +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW__SHIFT 0xe +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK_MASK 0x0002L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE_MASK 0x0020L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE_MASK 0x0040L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ_MASK 0x0080L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ_MASK 0x0100L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL_MASK 0x0200L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT_MASK 0x0400L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT_MASK 0x0800L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL_MASK 0x1000L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF_MASK 0x2000L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW_MASK 0x4000L +#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWCMN_DIG_AON_METADATA_LOCATION +#define C20_PHY_CR4_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION_MASK 0x7FFFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_MASK 0x7FFFL +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE0_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE0_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL +#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR4_LANE0_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR4_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL +#define C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL +#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE0_DIG_RX_LBERT_ERR +#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ +#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE1_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE1_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL +#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR4_LANE1_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR4_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL +#define C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL +#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE1_DIG_RX_LBERT_ERR +#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ +#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE2_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE2_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL +#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR4_LANE2_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR4_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL +#define C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL +#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE2_DIG_RX_LBERT_ERR +#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ +#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE3_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE3_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL +#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR4_LANE3_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR4_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL +#define C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL +#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE3_DIG_RX_LBERT_ERR +#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ +#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_SUP +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE0_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_SUP +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE1_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_SUP +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE2_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_SUP +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANE3_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_DONE +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CODE +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_TX_IN_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_RTRIM +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_DONE +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CODE +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_TX_IN_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_RTRIM +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_DONE +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CODE +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_TX_IN_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_RTRIM +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_DONE +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CODE +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_TX_IN_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_RTRIM +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0018L +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK 0x3000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK 0x007FL +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK 0x3F80L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK 0x0030L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK 0x000CL +#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x3800L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x0078L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x7F00L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x007FL +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x3F80L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK 0x000CL +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x007FL +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK 0x7F00L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK 0x6000L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK 0xF800L +//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x07FFL +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK 0x7800L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK 0x0038L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST +#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT +#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK 0x0018L +#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANEX_DIG_TX_STAT_LD_VAL_1 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANEX_DIG_TX_STAT_SMPL_CNT1 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CNT_0 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_STOP +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK 0x03FFL +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK 0x1C00L +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1 +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK 0x007FL +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK 0x0380L +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL +#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L +#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_0 +#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_1 +#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK 0xFFFFL +//C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_2 +#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK 0xFFFFL +//C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_3 +#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK 0xFFFFL +//C20_PHY_CR4_LANEX_DIG_TX_LVL_CALC_STAT +#define C20_PHY_CR4_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL +#define C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK 0x0003L +#define C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK 0x00F8L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK 0x03FFL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK 0x007FL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK 0xFFFFL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK 0x0003L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK 0x01FEL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK 0x000CL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK 0x0006L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK 0x00F0L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK 0x0300L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK 0x1800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0C00L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK 0x0700L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK 0x7000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK 0x0070L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK 0x0180L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK 0x1C00L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK 0x007FL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK 0x7F00L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK 0x007FL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK 0x7F00L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0380L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x1C00L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK 0x001CL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK 0x00E0L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK 0x007FL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK 0x0780L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0F80L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK 0x3000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK 0x0700L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK 0x1F00L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x001CL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK 0x003FL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK 0x1F80L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK 0x001FL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK 0x01C0L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK 0x0003L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK 0x01FCL +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK 0xFC00L +//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK 0x001FL +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK 0x0060L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK 0x0180L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x7E00L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK 0x003EL +#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x001FL +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x01C0L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0E00L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x0FF0L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK 0x03F8L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL +#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__BER_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__BER_SEL_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANEX_DIG_RX_LBERT_ERR +#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x03C0L +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L +//C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L +#define C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ +#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 +#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL +#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 +#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL +#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0300L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x00F0L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x0F00L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK 0x1E00L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK 0x6000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x01FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x0C00L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK 0x001FL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK 0x03E0L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK 0x007FL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK 0x03F0L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK 0x0C00L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK 0x01FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK 0x0E00L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK 0x3000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK 0x0700L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK 0x7000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK 0x0FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK 0x3800L +#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_1 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_DATA_MSK +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0006L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK 0x0180L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK 0x0380L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_STOP +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK 0x003EL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK 0x07C0L +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT2 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_1 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_2 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK 0x7FFFL +#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_STAT +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x001CL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x003FL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK 0x007FL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK 0x07FEL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK 0x6000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK 0x00FCL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x003FL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK 0x00F0L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK 0x0E00L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK 0x0003L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK 0x0600L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK 0x7000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK 0x0038L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK 0x7FFCL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK 0x01F0L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK 0x0003L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK 0x0E00L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK 0x0004L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK 0x0008L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK 0x000FL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK 0x000CL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK 0x0020L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK 0x0300L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK 0xFC00L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK 0x007EL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK 0xFF00L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK 0x0002L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK 0x000CL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK 0x0030L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK 0x0040L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK 0x1C00L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK 0xE000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK 0x00FEL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK 0x0100L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK 0x0200L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK 0x00FFL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK 0x0300L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK 0xF000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT 0x2 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT 0x4 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT 0x5 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT 0x7 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT 0x8 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK 0x0003L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK 0x000CL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK 0x0010L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK 0x0060L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK 0x0080L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK 0x0300L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK 0x0C00L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT 0x1 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT 0x3 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT 0x6 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT 0x9 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT 0xd +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT 0xf +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK 0x0001L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK 0x0006L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK 0x0038L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK 0x01C0L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK 0x0E00L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK 0x1000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK 0x2000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK 0x4000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK 0x8000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT 0xa +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT 0xb +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT 0xc +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK 0x03FFL +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK 0x0400L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK 0x0800L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK 0x3000L +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG11 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT 0x0 +#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK 0x003CL +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OUT_0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK 0x0007L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK 0x0038L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK 0x3C00L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK 0x8000L +//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK 0x0F00L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK 0xE000L +//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0007L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OUT_0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_CLK_CTL +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_TERM_CODE +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_IN_0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK 0x007FL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK 0x8000L +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK 0x0C00L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK 0x7F00L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK 0x1800L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OUT_0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK 0x0007L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK 0x0078L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK 0x0180L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK 0x3E00L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK 0xC000L +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK 0x0007L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK 0x0038L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK 0x07C0L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK 0x1800L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK 0xE000L +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK 0x000CL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK 0x0FF0L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK 0xF000L +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK 0xF000L +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK 0x0007L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK 0x03F8L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK 0xF800L +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK 0x0007L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK 0x0380L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK 0x00E0L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK 0x0E00L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK 0x003CL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OUT_0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_TERM_CODE +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_SEL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK 0x0007L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK 0x007FL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK 0x007FL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_IN_0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_JMP_BANK +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK_MASK 0x0007L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_CTL_0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_2 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_3 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_4 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_5 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_6 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_7 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_8 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_9 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_10 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_11 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_SUP +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_PWRUP +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEX_DIG_FSM_RX_CAL_STATUS +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK 0x3FFFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ITER +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_EN +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK 0xFFE0L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_DONE +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CODE +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CM_CODE +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_BANK_SEL +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_TX_IN_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT 0xf +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK 0x4000L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK 0x8000L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK 0x007FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK 0x1F80L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_RTRIM +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MAX +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MIN +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_RESET +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_BANK_SEL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CODE +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CODE +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL__VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE__VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK 0x0070L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK 0x03E0L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK 0x0003L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK 0xFFFCL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK 0x01FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK 0x0C00L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK 0xE000L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK 0x003FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK 0x007FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK 0xFFFEL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK 0x01E0L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK 0x0007L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK 0x0038L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK 0x000FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK 0x00F0L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK 0x03E0L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK 0xFC00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_5 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_7 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_9 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_10 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_11 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_12 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_13 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_14 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_15 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_16 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_17 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_18 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_19 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_20 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_21 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_22 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_23 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_24 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_25 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_26 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_27 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_28 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL_MASK 0xFFFFL +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK 0xFFF8L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK 0x0FFFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK 0xF000L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT 0xa +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT 0xb +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT 0xc +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT 0xd +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK 0x0080L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK 0x0200L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK 0x0400L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK 0x0800L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK 0x1000L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK 0x2000L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK 0x00FFL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK 0xFF00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT 0x8 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT 0x9 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK 0x001FL +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK 0x00E0L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK 0x0100L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK 0xFE00L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK 0xFFF0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK 0xFFC0L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT 0x3 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT 0x4 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT 0x5 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT 0x6 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7__SHIFT 0x7 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC_MASK 0x0004L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK 0x0008L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK 0x0010L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK 0x0020L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK 0x0040L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7_MASK 0xFF80L +//C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT 0x0 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT 0x1 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2__SHIFT 0x2 +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF_MASK 0x0001L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF_MASK 0x0002L +#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2_MASK 0xFFFCL + + +// addressBlock: c20_phy_lane0_pipe4_rdpcspipemsgbusind +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK 0x01L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK 0x02L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK 0x04L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK 0x08L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK 0x10L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK 0x7FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK 0x80L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK 0xFFL +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK 0x01L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK 0x02L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK 0x01L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK 0x02L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK 0x04L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK 0xF8L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK 0x01L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK 0x02L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK 0x01L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK 0xFEL +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK 0xFFL +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK 0xFFL +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT 0x7 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK 0x01L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK 0x1EL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK 0x20L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK 0x40L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK 0x80L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK 0x03L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK 0x03L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK 0xFCL +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK 0xFFL +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK 0x01L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK 0x02L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK 0x04L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK 0xF8L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK 0x3FL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x03L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x0CL +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x30L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK 0xC0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT 0x4 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK 0x10L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT 0x1 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK 0x01L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK 0x02L +#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK 0xFCL + + +// addressBlock: c20_phy_lane1_pipe4_rdpcspipemsgbusind +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK 0x01L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK 0x02L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK 0x04L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK 0x08L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK 0x10L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK 0x7FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK 0x80L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK 0xFFL +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK 0x01L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK 0x02L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK 0x01L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK 0x02L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK 0x04L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK 0xF8L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK 0x01L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK 0x02L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK 0x40L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK 0x80L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK 0x40L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK 0x80L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK 0x07L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK 0x08L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK 0xF0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK 0x01L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK 0xFEL +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK 0xFFL +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK 0xFFL +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT 0x7 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK 0x01L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK 0x1EL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK 0x20L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK 0x40L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK 0x80L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK 0x03L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK 0x03L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK 0xFCL +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK 0xFFL +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK 0x01L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK 0x02L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK 0x04L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK 0xF8L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK 0x3FL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT 0x6 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x03L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x0CL +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK 0x30L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK 0xC0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK 0x10L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT 0x3 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT 0x4 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT 0x5 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK 0x01L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK 0x02L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK 0x04L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK 0x08L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK 0x10L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK 0xE0L +//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT 0x0 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT 0x1 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT 0x2 +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK 0x01L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK 0x02L +#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK 0xFCL + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h new file mode 100644 index 000000000000..e40a924c02ce --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h @@ -0,0 +1,14559 @@ +/* + * Copyright (C) 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _dcn_3_2_1_OFFSET_HEADER +#define _dcn_3_2_1_OFFSET_HEADER + + + +// addressBlock: dce_dc_dccg_dccg_dfs_dispdec +// base address: 0x0 +#define regDENTIST_DISPCLK_CNTL 0x0064 +#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1 + + +// addressBlock: dce_dc_dccg_dccg_dispdec +// base address: 0x0 +#define regPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 +#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 +#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 +#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 +#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regDP_DTO_DBUF_EN 0x0044 +#define regDP_DTO_DBUF_EN_BASE_IDX 1 +#define regDSCCLK3_DTO_PARAM 0x0045 +#define regDSCCLK3_DTO_PARAM_BASE_IDX 1 +#define regDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 +#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL4 0x0049 +#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX 1 +#define regDPSTREAMCLK_CNTL 0x004a +#define regDPSTREAMCLK_CNTL_BASE_IDX 1 +#define regREFCLK_CGTT_BLK_CTRL_REG 0x004b +#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c +#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regDCCG_GLOBAL_FGCG_REP_CNTL 0x0050 +#define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX 1 +#define regDCCG_DS_DTO_INCR 0x0053 +#define regDCCG_DS_DTO_INCR_BASE_IDX 1 +#define regDCCG_DS_DTO_MODULO 0x0054 +#define regDCCG_DS_DTO_MODULO_BASE_IDX 1 +#define regDCCG_DS_CNTL 0x0055 +#define regDCCG_DS_CNTL_BASE_IDX 1 +#define regDCCG_DS_HW_CAL_INTERVAL 0x0056 +#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 +#define regDPREFCLK_CNTL 0x0058 +#define regDPREFCLK_CNTL_BASE_IDX 1 +#define regDCE_VERSION 0x005e +#define regDCE_VERSION_BASE_IDX 1 +#define regDCCG_GTC_CNTL 0x0060 +#define regDCCG_GTC_CNTL_BASE_IDX 1 +#define regDCCG_GTC_DTO_INCR 0x0061 +#define regDCCG_GTC_DTO_INCR_BASE_IDX 1 +#define regDCCG_GTC_DTO_MODULO 0x0062 +#define regDCCG_GTC_DTO_MODULO_BASE_IDX 1 +#define regDCCG_GTC_CURRENT 0x0063 +#define regDCCG_GTC_CURRENT_BASE_IDX 1 +#define regSYMCLK32_SE_CNTL 0x0065 +#define regSYMCLK32_SE_CNTL_BASE_IDX 1 +#define regSYMCLK32_LE_CNTL 0x0066 +#define regSYMCLK32_LE_CNTL_BASE_IDX 1 +#define regDTBCLK_P_CNTL 0x0068 +#define regDTBCLK_P_CNTL_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL5 0x0069 +#define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX 1 +#define regDSCCLK0_DTO_PARAM 0x006c +#define regDSCCLK0_DTO_PARAM_BASE_IDX 1 +#define regDSCCLK1_DTO_PARAM 0x006d +#define regDSCCLK1_DTO_PARAM_BASE_IDX 1 +#define regDSCCLK2_DTO_PARAM 0x006e +#define regDSCCLK2_DTO_PARAM_BASE_IDX 1 +#define regOTG_PIXEL_RATE_DIV 0x006f +#define regOTG_PIXEL_RATE_DIV_BASE_IDX 1 +#define regMILLISECOND_TIME_BASE_DIV 0x0070 +#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 +#define regDISPCLK_FREQ_CHANGE_CNTL 0x0071 +#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 +#define regDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 +#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL 0x0074 +#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 +#define regDISPCLK_CGTT_BLK_CTRL_REG 0x0075 +#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regSOCCLK_CGTT_BLK_CTRL_REG 0x0076 +#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDCCG_CAC_STATUS 0x0077 +#define regDCCG_CAC_STATUS_BASE_IDX 1 +#define regMICROSECOND_TIME_BASE_DIV 0x007b +#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL2 0x007c +#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 +#define regSYMCLK_CGTT_BLK_CTRL_REG 0x007d +#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDCCG_DISP_CNTL_REG 0x007f +#define regDCCG_DISP_CNTL_REG_BASE_IDX 1 +#define regOTG0_PIXEL_RATE_CNTL 0x0080 +#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO0_PHASE 0x0081 +#define regDP_DTO0_PHASE_BASE_IDX 1 +#define regDP_DTO0_MODULO 0x0082 +#define regDP_DTO0_MODULO_BASE_IDX 1 +#define regOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 +#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regOTG1_PIXEL_RATE_CNTL 0x0084 +#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO1_PHASE 0x0085 +#define regDP_DTO1_PHASE_BASE_IDX 1 +#define regDP_DTO1_MODULO 0x0086 +#define regDP_DTO1_MODULO_BASE_IDX 1 +#define regOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 +#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regOTG2_PIXEL_RATE_CNTL 0x0088 +#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO2_PHASE 0x0089 +#define regDP_DTO2_PHASE_BASE_IDX 1 +#define regDP_DTO2_MODULO 0x008a +#define regDP_DTO2_MODULO_BASE_IDX 1 +#define regOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b +#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regOTG3_PIXEL_RATE_CNTL 0x008c +#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO3_PHASE 0x008d +#define regDP_DTO3_PHASE_BASE_IDX 1 +#define regDP_DTO3_MODULO 0x008e +#define regDP_DTO3_MODULO_BASE_IDX 1 +#define regOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f +#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDPPCLK_CGTT_BLK_CTRL_REG 0x0098 +#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDPPCLK0_DTO_PARAM 0x0099 +#define regDPPCLK0_DTO_PARAM_BASE_IDX 1 +#define regDPPCLK1_DTO_PARAM 0x009a +#define regDPPCLK1_DTO_PARAM_BASE_IDX 1 +#define regDPPCLK2_DTO_PARAM 0x009b +#define regDPPCLK2_DTO_PARAM_BASE_IDX 1 +#define regDPPCLK3_DTO_PARAM 0x009c +#define regDPPCLK3_DTO_PARAM_BASE_IDX 1 +#define regDCCG_CAC_STATUS2 0x009f +#define regDCCG_CAC_STATUS2_BASE_IDX 1 +#define regSYMCLKA_CLOCK_ENABLE 0x00a0 +#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKB_CLOCK_ENABLE 0x00a1 +#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKC_CLOCK_ENABLE 0x00a2 +#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKD_CLOCK_ENABLE 0x00a3 +#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKE_CLOCK_ENABLE 0x00a4 +#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 +#define regDCCG_SOFT_RESET 0x00a6 +#define regDCCG_SOFT_RESET_BASE_IDX 1 +#define regDSCCLK_DTO_CTRL 0x00a7 +#define regDSCCLK_DTO_CTRL_BASE_IDX 1 +#define regDCCG_AUDIO_DTO_SOURCE 0x00ab +#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO0_PHASE 0x00ac +#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO0_MODULE 0x00ad +#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO1_PHASE 0x00ae +#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO1_MODULE 0x00af +#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 +#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 +#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 +#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 +#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 +#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 +#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 +#define regDPPCLK_DTO_CTRL 0x00b6 +#define regDPPCLK_DTO_CTRL_BASE_IDX 1 +#define regDCCG_VSYNC_CNT_CTRL 0x00b8 +#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 +#define regDCCG_VSYNC_CNT_INT_CTRL 0x00b9 +#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 +#define regFORCE_SYMCLK_DISABLE 0x00ba +#define regFORCE_SYMCLK_DISABLE_BASE_IDX 1 +#define regDCCG_TEST_CLK_SEL 0x00be +#define regDCCG_TEST_CLK_SEL_BASE_IDX 1 +#define regDTBCLK_DTO0_PHASE 0x0018 +#define regDTBCLK_DTO0_PHASE_BASE_IDX 2 +#define regDTBCLK_DTO1_PHASE 0x0019 +#define regDTBCLK_DTO1_PHASE_BASE_IDX 2 +#define regDTBCLK_DTO2_PHASE 0x001a +#define regDTBCLK_DTO2_PHASE_BASE_IDX 2 +#define regDTBCLK_DTO3_PHASE 0x001b +#define regDTBCLK_DTO3_PHASE_BASE_IDX 2 +#define regDTBCLK_DTO0_MODULO 0x001f +#define regDTBCLK_DTO0_MODULO_BASE_IDX 2 +#define regDTBCLK_DTO1_MODULO 0x0020 +#define regDTBCLK_DTO1_MODULO_BASE_IDX 2 +#define regDTBCLK_DTO2_MODULO 0x0021 +#define regDTBCLK_DTO2_MODULO_BASE_IDX 2 +#define regDTBCLK_DTO3_MODULO 0x0022 +#define regDTBCLK_DTO3_MODULO_BASE_IDX 2 +#define regHDMICHARCLK0_CLOCK_CNTL 0x004a +#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX 2 +#define regPHYASYMCLK_CLOCK_CNTL 0x0052 +#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYBSYMCLK_CLOCK_CNTL 0x0053 +#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYCSYMCLK_CLOCK_CNTL 0x0054 +#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYDSYMCLK_CLOCK_CNTL 0x0055 +#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYESYMCLK_CLOCK_CNTL 0x0056 +#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regHDMISTREAMCLK_CNTL 0x0059 +#define regHDMISTREAMCLK_CNTL_BASE_IDX 2 +#define regDCCG_GATE_DISABLE_CNTL3 0x005a +#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2 +#define regHDMISTREAMCLK0_DTO_PARAM 0x005b +#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX 2 +#define regDCCG_AUDIO_DTBCLK_DTO_PHASE 0x0061 +#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX 2 +#define regDCCG_AUDIO_DTBCLK_DTO_MODULO 0x0062 +#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX 2 +#define regDTBCLK_DTO_DBUF_EN 0x0063 +#define regDTBCLK_DTO_DBUF_EN_BASE_IDX 2 +#define regDMCUBCLK_CNTL 0x0067 +#define regDMCUBCLK_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_rbbmif_dispdec +// base address: 0x0 +#define regRBBMIF_TIMEOUT 0x017f +#define regRBBMIF_TIMEOUT_BASE_IDX 2 +#define regRBBMIF_STATUS 0x0180 +#define regRBBMIF_STATUS_BASE_IDX 2 +#define regRBBMIF_STATUS_2 0x0181 +#define regRBBMIF_STATUS_2_BASE_IDX 2 +#define regRBBMIF_INT_STATUS 0x0182 +#define regRBBMIF_INT_STATUS_BASE_IDX 2 +#define regRBBMIF_TIMEOUT_DIS 0x0183 +#define regRBBMIF_TIMEOUT_DIS_BASE_IDX 2 +#define regRBBMIF_TIMEOUT_DIS_2 0x0184 +#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 +#define regRBBMIF_STATUS_FLAG 0x0185 +#define regRBBMIF_STATUS_FLAG_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_ihc_dispdec +// base address: 0x0 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 +#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 +#define regDC_GPU_TIMER_READ 0x0128 +#define regDC_GPU_TIMER_READ_BASE_IDX 2 +#define regDC_GPU_TIMER_READ_CNTL 0x0129 +#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS 0x012a +#define regDISP_INTERRUPT_STATUS_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE 0x012b +#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE2 0x012c +#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE3 0x012d +#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE4 0x012e +#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE5 0x012f +#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 +#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 +#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 +#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 +#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 +#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 +#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 +#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 +#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 +#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 +#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE16 0x013a +#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE17 0x013b +#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE18 0x013c +#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE19 0x013d +#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE20 0x013e +#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE21 0x013f +#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 +#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_VREADY 0x0141 +#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_FLIP 0x0142 +#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 +#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 +#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 +#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 +#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 +#define regDCCG_INTERRUPT_DEST 0x0148 +#define regDCCG_INTERRUPT_DEST_BASE_IDX 2 +#define regDMU_INTERRUPT_DEST 0x0149 +#define regDMU_INTERRUPT_DEST_BASE_IDX 2 +#define regDMU_INTERRUPT_DEST2 0x014a +#define regDMU_INTERRUPT_DEST2_BASE_IDX 2 +#define regDCPG_INTERRUPT_DEST 0x014b +#define regDCPG_INTERRUPT_DEST_BASE_IDX 2 +#define regDCPG_INTERRUPT_DEST2 0x014c +#define regDCPG_INTERRUPT_DEST2_BASE_IDX 2 +#define regMMHUBBUB_INTERRUPT_DEST 0x014d +#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 +#define regWB_INTERRUPT_DEST 0x014e +#define regWB_INTERRUPT_DEST_BASE_IDX 2 +#define regDCHUB_INTERRUPT_DEST 0x014f +#define regDCHUB_INTERRUPT_DEST_BASE_IDX 2 +#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 +#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 +#define regDCHUB_INTERRUPT_DEST2 0x0151 +#define regDCHUB_INTERRUPT_DEST2_BASE_IDX 2 +#define regDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 +#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 +#define regMPC_INTERRUPT_DEST 0x0153 +#define regMPC_INTERRUPT_DEST_BASE_IDX 2 +#define regOPP_INTERRUPT_DEST 0x0154 +#define regOPP_INTERRUPT_DEST_BASE_IDX 2 +#define regOPTC_INTERRUPT_DEST 0x0155 +#define regOPTC_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG0_INTERRUPT_DEST 0x0156 +#define regOTG0_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG1_INTERRUPT_DEST 0x0157 +#define regOTG1_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG2_INTERRUPT_DEST 0x0158 +#define regOTG2_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG3_INTERRUPT_DEST 0x0159 +#define regOTG3_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG4_INTERRUPT_DEST 0x015a +#define regOTG4_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG5_INTERRUPT_DEST 0x015b +#define regOTG5_INTERRUPT_DEST_BASE_IDX 2 +#define regDIG_INTERRUPT_DEST 0x015c +#define regDIG_INTERRUPT_DEST_BASE_IDX 2 +#define regI2C_DDC_HPD_INTERRUPT_DEST 0x015d +#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 +#define regDIO_INTERRUPT_DEST 0x015f +#define regDIO_INTERRUPT_DEST_BASE_IDX 2 +#define regDCIO_INTERRUPT_DEST 0x0160 +#define regDCIO_INTERRUPT_DEST_BASE_IDX 2 +#define regHPD_INTERRUPT_DEST 0x0161 +#define regHPD_INTERRUPT_DEST_BASE_IDX 2 +#define regAZ_INTERRUPT_DEST 0x0162 +#define regAZ_INTERRUPT_DEST_BASE_IDX 2 +#define regAUX_INTERRUPT_DEST 0x0163 +#define regAUX_INTERRUPT_DEST_BASE_IDX 2 +#define regDSC_INTERRUPT_DEST 0x0164 +#define regDSC_INTERRUPT_DEST_BASE_IDX 2 +#define regHPO_INTERRUPT_DEST 0x0165 +#define regHPO_INTERRUPT_DEST_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmu_misc_dispdec +// base address: 0x0 +#define regCC_DC_PIPE_DIS 0x00ca +#define regCC_DC_PIPE_DIS_BASE_IDX 2 +#define regDMU_CLK_CNTL 0x00cb +#define regDMU_CLK_CNTL_BASE_IDX 2 +#define regDMCUB_SMU_INTERRUPT_CNTL 0x00cd +#define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX 2 +#define regSMU_INTERRUPT_CONTROL 0x00ce +#define regSMU_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDMU_MISC_ALLOW_DS_FORCE 0x00d6 +#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dc_pg_dispdec +// base address: 0x0 +#define regDOMAIN0_PG_CONFIG 0x0080 +#define regDOMAIN0_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN0_PG_STATUS 0x0081 +#define regDOMAIN0_PG_STATUS_BASE_IDX 2 +#define regDOMAIN1_PG_CONFIG 0x0082 +#define regDOMAIN1_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN1_PG_STATUS 0x0083 +#define regDOMAIN1_PG_STATUS_BASE_IDX 2 +#define regDOMAIN2_PG_CONFIG 0x0084 +#define regDOMAIN2_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN2_PG_STATUS 0x0085 +#define regDOMAIN2_PG_STATUS_BASE_IDX 2 +#define regDOMAIN3_PG_CONFIG 0x0086 +#define regDOMAIN3_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN3_PG_STATUS 0x0087 +#define regDOMAIN3_PG_STATUS_BASE_IDX 2 +#define regDOMAIN16_PG_CONFIG 0x0089 +#define regDOMAIN16_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN16_PG_STATUS 0x008a +#define regDOMAIN16_PG_STATUS_BASE_IDX 2 +#define regDOMAIN17_PG_CONFIG 0x008b +#define regDOMAIN17_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN17_PG_STATUS 0x008c +#define regDOMAIN17_PG_STATUS_BASE_IDX 2 +#define regDOMAIN18_PG_CONFIG 0x008d +#define regDOMAIN18_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN18_PG_STATUS 0x008e +#define regDOMAIN18_PG_STATUS_BASE_IDX 2 +#define regDOMAIN19_PG_CONFIG 0x008f +#define regDOMAIN19_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN19_PG_STATUS 0x0090 +#define regDOMAIN19_PG_STATUS_BASE_IDX 2 +#define regDCPG_INTERRUPT_STATUS 0x0091 +#define regDCPG_INTERRUPT_STATUS_BASE_IDX 2 +#define regDCPG_INTERRUPT_STATUS_2 0x0092 +#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 +#define regDCPG_INTERRUPT_CONTROL_1 0x0093 +#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 +#define regDCPG_INTERRUPT_CONTROL_3 0x0094 +#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 +#define regDC_IP_REQUEST_CNTL 0x0095 +#define regDC_IP_REQUEST_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmcub_dispdec +// base address: 0x0 +#define regDMCUB_REGION0_OFFSET 0x018e +#define regDMCUB_REGION0_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION0_OFFSET_HIGH 0x018f +#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION1_OFFSET 0x0190 +#define regDMCUB_REGION1_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION1_OFFSET_HIGH 0x0191 +#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION2_OFFSET 0x0192 +#define regDMCUB_REGION2_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION2_OFFSET_HIGH 0x0193 +#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION4_OFFSET 0x0196 +#define regDMCUB_REGION4_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION4_OFFSET_HIGH 0x0197 +#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION5_OFFSET 0x0198 +#define regDMCUB_REGION5_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION5_OFFSET_HIGH 0x0199 +#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION6_OFFSET 0x019a +#define regDMCUB_REGION6_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION6_OFFSET_HIGH 0x019b +#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION7_OFFSET 0x019c +#define regDMCUB_REGION7_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION7_OFFSET_HIGH 0x019d +#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION0_TOP_ADDRESS 0x019e +#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION1_TOP_ADDRESS 0x019f +#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION2_TOP_ADDRESS 0x01a0 +#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION4_TOP_ADDRESS 0x01a1 +#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION5_TOP_ADDRESS 0x01a2 +#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION6_TOP_ADDRESS 0x01a3 +#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION7_TOP_ADDRESS 0x01a4 +#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 +#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 +#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 +#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 +#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 +#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa +#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab +#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac +#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad +#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae +#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af +#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 +#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 +#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 +#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 +#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 +#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_OFFSET 0x01b5 +#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 +#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_OFFSET 0x01b7 +#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 +#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_OFFSET 0x01b9 +#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba +#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_OFFSET 0x01bb +#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc +#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_OFFSET 0x01bd +#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be +#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_OFFSET 0x01bf +#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 +#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_OFFSET 0x01c1 +#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 +#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_OFFSET 0x01c3 +#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 +#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_INTERRUPT_ENABLE 0x01c5 +#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 +#define regDMCUB_INTERRUPT_ACK 0x01c6 +#define regDMCUB_INTERRUPT_ACK_BASE_IDX 2 +#define regDMCUB_INTERRUPT_STATUS 0x01c7 +#define regDMCUB_INTERRUPT_STATUS_BASE_IDX 2 +#define regDMCUB_INTERRUPT_TYPE 0x01c8 +#define regDMCUB_INTERRUPT_TYPE_BASE_IDX 2 +#define regDMCUB_EXT_INTERRUPT_STATUS 0x01c9 +#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 +#define regDMCUB_EXT_INTERRUPT_CTXID 0x01ca +#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 +#define regDMCUB_EXT_INTERRUPT_ACK 0x01cb +#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 +#define regDMCUB_INST_FETCH_FAULT_ADDR 0x01cc +#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 +#define regDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd +#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 +#define regDMCUB_SEC_CNTL 0x01ce +#define regDMCUB_SEC_CNTL_BASE_IDX 2 +#define regDMCUB_MEM_CNTL 0x01cf +#define regDMCUB_MEM_CNTL_BASE_IDX 2 +#define regDMCUB_INBOX0_BASE_ADDRESS 0x01d0 +#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_INBOX0_SIZE 0x01d1 +#define regDMCUB_INBOX0_SIZE_BASE_IDX 2 +#define regDMCUB_INBOX0_WPTR 0x01d2 +#define regDMCUB_INBOX0_WPTR_BASE_IDX 2 +#define regDMCUB_INBOX0_RPTR 0x01d3 +#define regDMCUB_INBOX0_RPTR_BASE_IDX 2 +#define regDMCUB_INBOX1_BASE_ADDRESS 0x01d4 +#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_INBOX1_SIZE 0x01d5 +#define regDMCUB_INBOX1_SIZE_BASE_IDX 2 +#define regDMCUB_INBOX1_WPTR 0x01d6 +#define regDMCUB_INBOX1_WPTR_BASE_IDX 2 +#define regDMCUB_INBOX1_RPTR 0x01d7 +#define regDMCUB_INBOX1_RPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 +#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_OUTBOX0_SIZE 0x01d9 +#define regDMCUB_OUTBOX0_SIZE_BASE_IDX 2 +#define regDMCUB_OUTBOX0_WPTR 0x01da +#define regDMCUB_OUTBOX0_WPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX0_RPTR 0x01db +#define regDMCUB_OUTBOX0_RPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc +#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_OUTBOX1_SIZE 0x01dd +#define regDMCUB_OUTBOX1_SIZE_BASE_IDX 2 +#define regDMCUB_OUTBOX1_WPTR 0x01de +#define regDMCUB_OUTBOX1_WPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX1_RPTR 0x01df +#define regDMCUB_OUTBOX1_RPTR_BASE_IDX 2 +#define regDMCUB_TIMER_TRIGGER0 0x01e0 +#define regDMCUB_TIMER_TRIGGER0_BASE_IDX 2 +#define regDMCUB_TIMER_TRIGGER1 0x01e1 +#define regDMCUB_TIMER_TRIGGER1_BASE_IDX 2 +#define regDMCUB_TIMER_WINDOW 0x01e2 +#define regDMCUB_TIMER_WINDOW_BASE_IDX 2 +#define regDMCUB_SCRATCH0 0x01e3 +#define regDMCUB_SCRATCH0_BASE_IDX 2 +#define regDMCUB_SCRATCH1 0x01e4 +#define regDMCUB_SCRATCH1_BASE_IDX 2 +#define regDMCUB_SCRATCH2 0x01e5 +#define regDMCUB_SCRATCH2_BASE_IDX 2 +#define regDMCUB_SCRATCH3 0x01e6 +#define regDMCUB_SCRATCH3_BASE_IDX 2 +#define regDMCUB_SCRATCH4 0x01e7 +#define regDMCUB_SCRATCH4_BASE_IDX 2 +#define regDMCUB_SCRATCH5 0x01e8 +#define regDMCUB_SCRATCH5_BASE_IDX 2 +#define regDMCUB_SCRATCH6 0x01e9 +#define regDMCUB_SCRATCH6_BASE_IDX 2 +#define regDMCUB_SCRATCH7 0x01ea +#define regDMCUB_SCRATCH7_BASE_IDX 2 +#define regDMCUB_SCRATCH8 0x01eb +#define regDMCUB_SCRATCH8_BASE_IDX 2 +#define regDMCUB_SCRATCH9 0x01ec +#define regDMCUB_SCRATCH9_BASE_IDX 2 +#define regDMCUB_SCRATCH10 0x01ed +#define regDMCUB_SCRATCH10_BASE_IDX 2 +#define regDMCUB_SCRATCH11 0x01ee +#define regDMCUB_SCRATCH11_BASE_IDX 2 +#define regDMCUB_SCRATCH12 0x01ef +#define regDMCUB_SCRATCH12_BASE_IDX 2 +#define regDMCUB_SCRATCH13 0x01f0 +#define regDMCUB_SCRATCH13_BASE_IDX 2 +#define regDMCUB_SCRATCH14 0x01f1 +#define regDMCUB_SCRATCH14_BASE_IDX 2 +#define regDMCUB_SCRATCH15 0x01f2 +#define regDMCUB_SCRATCH15_BASE_IDX 2 +#define regDMCUB_SCRATCH16 0x01f3 +#define regDMCUB_SCRATCH16_BASE_IDX 2 +#define regDMCUB_SCRATCH17 0x01f4 +#define regDMCUB_SCRATCH17_BASE_IDX 2 +#define regDMCUB_SCRATCH18 0x01f5 +#define regDMCUB_SCRATCH18_BASE_IDX 2 +#define regDMCUB_CNTL 0x01f6 +#define regDMCUB_CNTL_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN0 0x01f7 +#define regDMCUB_GPINT_DATAIN0_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN1 0x01f8 +#define regDMCUB_GPINT_DATAIN1_BASE_IDX 2 +#define regDMCUB_GPINT_DATAOUT 0x01f9 +#define regDMCUB_GPINT_DATAOUT_BASE_IDX 2 +#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa +#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 +#define regDMCUB_LS_WAKE_INT_ENABLE 0x01fb +#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 +#define regDMCUB_MEM_PWR_CNTL 0x01fc +#define regDMCUB_MEM_PWR_CNTL_BASE_IDX 2 +#define regDMCUB_TIMER_CURRENT 0x01fd +#define regDMCUB_TIMER_CURRENT_BASE_IDX 2 +#define regDMCUB_PROC_ID 0x01ff +#define regDMCUB_PROC_ID_BASE_IDX 2 +#define regDMCUB_CNTL2 0x0200 +#define regDMCUB_CNTL2_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN2 0x0215 +#define regDMCUB_GPINT_DATAIN2_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN3 0x0216 +#define regDMCUB_GPINT_DATAIN3_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN4 0x0217 +#define regDMCUB_GPINT_DATAIN4_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN5 0x0218 +#define regDMCUB_GPINT_DATAIN5_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN6 0x0219 +#define regDMCUB_GPINT_DATAIN6_BASE_IDX 2 +#define regDMCUB_REGION3_TMR_AXI_SPACE 0x021a +#define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX 2 +#define regDMCUB_SCRATCH19 0x022e +#define regDMCUB_SCRATCH19_BASE_IDX 2 +#define regDMCUB_SCRATCH20 0x022f +#define regDMCUB_SCRATCH20_BASE_IDX 2 +#define regDMCUB_SCRATCH21 0x0230 +#define regDMCUB_SCRATCH21_BASE_IDX 2 +#define regDMCUB_SCRATCH22 0x0231 +#define regDMCUB_SCRATCH22_BASE_IDX 2 +#define regDMCUB_SCRATCH23 0x0232 +#define regDMCUB_SCRATCH23_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec +// base address: 0x0 +#define regDWB_ENABLE_CLK_CTRL 0x3228 +#define regDWB_ENABLE_CLK_CTRL_BASE_IDX 2 +#define regDWB_MEM_PWR_CTRL 0x3229 +#define regDWB_MEM_PWR_CTRL_BASE_IDX 2 +#define regFC_MODE_CTRL 0x322a +#define regFC_MODE_CTRL_BASE_IDX 2 +#define regFC_FLOW_CTRL 0x322b +#define regFC_FLOW_CTRL_BASE_IDX 2 +#define regFC_WINDOW_START 0x322c +#define regFC_WINDOW_START_BASE_IDX 2 +#define regFC_WINDOW_SIZE 0x322d +#define regFC_WINDOW_SIZE_BASE_IDX 2 +#define regFC_SOURCE_SIZE 0x322e +#define regFC_SOURCE_SIZE_BASE_IDX 2 +#define regDWB_UPDATE_CTRL 0x322f +#define regDWB_UPDATE_CTRL_BASE_IDX 2 +#define regDWB_CRC_CTRL 0x3230 +#define regDWB_CRC_CTRL_BASE_IDX 2 +#define regDWB_CRC_MASK_R_G 0x3231 +#define regDWB_CRC_MASK_R_G_BASE_IDX 2 +#define regDWB_CRC_MASK_B_A 0x3232 +#define regDWB_CRC_MASK_B_A_BASE_IDX 2 +#define regDWB_CRC_VAL_R_G 0x3233 +#define regDWB_CRC_VAL_R_G_BASE_IDX 2 +#define regDWB_CRC_VAL_B_A 0x3234 +#define regDWB_CRC_VAL_B_A_BASE_IDX 2 +#define regDWB_OUT_CTRL 0x3235 +#define regDWB_OUT_CTRL_BASE_IDX 2 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 +#define regDWB_HOST_READ_CONTROL 0x3238 +#define regDWB_HOST_READ_CONTROL_BASE_IDX 2 +#define regDWB_OVERFLOW_STATUS 0x3239 +#define regDWB_OVERFLOW_STATUS_BASE_IDX 2 +#define regDWB_OVERFLOW_COUNTER 0x323a +#define regDWB_OVERFLOW_COUNTER_BASE_IDX 2 +#define regDWB_SOFT_RESET 0x323b +#define regDWB_SOFT_RESET_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec +// base address: 0x0 +#define regDWB_HDR_MULT_COEF 0x3294 +#define regDWB_HDR_MULT_COEF_BASE_IDX 2 +#define regDWB_GAMUT_REMAP_MODE 0x3295 +#define regDWB_GAMUT_REMAP_MODE_BASE_IDX 2 +#define regDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 +#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C11_C12 0x3297 +#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C13_C14 0x3298 +#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C21_C22 0x3299 +#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C23_C24 0x329a +#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C31_C32 0x329b +#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C33_C34 0x329c +#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C11_C12 0x329d +#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C13_C14 0x329e +#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C21_C22 0x329f +#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C23_C24 0x32a0 +#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C31_C32 0x32a1 +#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C33_C34 0x32a2 +#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 +#define regDWB_OGAM_CONTROL 0x32a3 +#define regDWB_OGAM_CONTROL_BASE_IDX 2 +#define regDWB_OGAM_LUT_INDEX 0x32a4 +#define regDWB_OGAM_LUT_INDEX_BASE_IDX 2 +#define regDWB_OGAM_LUT_DATA 0x32a5 +#define regDWB_OGAM_LUT_DATA_BASE_IDX 2 +#define regDWB_OGAM_LUT_CONTROL 0x32a6 +#define regDWB_OGAM_LUT_CONTROL_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_CNTL_B 0x32a7 +#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_CNTL_G 0x32a8 +#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_CNTL_R 0x32a9 +#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa +#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac +#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae +#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 +#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 +#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 +#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 +#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 +#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 +#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_OFFSET_B 0x32b6 +#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_OFFSET_G 0x32b7 +#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_OFFSET_R 0x32b8 +#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_0_1 0x32b9 +#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_2_3 0x32ba +#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_4_5 0x32bb +#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_6_7 0x32bc +#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_8_9 0x32bd +#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_10_11 0x32be +#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_12_13 0x32bf +#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_14_15 0x32c0 +#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_16_17 0x32c1 +#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_18_19 0x32c2 +#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_20_21 0x32c3 +#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_22_23 0x32c4 +#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_24_25 0x32c5 +#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_26_27 0x32c6 +#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_28_29 0x32c7 +#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_30_31 0x32c8 +#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_32_33 0x32c9 +#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_CNTL_B 0x32ca +#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_CNTL_G 0x32cb +#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_CNTL_R 0x32cc +#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd +#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf +#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 +#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 +#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 +#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 +#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 +#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 +#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_OFFSET_B 0x32d9 +#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_OFFSET_G 0x32da +#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_OFFSET_R 0x32db +#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_0_1 0x32dc +#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_2_3 0x32dd +#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_4_5 0x32de +#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_6_7 0x32df +#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_8_9 0x32e0 +#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_10_11 0x32e1 +#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_12_13 0x32e2 +#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_14_15 0x32e3 +#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_16_17 0x32e4 +#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_18_19 0x32e5 +#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_20_21 0x32e6 +#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_22_23 0x32e7 +#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_24_25 0x32e8 +#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_26_27 0x32e9 +#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_28_29 0x32ea +#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_30_31 0x32eb +#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_32_33 0x32ec +#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec +// base address: 0x0 +#define regVGA_MEM_WRITE_PAGE_ADDR 0x0000 +#define regVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 +#define regVGA_MEM_READ_PAGE_ADDR 0x0001 +#define regVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 +#define regVGA_RENDER_CONTROL 0x0000 +#define regVGA_RENDER_CONTROL_BASE_IDX 1 +#define regVGA_SEQUENCER_RESET_CONTROL 0x0001 +#define regVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 +#define regVGA_MODE_CONTROL 0x0002 +#define regVGA_MODE_CONTROL_BASE_IDX 1 +#define regVGA_SURFACE_PITCH_SELECT 0x0003 +#define regVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 +#define regVGA_MEMORY_BASE_ADDRESS 0x0004 +#define regVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 +#define regVGA_DISPBUF1_SURFACE_ADDR 0x0006 +#define regVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 +#define regVGA_DISPBUF2_SURFACE_ADDR 0x0008 +#define regVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 +#define regVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 +#define regVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 +#define regVGA_HDP_CONTROL 0x000a +#define regVGA_HDP_CONTROL_BASE_IDX 1 +#define regVGA_CACHE_CONTROL 0x000b +#define regVGA_CACHE_CONTROL_BASE_IDX 1 +#define regD1VGA_CONTROL 0x000c +#define regD1VGA_CONTROL_BASE_IDX 1 +#define regD2VGA_CONTROL 0x000e +#define regD2VGA_CONTROL_BASE_IDX 1 +#define regVGA_STATUS 0x0010 +#define regVGA_STATUS_BASE_IDX 1 +#define regVGA_INTERRUPT_CONTROL 0x0011 +#define regVGA_INTERRUPT_CONTROL_BASE_IDX 1 +#define regVGA_STATUS_CLEAR 0x0012 +#define regVGA_STATUS_CLEAR_BASE_IDX 1 +#define regVGA_INTERRUPT_STATUS 0x0013 +#define regVGA_INTERRUPT_STATUS_BASE_IDX 1 +#define regVGA_MAIN_CONTROL 0x0014 +#define regVGA_MAIN_CONTROL_BASE_IDX 1 +#define regVGA_TEST_CONTROL 0x0015 +#define regVGA_TEST_CONTROL_BASE_IDX 1 +#define regVGA_QOS_CTRL 0x0018 +#define regVGA_QOS_CTRL_BASE_IDX 1 +#define regCRTC8_IDX 0x002d +#define regCRTC8_IDX_BASE_IDX 1 +#define regCRTC8_DATA 0x002d +#define regCRTC8_DATA_BASE_IDX 1 +#define regGENFC_WT 0x002e +#define regGENFC_WT_BASE_IDX 1 +#define regGENS1 0x002e +#define regGENS1_BASE_IDX 1 +#define regATTRDW 0x0030 +#define regATTRDW_BASE_IDX 1 +#define regATTRX 0x0030 +#define regATTRX_BASE_IDX 1 +#define regATTRDR 0x0030 +#define regATTRDR_BASE_IDX 1 +#define regGENMO_WT 0x0030 +#define regGENMO_WT_BASE_IDX 1 +#define regGENS0 0x0030 +#define regGENS0_BASE_IDX 1 +#define regGENENB 0x0030 +#define regGENENB_BASE_IDX 1 +#define regSEQ8_IDX 0x0031 +#define regSEQ8_IDX_BASE_IDX 1 +#define regSEQ8_DATA 0x0031 +#define regSEQ8_DATA_BASE_IDX 1 +#define regDAC_MASK 0x0031 +#define regDAC_MASK_BASE_IDX 1 +#define regDAC_R_INDEX 0x0031 +#define regDAC_R_INDEX_BASE_IDX 1 +#define regDAC_W_INDEX 0x0032 +#define regDAC_W_INDEX_BASE_IDX 1 +#define regDAC_DATA 0x0032 +#define regDAC_DATA_BASE_IDX 1 +#define regGENFC_RD 0x0032 +#define regGENFC_RD_BASE_IDX 1 +#define regGENMO_RD 0x0033 +#define regGENMO_RD_BASE_IDX 1 +#define regGRPH8_IDX 0x0033 +#define regGRPH8_IDX_BASE_IDX 1 +#define regGRPH8_DATA 0x0033 +#define regGRPH8_DATA_BASE_IDX 1 +#define regCRTC8_IDX_1 0x0035 +#define regCRTC8_IDX_1_BASE_IDX 1 +#define regCRTC8_DATA_1 0x0035 +#define regCRTC8_DATA_1_BASE_IDX 1 +#define regGENFC_WT_1 0x0036 +#define regGENFC_WT_1_BASE_IDX 1 +#define regGENS1_1 0x0036 +#define regGENS1_1_BASE_IDX 1 +#define regD3VGA_CONTROL 0x0038 +#define regD3VGA_CONTROL_BASE_IDX 1 +#define regD4VGA_CONTROL 0x0039 +#define regD4VGA_CONTROL_BASE_IDX 1 +#define regD5VGA_CONTROL 0x003a +#define regD5VGA_CONTROL_BASE_IDX 1 +#define regD6VGA_CONTROL 0x003b +#define regD6VGA_CONTROL_BASE_IDX 1 +#define regVGA_SOURCE_SELECT 0x003c +#define regVGA_SOURCE_SELECT_BASE_IDX 1 + + +// addressBlock: dce_dc_mmhubbub_vgaif_dispdec +// base address: 0x0 +#define regMCIF_CONTROL 0x034a +#define regMCIF_CONTROL_BASE_IDX 2 +#define regMCIF_WRITE_COMBINE_CONTROL 0x034b +#define regMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 +#define regMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e +#define regMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 +#define regMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f +#define regMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 +#define regMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 +#define regMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec +// base address: 0x0 +#define regMCIF_WB_BUFMGR_SW_CONTROL 0x0272 +#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 +#define regMCIF_WB_BUFMGR_STATUS 0x0274 +#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_PITCH 0x0275 +#define regMCIF_WB_BUF_PITCH_BASE_IDX 2 +#define regMCIF_WB_BUF_1_STATUS 0x0276 +#define regMCIF_WB_BUF_1_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_1_STATUS2 0x0277 +#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 +#define regMCIF_WB_BUF_2_STATUS 0x0278 +#define regMCIF_WB_BUF_2_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_2_STATUS2 0x0279 +#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 +#define regMCIF_WB_BUF_3_STATUS 0x027a +#define regMCIF_WB_BUF_3_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_3_STATUS2 0x027b +#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 +#define regMCIF_WB_BUF_4_STATUS 0x027c +#define regMCIF_WB_BUF_4_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_4_STATUS2 0x027d +#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 +#define regMCIF_WB_ARBITRATION_CONTROL 0x027e +#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 +#define regMCIF_WB_SCLK_CHANGE 0x027f +#define regMCIF_WB_SCLK_CHANGE_BASE_IDX 2 +#define regMCIF_WB_TEST_DEBUG_INDEX 0x0280 +#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regMCIF_WB_TEST_DEBUG_DATA 0x0281 +#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_Y 0x0282 +#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_C 0x0284 +#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_Y 0x0286 +#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_C 0x0288 +#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_Y 0x028a +#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_C 0x028c +#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_Y 0x028e +#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_C 0x0290 +#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 +#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 +#define regMCIF_WB_NB_PSTATE_CONTROL 0x0293 +#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 +#define regMCIF_WB_CLOCK_GATER_CONTROL 0x0294 +#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 +#define regMCIF_WB_SELF_REFRESH_CONTROL 0x0296 +#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 +#define regMULTI_LEVEL_QOS_CTRL 0x0297 +#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 +#define regMCIF_WB_SECURITY_LEVEL 0x0298 +#define regMCIF_WB_SECURITY_LEVEL_BASE_IDX 2 +#define regMCIF_WB_BUF_LUMA_SIZE 0x0299 +#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 +#define regMCIF_WB_BUF_CHROMA_SIZE 0x029a +#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b +#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c +#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d +#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e +#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f +#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 +#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 +#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 +#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_1_RESOLUTION 0x02a3 +#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_BUF_2_RESOLUTION 0x02a4 +#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_BUF_3_RESOLUTION 0x02a5 +#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_BUF_4_RESOLUTION 0x02a6 +#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI 0x02a7 +#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX 2 +#define regMCIF_WB_VMID_CONTROL 0x02a8 +#define regMCIF_WB_VMID_CONTROL_BASE_IDX 2 +#define regMCIF_WB_MIN_TTO 0x02a9 +#define regMCIF_WB_MIN_TTO_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec +// base address: 0x0 +#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa +#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 +#define regMCIF_WB_WATERMARK 0x02ab +#define regMCIF_WB_WATERMARK_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_CONFIG 0x02ac +#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad +#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae +#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af +#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 +#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 +#define regMMHUBBUB_MIN_TTO 0x02b1 +#define regMMHUBBUB_MIN_TTO_BASE_IDX 2 +#define regMMHUBBUB_CTRL 0x0333 +#define regMMHUBBUB_CTRL_BASE_IDX 2 +#define regWBIF_SMU_WM_CONTROL 0x0334 +#define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 +#define regWBIF0_MISC_CTRL 0x0335 +#define regWBIF0_MISC_CTRL_BASE_IDX 2 +#define regWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0336 +#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 +#define regWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0337 +#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 +#define regVGA_SRC_SPLIT_CNTL 0x033e +#define regVGA_SRC_SPLIT_CNTL_BASE_IDX 2 +#define regMMHUBBUB_MEM_PWR_STATUS 0x033f +#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 +#define regMMHUBBUB_MEM_PWR_CNTL 0x0340 +#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 +#define regMMHUBBUB_CLOCK_CNTL 0x0341 +#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 +#define regMMHUBBUB_SOFT_RESET 0x0342 +#define regMMHUBBUB_SOFT_RESET_BASE_IDX 2 +#define regDMU_IF_ERR_STATUS 0x0346 +#define regDMU_IF_ERR_STATUS_BASE_IDX 2 +#define regMMHUBBUB_CLIENT_UNIT_ID 0x0347 +#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_VMID_CONTROL 0x0349 +#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0controller_dispdec +// base address: 0x0 +#define regAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 +#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 +#define regAZALIA_AUDIO_DTO 0x03c3 +#define regAZALIA_AUDIO_DTO_BASE_IDX 2 +#define regAZALIA_AUDIO_DTO_CONTROL 0x03c4 +#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 +#define regAZALIA_SOCCLK_CONTROL 0x03c5 +#define regAZALIA_SOCCLK_CONTROL_BASE_IDX 2 +#define regAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 +#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 +#define regAZALIA_DATA_DMA_CONTROL 0x03c7 +#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 +#define regAZALIA_BDL_DMA_CONTROL 0x03c8 +#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 +#define regAZALIA_RIRB_AND_DP_CONTROL 0x03c9 +#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 +#define regAZALIA_CORB_DMA_CONTROL 0x03ca +#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 +#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 +#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 +#define regAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 +#define regAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 +#define regAZALIA_GLOBAL_CAPABILITIES 0x03d3 +#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 +#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 +#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 +#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 +#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 +#define regAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 +#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL0 0x03d9 +#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL1 0x03da +#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL2 0x03db +#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL3 0x03dc +#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_RESULT 0x03dd +#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL0 0x03de +#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL1 0x03df +#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL2 0x03e0 +#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL3 0x03e1 +#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_RESULT 0x03e2 +#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL0 0x03e3 +#define regAZALIA_CRC0_CONTROL0_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL1 0x03e4 +#define regAZALIA_CRC0_CONTROL1_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL2 0x03e5 +#define regAZALIA_CRC0_CONTROL2_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL3 0x03e6 +#define regAZALIA_CRC0_CONTROL3_BASE_IDX 2 +#define regAZALIA_CRC0_RESULT 0x03e7 +#define regAZALIA_CRC0_RESULT_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL0 0x03e8 +#define regAZALIA_CRC1_CONTROL0_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL1 0x03e9 +#define regAZALIA_CRC1_CONTROL1_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL2 0x03ea +#define regAZALIA_CRC1_CONTROL2_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL3 0x03eb +#define regAZALIA_CRC1_CONTROL3_BASE_IDX 2 +#define regAZALIA_CRC1_RESULT 0x03ec +#define regAZALIA_CRC1_RESULT_BASE_IDX 2 +#define regAZALIA_MEM_PWR_CTRL 0x03ee +#define regAZALIA_MEM_PWR_CTRL_BASE_IDX 2 +#define regAZALIA_MEM_PWR_STATUS 0x03ef +#define regAZALIA_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0root_dispdec +// base address: 0x0 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 +#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 +#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 +#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 +#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 +#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 +#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 +#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 +#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 +#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 +#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 +#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 +#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 +#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET5 0x041a +#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET6 0x041b +#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 +#define regREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c +#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 +#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d +#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_az_misc_dispdec +// base address: 0x0 +#define regAZ_CLOCK_CNTL 0x0372 +#define regAZ_CLOCK_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream0_dispdec +// base address: 0x0 +#define regAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e +#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM0_AZALIA_STREAM_DATA 0x035f +#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream1_dispdec +// base address: 0x8 +#define regAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 +#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 +#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream2_dispdec +// base address: 0x10 +#define regAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 +#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 +#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream3_dispdec +// base address: 0x18 +#define regAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 +#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 +#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream4_dispdec +// base address: 0x20 +#define regAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 +#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 +#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream5_dispdec +// base address: 0x28 +#define regAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 +#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 +#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream6_dispdec +// base address: 0x30 +#define regAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a +#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM6_AZALIA_STREAM_DATA 0x036b +#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream7_dispdec +// base address: 0x38 +#define regAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c +#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM7_AZALIA_STREAM_DATA 0x036d +#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream8_dispdec +// base address: 0x320 +#define regAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 +#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 +#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream9_dispdec +// base address: 0x328 +#define regAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 +#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 +#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream10_dispdec +// base address: 0x330 +#define regAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a +#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM10_AZALIA_STREAM_DATA 0x042b +#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream11_dispdec +// base address: 0x338 +#define regAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c +#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM11_AZALIA_STREAM_DATA 0x042d +#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream12_dispdec +// base address: 0x340 +#define regAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e +#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM12_AZALIA_STREAM_DATA 0x042f +#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream13_dispdec +// base address: 0x348 +#define regAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 +#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 +#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream14_dispdec +// base address: 0x350 +#define regAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 +#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 +#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream15_dispdec +// base address: 0x358 +#define regAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 +#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 +#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint0_dispdec +// base address: 0x0 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint1_dispdec +// base address: 0x18 +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint2_dispdec +// base address: 0x30 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint3_dispdec +// base address: 0x48 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint4_dispdec +// base address: 0x60 +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint5_dispdec +// base address: 0x78 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint6_dispdec +// base address: 0x90 +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint7_dispdec +// base address: 0xa8 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec +// base address: 0x0 +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec +// base address: 0x10 +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec +// base address: 0x20 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec +// base address: 0x30 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec +// base address: 0x40 +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec +// base address: 0x50 +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec +// base address: 0x60 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec +// base address: 0x70 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_hubbub_dispdec +// base address: 0x0 +#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x04f9 +#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 +#define regDCHUBBUB_ARB_SAT_LEVEL 0x04fa +#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 +#define regDCHUBBUB_ARB_QOS_FORCE 0x04fb +#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 +#define regDCHUBBUB_ARB_DRAM_STATE_CNTL 0x04fc +#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL 0x04fd +#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x04fe +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A 0x04ff +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x0500 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x0501 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x0502 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A 0x0503 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A 0x0504 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x0505 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0506 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x0507 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B 0x0508 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x0509 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x050a +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x050b +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B 0x050c +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B 0x050d +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x050e +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x050f +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0510 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C 0x0511 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0512 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0513 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0514 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C 0x0515 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C 0x0516 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0517 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0518 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0519 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D 0x051a +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x051b +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051c +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051d +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D 0x051e +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D 0x051f +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x0520 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0521 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x0522 +#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_MALL_CNTL 0x0523 +#define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_TIMEOUT_ENABLE 0x0524 +#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 +#define regDCHUBBUB_GLOBAL_TIMER_CNTL 0x0525 +#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 +#define regSURFACE_CHECK0_ADDRESS_LSB 0x0526 +#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK0_ADDRESS_MSB 0x0527 +#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 +#define regSURFACE_CHECK1_ADDRESS_LSB 0x0528 +#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK1_ADDRESS_MSB 0x0529 +#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 +#define regSURFACE_CHECK2_ADDRESS_LSB 0x052a +#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK2_ADDRESS_MSB 0x052b +#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 +#define regSURFACE_CHECK3_ADDRESS_LSB 0x052c +#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK3_ADDRESS_MSB 0x052d +#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 +#define regVTG0_CONTROL 0x052e +#define regVTG0_CONTROL_BASE_IDX 2 +#define regVTG1_CONTROL 0x052f +#define regVTG1_CONTROL_BASE_IDX 2 +#define regVTG2_CONTROL 0x0530 +#define regVTG2_CONTROL_BASE_IDX 2 +#define regVTG3_CONTROL 0x0531 +#define regVTG3_CONTROL_BASE_IDX 2 +#define regDCHUBBUB_SOFT_RESET 0x0532 +#define regDCHUBBUB_SOFT_RESET_BASE_IDX 2 +#define regDCHUBBUB_CLOCK_CNTL 0x0533 +#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 +#define regDCFCLK_CNTL 0x0534 +#define regDCFCLK_CNTL_BASE_IDX 2 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0535 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0536 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 +#define regDCHUBBUB_VLINE_SNAPSHOT 0x0537 +#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 +#define regDCHUBBUB_CTRL_STATUS 0x0538 +#define regDCHUBBUB_CTRL_STATUS_BASE_IDX 2 +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053e +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053f +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 +#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x0540 +#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 +#define regFMON_CTRL 0x0541 +#define regFMON_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec +// base address: 0x0 +#define regDCHUBBUB_SDPIF_CFG0 0x046f +#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_CFG1 0x0470 +#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_CFG2 0x0471 +#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 +#define regVM_REQUEST_PHYSICAL 0x0472 +#define regVM_REQUEST_PHYSICAL_BASE_IDX 2 +#define regDCHUBBUB_FORCE_IO_STATUS_0 0x0473 +#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 +#define regDCHUBBUB_FORCE_IO_STATUS_1 0x0474 +#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 +#define regDCN_VM_FB_LOCATION_BASE 0x0475 +#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 +#define regDCN_VM_FB_LOCATION_TOP 0x0476 +#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 +#define regDCN_VM_FB_OFFSET 0x0477 +#define regDCN_VM_FB_OFFSET_BASE_IDX 2 +#define regDCN_VM_AGP_BOT 0x0478 +#define regDCN_VM_AGP_BOT_BASE_IDX 2 +#define regDCN_VM_AGP_TOP 0x0479 +#define regDCN_VM_AGP_TOP_BASE_IDX 2 +#define regDCN_VM_AGP_BASE 0x047a +#define regDCN_VM_AGP_BASE_BASE_IDX 2 +#define regDCN_VM_LOCAL_HBM_ADDRESS_START 0x047b +#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 +#define regDCN_VM_LOCAL_HBM_ADDRESS_END 0x047c +#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 +#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x047d +#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x047e +#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_NOALLOC 0x047f +#define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL 0x0480 +#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL 0x0481 +#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL 0x0482 +#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL 0x0483 +#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX 2 +#define regSDPIF_REQUEST_RATE_LIMIT 0x0484 +#define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x0485 +#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x0486 +#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec +// base address: 0x0 +#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04af +#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04b0 +#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 +#define regDCHUBBUB_CRC_CTRL 0x04b1 +#define regDCHUBBUB_CRC_CTRL_BASE_IDX 2 +#define regDCHUBBUB_CRC0_VAL_R_G 0x04b2 +#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 +#define regDCHUBBUB_CRC0_VAL_B_A 0x04b3 +#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 +#define regDCHUBBUB_CRC1_VAL_R_G 0x04b4 +#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 +#define regDCHUBBUB_CRC1_VAL_B_A 0x04b5 +#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT_CNTL 0x04b6 +#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT0 0x04b7 +#define regDCHUBBUB_DCC_STAT0_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT1 0x04b8 +#define regDCHUBBUB_DCC_STAT1_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT2 0x04b9 +#define regDCHUBBUB_DCC_STAT2_BASE_IDX 2 +#define regDCHUBBUB_COMPBUF_CTRL 0x04ba +#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET0_CTRL 0x04bb +#define regDCHUBBUB_DET0_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET1_CTRL 0x04bc +#define regDCHUBBUB_DET1_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET2_CTRL 0x04bd +#define regDCHUBBUB_DET2_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET3_CTRL 0x04be +#define regDCHUBBUB_DET3_CTRL_BASE_IDX 2 +#define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04c0 +#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2 +#define regCOMPBUF_MEM_PWR_CTRL_1 0x04c1 +#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX 2 +#define regCOMPBUF_MEM_PWR_CTRL_2 0x04c2 +#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX 2 +#define regDCHUBBUB_MEM_PWR_STATUS 0x04c3 +#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 +#define regCOMPBUF_RESERVED_SPACE 0x04c4 +#define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec +// base address: 0x0 +#define regDCN_VM_CONTEXT0_CNTL 0x0559 +#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_CNTL 0x0560 +#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_CNTL 0x0567 +#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_CNTL 0x056e +#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_CNTL 0x0575 +#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_CNTL 0x057c +#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_CNTL 0x0583 +#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_CNTL 0x058a +#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_CNTL 0x0591 +#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_CNTL 0x0598 +#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_CNTL 0x059f +#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_CNTL 0x05a6 +#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_CNTL 0x05ad +#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_CNTL 0x05b4 +#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_CNTL 0x05bb +#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_CNTL 0x05c2 +#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_DEFAULT_ADDR_MSB 0x05c9 +#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 +#define regDCN_VM_DEFAULT_ADDR_LSB 0x05ca +#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 +#define regDCN_VM_FAULT_CNTL 0x05cb +#define regDCN_VM_FAULT_CNTL_BASE_IDX 2 +#define regDCN_VM_FAULT_STATUS 0x05cc +#define regDCN_VM_FAULT_STATUS_BASE_IDX 2 +#define regDCN_VM_FAULT_ADDR_MSB 0x05cd +#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 +#define regDCN_VM_FAULT_ADDR_LSB 0x05ce +#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec +// base address: 0x0 +#define regHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 +#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP0_DCSURF_ADDR_CONFIG 0x05e6 +#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP0_DCSURF_TILING_CONFIG 0x05e7 +#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 +#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb +#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed +#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef +#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP0_DCHUBP_CNTL 0x05f3 +#define regHUBP0_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP0_HUBP_CLK_CNTL 0x05f4 +#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 +#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP0_DCHUBP_MALL_CONFIG 0x05f6 +#define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX 2 +#define regHUBP0_DCHUBP_MALL_SUB_VP 0x05f7 +#define regHUBP0_DCHUBP_MALL_SUB_VP_BASE_IDX 2 +#define regHUBP0_HUBPREQ_DEBUG_DB 0x05f8 +#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP0_HUBPREQ_DEBUG 0x05f9 +#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fd +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fe +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 +#define regHUBP0_HUBP_MALL_STATUS 0x05ff +#define regHUBP0_HUBP_MALL_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec +// base address: 0x0 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ0_VMID_SETTINGS_0 0x0609 +#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a +#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b +#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c +#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x061f +#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE 0x0620 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0621 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0622 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0623 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0624 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0625 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0626 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0627 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCN_EXPANSION_MODE 0x0628 +#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ0_DCN_TTU_QOS_WM 0x0629 +#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062a +#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062b +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062c +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062d +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062e +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x062f +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0630 +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0631 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0632 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0633 +#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0634 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0635 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0642 +#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ0_BLANK_OFFSET_0 0x0643 +#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ0_BLANK_OFFSET_1 0x0644 +#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ0_DST_DIMENSIONS 0x0645 +#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ0_DST_AFTER_SCALER 0x0646 +#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ0_PREFETCH_SETTINGS 0x0647 +#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ0_PREFETCH_SETTINGS_C 0x0648 +#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_0 0x0649 +#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_1 0x064a +#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_2 0x064b +#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_3 0x064c +#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_4 0x064d +#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_0 0x064e +#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_1 0x064f +#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_2 0x0650 +#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_0 0x0651 +#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_1 0x0652 +#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_2 0x0653 +#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_3 0x0654 +#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_4 0x0655 +#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_5 0x0656 +#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_6 0x0657 +#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_7 0x0658 +#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ0_PER_LINE_DELIVERY_PRE 0x0659 +#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ0_PER_LINE_DELIVERY 0x065a +#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ0_CURSOR_SETTINGS 0x065b +#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065c +#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065d +#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065e +#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x065f +#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_5 0x0662 +#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_6 0x0663 +#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_3 0x0664 +#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_4 0x0665 +#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_5 0x0666 +#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_6 0x0667 +#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ0_UCLK_PSTATE_FORCE 0x0668 +#define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_STATUS_REG0 0x0669 +#define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_STATUS_REG1 0x066a +#define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_STATUS_REG2 0x066b +#define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec +// base address: 0x0 +#define regHUBPRET0_HUBPRET_CONTROL 0x066c +#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d +#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e +#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE0 0x0671 +#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE1 0x0672 +#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_INTERRUPT 0x0673 +#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 +#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 +#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec +// base address: 0x0 +#define regCURSOR0_0_CURSOR_CONTROL 0x0678 +#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_SIZE 0x067b +#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_POSITION 0x067c +#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_HOT_SPOT 0x067d +#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e +#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_DST_OFFSET 0x067f +#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 +#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 +#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 +#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 +#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_CNTL 0x0684 +#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_QOS_CNTL 0x0685 +#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_STATUS 0x0686 +#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_SW_CNTL 0x0687 +#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_SW_DATA 0x0688 +#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec +// base address: 0x370 +#define regHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 +#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP1_DCSURF_ADDR_CONFIG 0x06c2 +#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP1_DCSURF_TILING_CONFIG 0x06c3 +#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 +#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb +#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP1_DCHUBP_CNTL 0x06cf +#define regHUBP1_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP1_HUBP_CLK_CNTL 0x06d0 +#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 +#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP1_DCHUBP_MALL_CONFIG 0x06d2 +#define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX 2 +#define regHUBP1_DCHUBP_MALL_SUB_VP 0x06d3 +#define regHUBP1_DCHUBP_MALL_SUB_VP_BASE_IDX 2 +#define regHUBP1_HUBPREQ_DEBUG_DB 0x06d4 +#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP1_HUBPREQ_DEBUG 0x06d5 +#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d9 +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06da +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 +#define regHUBP1_HUBP_MALL_STATUS 0x06db +#define regHUBP1_HUBP_MALL_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec +// base address: 0x370 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ1_VMID_SETTINGS_0 0x06e5 +#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 +#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fb +#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fc +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fd +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06fe +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x06ff +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0700 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0701 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0702 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0703 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCN_EXPANSION_MODE 0x0704 +#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ1_DCN_TTU_QOS_WM 0x0705 +#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0706 +#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0707 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0708 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x0709 +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070a +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070b +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070c +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070d +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070e +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_DMDATA_VM_CNTL 0x070f +#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0710 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0711 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071e +#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ1_BLANK_OFFSET_0 0x071f +#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ1_BLANK_OFFSET_1 0x0720 +#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ1_DST_DIMENSIONS 0x0721 +#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ1_DST_AFTER_SCALER 0x0722 +#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ1_PREFETCH_SETTINGS 0x0723 +#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ1_PREFETCH_SETTINGS_C 0x0724 +#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_0 0x0725 +#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_1 0x0726 +#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_2 0x0727 +#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_3 0x0728 +#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_4 0x0729 +#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_0 0x072a +#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_1 0x072b +#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_2 0x072c +#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_0 0x072d +#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_1 0x072e +#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_2 0x072f +#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_3 0x0730 +#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_4 0x0731 +#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_5 0x0732 +#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_6 0x0733 +#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_7 0x0734 +#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0735 +#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ1_PER_LINE_DELIVERY 0x0736 +#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ1_CURSOR_SETTINGS 0x0737 +#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0738 +#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x0739 +#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073a +#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073b +#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_5 0x073e +#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_6 0x073f +#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_3 0x0740 +#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_4 0x0741 +#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_5 0x0742 +#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_6 0x0743 +#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ1_UCLK_PSTATE_FORCE 0x0744 +#define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_STATUS_REG0 0x0745 +#define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_STATUS_REG1 0x0746 +#define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_STATUS_REG2 0x0747 +#define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec +// base address: 0x370 +#define regHUBPRET1_HUBPRET_CONTROL 0x0748 +#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 +#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a +#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE0 0x074d +#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE1 0x074e +#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_INTERRUPT 0x074f +#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 +#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 +#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec +// base address: 0x370 +#define regCURSOR0_1_CURSOR_CONTROL 0x0754 +#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_SIZE 0x0757 +#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_POSITION 0x0758 +#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_HOT_SPOT 0x0759 +#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a +#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_DST_OFFSET 0x075b +#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c +#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d +#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e +#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f +#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_CNTL 0x0760 +#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_QOS_CNTL 0x0761 +#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_STATUS 0x0762 +#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_SW_CNTL 0x0763 +#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_SW_DATA 0x0764 +#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec +// base address: 0x6e0 +#define regHUBP2_DCSURF_SURFACE_CONFIG 0x079d +#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP2_DCSURF_ADDR_CONFIG 0x079e +#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP2_DCSURF_TILING_CONFIG 0x079f +#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP2_DCHUBP_CNTL 0x07ab +#define regHUBP2_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP2_HUBP_CLK_CNTL 0x07ac +#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP2_DCHUBP_VMPG_CONFIG 0x07ad +#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP2_DCHUBP_MALL_CONFIG 0x07ae +#define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX 2 +#define regHUBP2_DCHUBP_MALL_SUB_VP 0x07af +#define regHUBP2_DCHUBP_MALL_SUB_VP_BASE_IDX 2 +#define regHUBP2_HUBPREQ_DEBUG_DB 0x07b0 +#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP2_HUBPREQ_DEBUG 0x07b1 +#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b5 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b6 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 +#define regHUBP2_HUBP_MALL_STATUS 0x07b7 +#define regHUBP2_HUBP_MALL_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec +// base address: 0x6e0 +#define regHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf +#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 +#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ2_VMID_SETTINGS_0 0x07c1 +#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 +#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d7 +#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d8 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07d9 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07da +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07db +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dc +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07dd +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07de +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07df +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCN_EXPANSION_MODE 0x07e0 +#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ2_DCN_TTU_QOS_WM 0x07e1 +#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e2 +#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e3 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e4 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e5 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e6 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e7 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e8 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07e9 +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07ea +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07eb +#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ec +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ed +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fa +#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ2_BLANK_OFFSET_0 0x07fb +#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ2_BLANK_OFFSET_1 0x07fc +#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ2_DST_DIMENSIONS 0x07fd +#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ2_DST_AFTER_SCALER 0x07fe +#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ2_PREFETCH_SETTINGS 0x07ff +#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ2_PREFETCH_SETTINGS_C 0x0800 +#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_0 0x0801 +#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_1 0x0802 +#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_2 0x0803 +#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_3 0x0804 +#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_4 0x0805 +#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_0 0x0806 +#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_1 0x0807 +#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_2 0x0808 +#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_0 0x0809 +#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_1 0x080a +#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_2 0x080b +#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_3 0x080c +#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_4 0x080d +#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_5 0x080e +#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_6 0x080f +#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_7 0x0810 +#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0811 +#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ2_PER_LINE_DELIVERY 0x0812 +#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ2_CURSOR_SETTINGS 0x0813 +#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0814 +#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0815 +#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0816 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0817 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_5 0x081a +#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_6 0x081b +#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_3 0x081c +#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_4 0x081d +#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_5 0x081e +#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_6 0x081f +#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ2_UCLK_PSTATE_FORCE 0x0820 +#define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_STATUS_REG0 0x0821 +#define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_STATUS_REG1 0x0822 +#define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_STATUS_REG2 0x0823 +#define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec +// base address: 0x6e0 +#define regHUBPRET2_HUBPRET_CONTROL 0x0824 +#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 +#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 +#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE0 0x0829 +#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE1 0x082a +#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_INTERRUPT 0x082b +#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c +#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d +#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec +// base address: 0x6e0 +#define regCURSOR0_2_CURSOR_CONTROL 0x0830 +#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_SIZE 0x0833 +#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_POSITION 0x0834 +#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_HOT_SPOT 0x0835 +#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 +#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_DST_OFFSET 0x0837 +#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 +#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 +#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a +#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b +#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_CNTL 0x083c +#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_QOS_CNTL 0x083d +#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_STATUS 0x083e +#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_SW_CNTL 0x083f +#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_SW_DATA 0x0840 +#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec +// base address: 0xa50 +#define regHUBP3_DCSURF_SURFACE_CONFIG 0x0879 +#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP3_DCSURF_ADDR_CONFIG 0x087a +#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP3_DCSURF_TILING_CONFIG 0x087b +#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d +#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f +#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP3_DCHUBP_CNTL 0x0887 +#define regHUBP3_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP3_HUBP_CLK_CNTL 0x0888 +#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP3_DCHUBP_VMPG_CONFIG 0x0889 +#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP3_DCHUBP_MALL_CONFIG 0x088a +#define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX 2 +#define regHUBP3_DCHUBP_MALL_SUB_VP 0x088b +#define regHUBP3_DCHUBP_MALL_SUB_VP_BASE_IDX 2 +#define regHUBP3_HUBPREQ_DEBUG_DB 0x088c +#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP3_HUBPREQ_DEBUG 0x088d +#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0891 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0892 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 +#define regHUBP3_HUBP_MALL_STATUS 0x0893 +#define regHUBP3_HUBP_MALL_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec +// base address: 0xa50 +#define regHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b +#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c +#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ3_VMID_SETTINGS_0 0x089d +#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae +#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af +#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 +#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b3 +#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b4 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b5 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b6 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b7 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b8 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08b9 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08ba +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bb +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCN_EXPANSION_MODE 0x08bc +#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ3_DCN_TTU_QOS_WM 0x08bd +#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08be +#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08bf +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c0 +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c1 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c2 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c3 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c4 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c5 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c6 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c7 +#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c8 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08c9 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d6 +#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ3_BLANK_OFFSET_0 0x08d7 +#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ3_BLANK_OFFSET_1 0x08d8 +#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ3_DST_DIMENSIONS 0x08d9 +#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ3_DST_AFTER_SCALER 0x08da +#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ3_PREFETCH_SETTINGS 0x08db +#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ3_PREFETCH_SETTINGS_C 0x08dc +#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_0 0x08dd +#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_1 0x08de +#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_2 0x08df +#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_3 0x08e0 +#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_4 0x08e1 +#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_0 0x08e2 +#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_1 0x08e3 +#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_2 0x08e4 +#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_0 0x08e5 +#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_1 0x08e6 +#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_2 0x08e7 +#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_3 0x08e8 +#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_4 0x08e9 +#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_5 0x08ea +#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_6 0x08eb +#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_7 0x08ec +#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ed +#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ3_PER_LINE_DELIVERY 0x08ee +#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ3_CURSOR_SETTINGS 0x08ef +#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f0 +#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f1 +#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f2 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f3 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_5 0x08f6 +#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_6 0x08f7 +#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_3 0x08f8 +#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_4 0x08f9 +#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_5 0x08fa +#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_6 0x08fb +#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ3_UCLK_PSTATE_FORCE 0x08fc +#define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_STATUS_REG0 0x08fd +#define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_STATUS_REG1 0x08fe +#define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_STATUS_REG2 0x08ff +#define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec +// base address: 0xa50 +#define regHUBPRET3_HUBPRET_CONTROL 0x0900 +#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 +#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 +#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE0 0x0905 +#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE1 0x0906 +#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_INTERRUPT 0x0907 +#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 +#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 +#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec +// base address: 0xa50 +#define regCURSOR0_3_CURSOR_CONTROL 0x090c +#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_SIZE 0x090f +#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_POSITION 0x0910 +#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_HOT_SPOT 0x0911 +#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 +#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_DST_OFFSET 0x0913 +#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 +#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 +#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 +#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 +#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_CNTL 0x0918 +#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_QOS_CNTL 0x0919 +#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_STATUS 0x091a +#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_SW_CNTL 0x091b +#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_SW_DATA 0x091c +#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec +// base address: 0x0 +#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf +#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG0_FORMAT_CONTROL 0x0cd0 +#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 +#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 +#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 +#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 +#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 +#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 +#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 +#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 +#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 +#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda +#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb +#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd +#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 +#define regCNVC_CFG0_PRE_DEALPHA 0x0cde +#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_MODE 0x0cdf +#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0 +#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1 +#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2 +#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3 +#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4 +#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5 +#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6 +#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7 +#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8 +#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9 +#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea +#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb +#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec +#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG0_PRE_DEGAM 0x0ced +#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG0_PRE_REALPHA 0x0cee +#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec +// base address: 0x0 +#define regCNVC_CUR0_CURSOR0_CONTROL 0x0cf1 +#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 +#define regCNVC_CUR0_CURSOR0_COLOR0 0x0cf2 +#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 +#define regCNVC_CUR0_CURSOR0_COLOR1 0x0cf3 +#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 +#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4 +#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec +// base address: 0x0 +#define regDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9 +#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa +#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL0_SCL_MODE 0x0cfb +#define regDSCL0_SCL_MODE_BASE_IDX 2 +#define regDSCL0_SCL_TAP_CONTROL 0x0cfc +#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL0_DSCL_CONTROL 0x0cfd +#define regDSCL0_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL0_DSCL_2TAP_CONTROL 0x0cfe +#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff +#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00 +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_INIT 0x0d01 +#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02 +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03 +#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT 0x0d05 +#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08 +#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL0_SCL_BLACK_COLOR 0x0d0a +#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL0_DSCL_UPDATE 0x0d0b +#define regDSCL0_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL0_DSCL_AUTOCAL 0x0d0c +#define regDSCL0_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d +#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e +#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL0_OTG_H_BLANK 0x0d0f +#define regDSCL0_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL0_OTG_V_BLANK 0x0d10 +#define regDSCL0_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL0_RECOUT_START 0x0d11 +#define regDSCL0_RECOUT_START_BASE_IDX 2 +#define regDSCL0_RECOUT_SIZE 0x0d12 +#define regDSCL0_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL0_MPC_SIZE 0x0d13 +#define regDSCL0_MPC_SIZE_BASE_IDX 2 +#define regDSCL0_LB_DATA_FORMAT 0x0d14 +#define regDSCL0_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL0_LB_MEMORY_CTRL 0x0d15 +#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL0_LB_V_COUNTER 0x0d16 +#define regDSCL0_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL0_DSCL_MEM_PWR_CTRL 0x0d17 +#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL0_DSCL_MEM_PWR_STATUS 0x0d18 +#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL0_OBUF_CONTROL 0x0d19 +#define regDSCL0_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a +#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec +// base address: 0x0 +#define regCM0_CM_CONTROL 0x0d20 +#define regCM0_CM_CONTROL_BASE_IDX 2 +#define regCM0_CM_POST_CSC_CONTROL 0x0d21 +#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C11_C12 0x0d22 +#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C13_C14 0x0d23 +#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C21_C22 0x0d24 +#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C23_C24 0x0d25 +#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C31_C32 0x0d26 +#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C33_C34 0x0d27 +#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C11_C12 0x0d28 +#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C13_C14 0x0d29 +#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C21_C22 0x0d2a +#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C23_C24 0x0d2b +#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C31_C32 0x0d2c +#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C33_C34 0x0d2d +#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e +#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f +#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_C13_C14 0x0d30 +#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_C21_C22 0x0d31 +#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_C23_C24 0x0d32 +#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_C31_C32 0x0d33 +#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_C33_C34 0x0d34 +#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35 +#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36 +#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37 +#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38 +#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39 +#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a +#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 +#define regCM0_CM_BIAS_CR_R 0x0d3b +#define regCM0_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM0_CM_BIAS_Y_G_CB_B 0x0d3c +#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_CONTROL 0x0d3d +#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM0_CM_GAMCOR_LUT_INDEX 0x0d3e +#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM0_CM_GAMCOR_LUT_DATA 0x0d3f +#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM0_CM_GAMCOR_LUT_CONTROL 0x0d40 +#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53 +#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54 +#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55 +#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56 +#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57 +#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58 +#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59 +#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a +#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b +#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c +#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d +#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e +#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f +#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60 +#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61 +#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62 +#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63 +#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76 +#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77 +#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78 +#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79 +#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a +#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b +#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c +#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d +#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e +#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f +#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80 +#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81 +#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82 +#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83 +#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84 +#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85 +#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86 +#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM0_CM_HDR_MULT_COEF 0x0d87 +#define regCM0_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM0_CM_MEM_PWR_CTRL 0x0d88 +#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM0_CM_MEM_PWR_STATUS 0x0d89 +#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM0_CM_DEALPHA 0x0d8b +#define regCM0_CM_DEALPHA_BASE_IDX 2 +#define regCM0_CM_COEF_FORMAT 0x0d8c +#define regCM0_CM_COEF_FORMAT_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec +// base address: 0x0 +#define regDPP_TOP0_DPP_CONTROL 0x0cc5 +#define regDPP_TOP0_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP0_DPP_SOFT_RESET 0x0cc6 +#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 +#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 +#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_CTRL 0x0cc9 +#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP0_HOST_READ_CONTROL 0x0cca +#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec +// base address: 0x5ac +#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a +#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG1_FORMAT_CONTROL 0x0e3b +#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c +#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d +#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e +#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f +#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 +#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 +#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 +#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 +#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_RED 0x0e44 +#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 +#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 +#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 +#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 +#define regCNVC_CFG1_PRE_DEALPHA 0x0e49 +#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_MODE 0x0e4a +#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b +#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c +#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d +#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e +#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f +#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C33_C34 0x0e50 +#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51 +#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52 +#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53 +#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54 +#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55 +#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56 +#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57 +#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG1_PRE_DEGAM 0x0e58 +#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG1_PRE_REALPHA 0x0e59 +#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec +// base address: 0x5ac +#define regCNVC_CUR1_CURSOR0_CONTROL 0x0e5c +#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 +#define regCNVC_CUR1_CURSOR0_COLOR0 0x0e5d +#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 +#define regCNVC_CUR1_CURSOR0_COLOR1 0x0e5e +#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 +#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f +#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec +// base address: 0x5ac +#define regDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64 +#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65 +#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL1_SCL_MODE 0x0e66 +#define regDSCL1_SCL_MODE_BASE_IDX 2 +#define regDSCL1_SCL_TAP_CONTROL 0x0e67 +#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL1_DSCL_CONTROL 0x0e68 +#define regDSCL1_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL1_DSCL_2TAP_CONTROL 0x0e69 +#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a +#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c +#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e +#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT 0x0e70 +#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72 +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73 +#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL1_SCL_BLACK_COLOR 0x0e75 +#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL1_DSCL_UPDATE 0x0e76 +#define regDSCL1_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL1_DSCL_AUTOCAL 0x0e77 +#define regDSCL1_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78 +#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79 +#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL1_OTG_H_BLANK 0x0e7a +#define regDSCL1_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL1_OTG_V_BLANK 0x0e7b +#define regDSCL1_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL1_RECOUT_START 0x0e7c +#define regDSCL1_RECOUT_START_BASE_IDX 2 +#define regDSCL1_RECOUT_SIZE 0x0e7d +#define regDSCL1_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL1_MPC_SIZE 0x0e7e +#define regDSCL1_MPC_SIZE_BASE_IDX 2 +#define regDSCL1_LB_DATA_FORMAT 0x0e7f +#define regDSCL1_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL1_LB_MEMORY_CTRL 0x0e80 +#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL1_LB_V_COUNTER 0x0e81 +#define regDSCL1_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL1_DSCL_MEM_PWR_CTRL 0x0e82 +#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL1_DSCL_MEM_PWR_STATUS 0x0e83 +#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL1_OBUF_CONTROL 0x0e84 +#define regDSCL1_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL1_OBUF_MEM_PWR_CTRL 0x0e85 +#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec +// base address: 0x5ac +#define regCM1_CM_CONTROL 0x0e8b +#define regCM1_CM_CONTROL_BASE_IDX 2 +#define regCM1_CM_POST_CSC_CONTROL 0x0e8c +#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C11_C12 0x0e8d +#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C13_C14 0x0e8e +#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C21_C22 0x0e8f +#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C23_C24 0x0e90 +#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C31_C32 0x0e91 +#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C33_C34 0x0e92 +#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C11_C12 0x0e93 +#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C13_C14 0x0e94 +#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C21_C22 0x0e95 +#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C23_C24 0x0e96 +#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C31_C32 0x0e97 +#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C33_C34 0x0e98 +#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_CONTROL 0x0e99 +#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a +#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b +#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c +#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d +#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e +#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f +#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0 +#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1 +#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2 +#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3 +#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4 +#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5 +#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 +#define regCM1_CM_BIAS_CR_R 0x0ea6 +#define regCM1_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM1_CM_BIAS_Y_G_CB_B 0x0ea7 +#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_CONTROL 0x0ea8 +#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM1_CM_GAMCOR_LUT_INDEX 0x0ea9 +#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM1_CM_GAMCOR_LUT_DATA 0x0eaa +#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM1_CM_GAMCOR_LUT_CONTROL 0x0eab +#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb +#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc +#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd +#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe +#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf +#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0 +#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1 +#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2 +#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3 +#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4 +#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5 +#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6 +#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7 +#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8 +#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9 +#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca +#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb +#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc +#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd +#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece +#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede +#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf +#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0 +#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1 +#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2 +#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3 +#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4 +#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5 +#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6 +#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7 +#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8 +#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9 +#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea +#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb +#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec +#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed +#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee +#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef +#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0 +#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1 +#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM1_CM_HDR_MULT_COEF 0x0ef2 +#define regCM1_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM1_CM_MEM_PWR_CTRL 0x0ef3 +#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM1_CM_MEM_PWR_STATUS 0x0ef4 +#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM1_CM_DEALPHA 0x0ef6 +#define regCM1_CM_DEALPHA_BASE_IDX 2 +#define regCM1_CM_COEF_FORMAT 0x0ef7 +#define regCM1_CM_COEF_FORMAT_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec +// base address: 0x5ac +#define regDPP_TOP1_DPP_CONTROL 0x0e30 +#define regDPP_TOP1_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP1_DPP_SOFT_RESET 0x0e31 +#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 +#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 +#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_CTRL 0x0e34 +#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP1_HOST_READ_CONTROL 0x0e35 +#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec +// base address: 0xb58 +#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 +#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG2_FORMAT_CONTROL 0x0fa6 +#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 +#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 +#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 +#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa +#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab +#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac +#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad +#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae +#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_RED 0x0faf +#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 +#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 +#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 +#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 +#define regCNVC_CFG2_PRE_DEALPHA 0x0fb4 +#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_MODE 0x0fb5 +#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6 +#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7 +#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8 +#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9 +#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C31_C32 0x0fba +#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb +#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc +#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd +#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe +#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf +#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0 +#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1 +#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2 +#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG2_PRE_DEGAM 0x0fc3 +#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG2_PRE_REALPHA 0x0fc4 +#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec +// base address: 0xb58 +#define regCNVC_CUR2_CURSOR0_CONTROL 0x0fc7 +#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 +#define regCNVC_CUR2_CURSOR0_COLOR0 0x0fc8 +#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 +#define regCNVC_CUR2_CURSOR0_COLOR1 0x0fc9 +#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 +#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fca +#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec +// base address: 0xb58 +#define regDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fcf +#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fd0 +#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL2_SCL_MODE 0x0fd1 +#define regDSCL2_SCL_MODE_BASE_IDX 2 +#define regDSCL2_SCL_TAP_CONTROL 0x0fd2 +#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL2_DSCL_CONTROL 0x0fd3 +#define regDSCL2_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL2_DSCL_2TAP_CONTROL 0x0fd4 +#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fd5 +#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fd6 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_INIT 0x0fd7 +#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fd8 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fd9 +#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fda +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT 0x0fdb +#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fdc +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fdd +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT_C 0x0fde +#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fdf +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL2_SCL_BLACK_COLOR 0x0fe0 +#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL2_DSCL_UPDATE 0x0fe1 +#define regDSCL2_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL2_DSCL_AUTOCAL 0x0fe2 +#define regDSCL2_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fe3 +#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fe4 +#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL2_OTG_H_BLANK 0x0fe5 +#define regDSCL2_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL2_OTG_V_BLANK 0x0fe6 +#define regDSCL2_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL2_RECOUT_START 0x0fe7 +#define regDSCL2_RECOUT_START_BASE_IDX 2 +#define regDSCL2_RECOUT_SIZE 0x0fe8 +#define regDSCL2_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL2_MPC_SIZE 0x0fe9 +#define regDSCL2_MPC_SIZE_BASE_IDX 2 +#define regDSCL2_LB_DATA_FORMAT 0x0fea +#define regDSCL2_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL2_LB_MEMORY_CTRL 0x0feb +#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL2_LB_V_COUNTER 0x0fec +#define regDSCL2_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL2_DSCL_MEM_PWR_CTRL 0x0fed +#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL2_DSCL_MEM_PWR_STATUS 0x0fee +#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL2_OBUF_CONTROL 0x0fef +#define regDSCL2_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL2_OBUF_MEM_PWR_CTRL 0x0ff0 +#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec +// base address: 0xb58 +#define regCM2_CM_CONTROL 0x0ff6 +#define regCM2_CM_CONTROL_BASE_IDX 2 +#define regCM2_CM_POST_CSC_CONTROL 0x0ff7 +#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C11_C12 0x0ff8 +#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C13_C14 0x0ff9 +#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C21_C22 0x0ffa +#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C23_C24 0x0ffb +#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C31_C32 0x0ffc +#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C33_C34 0x0ffd +#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C11_C12 0x0ffe +#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C13_C14 0x0fff +#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C21_C22 0x1000 +#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C23_C24 0x1001 +#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C31_C32 0x1002 +#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C33_C34 0x1003 +#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_CONTROL 0x1004 +#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_C11_C12 0x1005 +#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_C13_C14 0x1006 +#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_C21_C22 0x1007 +#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_C23_C24 0x1008 +#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_C31_C32 0x1009 +#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_C33_C34 0x100a +#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_B_C11_C12 0x100b +#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_B_C13_C14 0x100c +#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_B_C21_C22 0x100d +#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_B_C23_C24 0x100e +#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_B_C31_C32 0x100f +#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_B_C33_C34 0x1010 +#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 +#define regCM2_CM_BIAS_CR_R 0x1011 +#define regCM2_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM2_CM_BIAS_Y_G_CB_B 0x1012 +#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_CONTROL 0x1013 +#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM2_CM_GAMCOR_LUT_INDEX 0x1014 +#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM2_CM_GAMCOR_LUT_DATA 0x1015 +#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM2_CM_GAMCOR_LUT_CONTROL 0x1016 +#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1017 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1018 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1019 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x101a +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x101b +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x101c +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x101d +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x101e +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x101f +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x1020 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x1021 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x1022 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x1023 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1024 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1025 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1026 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1027 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1028 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1029 +#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_2_3 0x102a +#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_4_5 0x102b +#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_6_7 0x102c +#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_8_9 0x102d +#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_10_11 0x102e +#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_12_13 0x102f +#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_14_15 0x1030 +#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_16_17 0x1031 +#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_18_19 0x1032 +#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_20_21 0x1033 +#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1034 +#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1035 +#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1036 +#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1037 +#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1038 +#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1039 +#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x103a +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x103b +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x103c +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x103d +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x103e +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x103f +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1040 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1041 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1042 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x1043 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1044 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1045 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1046 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1047 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1048 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1049 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_G 0x104a +#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_R 0x104b +#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_0_1 0x104c +#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_2_3 0x104d +#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_4_5 0x104e +#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_6_7 0x104f +#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_8_9 0x1050 +#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_10_11 0x1051 +#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_12_13 0x1052 +#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_14_15 0x1053 +#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1054 +#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1055 +#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1056 +#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1057 +#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1058 +#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1059 +#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_28_29 0x105a +#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_30_31 0x105b +#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_32_33 0x105c +#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM2_CM_HDR_MULT_COEF 0x105d +#define regCM2_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM2_CM_MEM_PWR_CTRL 0x105e +#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM2_CM_MEM_PWR_STATUS 0x105f +#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM2_CM_DEALPHA 0x1061 +#define regCM2_CM_DEALPHA_BASE_IDX 2 +#define regCM2_CM_COEF_FORMAT 0x1062 +#define regCM2_CM_COEF_FORMAT_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec +// base address: 0xb58 +#define regDPP_TOP2_DPP_CONTROL 0x0f9b +#define regDPP_TOP2_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP2_DPP_SOFT_RESET 0x0f9c +#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d +#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e +#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_CTRL 0x0f9f +#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP2_HOST_READ_CONTROL 0x0fa0 +#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec +// base address: 0x1104 +#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 +#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG3_FORMAT_CONTROL 0x1111 +#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 +#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 +#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 +#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 +#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 +#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 +#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 +#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 +#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_RED 0x111a +#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_GREEN 0x111b +#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_BLUE 0x111c +#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG3_ALPHA_2BIT_LUT 0x111e +#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 +#define regCNVC_CFG3_PRE_DEALPHA 0x111f +#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_MODE 0x1120 +#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C11_C12 0x1121 +#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C13_C14 0x1122 +#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C21_C22 0x1123 +#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C23_C24 0x1124 +#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C31_C32 0x1125 +#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C33_C34 0x1126 +#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127 +#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128 +#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129 +#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a +#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b +#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c +#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG3_CNVC_COEF_FORMAT 0x112d +#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG3_PRE_DEGAM 0x112e +#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG3_PRE_REALPHA 0x112f +#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec +// base address: 0x1104 +#define regCNVC_CUR3_CURSOR0_CONTROL 0x1132 +#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 +#define regCNVC_CUR3_CURSOR0_COLOR0 0x1133 +#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 +#define regCNVC_CUR3_CURSOR0_COLOR1 0x1134 +#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 +#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1135 +#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec +// base address: 0x1104 +#define regDSCL3_SCL_COEF_RAM_TAP_SELECT 0x113a +#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL3_SCL_COEF_RAM_TAP_DATA 0x113b +#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL3_SCL_MODE 0x113c +#define regDSCL3_SCL_MODE_BASE_IDX 2 +#define regDSCL3_SCL_TAP_CONTROL 0x113d +#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL3_DSCL_CONTROL 0x113e +#define regDSCL3_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL3_DSCL_2TAP_CONTROL 0x113f +#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1140 +#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1141 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_INIT 0x1142 +#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1143 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_INIT_C 0x1144 +#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1145 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT 0x1146 +#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1147 +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1148 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT_C 0x1149 +#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x114a +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL3_SCL_BLACK_COLOR 0x114b +#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL3_DSCL_UPDATE 0x114c +#define regDSCL3_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL3_DSCL_AUTOCAL 0x114d +#define regDSCL3_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x114e +#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x114f +#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL3_OTG_H_BLANK 0x1150 +#define regDSCL3_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL3_OTG_V_BLANK 0x1151 +#define regDSCL3_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL3_RECOUT_START 0x1152 +#define regDSCL3_RECOUT_START_BASE_IDX 2 +#define regDSCL3_RECOUT_SIZE 0x1153 +#define regDSCL3_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL3_MPC_SIZE 0x1154 +#define regDSCL3_MPC_SIZE_BASE_IDX 2 +#define regDSCL3_LB_DATA_FORMAT 0x1155 +#define regDSCL3_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL3_LB_MEMORY_CTRL 0x1156 +#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL3_LB_V_COUNTER 0x1157 +#define regDSCL3_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL3_DSCL_MEM_PWR_CTRL 0x1158 +#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL3_DSCL_MEM_PWR_STATUS 0x1159 +#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL3_OBUF_CONTROL 0x115a +#define regDSCL3_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL3_OBUF_MEM_PWR_CTRL 0x115b +#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec +// base address: 0x1104 +#define regCM3_CM_CONTROL 0x1161 +#define regCM3_CM_CONTROL_BASE_IDX 2 +#define regCM3_CM_POST_CSC_CONTROL 0x1162 +#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C11_C12 0x1163 +#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C13_C14 0x1164 +#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C21_C22 0x1165 +#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C23_C24 0x1166 +#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C31_C32 0x1167 +#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C33_C34 0x1168 +#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C11_C12 0x1169 +#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C13_C14 0x116a +#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C21_C22 0x116b +#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C23_C24 0x116c +#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C31_C32 0x116d +#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C33_C34 0x116e +#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_CONTROL 0x116f +#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_C11_C12 0x1170 +#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_C13_C14 0x1171 +#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_C21_C22 0x1172 +#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_C23_C24 0x1173 +#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_C31_C32 0x1174 +#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_C33_C34 0x1175 +#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_B_C11_C12 0x1176 +#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_B_C13_C14 0x1177 +#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_B_C21_C22 0x1178 +#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_B_C23_C24 0x1179 +#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_B_C31_C32 0x117a +#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_B_C33_C34 0x117b +#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 +#define regCM3_CM_BIAS_CR_R 0x117c +#define regCM3_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM3_CM_BIAS_Y_G_CB_B 0x117d +#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_CONTROL 0x117e +#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM3_CM_GAMCOR_LUT_INDEX 0x117f +#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM3_CM_GAMCOR_LUT_DATA 0x1180 +#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM3_CM_GAMCOR_LUT_CONTROL 0x1181 +#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x1182 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x1183 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x1184 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1185 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1186 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1187 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1188 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1189 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x118a +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x118b +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x118c +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x118d +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x118e +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x118f +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x1190 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_B 0x1191 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_G 0x1192 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_R 0x1193 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_0_1 0x1194 +#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_2_3 0x1195 +#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_4_5 0x1196 +#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_6_7 0x1197 +#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_8_9 0x1198 +#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_10_11 0x1199 +#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_12_13 0x119a +#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_14_15 0x119b +#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_16_17 0x119c +#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_18_19 0x119d +#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_20_21 0x119e +#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_22_23 0x119f +#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11a0 +#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11a1 +#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11a2 +#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11a3 +#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11a4 +#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11a5 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11a6 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11a7 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11a8 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11a9 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11aa +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11ab +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11ac +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11ad +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ae +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11af +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11b0 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11b1 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11b2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11b3 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11b4 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11b5 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11b6 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11b7 +#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11b8 +#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11b9 +#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11ba +#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11bb +#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11bc +#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11bd +#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11be +#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11bf +#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11c0 +#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11c1 +#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11c2 +#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11c3 +#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11c4 +#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11c5 +#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_30_31 0x11c6 +#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_32_33 0x11c7 +#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM3_CM_HDR_MULT_COEF 0x11c8 +#define regCM3_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM3_CM_MEM_PWR_CTRL 0x11c9 +#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM3_CM_MEM_PWR_STATUS 0x11ca +#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM3_CM_DEALPHA 0x11cc +#define regCM3_CM_DEALPHA_BASE_IDX 2 +#define regCM3_CM_COEF_FORMAT 0x11cd +#define regCM3_CM_COEF_FORMAT_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec +// base address: 0x1104 +#define regDPP_TOP3_DPP_CONTROL 0x1106 +#define regDPP_TOP3_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP3_DPP_SOFT_RESET 0x1107 +#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_VAL_R_G 0x1108 +#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_VAL_B_A 0x1109 +#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_CTRL 0x110a +#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP3_HOST_READ_CONTROL 0x110b +#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc0_dispdec +// base address: 0x0 +#define regMPCC0_MPCC_TOP_SEL 0x0000 +#define regMPCC0_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC0_MPCC_BOT_SEL 0x0001 +#define regMPCC0_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC0_MPCC_OPP_ID 0x0002 +#define regMPCC0_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC0_MPCC_CONTROL 0x0003 +#define regMPCC0_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC0_MPCC_SM_CONTROL 0x0004 +#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005 +#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC0_MPCC_TOP_GAIN 0x0006 +#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007 +#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008 +#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0009 +#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 +#define regMPCC0_MPCC_BG_R_CR 0x000a +#define regMPCC0_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC0_MPCC_BG_G_Y 0x000b +#define regMPCC0_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC0_MPCC_BG_B_CB 0x000c +#define regMPCC0_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC0_MPCC_MEM_PWR_CTRL 0x000d +#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC0_MPCC_STATUS 0x000e +#define regMPCC0_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc1_dispdec +// base address: 0x54 +#define regMPCC1_MPCC_TOP_SEL 0x0015 +#define regMPCC1_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC1_MPCC_BOT_SEL 0x0016 +#define regMPCC1_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC1_MPCC_OPP_ID 0x0017 +#define regMPCC1_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC1_MPCC_CONTROL 0x0018 +#define regMPCC1_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC1_MPCC_SM_CONTROL 0x0019 +#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC1_MPCC_UPDATE_LOCK_SEL 0x001a +#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC1_MPCC_TOP_GAIN 0x001b +#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC1_MPCC_BOT_GAIN_INSIDE 0x001c +#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x001d +#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x001e +#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 +#define regMPCC1_MPCC_BG_R_CR 0x001f +#define regMPCC1_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC1_MPCC_BG_G_Y 0x0020 +#define regMPCC1_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC1_MPCC_BG_B_CB 0x0021 +#define regMPCC1_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC1_MPCC_MEM_PWR_CTRL 0x0022 +#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC1_MPCC_STATUS 0x0023 +#define regMPCC1_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc2_dispdec +// base address: 0xa8 +#define regMPCC2_MPCC_TOP_SEL 0x002a +#define regMPCC2_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC2_MPCC_BOT_SEL 0x002b +#define regMPCC2_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC2_MPCC_OPP_ID 0x002c +#define regMPCC2_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC2_MPCC_CONTROL 0x002d +#define regMPCC2_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC2_MPCC_SM_CONTROL 0x002e +#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC2_MPCC_UPDATE_LOCK_SEL 0x002f +#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC2_MPCC_TOP_GAIN 0x0030 +#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC2_MPCC_BOT_GAIN_INSIDE 0x0031 +#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0032 +#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0033 +#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 +#define regMPCC2_MPCC_BG_R_CR 0x0034 +#define regMPCC2_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC2_MPCC_BG_G_Y 0x0035 +#define regMPCC2_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC2_MPCC_BG_B_CB 0x0036 +#define regMPCC2_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC2_MPCC_MEM_PWR_CTRL 0x0037 +#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC2_MPCC_STATUS 0x0038 +#define regMPCC2_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc3_dispdec +// base address: 0xfc +#define regMPCC3_MPCC_TOP_SEL 0x003f +#define regMPCC3_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC3_MPCC_BOT_SEL 0x0040 +#define regMPCC3_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC3_MPCC_OPP_ID 0x0041 +#define regMPCC3_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC3_MPCC_CONTROL 0x0042 +#define regMPCC3_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC3_MPCC_SM_CONTROL 0x0043 +#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC3_MPCC_UPDATE_LOCK_SEL 0x0044 +#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC3_MPCC_TOP_GAIN 0x0045 +#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC3_MPCC_BOT_GAIN_INSIDE 0x0046 +#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0047 +#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0048 +#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 +#define regMPCC3_MPCC_BG_R_CR 0x0049 +#define regMPCC3_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC3_MPCC_BG_G_Y 0x004a +#define regMPCC3_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC3_MPCC_BG_B_CB 0x004b +#define regMPCC3_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC3_MPCC_MEM_PWR_CTRL 0x004c +#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC3_MPCC_STATUS 0x004d +#define regMPCC3_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_cfg_dispdec +// base address: 0x0 +#define regMPC_CLOCK_CONTROL 0x0398 +#define regMPC_CLOCK_CONTROL_BASE_IDX 3 +#define regMPC_SOFT_RESET 0x0399 +#define regMPC_SOFT_RESET_BASE_IDX 3 +#define regMPC_CRC_CTRL 0x039a +#define regMPC_CRC_CTRL_BASE_IDX 3 +#define regMPC_CRC_SEL_CONTROL 0x039b +#define regMPC_CRC_SEL_CONTROL_BASE_IDX 3 +#define regMPC_CRC_RESULT_AR 0x039c +#define regMPC_CRC_RESULT_AR_BASE_IDX 3 +#define regMPC_CRC_RESULT_GB 0x039d +#define regMPC_CRC_RESULT_GB_BASE_IDX 3 +#define regMPC_CRC_RESULT_C 0x039e +#define regMPC_CRC_RESULT_C_BASE_IDX 3 +#define regMPC_BYPASS_BG_AR 0x03a2 +#define regMPC_BYPASS_BG_AR_BASE_IDX 3 +#define regMPC_BYPASS_BG_GB 0x03a3 +#define regMPC_BYPASS_BG_GB_BASE_IDX 3 +#define regMPC_HOST_READ_CONTROL 0x03a4 +#define regMPC_HOST_READ_CONTROL_BASE_IDX 3 +#define regMPC_DPP_PENDING_STATUS 0x03a5 +#define regMPC_DPP_PENDING_STATUS_BASE_IDX 3 +#define regMPC_PENDING_STATUS_MISC 0x03a6 +#define regMPC_PENDING_STATUS_MISC_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET0 0x03a7 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET0 0x03a8 +#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET0 0x03a9 +#define regADR_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET0 0x03aa +#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET0 0x03ab +#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET1 0x03ac +#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET1 0x03ad +#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET1 0x03ae +#define regADR_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET1 0x03af +#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET1 0x03b0 +#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET2 0x03b1 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET2 0x03b2 +#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET2 0x03b3 +#define regADR_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET2 0x03b4 +#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET2 0x03b5 +#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET3 0x03b6 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET3 0x03b7 +#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET3 0x03b8 +#define regADR_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET3 0x03b9 +#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET3 0x03ba +#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regMPC_DWB0_MUX 0x03c6 +#define regMPC_DWB0_MUX_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec +// base address: 0x0 +#define regMPCC_OGAM0_MPCC_OGAM_CONTROL 0x00a8 +#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x00a9 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x00aa +#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x00ab +#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x00ac +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x00ad +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x00ae +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x00af +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x00b0 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x00b1 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x00b2 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x00b3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x00b4 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x00b5 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x00b6 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x00b7 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x00b8 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x00b9 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x00ba +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x00bb +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x00bc +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x00bd +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x00be +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x00bf +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x00c0 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x00c1 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x00c2 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x00c3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x00c4 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x00c5 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x00c6 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x00c7 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x00c8 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x00c9 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x00ca +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x00cb +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x00cc +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x00cd +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x00ce +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x00cf +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x00d0 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x00d1 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x00d2 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x00d3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x00d4 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x00d5 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x00d6 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x00d7 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x00d8 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x00d9 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x00da +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x00db +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x00dc +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x00dd +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x00de +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x00df +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x00e0 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x00e1 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x00e2 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x00e3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x00e4 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x00e5 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x00e6 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x00e7 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x00e8 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x00e9 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x00ea +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x00eb +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x00ec +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x00ed +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x00ee +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x00ef +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x00f0 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x00f1 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x00f2 +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x00f3 +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x00f4 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x00f5 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x00f6 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x00f7 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x00f8 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x00f9 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x00fa +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x00fb +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x00fc +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x00fd +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x00fe +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x00ff +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec +// base address: 0x178 +#define regMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0106 +#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0107 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0108 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0109 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x010a +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x010b +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x010c +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x010d +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x010e +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x010f +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x0110 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x0111 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x0112 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x0113 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x0114 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x0115 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0116 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0117 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0118 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0119 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x011a +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x011b +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x011c +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x011d +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x011e +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x011f +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x0120 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x0121 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x0122 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x0123 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x0124 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x0125 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x0126 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x0127 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x0128 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x0129 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x012a +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x012b +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x012c +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x012d +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x012e +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x012f +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x0130 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x0131 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0132 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0133 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x0134 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x0135 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x0136 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x0137 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x0138 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x0139 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x013a +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x013b +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x013c +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x013d +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x013e +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x013f +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x0140 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x0141 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x0142 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x0143 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x0144 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x0145 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x0146 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x0147 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x0148 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x0149 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x014a +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x014b +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x014c +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x014d +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x014e +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x014f +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x0150 +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x0151 +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x0152 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x0153 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x0154 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x0155 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x0156 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x0157 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x0158 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x0159 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x015a +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x015b +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x015c +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x015d +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec +// base address: 0x2f0 +#define regMPCC_OGAM2_MPCC_OGAM_CONTROL 0x0164 +#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x0165 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x0166 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x0167 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x0168 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x0169 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x016a +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x016b +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x016c +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x016d +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x016e +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x016f +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x0170 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x0171 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x0172 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x0173 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x0174 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x0175 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x0176 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x0177 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x0178 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x0179 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x017a +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x017b +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x017c +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x017d +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x017e +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x017f +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x0180 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x0181 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x0182 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x0183 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x0184 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x0185 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x0186 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x0187 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x0188 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x0189 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x018a +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x018b +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x018c +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x018d +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x018e +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x018f +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0190 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0191 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x0192 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x0193 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x0194 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x0195 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x0196 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x0197 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x0198 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x0199 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x019a +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x019b +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x019c +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x019d +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x019e +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x019f +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x01a0 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x01a1 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x01a2 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x01a3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x01a4 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x01a5 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x01a6 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x01a7 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x01a8 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x01a9 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x01aa +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x01ab +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x01ac +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x01ad +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ae +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x01af +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x01b0 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x01b1 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x01b2 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x01b3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x01b4 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x01b5 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x01b6 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x01b7 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x01b8 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x01b9 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x01ba +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x01bb +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec +// base address: 0x468 +#define regMPCC_OGAM3_MPCC_OGAM_CONTROL 0x01c2 +#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x01c3 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x01c4 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x01c5 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x01c6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x01c7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x01c8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x01c9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x01ca +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x01cb +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x01cc +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x01cd +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x01ce +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x01cf +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x01d0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x01d1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x01d2 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x01d3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x01d4 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x01d5 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x01d6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x01d7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x01d8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x01d9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x01da +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x01db +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x01dc +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x01dd +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x01de +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x01df +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x01e0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x01e1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x01e2 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x01e3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x01e4 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x01e5 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x01e6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x01e7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x01e8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x01e9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x01ea +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x01eb +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01ec +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ed +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ee +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ef +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01f0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01f1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x01f2 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x01f3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x01f4 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x01f5 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x01f6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x01f7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x01f8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x01f9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x01fa +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x01fb +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x01fc +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x01fd +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x01fe +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x01ff +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x0200 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x0201 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x0202 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x0203 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x0204 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x0205 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x0206 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x0207 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x0208 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x0209 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x020a +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x020b +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x020c +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x020d +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x020e +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x020f +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x0210 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x0211 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x0212 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x0213 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x0214 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x0215 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x0216 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x0217 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x0218 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x0219 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_mcm0_dispdec +// base address: 0x0 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL 0x0453 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R 0x0454 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G 0x0455 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B 0x0456 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R 0x0457 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B 0x0458 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX 0x0459 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA 0x045a +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x045b +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x045c +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x045d +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x045e +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x045f +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0460 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0461 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0462 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0463 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0464 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0465 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0466 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0467 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0468 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0469 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x046a +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x046b +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x046c +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x046d +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x046e +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x046f +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0470 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0471 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0472 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0473 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0474 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0475 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0476 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0477 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0478 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0479 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x047a +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x047b +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x047c +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x047d +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x047e +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x047f +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0480 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0481 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0482 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0483 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0484 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0485 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0486 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0487 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0488 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0489 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE 0x048a +#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX 0x048b +#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA 0x048c +#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT 0x048d +#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x048e +#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x048f +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0490 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0491 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0492 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL 0x0493 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX 0x0494 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA 0x0495 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL 0x0496 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0497 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0498 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0499 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x049a +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x049b +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x049c +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x049d +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x049e +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x049f +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x04a0 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x04a1 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x04a2 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x04a3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x04a4 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x04a5 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x04a6 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x04a7 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x04a8 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x04a9 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x04aa +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x04ab +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x04ac +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x04ad +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x04ae +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x04af +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x04b0 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x04b1 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x04b2 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x04b3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x04b4 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x04b5 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x04b6 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x04b7 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x04b8 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x04b9 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x04ba +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x04bb +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x04bc +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x04bd +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x04be +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x04bf +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x04c0 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x04c1 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x04c2 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x04c3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x04c4 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x04c5 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x04c6 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x04c7 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x04c8 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x04c9 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x04ca +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x04cb +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x04cc +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x04cd +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x04ce +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x04cf +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x04d0 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x04d1 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x04d2 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x04d3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x04d4 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x04d5 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x04d6 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x04d7 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x04d8 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x04d9 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x04da +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x04db +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x04dc +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL 0x04dd +#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_mcm1_dispdec +// base address: 0x240 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL 0x04e3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R 0x04e4 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G 0x04e5 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B 0x04e6 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R 0x04e7 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B 0x04e8 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX 0x04e9 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA 0x04ea +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x04eb +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x04ec +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x04ed +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x04ee +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x04ef +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x04f0 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x04f1 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x04f2 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x04f3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x04f4 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x04f5 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x04f6 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x04f7 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x04f8 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x04f9 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x04fa +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x04fb +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x04fc +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x04fd +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x04fe +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x04ff +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0500 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0501 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0502 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0503 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0504 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0505 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0506 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0507 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0508 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0509 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x050a +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x050b +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x050c +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x050d +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x050e +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x050f +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0510 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0511 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0512 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0513 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0514 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0515 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0516 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0517 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0518 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0519 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE 0x051a +#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX 0x051b +#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA 0x051c +#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT 0x051d +#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x051e +#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x051f +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0520 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0521 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0522 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL 0x0523 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX 0x0524 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA 0x0525 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL 0x0526 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0527 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0528 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0529 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x052a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x052b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x052c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x052d +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x052e +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x052f +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0530 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0531 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0532 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0533 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0534 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0535 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0536 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0537 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0538 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0539 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x053a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x053b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x053c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x053d +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x053e +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x053f +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0540 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0541 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0542 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0543 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0544 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0545 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0546 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0547 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0548 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0549 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x054a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x054b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x054c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x054d +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x054e +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x054f +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0550 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0551 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0552 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0553 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0554 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0555 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0556 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0557 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0558 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0559 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x055a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x055b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x055c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x055d +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x055e +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x055f +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0560 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0561 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0562 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0563 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0564 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0565 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0566 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0567 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0568 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0569 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x056a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x056b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x056c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL 0x056d +#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_mcm2_dispdec +// base address: 0x480 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL 0x0573 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R 0x0574 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G 0x0575 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B 0x0576 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R 0x0577 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B 0x0578 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX 0x0579 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA 0x057a +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x057b +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x057c +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x057d +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x057e +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x057f +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0580 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0581 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0582 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0583 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0584 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0585 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0586 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0587 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0588 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0589 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x058a +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x058b +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x058c +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x058d +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x058e +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x058f +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0590 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0591 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0592 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0593 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0594 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0595 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0596 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0597 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0598 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0599 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x059a +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x059b +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x059c +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x059d +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x059e +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x059f +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x05a0 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x05a1 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x05a2 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x05a3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x05a4 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x05a5 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x05a6 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x05a7 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x05a8 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x05a9 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE 0x05aa +#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX 0x05ab +#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA 0x05ac +#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT 0x05ad +#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x05ae +#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x05af +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x05b0 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x05b1 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x05b2 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL 0x05b3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX 0x05b4 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA 0x05b5 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL 0x05b6 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x05b7 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x05b8 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x05b9 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x05ba +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x05bb +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x05bc +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x05bd +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x05be +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x05bf +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x05c0 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x05c1 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x05c2 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x05c3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x05c4 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x05c5 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x05c6 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x05c7 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x05c8 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x05c9 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x05ca +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x05cb +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x05cc +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x05cd +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x05ce +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x05cf +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x05d0 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x05d1 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x05d2 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x05d3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x05d4 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x05d5 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x05d6 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x05d7 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x05d8 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x05d9 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x05da +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x05db +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x05dc +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x05dd +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x05de +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x05df +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x05e0 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x05e1 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x05e2 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x05e3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x05e4 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x05e5 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x05e6 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x05e7 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x05e8 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x05e9 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x05ea +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x05eb +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x05ec +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x05ed +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x05ee +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x05ef +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x05f0 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x05f1 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x05f2 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x05f3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x05f4 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x05f5 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x05f6 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x05f7 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x05f8 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x05f9 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x05fa +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x05fb +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x05fc +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL 0x05fd +#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_mcm3_dispdec +// base address: 0x6c0 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL 0x0603 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R 0x0604 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G 0x0605 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B 0x0606 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R 0x0607 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B 0x0608 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX 0x0609 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA 0x060a +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x060b +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x060c +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x060d +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x060e +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x060f +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0610 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0611 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0612 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0613 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0614 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0615 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0616 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0617 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0618 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0619 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x061a +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x061b +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x061c +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x061d +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x061e +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x061f +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0620 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0621 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0622 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0623 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0624 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0625 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0626 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0627 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0628 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0629 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x062a +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x062b +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x062c +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x062d +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x062e +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x062f +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0630 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0631 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0632 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0633 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0634 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0635 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0636 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0637 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0638 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0639 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE 0x063a +#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX 0x063b +#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA 0x063c +#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT 0x063d +#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x063e +#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x063f +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0640 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0641 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0642 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL 0x0643 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX 0x0644 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA 0x0645 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL 0x0646 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0647 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0648 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0649 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x064a +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x064b +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x064c +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x064d +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x064e +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x064f +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0650 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0651 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0652 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0653 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0654 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0655 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0656 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0657 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0658 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0659 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x065a +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x065b +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x065c +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x065d +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x065e +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x065f +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0660 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0661 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0662 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0663 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0664 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0665 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0666 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0667 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0668 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0669 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x066a +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x066b +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x066c +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x066d +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x066e +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x066f +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0670 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0671 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0672 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0673 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0674 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0675 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0676 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0677 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0678 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0679 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x067a +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x067b +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x067c +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x067d +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x067e +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x067f +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0680 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0681 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0682 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0683 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0684 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0685 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0686 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0687 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0688 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0689 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x068a +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x068b +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x068c +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL 0x068d +#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec +// base address: 0x0 +#define regMPC_OUT0_MUX 0x03d8 +#define regMPC_OUT0_MUX_BASE_IDX 3 +#define regMPC_OUT0_DENORM_CONTROL 0x03d9 +#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT0_DENORM_CLAMP_G_Y 0x03da +#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT0_DENORM_CLAMP_B_CB 0x03db +#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT1_MUX 0x03dc +#define regMPC_OUT1_MUX_BASE_IDX 3 +#define regMPC_OUT1_DENORM_CONTROL 0x03dd +#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT1_DENORM_CLAMP_G_Y 0x03de +#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT1_DENORM_CLAMP_B_CB 0x03df +#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT2_MUX 0x03e0 +#define regMPC_OUT2_MUX_BASE_IDX 3 +#define regMPC_OUT2_DENORM_CONTROL 0x03e1 +#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT2_DENORM_CLAMP_G_Y 0x03e2 +#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT2_DENORM_CLAMP_B_CB 0x03e3 +#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT3_MUX 0x03e4 +#define regMPC_OUT3_MUX_BASE_IDX 3 +#define regMPC_OUT3_DENORM_CONTROL 0x03e5 +#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT3_DENORM_CLAMP_G_Y 0x03e6 +#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT3_DENORM_CLAMP_B_CB 0x03e7 +#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT_CSC_COEF_FORMAT 0x03f0 +#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 +#define regMPC_OUT0_CSC_MODE 0x03f1 +#define regMPC_OUT0_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT0_CSC_C11_C12_A 0x03f2 +#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C13_C14_A 0x03f3 +#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C21_C22_A 0x03f4 +#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C23_C24_A 0x03f5 +#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C31_C32_A 0x03f6 +#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C33_C34_A 0x03f7 +#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C11_C12_B 0x03f8 +#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C13_C14_B 0x03f9 +#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C21_C22_B 0x03fa +#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C23_C24_B 0x03fb +#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C31_C32_B 0x03fc +#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C33_C34_B 0x03fd +#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_MODE 0x03fe +#define regMPC_OUT1_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT1_CSC_C11_C12_A 0x03ff +#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C13_C14_A 0x0400 +#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C21_C22_A 0x0401 +#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C23_C24_A 0x0402 +#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C31_C32_A 0x0403 +#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C33_C34_A 0x0404 +#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C11_C12_B 0x0405 +#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C13_C14_B 0x0406 +#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C21_C22_B 0x0407 +#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C23_C24_B 0x0408 +#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C31_C32_B 0x0409 +#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C33_C34_B 0x040a +#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_MODE 0x040b +#define regMPC_OUT2_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT2_CSC_C11_C12_A 0x040c +#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C13_C14_A 0x040d +#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C21_C22_A 0x040e +#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C23_C24_A 0x040f +#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C31_C32_A 0x0410 +#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C33_C34_A 0x0411 +#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C11_C12_B 0x0412 +#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C13_C14_B 0x0413 +#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C21_C22_B 0x0414 +#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C23_C24_B 0x0415 +#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C31_C32_B 0x0416 +#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C33_C34_B 0x0417 +#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_MODE 0x0418 +#define regMPC_OUT3_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT3_CSC_C11_C12_A 0x0419 +#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C13_C14_A 0x041a +#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C21_C22_A 0x041b +#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C23_C24_A 0x041c +#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C31_C32_A 0x041d +#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C33_C34_A 0x041e +#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C11_C12_B 0x041f +#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C13_C14_B 0x0420 +#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C21_C22_B 0x0421 +#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C23_C24_B 0x0422 +#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C31_C32_B 0x0423 +#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C33_C34_B 0x0424 +#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_abm0_dispdec +// base address: 0x0 +#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a +#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_USER_LEVEL 0x0e7b +#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c +#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d +#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e +#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f +#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM0_BL1_PWM_ABM_CNTL 0x0e80 +#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 +#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82 +#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 +#define regABM0_DC_ABM1_CNTL 0x0e83 +#define regABM0_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84 +#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_THRES_12 0x0e8a +#define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_THRES_34 0x0e8b +#define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c +#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e +#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f +#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90 +#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91 +#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92 +#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93 +#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94 +#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95 +#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96 +#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97 +#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98 +#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99 +#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a +#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b +#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c +#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d +#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_1 0x0e9e +#define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_2 0x0e9f +#define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_3 0x0ea0 +#define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_4 0x0ea1 +#define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_5 0x0ea2 +#define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_6 0x0ea3 +#define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_7 0x0ea4 +#define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_8 0x0ea5 +#define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_9 0x0ea6 +#define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_10 0x0ea7 +#define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_11 0x0ea8 +#define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_12 0x0ea9 +#define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_13 0x0eaa +#define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_14 0x0eab +#define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_15 0x0eac +#define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_16 0x0ead +#define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_17 0x0eae +#define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_18 0x0eaf +#define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_19 0x0eb0 +#define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_20 0x0eb1 +#define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_21 0x0eb2 +#define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_22 0x0eb3 +#define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_23 0x0eb4 +#define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_24 0x0eb5 +#define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3 +#define regABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6 +#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_abm1_dispdec +// base address: 0x104 +#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb +#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_USER_LEVEL 0x0ebc +#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd +#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe +#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf +#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 +#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM1_BL1_PWM_ABM_CNTL 0x0ec1 +#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 +#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3 +#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 +#define regABM1_DC_ABM1_CNTL 0x0ec4 +#define regABM1_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5 +#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_THRES_12 0x0ecb +#define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_THRES_34 0x0ecc +#define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd +#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf +#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0 +#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1 +#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2 +#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3 +#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4 +#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5 +#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6 +#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7 +#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8 +#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9 +#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda +#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb +#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc +#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd +#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede +#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_1 0x0edf +#define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_2 0x0ee0 +#define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_3 0x0ee1 +#define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_4 0x0ee2 +#define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_5 0x0ee3 +#define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_6 0x0ee4 +#define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_7 0x0ee5 +#define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_8 0x0ee6 +#define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_9 0x0ee7 +#define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_10 0x0ee8 +#define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_11 0x0ee9 +#define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_12 0x0eea +#define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_13 0x0eeb +#define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_14 0x0eec +#define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_15 0x0eed +#define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_16 0x0eee +#define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_17 0x0eef +#define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_18 0x0ef0 +#define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_19 0x0ef1 +#define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_20 0x0ef2 +#define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_21 0x0ef3 +#define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_22 0x0ef4 +#define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_23 0x0ef5 +#define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_24 0x0ef6 +#define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3 +#define regABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7 +#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_abm2_dispdec +// base address: 0x208 +#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc +#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_USER_LEVEL 0x0efd +#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe +#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff +#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00 +#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01 +#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM2_BL1_PWM_ABM_CNTL 0x0f02 +#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03 +#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04 +#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 +#define regABM2_DC_ABM1_CNTL 0x0f05 +#define regABM2_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06 +#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f07 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f08 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f09 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f0a +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f0b +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_THRES_12 0x0f0c +#define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_THRES_34 0x0f0d +#define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0e +#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f10 +#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_MISC_CTRL 0x0f11 +#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f12 +#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f13 +#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f14 +#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f15 +#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f16 +#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f17 +#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f18 +#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f19 +#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f1a +#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f1b +#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f1c +#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1d +#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1e +#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1f +#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_1 0x0f20 +#define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_2 0x0f21 +#define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_3 0x0f22 +#define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_4 0x0f23 +#define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_5 0x0f24 +#define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_6 0x0f25 +#define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_7 0x0f26 +#define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_8 0x0f27 +#define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_9 0x0f28 +#define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_10 0x0f29 +#define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_11 0x0f2a +#define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_12 0x0f2b +#define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_13 0x0f2c +#define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_14 0x0f2d +#define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_15 0x0f2e +#define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_16 0x0f2f +#define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_17 0x0f30 +#define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_18 0x0f31 +#define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_19 0x0f32 +#define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_20 0x0f33 +#define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_21 0x0f34 +#define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_22 0x0f35 +#define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_23 0x0f36 +#define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_24 0x0f37 +#define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX 3 +#define regABM2_DC_ABM1_BL_MASTER_LOCK 0x0f38 +#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_abm3_dispdec +// base address: 0x30c +#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d +#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_USER_LEVEL 0x0f3e +#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f +#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40 +#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41 +#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42 +#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM3_BL1_PWM_ABM_CNTL 0x0f43 +#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44 +#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45 +#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 +#define regABM3_DC_ABM1_CNTL 0x0f46 +#define regABM3_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47 +#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f48 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f49 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f4a +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f4b +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f4c +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_THRES_12 0x0f4d +#define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_THRES_34 0x0f4e +#define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4f +#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f51 +#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_MISC_CTRL 0x0f52 +#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f53 +#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f54 +#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f55 +#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f56 +#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f57 +#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f58 +#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f59 +#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f5a +#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f5b +#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f5c +#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5d +#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5e +#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5f +#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f60 +#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_1 0x0f61 +#define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_2 0x0f62 +#define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_3 0x0f63 +#define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_4 0x0f64 +#define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_5 0x0f65 +#define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_6 0x0f66 +#define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_7 0x0f67 +#define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_8 0x0f68 +#define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_9 0x0f69 +#define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_10 0x0f6a +#define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_11 0x0f6b +#define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_12 0x0f6c +#define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_13 0x0f6d +#define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_14 0x0f6e +#define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_15 0x0f6f +#define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_16 0x0f70 +#define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_17 0x0f71 +#define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_18 0x0f72 +#define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_19 0x0f73 +#define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_20 0x0f74 +#define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_21 0x0f75 +#define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_22 0x0f76 +#define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_23 0x0f77 +#define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_24 0x0f78 +#define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX 3 +#define regABM3_DC_ABM1_BL_MASTER_LOCK 0x0f79 +#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_dpg0_dispdec +// base address: 0x0 +#define regDPG0_DPG_CONTROL 0x1854 +#define regDPG0_DPG_CONTROL_BASE_IDX 2 +#define regDPG0_DPG_RAMP_CONTROL 0x1855 +#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG0_DPG_DIMENSIONS 0x1856 +#define regDPG0_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG0_DPG_COLOUR_R_CR 0x1857 +#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG0_DPG_COLOUR_G_Y 0x1858 +#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG0_DPG_COLOUR_B_CB 0x1859 +#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG0_DPG_OFFSET_SEGMENT 0x185a +#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG0_DPG_STATUS 0x185b +#define regDPG0_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt0_dispdec +// base address: 0x0 +#define regFMT0_FMT_CLAMP_COMPONENT_R 0x183c +#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT0_FMT_CLAMP_COMPONENT_G 0x183d +#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT0_FMT_CLAMP_COMPONENT_B 0x183e +#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f +#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT0_FMT_CONTROL 0x1840 +#define regFMT0_FMT_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 +#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_DITHER_RAND_R_SEED 0x1842 +#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT0_FMT_DITHER_RAND_G_SEED 0x1843 +#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT0_FMT_DITHER_RAND_B_SEED 0x1844 +#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT0_FMT_CLAMP_CNTL 0x1845 +#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 +#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 +#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_422_CONTROL 0x1849 +#define regFMT0_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf0_dispdec +// base address: 0x0 +#define regOPPBUF0_OPPBUF_CONTROL 0x1884 +#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF0_OPPBUF_CONTROL1 0x1889 +#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe0_dispdec +// base address: 0x0 +#define regOPP_PIPE0_OPP_PIPE_CONTROL 0x188c +#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec +// base address: 0x0 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg1_dispdec +// base address: 0x168 +#define regDPG1_DPG_CONTROL 0x18ae +#define regDPG1_DPG_CONTROL_BASE_IDX 2 +#define regDPG1_DPG_RAMP_CONTROL 0x18af +#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG1_DPG_DIMENSIONS 0x18b0 +#define regDPG1_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG1_DPG_COLOUR_R_CR 0x18b1 +#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG1_DPG_COLOUR_G_Y 0x18b2 +#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG1_DPG_COLOUR_B_CB 0x18b3 +#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG1_DPG_OFFSET_SEGMENT 0x18b4 +#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG1_DPG_STATUS 0x18b5 +#define regDPG1_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt1_dispdec +// base address: 0x168 +#define regFMT1_FMT_CLAMP_COMPONENT_R 0x1896 +#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT1_FMT_CLAMP_COMPONENT_G 0x1897 +#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT1_FMT_CLAMP_COMPONENT_B 0x1898 +#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 +#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT1_FMT_CONTROL 0x189a +#define regFMT1_FMT_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_BIT_DEPTH_CONTROL 0x189b +#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_DITHER_RAND_R_SEED 0x189c +#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT1_FMT_DITHER_RAND_G_SEED 0x189d +#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT1_FMT_DITHER_RAND_B_SEED 0x189e +#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT1_FMT_CLAMP_CNTL 0x189f +#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 +#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 +#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_422_CONTROL 0x18a3 +#define regFMT1_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf1_dispdec +// base address: 0x168 +#define regOPPBUF1_OPPBUF_CONTROL 0x18de +#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF1_OPPBUF_CONTROL1 0x18e3 +#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe1_dispdec +// base address: 0x168 +#define regOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 +#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec +// base address: 0x168 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg2_dispdec +// base address: 0x2d0 +#define regDPG2_DPG_CONTROL 0x1908 +#define regDPG2_DPG_CONTROL_BASE_IDX 2 +#define regDPG2_DPG_RAMP_CONTROL 0x1909 +#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG2_DPG_DIMENSIONS 0x190a +#define regDPG2_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG2_DPG_COLOUR_R_CR 0x190b +#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG2_DPG_COLOUR_G_Y 0x190c +#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG2_DPG_COLOUR_B_CB 0x190d +#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG2_DPG_OFFSET_SEGMENT 0x190e +#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG2_DPG_STATUS 0x190f +#define regDPG2_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt2_dispdec +// base address: 0x2d0 +#define regFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 +#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 +#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 +#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 +#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT2_FMT_CONTROL 0x18f4 +#define regFMT2_FMT_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 +#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 +#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 +#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 +#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT2_FMT_CLAMP_CNTL 0x18f9 +#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa +#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb +#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_422_CONTROL 0x18fd +#define regFMT2_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf2_dispdec +// base address: 0x2d0 +#define regOPPBUF2_OPPBUF_CONTROL 0x1938 +#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF2_OPPBUF_CONTROL1 0x193d +#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe2_dispdec +// base address: 0x2d0 +#define regOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 +#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec +// base address: 0x2d0 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg3_dispdec +// base address: 0x438 +#define regDPG3_DPG_CONTROL 0x1962 +#define regDPG3_DPG_CONTROL_BASE_IDX 2 +#define regDPG3_DPG_RAMP_CONTROL 0x1963 +#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG3_DPG_DIMENSIONS 0x1964 +#define regDPG3_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG3_DPG_COLOUR_R_CR 0x1965 +#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG3_DPG_COLOUR_G_Y 0x1966 +#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG3_DPG_COLOUR_B_CB 0x1967 +#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG3_DPG_OFFSET_SEGMENT 0x1968 +#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG3_DPG_STATUS 0x1969 +#define regDPG3_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt3_dispdec +// base address: 0x438 +#define regFMT3_FMT_CLAMP_COMPONENT_R 0x194a +#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT3_FMT_CLAMP_COMPONENT_G 0x194b +#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT3_FMT_CLAMP_COMPONENT_B 0x194c +#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d +#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT3_FMT_CONTROL 0x194e +#define regFMT3_FMT_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_BIT_DEPTH_CONTROL 0x194f +#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_DITHER_RAND_R_SEED 0x1950 +#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT3_FMT_DITHER_RAND_G_SEED 0x1951 +#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT3_FMT_DITHER_RAND_B_SEED 0x1952 +#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT3_FMT_CLAMP_CNTL 0x1953 +#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 +#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 +#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_422_CONTROL 0x1957 +#define regFMT3_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf3_dispdec +// base address: 0x438 +#define regOPPBUF3_OPPBUF_CONTROL 0x1992 +#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF3_OPPBUF_CONTROL1 0x1997 +#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe3_dispdec +// base address: 0x438 +#define regOPP_PIPE3_OPP_PIPE_CONTROL 0x199a +#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec +// base address: 0x438 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm0_dispdec +// base address: 0x0 +#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 +#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm1_dispdec +// base address: 0x4 +#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 +#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm2_dispdec +// base address: 0x8 +#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 +#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm3_dispdec +// base address: 0xc +#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67 +#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_top_dispdec +// base address: 0x0 +#define regOPP_TOP_CLK_CONTROL 0x1a5e +#define regOPP_TOP_CLK_CONTROL_BASE_IDX 2 +#define regOPP_ABM_CONTROL 0x1a60 +#define regOPP_ABM_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm0_dispdec +// base address: 0x0 +#define regODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca +#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_DATA_SOURCE_SELECT 0x1acb +#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc +#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_BYTES_PER_PIXEL 0x1acd +#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM0_OPTC_WIDTH_CONTROL 0x1ace +#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf +#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_MEMORY_CONFIG 0x1ad0 +#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 +#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm1_dispdec +// base address: 0x40 +#define regODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada +#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_DATA_SOURCE_SELECT 0x1adb +#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc +#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_BYTES_PER_PIXEL 0x1add +#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM1_OPTC_WIDTH_CONTROL 0x1ade +#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf +#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_MEMORY_CONFIG 0x1ae0 +#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 +#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm2_dispdec +// base address: 0x80 +#define regODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea +#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb +#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec +#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_BYTES_PER_PIXEL 0x1aed +#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM2_OPTC_WIDTH_CONTROL 0x1aee +#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef +#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_MEMORY_CONFIG 0x1af0 +#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1 +#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm3_dispdec +// base address: 0xc0 +#define regODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa +#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_DATA_SOURCE_SELECT 0x1afb +#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc +#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_BYTES_PER_PIXEL 0x1afd +#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM3_OPTC_WIDTH_CONTROL 0x1afe +#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff +#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_MEMORY_CONFIG 0x1b00 +#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01 +#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg0_dispdec +// base address: 0x0 +#define regOTG0_OTG_H_TOTAL 0x1b2a +#define regOTG0_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG0_OTG_H_BLANK_START_END 0x1b2b +#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG0_OTG_H_SYNC_A 0x1b2c +#define regOTG0_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG0_OTG_H_SYNC_A_CNTL 0x1b2d +#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG0_OTG_H_TIMING_CNTL 0x1b2e +#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL 0x1b2f +#define regOTG0_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_MIN 0x1b30 +#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_MAX 0x1b31 +#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_MID 0x1b32 +#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_CONTROL 0x1b33 +#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 +#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 +#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_V_BLANK_START_END 0x1b36 +#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG0_OTG_V_SYNC_A 0x1b37 +#define regOTG0_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG0_OTG_V_SYNC_A_CNTL 0x1b38 +#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG0_OTG_TRIGA_CNTL 0x1b39 +#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a +#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG0_OTG_TRIGB_CNTL 0x1b3b +#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c +#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d +#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG0_OTG_FLOW_CONTROL 0x1b3e +#define regOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f +#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG0_OTG_CONTROL 0x1b41 +#define regOTG0_OTG_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_INTERLACE_CONTROL 0x1b44 +#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_INTERLACE_STATUS 0x1b45 +#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 +#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 +#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG0_OTG_STATUS 0x1b49 +#define regOTG0_OTG_STATUS_BASE_IDX 2 +#define regOTG0_OTG_STATUS_POSITION 0x1b4a +#define regOTG0_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG0_OTG_NOM_VERT_POSITION 0x1b4b +#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c +#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG0_OTG_STATUS_VF_COUNT 0x1b4d +#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG0_OTG_STATUS_HV_COUNT 0x1b4e +#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG0_OTG_COUNT_CONTROL 0x1b4f +#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_COUNT_RESET 0x1b50 +#define regOTG0_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 +#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 +#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_STEREO_STATUS 0x1b53 +#define regOTG0_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG0_OTG_STEREO_CONTROL 0x1b54 +#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_STATUS 0x1b55 +#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 +#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_POSITION 0x1b57 +#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_FRAME 0x1b58 +#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG0_OTG_INTERRUPT_CONTROL 0x1b59 +#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_UPDATE_LOCK 0x1b5a +#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b +#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_MASTER_EN 0x1b5c +#define regOTG0_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC_CNTL 0x1b68 +#define regOTG0_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b69 +#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6a +#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6b +#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6c +#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_DATA_RG 0x1b6d +#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define regOTG0_OTG_CRC0_DATA_B 0x1b6e +#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b6f +#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b70 +#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b71 +#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b72 +#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_DATA_RG 0x1b73 +#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define regOTG0_OTG_CRC1_DATA_B 0x1b74 +#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC2_DATA_RG 0x1b75 +#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define regOTG0_OTG_CRC2_DATA_B 0x1b76 +#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC3_DATA_RG 0x1b77 +#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define regOTG0_OTG_CRC3_DATA_B 0x1b78 +#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b79 +#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7a +#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b81 +#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b82 +#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_GSL_VSYNC_GAP 0x1b83 +#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG0_OTG_MASTER_UPDATE_MODE 0x1b84 +#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG0_OTG_CLOCK_CONTROL 0x1b85 +#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_VSTARTUP_PARAM 0x1b86 +#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG0_OTG_VUPDATE_PARAM 0x1b87 +#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG0_OTG_VREADY_PARAM 0x1b88 +#define regOTG0_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b89 +#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8a +#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG0_OTG_GSL_CONTROL 0x1b8b +#define regOTG0_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_GSL_WINDOW_X 0x1b8c +#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG0_OTG_GSL_WINDOW_Y 0x1b8d +#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG0_OTG_VUPDATE_KEEPOUT 0x1b8e +#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL0 0x1b8f +#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL1 0x1b90 +#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL2 0x1b91 +#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL3 0x1b92 +#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL4 0x1b93 +#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b94 +#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b95 +#define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b96 +#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b97 +#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b98 +#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b99 +#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG0_OTG_DRR_CONTROL 0x1b9a +#define regOTG0_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_M_CONST_DTO0 0x1b9b +#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG0_OTG_M_CONST_DTO1 0x1b9c +#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG0_OTG_REQUEST_CONTROL 0x1b9d +#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_DSC_START_POSITION 0x1b9e +#define regOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 +#define regOTG0_OTG_PIPE_UPDATE_STATUS 0x1b9f +#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG0_OTG_SPARE_REGISTER 0x1ba1 +#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg1_dispdec +// base address: 0x200 +#define regOTG1_OTG_H_TOTAL 0x1baa +#define regOTG1_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG1_OTG_H_BLANK_START_END 0x1bab +#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG1_OTG_H_SYNC_A 0x1bac +#define regOTG1_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG1_OTG_H_SYNC_A_CNTL 0x1bad +#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG1_OTG_H_TIMING_CNTL 0x1bae +#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL 0x1baf +#define regOTG1_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_MIN 0x1bb0 +#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_MAX 0x1bb1 +#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_MID 0x1bb2 +#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 +#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 +#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 +#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_V_BLANK_START_END 0x1bb6 +#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG1_OTG_V_SYNC_A 0x1bb7 +#define regOTG1_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 +#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG1_OTG_TRIGA_CNTL 0x1bb9 +#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba +#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG1_OTG_TRIGB_CNTL 0x1bbb +#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc +#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd +#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG1_OTG_FLOW_CONTROL 0x1bbe +#define regOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf +#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG1_OTG_CONTROL 0x1bc1 +#define regOTG1_OTG_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_INTERLACE_CONTROL 0x1bc4 +#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_INTERLACE_STATUS 0x1bc5 +#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 +#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 +#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG1_OTG_STATUS 0x1bc9 +#define regOTG1_OTG_STATUS_BASE_IDX 2 +#define regOTG1_OTG_STATUS_POSITION 0x1bca +#define regOTG1_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG1_OTG_NOM_VERT_POSITION 0x1bcb +#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc +#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG1_OTG_STATUS_VF_COUNT 0x1bcd +#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG1_OTG_STATUS_HV_COUNT 0x1bce +#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG1_OTG_COUNT_CONTROL 0x1bcf +#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_COUNT_RESET 0x1bd0 +#define regOTG1_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 +#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 +#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_STEREO_STATUS 0x1bd3 +#define regOTG1_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG1_OTG_STEREO_CONTROL 0x1bd4 +#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 +#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 +#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 +#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 +#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG1_OTG_INTERRUPT_CONTROL 0x1bd9 +#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_UPDATE_LOCK 0x1bda +#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb +#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_MASTER_EN 0x1bdc +#define regOTG1_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4 +#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5 +#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6 +#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7 +#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC_CNTL 0x1be8 +#define regOTG1_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1be9 +#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1bea +#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1beb +#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bec +#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_DATA_RG 0x1bed +#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define regOTG1_OTG_CRC0_DATA_B 0x1bee +#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bef +#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf0 +#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf1 +#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf2 +#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_DATA_RG 0x1bf3 +#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define regOTG1_OTG_CRC1_DATA_B 0x1bf4 +#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC2_DATA_RG 0x1bf5 +#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define regOTG1_OTG_CRC2_DATA_B 0x1bf6 +#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC3_DATA_RG 0x1bf7 +#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define regOTG1_OTG_CRC3_DATA_B 0x1bf8 +#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bf9 +#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfa +#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c01 +#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c02 +#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_GSL_VSYNC_GAP 0x1c03 +#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG1_OTG_MASTER_UPDATE_MODE 0x1c04 +#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG1_OTG_CLOCK_CONTROL 0x1c05 +#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_VSTARTUP_PARAM 0x1c06 +#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG1_OTG_VUPDATE_PARAM 0x1c07 +#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG1_OTG_VREADY_PARAM 0x1c08 +#define regOTG1_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c09 +#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0a +#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG1_OTG_GSL_CONTROL 0x1c0b +#define regOTG1_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_GSL_WINDOW_X 0x1c0c +#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG1_OTG_GSL_WINDOW_Y 0x1c0d +#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG1_OTG_VUPDATE_KEEPOUT 0x1c0e +#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL0 0x1c0f +#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL1 0x1c10 +#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL2 0x1c11 +#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL3 0x1c12 +#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL4 0x1c13 +#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c14 +#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c15 +#define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c16 +#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c17 +#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c18 +#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c19 +#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG1_OTG_DRR_CONTROL 0x1c1a +#define regOTG1_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_M_CONST_DTO0 0x1c1b +#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG1_OTG_M_CONST_DTO1 0x1c1c +#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG1_OTG_REQUEST_CONTROL 0x1c1d +#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_DSC_START_POSITION 0x1c1e +#define regOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 +#define regOTG1_OTG_PIPE_UPDATE_STATUS 0x1c1f +#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG1_OTG_SPARE_REGISTER 0x1c21 +#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg2_dispdec +// base address: 0x400 +#define regOTG2_OTG_H_TOTAL 0x1c2a +#define regOTG2_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG2_OTG_H_BLANK_START_END 0x1c2b +#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG2_OTG_H_SYNC_A 0x1c2c +#define regOTG2_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG2_OTG_H_SYNC_A_CNTL 0x1c2d +#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG2_OTG_H_TIMING_CNTL 0x1c2e +#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL 0x1c2f +#define regOTG2_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_MIN 0x1c30 +#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_MAX 0x1c31 +#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_MID 0x1c32 +#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_CONTROL 0x1c33 +#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34 +#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35 +#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_V_BLANK_START_END 0x1c36 +#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG2_OTG_V_SYNC_A 0x1c37 +#define regOTG2_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG2_OTG_V_SYNC_A_CNTL 0x1c38 +#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG2_OTG_TRIGA_CNTL 0x1c39 +#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a +#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG2_OTG_TRIGB_CNTL 0x1c3b +#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c +#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d +#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG2_OTG_FLOW_CONTROL 0x1c3e +#define regOTG2_OTG_FLOW_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f +#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG2_OTG_CONTROL 0x1c41 +#define regOTG2_OTG_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_INTERLACE_CONTROL 0x1c44 +#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_INTERLACE_STATUS 0x1c45 +#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 +#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 +#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG2_OTG_STATUS 0x1c49 +#define regOTG2_OTG_STATUS_BASE_IDX 2 +#define regOTG2_OTG_STATUS_POSITION 0x1c4a +#define regOTG2_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG2_OTG_NOM_VERT_POSITION 0x1c4b +#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c +#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG2_OTG_STATUS_VF_COUNT 0x1c4d +#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG2_OTG_STATUS_HV_COUNT 0x1c4e +#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG2_OTG_COUNT_CONTROL 0x1c4f +#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_COUNT_RESET 0x1c50 +#define regOTG2_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51 +#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG2_OTG_VERT_SYNC_CONTROL 0x1c52 +#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_STEREO_STATUS 0x1c53 +#define regOTG2_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG2_OTG_STEREO_CONTROL 0x1c54 +#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_STATUS 0x1c55 +#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_CONTROL 0x1c56 +#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_POSITION 0x1c57 +#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_FRAME 0x1c58 +#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG2_OTG_INTERRUPT_CONTROL 0x1c59 +#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_UPDATE_LOCK 0x1c5a +#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b +#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_MASTER_EN 0x1c5c +#define regOTG2_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC_CNTL 0x1c68 +#define regOTG2_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c69 +#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6a +#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6b +#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6c +#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_DATA_RG 0x1c6d +#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define regOTG2_OTG_CRC0_DATA_B 0x1c6e +#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c6f +#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c70 +#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c71 +#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c72 +#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_DATA_RG 0x1c73 +#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define regOTG2_OTG_CRC1_DATA_B 0x1c74 +#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC2_DATA_RG 0x1c75 +#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define regOTG2_OTG_CRC2_DATA_B 0x1c76 +#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC3_DATA_RG 0x1c77 +#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define regOTG2_OTG_CRC3_DATA_B 0x1c78 +#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c79 +#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7a +#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c81 +#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c82 +#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_GSL_VSYNC_GAP 0x1c83 +#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG2_OTG_MASTER_UPDATE_MODE 0x1c84 +#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG2_OTG_CLOCK_CONTROL 0x1c85 +#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_VSTARTUP_PARAM 0x1c86 +#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG2_OTG_VUPDATE_PARAM 0x1c87 +#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG2_OTG_VREADY_PARAM 0x1c88 +#define regOTG2_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c89 +#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8a +#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG2_OTG_GSL_CONTROL 0x1c8b +#define regOTG2_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_GSL_WINDOW_X 0x1c8c +#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG2_OTG_GSL_WINDOW_Y 0x1c8d +#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG2_OTG_VUPDATE_KEEPOUT 0x1c8e +#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL0 0x1c8f +#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL1 0x1c90 +#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL2 0x1c91 +#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL3 0x1c92 +#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL4 0x1c93 +#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c94 +#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c95 +#define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c96 +#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c97 +#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c98 +#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c99 +#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG2_OTG_DRR_CONTROL 0x1c9a +#define regOTG2_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_M_CONST_DTO0 0x1c9b +#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG2_OTG_M_CONST_DTO1 0x1c9c +#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG2_OTG_REQUEST_CONTROL 0x1c9d +#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_DSC_START_POSITION 0x1c9e +#define regOTG2_OTG_DSC_START_POSITION_BASE_IDX 2 +#define regOTG2_OTG_PIPE_UPDATE_STATUS 0x1c9f +#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG2_OTG_SPARE_REGISTER 0x1ca1 +#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg3_dispdec +// base address: 0x600 +#define regOTG3_OTG_H_TOTAL 0x1caa +#define regOTG3_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG3_OTG_H_BLANK_START_END 0x1cab +#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG3_OTG_H_SYNC_A 0x1cac +#define regOTG3_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG3_OTG_H_SYNC_A_CNTL 0x1cad +#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG3_OTG_H_TIMING_CNTL 0x1cae +#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL 0x1caf +#define regOTG3_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_MIN 0x1cb0 +#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_MAX 0x1cb1 +#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_MID 0x1cb2 +#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 +#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4 +#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5 +#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_V_BLANK_START_END 0x1cb6 +#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG3_OTG_V_SYNC_A 0x1cb7 +#define regOTG3_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG3_OTG_V_SYNC_A_CNTL 0x1cb8 +#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG3_OTG_TRIGA_CNTL 0x1cb9 +#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba +#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG3_OTG_TRIGB_CNTL 0x1cbb +#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc +#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd +#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG3_OTG_FLOW_CONTROL 0x1cbe +#define regOTG3_OTG_FLOW_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf +#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG3_OTG_CONTROL 0x1cc1 +#define regOTG3_OTG_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_INTERLACE_CONTROL 0x1cc4 +#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_INTERLACE_STATUS 0x1cc5 +#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 +#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 +#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG3_OTG_STATUS 0x1cc9 +#define regOTG3_OTG_STATUS_BASE_IDX 2 +#define regOTG3_OTG_STATUS_POSITION 0x1cca +#define regOTG3_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG3_OTG_NOM_VERT_POSITION 0x1ccb +#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc +#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG3_OTG_STATUS_VF_COUNT 0x1ccd +#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG3_OTG_STATUS_HV_COUNT 0x1cce +#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG3_OTG_COUNT_CONTROL 0x1ccf +#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_COUNT_RESET 0x1cd0 +#define regOTG3_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1 +#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2 +#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_STEREO_STATUS 0x1cd3 +#define regOTG3_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG3_OTG_STEREO_CONTROL 0x1cd4 +#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_STATUS 0x1cd5 +#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6 +#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_POSITION 0x1cd7 +#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_FRAME 0x1cd8 +#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG3_OTG_INTERRUPT_CONTROL 0x1cd9 +#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_UPDATE_LOCK 0x1cda +#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb +#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_MASTER_EN 0x1cdc +#define regOTG3_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4 +#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5 +#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6 +#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7 +#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC_CNTL 0x1ce8 +#define regOTG3_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1ce9 +#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1cea +#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1ceb +#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1cec +#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_DATA_RG 0x1ced +#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define regOTG3_OTG_CRC0_DATA_B 0x1cee +#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cef +#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf0 +#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf1 +#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf2 +#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_DATA_RG 0x1cf3 +#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define regOTG3_OTG_CRC1_DATA_B 0x1cf4 +#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC2_DATA_RG 0x1cf5 +#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define regOTG3_OTG_CRC2_DATA_B 0x1cf6 +#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC3_DATA_RG 0x1cf7 +#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define regOTG3_OTG_CRC3_DATA_B 0x1cf8 +#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cf9 +#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfa +#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d01 +#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d02 +#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_GSL_VSYNC_GAP 0x1d03 +#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG3_OTG_MASTER_UPDATE_MODE 0x1d04 +#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG3_OTG_CLOCK_CONTROL 0x1d05 +#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_VSTARTUP_PARAM 0x1d06 +#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG3_OTG_VUPDATE_PARAM 0x1d07 +#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG3_OTG_VREADY_PARAM 0x1d08 +#define regOTG3_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d09 +#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0a +#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG3_OTG_GSL_CONTROL 0x1d0b +#define regOTG3_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_GSL_WINDOW_X 0x1d0c +#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG3_OTG_GSL_WINDOW_Y 0x1d0d +#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG3_OTG_VUPDATE_KEEPOUT 0x1d0e +#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL0 0x1d0f +#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL1 0x1d10 +#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL2 0x1d11 +#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL3 0x1d12 +#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL4 0x1d13 +#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d14 +#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d15 +#define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d16 +#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d17 +#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d18 +#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d19 +#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG3_OTG_DRR_CONTROL 0x1d1a +#define regOTG3_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_M_CONST_DTO0 0x1d1b +#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG3_OTG_M_CONST_DTO1 0x1d1c +#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG3_OTG_REQUEST_CONTROL 0x1d1d +#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_DSC_START_POSITION 0x1d1e +#define regOTG3_OTG_DSC_START_POSITION_BASE_IDX 2 +#define regOTG3_OTG_PIPE_UPDATE_STATUS 0x1d1f +#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG3_OTG_SPARE_REGISTER 0x1d21 +#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_optc_misc_dispdec +// base address: 0x0 +#define regGSL_SOURCE_SELECT 0x1e2b +#define regGSL_SOURCE_SELECT_BASE_IDX 2 +#define regOPTC_CLOCK_CONTROL 0x1e2c +#define regOPTC_CLOCK_CONTROL_BASE_IDX 2 +#define regODM_MEM_PWR_CTRL 0x1e2d +#define regODM_MEM_PWR_CTRL_BASE_IDX 2 +#define regODM_MEM_PWR_CTRL3 0x1e2f +#define regODM_MEM_PWR_CTRL3_BASE_IDX 2 +#define regODM_MEM_PWR_STATUS 0x1e30 +#define regODM_MEM_PWR_STATUS_BASE_IDX 2 +#define regOPTC_MISC_SPARE_REGISTER 0x1e31 +#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd0_dispdec +// base address: 0x0 +#define regHPD0_DC_HPD_INT_STATUS 0x1f14 +#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD0_DC_HPD_INT_CONTROL 0x1f15 +#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD0_DC_HPD_CONTROL 0x1f16 +#define regHPD0_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 +#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 +#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd1_dispdec +// base address: 0x20 +#define regHPD1_DC_HPD_INT_STATUS 0x1f1c +#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD1_DC_HPD_INT_CONTROL 0x1f1d +#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD1_DC_HPD_CONTROL 0x1f1e +#define regHPD1_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f +#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 +#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd2_dispdec +// base address: 0x40 +#define regHPD2_DC_HPD_INT_STATUS 0x1f24 +#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD2_DC_HPD_INT_CONTROL 0x1f25 +#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD2_DC_HPD_CONTROL 0x1f26 +#define regHPD2_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 +#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 +#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd3_dispdec +// base address: 0x60 +#define regHPD3_DC_HPD_INT_STATUS 0x1f2c +#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD3_DC_HPD_INT_CONTROL 0x1f2d +#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD3_DC_HPD_CONTROL 0x1f2e +#define regHPD3_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f +#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 +#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd4_dispdec +// base address: 0x80 +#define regHPD4_DC_HPD_INT_STATUS 0x1f34 +#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD4_DC_HPD_INT_CONTROL 0x1f35 +#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD4_DC_HPD_CONTROL 0x1f36 +#define regHPD4_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 +#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 +#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp0_dispdec +// base address: 0x0 +#define regDP0_DP_LINK_CNTL 0x2108 +#define regDP0_DP_LINK_CNTL_BASE_IDX 2 +#define regDP0_DP_PIXEL_FORMAT 0x2109 +#define regDP0_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP0_DP_MSA_COLORIMETRY 0x210a +#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP0_DP_CONFIG 0x210b +#define regDP0_DP_CONFIG_BASE_IDX 2 +#define regDP0_DP_VID_STREAM_CNTL 0x210c +#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP0_DP_STEER_FIFO 0x210d +#define regDP0_DP_STEER_FIFO_BASE_IDX 2 +#define regDP0_DP_MSA_MISC 0x210e +#define regDP0_DP_MSA_MISC_BASE_IDX 2 +#define regDP0_DP_DPHY_INTERNAL_CTRL 0x210f +#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP0_DP_VID_TIMING 0x2110 +#define regDP0_DP_VID_TIMING_BASE_IDX 2 +#define regDP0_DP_VID_N 0x2111 +#define regDP0_DP_VID_N_BASE_IDX 2 +#define regDP0_DP_VID_M 0x2112 +#define regDP0_DP_VID_M_BASE_IDX 2 +#define regDP0_DP_LINK_FRAMING_CNTL 0x2113 +#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP0_DP_HBR2_EYE_PATTERN 0x2114 +#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP0_DP_VID_MSA_VBID 0x2115 +#define regDP0_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP0_DP_VID_INTERRUPT_CNTL 0x2116 +#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_CNTL 0x2117 +#define regDP0_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 +#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP0_DP_DPHY_SYM0 0x2119 +#define regDP0_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP0_DP_DPHY_SYM1 0x211a +#define regDP0_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP0_DP_DPHY_SYM2 0x211b +#define regDP0_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP0_DP_DPHY_8B10B_CNTL 0x211c +#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_PRBS_CNTL 0x211d +#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_SCRAM_CNTL 0x211e +#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_EN 0x211f +#define regDP0_DP_DPHY_CRC_EN_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_CNTL 0x2120 +#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_RESULT 0x2121 +#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_MST_CNTL 0x2122 +#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_MST_STATUS 0x2123 +#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define regDP0_DP_DPHY_FAST_TRAINING 0x2124 +#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 +#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL 0x212b +#define regDP0_DP_SEC_CNTL_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL1 0x212c +#define regDP0_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING1 0x212d +#define regDP0_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING2 0x212e +#define regDP0_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING3 0x212f +#define regDP0_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING4 0x2130 +#define regDP0_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_N 0x2131 +#define regDP0_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_N_READBACK 0x2132 +#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_M 0x2133 +#define regDP0_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_M_READBACK 0x2134 +#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP0_DP_SEC_TIMESTAMP 0x2135 +#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP0_DP_SEC_PACKET_CNTL 0x2136 +#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP0_DP_MSE_RATE_CNTL 0x2137 +#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP0_DP_MSE_RATE_UPDATE 0x2139 +#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP0_DP_MSE_SAT0 0x213a +#define regDP0_DP_MSE_SAT0_BASE_IDX 2 +#define regDP0_DP_MSE_SAT1 0x213b +#define regDP0_DP_MSE_SAT1_BASE_IDX 2 +#define regDP0_DP_MSE_SAT2 0x213c +#define regDP0_DP_MSE_SAT2_BASE_IDX 2 +#define regDP0_DP_MSE_SAT_UPDATE 0x213d +#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP0_DP_MSE_LINK_TIMING 0x213e +#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP0_DP_MSE_MISC_CNTL 0x213f +#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 +#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 +#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP0_DP_MSE_SAT0_STATUS 0x2147 +#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP0_DP_MSE_SAT1_STATUS 0x2148 +#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP0_DP_MSE_SAT2_STATUS 0x2149 +#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP0_DP_DPIA_SPARE 0x214a +#define regDP0_DP_DPIA_SPARE_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM1 0x214c +#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM2 0x214d +#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM3 0x214e +#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM4 0x214f +#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP0_DP_MSO_CNTL 0x2150 +#define regDP0_DP_MSO_CNTL_BASE_IDX 2 +#define regDP0_DP_MSO_CNTL1 0x2151 +#define regDP0_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP0_DP_DSC_CNTL 0x2152 +#define regDP0_DP_DSC_CNTL_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL2 0x2153 +#define regDP0_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL3 0x2154 +#define regDP0_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL4 0x2155 +#define regDP0_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL5 0x2156 +#define regDP0_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL6 0x2157 +#define regDP0_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL7 0x2158 +#define regDP0_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP0_DP_DB_CNTL 0x2159 +#define regDP0_DP_DB_CNTL_BASE_IDX 2 +#define regDP0_DP_MSA_VBID_MISC 0x215a +#define regDP0_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP0_DP_SEC_METADATA_TRANSMISSION 0x215b +#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP0_DP_ALPM_CNTL 0x215d +#define regDP0_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP8_CNTL 0x215e +#define regDP0_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP9_CNTL 0x215f +#define regDP0_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP10_CNTL 0x2160 +#define regDP0_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP11_CNTL 0x2161 +#define regDP0_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP_EN_DB_STATUS 0x2162 +#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL1 0x2163 +#define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL2 0x2164 +#define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL3 0x2165 +#define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL4 0x2166 +#define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL5 0x2167 +#define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_dispdec +// base address: 0x0 +#define regDIG0_DIG_FE_CNTL 0x208b +#define regDIG0_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG0_DIG_OUTPUT_CRC_CNTL 0x208c +#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG0_DIG_OUTPUT_CRC_RESULT 0x208d +#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG0_DIG_CLOCK_PATTERN 0x208e +#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG0_DIG_TEST_PATTERN 0x208f +#define regDIG0_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG0_DIG_RANDOM_PATTERN_SEED 0x2090 +#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG0_DIG_FIFO_CTRL0 0x2091 +#define regDIG0_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG0_DIG_FIFO_CTRL1 0x2092 +#define regDIG0_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG0_HDMI_METADATA_PACKET_CONTROL 0x2093 +#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_CONTROL 0x2094 +#define regDIG0_HDMI_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_STATUS 0x2095 +#define regDIG0_HDMI_STATUS_BASE_IDX 2 +#define regDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2096 +#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_ACR_PACKET_CONTROL 0x2097 +#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_VBI_PACKET_CONTROL 0x2098 +#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_INFOFRAME_CONTROL0 0x2099 +#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG0_HDMI_INFOFRAME_CONTROL1 0x209a +#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x209b +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x209c +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x209d +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG0_HDMI_GC 0x209e +#define regDIG0_HDMI_GC_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x209f +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x20a0 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20a1 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20a2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20a3 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20a4 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20a5 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20a6 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG0_HDMI_DB_CONTROL 0x20a7 +#define regDIG0_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_ACR_32_0 0x20a8 +#define regDIG0_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_32_1 0x20a9 +#define regDIG0_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG0_HDMI_ACR_44_0 0x20aa +#define regDIG0_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_44_1 0x20ab +#define regDIG0_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG0_HDMI_ACR_48_0 0x20ac +#define regDIG0_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_48_1 0x20ad +#define regDIG0_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG0_HDMI_ACR_STATUS_0 0x20ae +#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_STATUS_1 0x20af +#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG0_AFMT_CNTL 0x20b0 +#define regDIG0_AFMT_CNTL_BASE_IDX 2 +#define regDIG0_DIG_BE_CNTL 0x20b1 +#define regDIG0_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG0_DIG_BE_EN_CNTL 0x20b2 +#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG0_TMDS_CNTL 0x20d8 +#define regDIG0_TMDS_CNTL_BASE_IDX 2 +#define regDIG0_TMDS_CONTROL_CHAR 0x20d9 +#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG0_TMDS_CONTROL0_FEEDBACK 0x20da +#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20db +#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20dc +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20dd +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG0_TMDS_CTL_BITS 0x20df +#define regDIG0_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG0_TMDS_DCBALANCER_CONTROL 0x20e0 +#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20e1 +#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG0_TMDS_CTL0_1_GEN_CNTL 0x20e2 +#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG0_TMDS_CTL2_3_GEN_CNTL 0x20e3 +#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG0_DIG_VERSION 0x20e5 +#define regDIG0_DIG_VERSION_BASE_IDX 2 +#define regDIG0_FORCE_DIG_DISABLE 0x20e6 +#define regDIG0_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp1_dispdec +// base address: 0x400 +#define regDP1_DP_LINK_CNTL 0x2208 +#define regDP1_DP_LINK_CNTL_BASE_IDX 2 +#define regDP1_DP_PIXEL_FORMAT 0x2209 +#define regDP1_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP1_DP_MSA_COLORIMETRY 0x220a +#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP1_DP_CONFIG 0x220b +#define regDP1_DP_CONFIG_BASE_IDX 2 +#define regDP1_DP_VID_STREAM_CNTL 0x220c +#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP1_DP_STEER_FIFO 0x220d +#define regDP1_DP_STEER_FIFO_BASE_IDX 2 +#define regDP1_DP_MSA_MISC 0x220e +#define regDP1_DP_MSA_MISC_BASE_IDX 2 +#define regDP1_DP_DPHY_INTERNAL_CTRL 0x220f +#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP1_DP_VID_TIMING 0x2210 +#define regDP1_DP_VID_TIMING_BASE_IDX 2 +#define regDP1_DP_VID_N 0x2211 +#define regDP1_DP_VID_N_BASE_IDX 2 +#define regDP1_DP_VID_M 0x2212 +#define regDP1_DP_VID_M_BASE_IDX 2 +#define regDP1_DP_LINK_FRAMING_CNTL 0x2213 +#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP1_DP_HBR2_EYE_PATTERN 0x2214 +#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP1_DP_VID_MSA_VBID 0x2215 +#define regDP1_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP1_DP_VID_INTERRUPT_CNTL 0x2216 +#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_CNTL 0x2217 +#define regDP1_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 +#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP1_DP_DPHY_SYM0 0x2219 +#define regDP1_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP1_DP_DPHY_SYM1 0x221a +#define regDP1_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP1_DP_DPHY_SYM2 0x221b +#define regDP1_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP1_DP_DPHY_8B10B_CNTL 0x221c +#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_PRBS_CNTL 0x221d +#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_SCRAM_CNTL 0x221e +#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_EN 0x221f +#define regDP1_DP_DPHY_CRC_EN_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_CNTL 0x2220 +#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_RESULT 0x2221 +#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_MST_CNTL 0x2222 +#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_MST_STATUS 0x2223 +#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define regDP1_DP_DPHY_FAST_TRAINING 0x2224 +#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 +#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL 0x222b +#define regDP1_DP_SEC_CNTL_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL1 0x222c +#define regDP1_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING1 0x222d +#define regDP1_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING2 0x222e +#define regDP1_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING3 0x222f +#define regDP1_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING4 0x2230 +#define regDP1_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_N 0x2231 +#define regDP1_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_N_READBACK 0x2232 +#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_M 0x2233 +#define regDP1_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_M_READBACK 0x2234 +#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP1_DP_SEC_TIMESTAMP 0x2235 +#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP1_DP_SEC_PACKET_CNTL 0x2236 +#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP1_DP_MSE_RATE_CNTL 0x2237 +#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP1_DP_MSE_RATE_UPDATE 0x2239 +#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP1_DP_MSE_SAT0 0x223a +#define regDP1_DP_MSE_SAT0_BASE_IDX 2 +#define regDP1_DP_MSE_SAT1 0x223b +#define regDP1_DP_MSE_SAT1_BASE_IDX 2 +#define regDP1_DP_MSE_SAT2 0x223c +#define regDP1_DP_MSE_SAT2_BASE_IDX 2 +#define regDP1_DP_MSE_SAT_UPDATE 0x223d +#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP1_DP_MSE_LINK_TIMING 0x223e +#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP1_DP_MSE_MISC_CNTL 0x223f +#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 +#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 +#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP1_DP_MSE_SAT0_STATUS 0x2247 +#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP1_DP_MSE_SAT1_STATUS 0x2248 +#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP1_DP_MSE_SAT2_STATUS 0x2249 +#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP1_DP_DPIA_SPARE 0x224a +#define regDP1_DP_DPIA_SPARE_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM1 0x224c +#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM2 0x224d +#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM3 0x224e +#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM4 0x224f +#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP1_DP_MSO_CNTL 0x2250 +#define regDP1_DP_MSO_CNTL_BASE_IDX 2 +#define regDP1_DP_MSO_CNTL1 0x2251 +#define regDP1_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP1_DP_DSC_CNTL 0x2252 +#define regDP1_DP_DSC_CNTL_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL2 0x2253 +#define regDP1_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL3 0x2254 +#define regDP1_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL4 0x2255 +#define regDP1_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL5 0x2256 +#define regDP1_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL6 0x2257 +#define regDP1_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL7 0x2258 +#define regDP1_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP1_DP_DB_CNTL 0x2259 +#define regDP1_DP_DB_CNTL_BASE_IDX 2 +#define regDP1_DP_MSA_VBID_MISC 0x225a +#define regDP1_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP1_DP_SEC_METADATA_TRANSMISSION 0x225b +#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP1_DP_ALPM_CNTL 0x225d +#define regDP1_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP8_CNTL 0x225e +#define regDP1_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP9_CNTL 0x225f +#define regDP1_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP10_CNTL 0x2260 +#define regDP1_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP11_CNTL 0x2261 +#define regDP1_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP_EN_DB_STATUS 0x2262 +#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL1 0x2263 +#define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL2 0x2264 +#define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL3 0x2265 +#define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL4 0x2266 +#define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL5 0x2267 +#define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_dispdec +// base address: 0x400 +#define regDIG1_DIG_FE_CNTL 0x218b +#define regDIG1_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG1_DIG_OUTPUT_CRC_CNTL 0x218c +#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG1_DIG_OUTPUT_CRC_RESULT 0x218d +#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG1_DIG_CLOCK_PATTERN 0x218e +#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG1_DIG_TEST_PATTERN 0x218f +#define regDIG1_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG1_DIG_RANDOM_PATTERN_SEED 0x2190 +#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG1_DIG_FIFO_CTRL0 0x2191 +#define regDIG1_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG1_DIG_FIFO_CTRL1 0x2192 +#define regDIG1_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG1_HDMI_METADATA_PACKET_CONTROL 0x2193 +#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_CONTROL 0x2194 +#define regDIG1_HDMI_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_STATUS 0x2195 +#define regDIG1_HDMI_STATUS_BASE_IDX 2 +#define regDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2196 +#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_ACR_PACKET_CONTROL 0x2197 +#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_VBI_PACKET_CONTROL 0x2198 +#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_INFOFRAME_CONTROL0 0x2199 +#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG1_HDMI_INFOFRAME_CONTROL1 0x219a +#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x219b +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x219c +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x219d +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG1_HDMI_GC 0x219e +#define regDIG1_HDMI_GC_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x219f +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x21a0 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21a1 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21a2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21a3 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21a4 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21a5 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21a6 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG1_HDMI_DB_CONTROL 0x21a7 +#define regDIG1_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_ACR_32_0 0x21a8 +#define regDIG1_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_32_1 0x21a9 +#define regDIG1_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG1_HDMI_ACR_44_0 0x21aa +#define regDIG1_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_44_1 0x21ab +#define regDIG1_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG1_HDMI_ACR_48_0 0x21ac +#define regDIG1_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_48_1 0x21ad +#define regDIG1_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG1_HDMI_ACR_STATUS_0 0x21ae +#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_STATUS_1 0x21af +#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG1_AFMT_CNTL 0x21b0 +#define regDIG1_AFMT_CNTL_BASE_IDX 2 +#define regDIG1_DIG_BE_CNTL 0x21b1 +#define regDIG1_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG1_DIG_BE_EN_CNTL 0x21b2 +#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG1_TMDS_CNTL 0x21d8 +#define regDIG1_TMDS_CNTL_BASE_IDX 2 +#define regDIG1_TMDS_CONTROL_CHAR 0x21d9 +#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG1_TMDS_CONTROL0_FEEDBACK 0x21da +#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21db +#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21dc +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21dd +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG1_TMDS_CTL_BITS 0x21df +#define regDIG1_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG1_TMDS_DCBALANCER_CONTROL 0x21e0 +#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21e1 +#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG1_TMDS_CTL0_1_GEN_CNTL 0x21e2 +#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG1_TMDS_CTL2_3_GEN_CNTL 0x21e3 +#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG1_DIG_VERSION 0x21e5 +#define regDIG1_DIG_VERSION_BASE_IDX 2 +#define regDIG1_FORCE_DIG_DISABLE 0x21e6 +#define regDIG1_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp2_dispdec +// base address: 0x800 +#define regDP2_DP_LINK_CNTL 0x2308 +#define regDP2_DP_LINK_CNTL_BASE_IDX 2 +#define regDP2_DP_PIXEL_FORMAT 0x2309 +#define regDP2_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP2_DP_MSA_COLORIMETRY 0x230a +#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP2_DP_CONFIG 0x230b +#define regDP2_DP_CONFIG_BASE_IDX 2 +#define regDP2_DP_VID_STREAM_CNTL 0x230c +#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP2_DP_STEER_FIFO 0x230d +#define regDP2_DP_STEER_FIFO_BASE_IDX 2 +#define regDP2_DP_MSA_MISC 0x230e +#define regDP2_DP_MSA_MISC_BASE_IDX 2 +#define regDP2_DP_DPHY_INTERNAL_CTRL 0x230f +#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP2_DP_VID_TIMING 0x2310 +#define regDP2_DP_VID_TIMING_BASE_IDX 2 +#define regDP2_DP_VID_N 0x2311 +#define regDP2_DP_VID_N_BASE_IDX 2 +#define regDP2_DP_VID_M 0x2312 +#define regDP2_DP_VID_M_BASE_IDX 2 +#define regDP2_DP_LINK_FRAMING_CNTL 0x2313 +#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP2_DP_HBR2_EYE_PATTERN 0x2314 +#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP2_DP_VID_MSA_VBID 0x2315 +#define regDP2_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP2_DP_VID_INTERRUPT_CNTL 0x2316 +#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_CNTL 0x2317 +#define regDP2_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318 +#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP2_DP_DPHY_SYM0 0x2319 +#define regDP2_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP2_DP_DPHY_SYM1 0x231a +#define regDP2_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP2_DP_DPHY_SYM2 0x231b +#define regDP2_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP2_DP_DPHY_8B10B_CNTL 0x231c +#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_PRBS_CNTL 0x231d +#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_SCRAM_CNTL 0x231e +#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_EN 0x231f +#define regDP2_DP_DPHY_CRC_EN_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_CNTL 0x2320 +#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_RESULT 0x2321 +#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_MST_CNTL 0x2322 +#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_MST_STATUS 0x2323 +#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define regDP2_DP_DPHY_FAST_TRAINING 0x2324 +#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325 +#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL 0x232b +#define regDP2_DP_SEC_CNTL_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL1 0x232c +#define regDP2_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING1 0x232d +#define regDP2_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING2 0x232e +#define regDP2_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING3 0x232f +#define regDP2_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING4 0x2330 +#define regDP2_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_N 0x2331 +#define regDP2_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_N_READBACK 0x2332 +#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_M 0x2333 +#define regDP2_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_M_READBACK 0x2334 +#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP2_DP_SEC_TIMESTAMP 0x2335 +#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP2_DP_SEC_PACKET_CNTL 0x2336 +#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP2_DP_MSE_RATE_CNTL 0x2337 +#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP2_DP_MSE_RATE_UPDATE 0x2339 +#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP2_DP_MSE_SAT0 0x233a +#define regDP2_DP_MSE_SAT0_BASE_IDX 2 +#define regDP2_DP_MSE_SAT1 0x233b +#define regDP2_DP_MSE_SAT1_BASE_IDX 2 +#define regDP2_DP_MSE_SAT2 0x233c +#define regDP2_DP_MSE_SAT2_BASE_IDX 2 +#define regDP2_DP_MSE_SAT_UPDATE 0x233d +#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP2_DP_MSE_LINK_TIMING 0x233e +#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP2_DP_MSE_MISC_CNTL 0x233f +#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344 +#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345 +#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP2_DP_MSE_SAT0_STATUS 0x2347 +#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP2_DP_MSE_SAT1_STATUS 0x2348 +#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP2_DP_MSE_SAT2_STATUS 0x2349 +#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP2_DP_DPIA_SPARE 0x234a +#define regDP2_DP_DPIA_SPARE_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM1 0x234c +#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM2 0x234d +#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM3 0x234e +#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM4 0x234f +#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP2_DP_MSO_CNTL 0x2350 +#define regDP2_DP_MSO_CNTL_BASE_IDX 2 +#define regDP2_DP_MSO_CNTL1 0x2351 +#define regDP2_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP2_DP_DSC_CNTL 0x2352 +#define regDP2_DP_DSC_CNTL_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL2 0x2353 +#define regDP2_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL3 0x2354 +#define regDP2_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL4 0x2355 +#define regDP2_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL5 0x2356 +#define regDP2_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL6 0x2357 +#define regDP2_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL7 0x2358 +#define regDP2_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP2_DP_DB_CNTL 0x2359 +#define regDP2_DP_DB_CNTL_BASE_IDX 2 +#define regDP2_DP_MSA_VBID_MISC 0x235a +#define regDP2_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP2_DP_SEC_METADATA_TRANSMISSION 0x235b +#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP2_DP_ALPM_CNTL 0x235d +#define regDP2_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP8_CNTL 0x235e +#define regDP2_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP9_CNTL 0x235f +#define regDP2_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP10_CNTL 0x2360 +#define regDP2_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP11_CNTL 0x2361 +#define regDP2_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP_EN_DB_STATUS 0x2362 +#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL1 0x2363 +#define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL2 0x2364 +#define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL3 0x2365 +#define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL4 0x2366 +#define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL5 0x2367 +#define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig2_dispdec +// base address: 0x800 +#define regDIG2_DIG_FE_CNTL 0x228b +#define regDIG2_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG2_DIG_OUTPUT_CRC_CNTL 0x228c +#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG2_DIG_OUTPUT_CRC_RESULT 0x228d +#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG2_DIG_CLOCK_PATTERN 0x228e +#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG2_DIG_TEST_PATTERN 0x228f +#define regDIG2_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG2_DIG_RANDOM_PATTERN_SEED 0x2290 +#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG2_DIG_FIFO_CTRL0 0x2291 +#define regDIG2_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG2_DIG_FIFO_CTRL1 0x2292 +#define regDIG2_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG2_HDMI_METADATA_PACKET_CONTROL 0x2293 +#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_CONTROL 0x2294 +#define regDIG2_HDMI_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_STATUS 0x2295 +#define regDIG2_HDMI_STATUS_BASE_IDX 2 +#define regDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2296 +#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_ACR_PACKET_CONTROL 0x2297 +#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_VBI_PACKET_CONTROL 0x2298 +#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_INFOFRAME_CONTROL0 0x2299 +#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG2_HDMI_INFOFRAME_CONTROL1 0x229a +#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x229b +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x229c +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x229d +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG2_HDMI_GC 0x229e +#define regDIG2_HDMI_GC_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x229f +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x22a0 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22a1 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22a2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22a3 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22a4 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22a5 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22a6 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG2_HDMI_DB_CONTROL 0x22a7 +#define regDIG2_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_ACR_32_0 0x22a8 +#define regDIG2_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_32_1 0x22a9 +#define regDIG2_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG2_HDMI_ACR_44_0 0x22aa +#define regDIG2_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_44_1 0x22ab +#define regDIG2_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG2_HDMI_ACR_48_0 0x22ac +#define regDIG2_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_48_1 0x22ad +#define regDIG2_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG2_HDMI_ACR_STATUS_0 0x22ae +#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_STATUS_1 0x22af +#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG2_AFMT_CNTL 0x22b0 +#define regDIG2_AFMT_CNTL_BASE_IDX 2 +#define regDIG2_DIG_BE_CNTL 0x22b1 +#define regDIG2_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG2_DIG_BE_EN_CNTL 0x22b2 +#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG2_TMDS_CNTL 0x22d8 +#define regDIG2_TMDS_CNTL_BASE_IDX 2 +#define regDIG2_TMDS_CONTROL_CHAR 0x22d9 +#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG2_TMDS_CONTROL0_FEEDBACK 0x22da +#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22db +#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22dc +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22dd +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG2_TMDS_CTL_BITS 0x22df +#define regDIG2_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG2_TMDS_DCBALANCER_CONTROL 0x22e0 +#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22e1 +#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG2_TMDS_CTL0_1_GEN_CNTL 0x22e2 +#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG2_TMDS_CTL2_3_GEN_CNTL 0x22e3 +#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG2_DIG_VERSION 0x22e5 +#define regDIG2_DIG_VERSION_BASE_IDX 2 +#define regDIG2_FORCE_DIG_DISABLE 0x22e6 +#define regDIG2_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp3_dispdec +// base address: 0xc00 +#define regDP3_DP_LINK_CNTL 0x2408 +#define regDP3_DP_LINK_CNTL_BASE_IDX 2 +#define regDP3_DP_PIXEL_FORMAT 0x2409 +#define regDP3_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP3_DP_MSA_COLORIMETRY 0x240a +#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP3_DP_CONFIG 0x240b +#define regDP3_DP_CONFIG_BASE_IDX 2 +#define regDP3_DP_VID_STREAM_CNTL 0x240c +#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP3_DP_STEER_FIFO 0x240d +#define regDP3_DP_STEER_FIFO_BASE_IDX 2 +#define regDP3_DP_MSA_MISC 0x240e +#define regDP3_DP_MSA_MISC_BASE_IDX 2 +#define regDP3_DP_DPHY_INTERNAL_CTRL 0x240f +#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP3_DP_VID_TIMING 0x2410 +#define regDP3_DP_VID_TIMING_BASE_IDX 2 +#define regDP3_DP_VID_N 0x2411 +#define regDP3_DP_VID_N_BASE_IDX 2 +#define regDP3_DP_VID_M 0x2412 +#define regDP3_DP_VID_M_BASE_IDX 2 +#define regDP3_DP_LINK_FRAMING_CNTL 0x2413 +#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP3_DP_HBR2_EYE_PATTERN 0x2414 +#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP3_DP_VID_MSA_VBID 0x2415 +#define regDP3_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP3_DP_VID_INTERRUPT_CNTL 0x2416 +#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_CNTL 0x2417 +#define regDP3_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418 +#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP3_DP_DPHY_SYM0 0x2419 +#define regDP3_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP3_DP_DPHY_SYM1 0x241a +#define regDP3_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP3_DP_DPHY_SYM2 0x241b +#define regDP3_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP3_DP_DPHY_8B10B_CNTL 0x241c +#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_PRBS_CNTL 0x241d +#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_SCRAM_CNTL 0x241e +#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_EN 0x241f +#define regDP3_DP_DPHY_CRC_EN_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_CNTL 0x2420 +#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_RESULT 0x2421 +#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_MST_CNTL 0x2422 +#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_MST_STATUS 0x2423 +#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define regDP3_DP_DPHY_FAST_TRAINING 0x2424 +#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425 +#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL 0x242b +#define regDP3_DP_SEC_CNTL_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL1 0x242c +#define regDP3_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING1 0x242d +#define regDP3_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING2 0x242e +#define regDP3_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING3 0x242f +#define regDP3_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING4 0x2430 +#define regDP3_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_N 0x2431 +#define regDP3_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_N_READBACK 0x2432 +#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_M 0x2433 +#define regDP3_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_M_READBACK 0x2434 +#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP3_DP_SEC_TIMESTAMP 0x2435 +#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP3_DP_SEC_PACKET_CNTL 0x2436 +#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP3_DP_MSE_RATE_CNTL 0x2437 +#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP3_DP_MSE_RATE_UPDATE 0x2439 +#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP3_DP_MSE_SAT0 0x243a +#define regDP3_DP_MSE_SAT0_BASE_IDX 2 +#define regDP3_DP_MSE_SAT1 0x243b +#define regDP3_DP_MSE_SAT1_BASE_IDX 2 +#define regDP3_DP_MSE_SAT2 0x243c +#define regDP3_DP_MSE_SAT2_BASE_IDX 2 +#define regDP3_DP_MSE_SAT_UPDATE 0x243d +#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP3_DP_MSE_LINK_TIMING 0x243e +#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP3_DP_MSE_MISC_CNTL 0x243f +#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444 +#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445 +#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP3_DP_MSE_SAT0_STATUS 0x2447 +#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP3_DP_MSE_SAT1_STATUS 0x2448 +#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP3_DP_MSE_SAT2_STATUS 0x2449 +#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP3_DP_DPIA_SPARE 0x244a +#define regDP3_DP_DPIA_SPARE_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM1 0x244c +#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM2 0x244d +#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM3 0x244e +#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM4 0x244f +#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP3_DP_MSO_CNTL 0x2450 +#define regDP3_DP_MSO_CNTL_BASE_IDX 2 +#define regDP3_DP_MSO_CNTL1 0x2451 +#define regDP3_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP3_DP_DSC_CNTL 0x2452 +#define regDP3_DP_DSC_CNTL_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL2 0x2453 +#define regDP3_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL3 0x2454 +#define regDP3_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL4 0x2455 +#define regDP3_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL5 0x2456 +#define regDP3_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL6 0x2457 +#define regDP3_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL7 0x2458 +#define regDP3_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP3_DP_DB_CNTL 0x2459 +#define regDP3_DP_DB_CNTL_BASE_IDX 2 +#define regDP3_DP_MSA_VBID_MISC 0x245a +#define regDP3_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP3_DP_SEC_METADATA_TRANSMISSION 0x245b +#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP3_DP_ALPM_CNTL 0x245d +#define regDP3_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP8_CNTL 0x245e +#define regDP3_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP9_CNTL 0x245f +#define regDP3_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP10_CNTL 0x2460 +#define regDP3_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP11_CNTL 0x2461 +#define regDP3_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP_EN_DB_STATUS 0x2462 +#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL1 0x2463 +#define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL2 0x2464 +#define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL3 0x2465 +#define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL4 0x2466 +#define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL5 0x2467 +#define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig3_dispdec +// base address: 0xc00 +#define regDIG3_DIG_FE_CNTL 0x238b +#define regDIG3_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG3_DIG_OUTPUT_CRC_CNTL 0x238c +#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG3_DIG_OUTPUT_CRC_RESULT 0x238d +#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG3_DIG_CLOCK_PATTERN 0x238e +#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG3_DIG_TEST_PATTERN 0x238f +#define regDIG3_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG3_DIG_RANDOM_PATTERN_SEED 0x2390 +#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG3_DIG_FIFO_CTRL0 0x2391 +#define regDIG3_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG3_DIG_FIFO_CTRL1 0x2392 +#define regDIG3_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG3_HDMI_METADATA_PACKET_CONTROL 0x2393 +#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_CONTROL 0x2394 +#define regDIG3_HDMI_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_STATUS 0x2395 +#define regDIG3_HDMI_STATUS_BASE_IDX 2 +#define regDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2396 +#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_ACR_PACKET_CONTROL 0x2397 +#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_VBI_PACKET_CONTROL 0x2398 +#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_INFOFRAME_CONTROL0 0x2399 +#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG3_HDMI_INFOFRAME_CONTROL1 0x239a +#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x239b +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x239c +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x239d +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG3_HDMI_GC 0x239e +#define regDIG3_HDMI_GC_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x239f +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x23a0 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x23a1 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x23a2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x23a3 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x23a4 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x23a5 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x23a6 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG3_HDMI_DB_CONTROL 0x23a7 +#define regDIG3_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_ACR_32_0 0x23a8 +#define regDIG3_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_32_1 0x23a9 +#define regDIG3_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG3_HDMI_ACR_44_0 0x23aa +#define regDIG3_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_44_1 0x23ab +#define regDIG3_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG3_HDMI_ACR_48_0 0x23ac +#define regDIG3_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_48_1 0x23ad +#define regDIG3_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG3_HDMI_ACR_STATUS_0 0x23ae +#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_STATUS_1 0x23af +#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG3_AFMT_CNTL 0x23b0 +#define regDIG3_AFMT_CNTL_BASE_IDX 2 +#define regDIG3_DIG_BE_CNTL 0x23b1 +#define regDIG3_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG3_DIG_BE_EN_CNTL 0x23b2 +#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG3_TMDS_CNTL 0x23d8 +#define regDIG3_TMDS_CNTL_BASE_IDX 2 +#define regDIG3_TMDS_CONTROL_CHAR 0x23d9 +#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG3_TMDS_CONTROL0_FEEDBACK 0x23da +#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23db +#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23dc +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23dd +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG3_TMDS_CTL_BITS 0x23df +#define regDIG3_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG3_TMDS_DCBALANCER_CONTROL 0x23e0 +#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23e1 +#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG3_TMDS_CTL0_1_GEN_CNTL 0x23e2 +#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG3_TMDS_CTL2_3_GEN_CNTL 0x23e3 +#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG3_DIG_VERSION 0x23e5 +#define regDIG3_DIG_VERSION_BASE_IDX 2 +#define regDIG3_FORCE_DIG_DISABLE 0x23e6 +#define regDIG3_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp4_dispdec +// base address: 0x1000 +#define regDP4_DP_LINK_CNTL 0x2508 +#define regDP4_DP_LINK_CNTL_BASE_IDX 2 +#define regDP4_DP_PIXEL_FORMAT 0x2509 +#define regDP4_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP4_DP_MSA_COLORIMETRY 0x250a +#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP4_DP_CONFIG 0x250b +#define regDP4_DP_CONFIG_BASE_IDX 2 +#define regDP4_DP_VID_STREAM_CNTL 0x250c +#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP4_DP_STEER_FIFO 0x250d +#define regDP4_DP_STEER_FIFO_BASE_IDX 2 +#define regDP4_DP_MSA_MISC 0x250e +#define regDP4_DP_MSA_MISC_BASE_IDX 2 +#define regDP4_DP_DPHY_INTERNAL_CTRL 0x250f +#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP4_DP_VID_TIMING 0x2510 +#define regDP4_DP_VID_TIMING_BASE_IDX 2 +#define regDP4_DP_VID_N 0x2511 +#define regDP4_DP_VID_N_BASE_IDX 2 +#define regDP4_DP_VID_M 0x2512 +#define regDP4_DP_VID_M_BASE_IDX 2 +#define regDP4_DP_LINK_FRAMING_CNTL 0x2513 +#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP4_DP_HBR2_EYE_PATTERN 0x2514 +#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP4_DP_VID_MSA_VBID 0x2515 +#define regDP4_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP4_DP_VID_INTERRUPT_CNTL 0x2516 +#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_CNTL 0x2517 +#define regDP4_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518 +#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP4_DP_DPHY_SYM0 0x2519 +#define regDP4_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP4_DP_DPHY_SYM1 0x251a +#define regDP4_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP4_DP_DPHY_SYM2 0x251b +#define regDP4_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP4_DP_DPHY_8B10B_CNTL 0x251c +#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_PRBS_CNTL 0x251d +#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_SCRAM_CNTL 0x251e +#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_EN 0x251f +#define regDP4_DP_DPHY_CRC_EN_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_CNTL 0x2520 +#define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_RESULT 0x2521 +#define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_MST_CNTL 0x2522 +#define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_MST_STATUS 0x2523 +#define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define regDP4_DP_DPHY_FAST_TRAINING 0x2524 +#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525 +#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL 0x252b +#define regDP4_DP_SEC_CNTL_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL1 0x252c +#define regDP4_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING1 0x252d +#define regDP4_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING2 0x252e +#define regDP4_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING3 0x252f +#define regDP4_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING4 0x2530 +#define regDP4_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_N 0x2531 +#define regDP4_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_N_READBACK 0x2532 +#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_M 0x2533 +#define regDP4_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_M_READBACK 0x2534 +#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP4_DP_SEC_TIMESTAMP 0x2535 +#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP4_DP_SEC_PACKET_CNTL 0x2536 +#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP4_DP_MSE_RATE_CNTL 0x2537 +#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP4_DP_MSE_RATE_UPDATE 0x2539 +#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP4_DP_MSE_SAT0 0x253a +#define regDP4_DP_MSE_SAT0_BASE_IDX 2 +#define regDP4_DP_MSE_SAT1 0x253b +#define regDP4_DP_MSE_SAT1_BASE_IDX 2 +#define regDP4_DP_MSE_SAT2 0x253c +#define regDP4_DP_MSE_SAT2_BASE_IDX 2 +#define regDP4_DP_MSE_SAT_UPDATE 0x253d +#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP4_DP_MSE_LINK_TIMING 0x253e +#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP4_DP_MSE_MISC_CNTL 0x253f +#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544 +#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545 +#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP4_DP_MSE_SAT0_STATUS 0x2547 +#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP4_DP_MSE_SAT1_STATUS 0x2548 +#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP4_DP_MSE_SAT2_STATUS 0x2549 +#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP4_DP_DPIA_SPARE 0x254a +#define regDP4_DP_DPIA_SPARE_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM1 0x254c +#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM2 0x254d +#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM3 0x254e +#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM4 0x254f +#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP4_DP_MSO_CNTL 0x2550 +#define regDP4_DP_MSO_CNTL_BASE_IDX 2 +#define regDP4_DP_MSO_CNTL1 0x2551 +#define regDP4_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP4_DP_DSC_CNTL 0x2552 +#define regDP4_DP_DSC_CNTL_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL2 0x2553 +#define regDP4_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL3 0x2554 +#define regDP4_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL4 0x2555 +#define regDP4_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL5 0x2556 +#define regDP4_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL6 0x2557 +#define regDP4_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL7 0x2558 +#define regDP4_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP4_DP_DB_CNTL 0x2559 +#define regDP4_DP_DB_CNTL_BASE_IDX 2 +#define regDP4_DP_MSA_VBID_MISC 0x255a +#define regDP4_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP4_DP_SEC_METADATA_TRANSMISSION 0x255b +#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP4_DP_ALPM_CNTL 0x255d +#define regDP4_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP8_CNTL 0x255e +#define regDP4_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP9_CNTL 0x255f +#define regDP4_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP10_CNTL 0x2560 +#define regDP4_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP11_CNTL 0x2561 +#define regDP4_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP_EN_DB_STATUS 0x2562 +#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL1 0x2563 +#define regDP4_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL2 0x2564 +#define regDP4_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL3 0x2565 +#define regDP4_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL4 0x2566 +#define regDP4_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL5 0x2567 +#define regDP4_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig4_dispdec +// base address: 0x1000 +#define regDIG4_DIG_FE_CNTL 0x248b +#define regDIG4_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG4_DIG_OUTPUT_CRC_CNTL 0x248c +#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG4_DIG_OUTPUT_CRC_RESULT 0x248d +#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG4_DIG_CLOCK_PATTERN 0x248e +#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG4_DIG_TEST_PATTERN 0x248f +#define regDIG4_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG4_DIG_RANDOM_PATTERN_SEED 0x2490 +#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG4_DIG_FIFO_CTRL0 0x2491 +#define regDIG4_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG4_DIG_FIFO_CTRL1 0x2492 +#define regDIG4_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG4_HDMI_METADATA_PACKET_CONTROL 0x2493 +#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_CONTROL 0x2494 +#define regDIG4_HDMI_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_STATUS 0x2495 +#define regDIG4_HDMI_STATUS_BASE_IDX 2 +#define regDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2496 +#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_ACR_PACKET_CONTROL 0x2497 +#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_VBI_PACKET_CONTROL 0x2498 +#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_INFOFRAME_CONTROL0 0x2499 +#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG4_HDMI_INFOFRAME_CONTROL1 0x249a +#define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x249b +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x249c +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x249d +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG4_HDMI_GC 0x249e +#define regDIG4_HDMI_GC_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x249f +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x24a0 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x24a1 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x24a2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x24a3 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x24a4 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x24a5 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x24a6 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG4_HDMI_DB_CONTROL 0x24a7 +#define regDIG4_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_ACR_32_0 0x24a8 +#define regDIG4_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_32_1 0x24a9 +#define regDIG4_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG4_HDMI_ACR_44_0 0x24aa +#define regDIG4_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_44_1 0x24ab +#define regDIG4_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG4_HDMI_ACR_48_0 0x24ac +#define regDIG4_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_48_1 0x24ad +#define regDIG4_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG4_HDMI_ACR_STATUS_0 0x24ae +#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_STATUS_1 0x24af +#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG4_AFMT_CNTL 0x24b0 +#define regDIG4_AFMT_CNTL_BASE_IDX 2 +#define regDIG4_DIG_BE_CNTL 0x24b1 +#define regDIG4_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG4_DIG_BE_EN_CNTL 0x24b2 +#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG4_TMDS_CNTL 0x24d8 +#define regDIG4_TMDS_CNTL_BASE_IDX 2 +#define regDIG4_TMDS_CONTROL_CHAR 0x24d9 +#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG4_TMDS_CONTROL0_FEEDBACK 0x24da +#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24db +#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24dc +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24dd +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG4_TMDS_CTL_BITS 0x24df +#define regDIG4_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG4_TMDS_DCBALANCER_CONTROL 0x24e0 +#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24e1 +#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG4_TMDS_CTL0_1_GEN_CNTL 0x24e2 +#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG4_TMDS_CTL2_3_GEN_CNTL 0x24e3 +#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG4_DIG_VERSION 0x24e5 +#define regDIG4_DIG_VERSION_BASE_IDX 2 +#define regDIG4_FORCE_DIG_DISABLE 0x24e6 +#define regDIG4_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec +// base address: 0x154cc +#define regAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074 +#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075 +#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_INFO0 0x2076 +#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_INFO1 0x2077 +#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define regAFMT0_AFMT_60958_0 0x2078 +#define regAFMT0_AFMT_60958_0_BASE_IDX 2 +#define regAFMT0_AFMT_60958_1 0x2079 +#define regAFMT0_AFMT_60958_1_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a +#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAFMT0_AFMT_RAMP_CONTROL0 0x207b +#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define regAFMT0_AFMT_RAMP_CONTROL1 0x207c +#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define regAFMT0_AFMT_RAMP_CONTROL2 0x207d +#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define regAFMT0_AFMT_RAMP_CONTROL3 0x207e +#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define regAFMT0_AFMT_60958_2 0x207f +#define regAFMT0_AFMT_60958_2_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080 +#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAFMT0_AFMT_STATUS 0x2081 +#define regAFMT0_AFMT_STATUS_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082 +#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083 +#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regAFMT0_AFMT_INTERRUPT_STATUS 0x2084 +#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085 +#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define regAFMT0_AFMT_MEM_PWR 0x2087 +#define regAFMT0_AFMT_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec +// base address: 0x158cc +#define regAFMT1_AFMT_VBI_PACKET_CONTROL 0x2174 +#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2175 +#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_INFO0 0x2176 +#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_INFO1 0x2177 +#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define regAFMT1_AFMT_60958_0 0x2178 +#define regAFMT1_AFMT_60958_0_BASE_IDX 2 +#define regAFMT1_AFMT_60958_1 0x2179 +#define regAFMT1_AFMT_60958_1_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_CRC_CONTROL 0x217a +#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAFMT1_AFMT_RAMP_CONTROL0 0x217b +#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define regAFMT1_AFMT_RAMP_CONTROL1 0x217c +#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define regAFMT1_AFMT_RAMP_CONTROL2 0x217d +#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define regAFMT1_AFMT_RAMP_CONTROL3 0x217e +#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define regAFMT1_AFMT_60958_2 0x217f +#define regAFMT1_AFMT_60958_2_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_CRC_RESULT 0x2180 +#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAFMT1_AFMT_STATUS 0x2181 +#define regAFMT1_AFMT_STATUS_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x2182 +#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT1_AFMT_INFOFRAME_CONTROL0 0x2183 +#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regAFMT1_AFMT_INTERRUPT_STATUS 0x2184 +#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_SRC_CONTROL 0x2185 +#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define regAFMT1_AFMT_MEM_PWR 0x2187 +#define regAFMT1_AFMT_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec +// base address: 0x15ccc +#define regAFMT2_AFMT_VBI_PACKET_CONTROL 0x2274 +#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x2275 +#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_INFO0 0x2276 +#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_INFO1 0x2277 +#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define regAFMT2_AFMT_60958_0 0x2278 +#define regAFMT2_AFMT_60958_0_BASE_IDX 2 +#define regAFMT2_AFMT_60958_1 0x2279 +#define regAFMT2_AFMT_60958_1_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_CRC_CONTROL 0x227a +#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAFMT2_AFMT_RAMP_CONTROL0 0x227b +#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define regAFMT2_AFMT_RAMP_CONTROL1 0x227c +#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define regAFMT2_AFMT_RAMP_CONTROL2 0x227d +#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define regAFMT2_AFMT_RAMP_CONTROL3 0x227e +#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define regAFMT2_AFMT_60958_2 0x227f +#define regAFMT2_AFMT_60958_2_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_CRC_RESULT 0x2280 +#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAFMT2_AFMT_STATUS 0x2281 +#define regAFMT2_AFMT_STATUS_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x2282 +#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT2_AFMT_INFOFRAME_CONTROL0 0x2283 +#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regAFMT2_AFMT_INTERRUPT_STATUS 0x2284 +#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_SRC_CONTROL 0x2285 +#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define regAFMT2_AFMT_MEM_PWR 0x2287 +#define regAFMT2_AFMT_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec +// base address: 0x160cc +#define regAFMT3_AFMT_VBI_PACKET_CONTROL 0x2374 +#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x2375 +#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_INFO0 0x2376 +#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_INFO1 0x2377 +#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define regAFMT3_AFMT_60958_0 0x2378 +#define regAFMT3_AFMT_60958_0_BASE_IDX 2 +#define regAFMT3_AFMT_60958_1 0x2379 +#define regAFMT3_AFMT_60958_1_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_CRC_CONTROL 0x237a +#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAFMT3_AFMT_RAMP_CONTROL0 0x237b +#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define regAFMT3_AFMT_RAMP_CONTROL1 0x237c +#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define regAFMT3_AFMT_RAMP_CONTROL2 0x237d +#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define regAFMT3_AFMT_RAMP_CONTROL3 0x237e +#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define regAFMT3_AFMT_60958_2 0x237f +#define regAFMT3_AFMT_60958_2_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_CRC_RESULT 0x2380 +#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAFMT3_AFMT_STATUS 0x2381 +#define regAFMT3_AFMT_STATUS_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x2382 +#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT3_AFMT_INFOFRAME_CONTROL0 0x2383 +#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regAFMT3_AFMT_INTERRUPT_STATUS 0x2384 +#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_SRC_CONTROL 0x2385 +#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define regAFMT3_AFMT_MEM_PWR 0x2387 +#define regAFMT3_AFMT_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec +// base address: 0x164cc +#define regAFMT4_AFMT_VBI_PACKET_CONTROL 0x2474 +#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x2475 +#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_INFO0 0x2476 +#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_INFO1 0x2477 +#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define regAFMT4_AFMT_60958_0 0x2478 +#define regAFMT4_AFMT_60958_0_BASE_IDX 2 +#define regAFMT4_AFMT_60958_1 0x2479 +#define regAFMT4_AFMT_60958_1_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_CRC_CONTROL 0x247a +#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAFMT4_AFMT_RAMP_CONTROL0 0x247b +#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define regAFMT4_AFMT_RAMP_CONTROL1 0x247c +#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define regAFMT4_AFMT_RAMP_CONTROL2 0x247d +#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define regAFMT4_AFMT_RAMP_CONTROL3 0x247e +#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define regAFMT4_AFMT_60958_2 0x247f +#define regAFMT4_AFMT_60958_2_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_CRC_RESULT 0x2480 +#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAFMT4_AFMT_STATUS 0x2481 +#define regAFMT4_AFMT_STATUS_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x2482 +#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT4_AFMT_INFOFRAME_CONTROL0 0x2483 +#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regAFMT4_AFMT_INTERRUPT_STATUS 0x2484 +#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_SRC_CONTROL 0x2485 +#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define regAFMT4_AFMT_MEM_PWR 0x2487 +#define regAFMT4_AFMT_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec +// base address: 0x15524 +#define regDME0_DME_CONTROL 0x2089 +#define regDME0_DME_CONTROL_BASE_IDX 2 +#define regDME0_DME_MEMORY_CONTROL 0x208a +#define regDME0_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec +// base address: 0x154a0 +#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 +#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG0_VPG_GENERIC_PACKET_DATA 0x2069 +#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a +#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b +#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG0_VPG_GENERIC_STATUS 0x206c +#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG0_VPG_MEM_PWR 0x206d +#define regVPG0_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e +#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG0_VPG_ISRC1_2_DATA 0x206f +#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG0_VPG_MPEG_INFO0 0x2070 +#define regVPG0_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG0_VPG_MPEG_INFO1 0x2071 +#define regVPG0_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec +// base address: 0x15924 +#define regDME1_DME_CONTROL 0x2189 +#define regDME1_DME_CONTROL_BASE_IDX 2 +#define regDME1_DME_MEMORY_CONTROL 0x218a +#define regDME1_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec +// base address: 0x158a0 +#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2168 +#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG1_VPG_GENERIC_PACKET_DATA 0x2169 +#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x216a +#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x216b +#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG1_VPG_GENERIC_STATUS 0x216c +#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG1_VPG_MEM_PWR 0x216d +#define regVPG1_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x216e +#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG1_VPG_ISRC1_2_DATA 0x216f +#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG1_VPG_MPEG_INFO0 0x2170 +#define regVPG1_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG1_VPG_MPEG_INFO1 0x2171 +#define regVPG1_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec +// base address: 0x15d24 +#define regDME2_DME_CONTROL 0x2289 +#define regDME2_DME_CONTROL_BASE_IDX 2 +#define regDME2_DME_MEMORY_CONTROL 0x228a +#define regDME2_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec +// base address: 0x15ca0 +#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2268 +#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG2_VPG_GENERIC_PACKET_DATA 0x2269 +#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x226a +#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x226b +#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG2_VPG_GENERIC_STATUS 0x226c +#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG2_VPG_MEM_PWR 0x226d +#define regVPG2_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x226e +#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG2_VPG_ISRC1_2_DATA 0x226f +#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG2_VPG_MPEG_INFO0 0x2270 +#define regVPG2_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG2_VPG_MPEG_INFO1 0x2271 +#define regVPG2_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec +// base address: 0x16124 +#define regDME3_DME_CONTROL 0x2389 +#define regDME3_DME_CONTROL_BASE_IDX 2 +#define regDME3_DME_MEMORY_CONTROL 0x238a +#define regDME3_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec +// base address: 0x160a0 +#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2368 +#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG3_VPG_GENERIC_PACKET_DATA 0x2369 +#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x236a +#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x236b +#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG3_VPG_GENERIC_STATUS 0x236c +#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG3_VPG_MEM_PWR 0x236d +#define regVPG3_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x236e +#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG3_VPG_ISRC1_2_DATA 0x236f +#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG3_VPG_MPEG_INFO0 0x2370 +#define regVPG3_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG3_VPG_MPEG_INFO1 0x2371 +#define regVPG3_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec +// base address: 0x16524 +#define regDME4_DME_CONTROL 0x2489 +#define regDME4_DME_CONTROL_BASE_IDX 2 +#define regDME4_DME_MEMORY_CONTROL 0x248a +#define regDME4_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec +// base address: 0x164a0 +#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2468 +#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG4_VPG_GENERIC_PACKET_DATA 0x2469 +#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x246a +#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x246b +#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG4_VPG_GENERIC_STATUS 0x246c +#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG4_VPG_MEM_PWR 0x246d +#define regVPG4_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x246e +#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG4_VPG_ISRC1_2_DATA 0x246f +#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG4_VPG_MPEG_INFO0 0x2470 +#define regVPG4_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG4_VPG_MPEG_INFO1 0x2471 +#define regVPG4_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux0_dispdec +// base address: 0x0 +#define regDP_AUX0_AUX_CONTROL 0x1f50 +#define regDP_AUX0_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_SW_CONTROL 0x1f51 +#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_ARB_CONTROL 0x1f52 +#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 +#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_SW_STATUS 0x1f54 +#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_LS_STATUS 0x1f55 +#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_SW_DATA 0x1f56 +#define regDP_AUX0_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX0_AUX_LS_DATA 0x1f57 +#define regDP_AUX0_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 +#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 +#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a +#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b +#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c +#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d +#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e +#define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f +#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 +#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 +#define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 +#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux1_dispdec +// base address: 0x70 +#define regDP_AUX1_AUX_CONTROL 0x1f6c +#define regDP_AUX1_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_SW_CONTROL 0x1f6d +#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_ARB_CONTROL 0x1f6e +#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f +#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_SW_STATUS 0x1f70 +#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_LS_STATUS 0x1f71 +#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_SW_DATA 0x1f72 +#define regDP_AUX1_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX1_AUX_LS_DATA 0x1f73 +#define regDP_AUX1_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 +#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 +#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 +#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 +#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a +#define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b +#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c +#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d +#define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 +#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux2_dispdec +// base address: 0xe0 +#define regDP_AUX2_AUX_CONTROL 0x1f88 +#define regDP_AUX2_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_SW_CONTROL 0x1f89 +#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_ARB_CONTROL 0x1f8a +#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b +#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_SW_STATUS 0x1f8c +#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_LS_STATUS 0x1f8d +#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_SW_DATA 0x1f8e +#define regDP_AUX2_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX2_AUX_LS_DATA 0x1f8f +#define regDP_AUX2_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 +#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 +#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 +#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 +#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96 +#define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 +#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 +#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 +#define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e +#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux3_dispdec +// base address: 0x150 +#define regDP_AUX3_AUX_CONTROL 0x1fa4 +#define regDP_AUX3_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_SW_CONTROL 0x1fa5 +#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_ARB_CONTROL 0x1fa6 +#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 +#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_SW_STATUS 0x1fa8 +#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_LS_STATUS 0x1fa9 +#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_SW_DATA 0x1faa +#define regDP_AUX3_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX3_AUX_LS_DATA 0x1fab +#define regDP_AUX3_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac +#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad +#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae +#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf +#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 +#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 +#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2 +#define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 +#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 +#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 +#define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba +#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux4_dispdec +// base address: 0x1c0 +#define regDP_AUX4_AUX_CONTROL 0x1fc0 +#define regDP_AUX4_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_SW_CONTROL 0x1fc1 +#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_ARB_CONTROL 0x1fc2 +#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 +#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_SW_STATUS 0x1fc4 +#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_LS_STATUS 0x1fc5 +#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_SW_DATA 0x1fc6 +#define regDP_AUX4_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX4_AUX_LS_DATA 0x1fc7 +#define regDP_AUX4_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 +#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 +#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca +#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb +#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc +#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd +#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce +#define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf +#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 +#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 +#define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6 +#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dout_i2c_dispdec +// base address: 0x0 +#define regDC_I2C_CONTROL 0x1e98 +#define regDC_I2C_CONTROL_BASE_IDX 2 +#define regDC_I2C_ARBITRATION 0x1e99 +#define regDC_I2C_ARBITRATION_BASE_IDX 2 +#define regDC_I2C_INTERRUPT_CONTROL 0x1e9a +#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDC_I2C_SW_STATUS 0x1e9b +#define regDC_I2C_SW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC1_HW_STATUS 0x1e9c +#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC2_HW_STATUS 0x1e9d +#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC3_HW_STATUS 0x1e9e +#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC4_HW_STATUS 0x1e9f +#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC5_HW_STATUS 0x1ea0 +#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC1_SPEED 0x1ea2 +#define regDC_I2C_DDC1_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC1_SETUP 0x1ea3 +#define regDC_I2C_DDC1_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC2_SPEED 0x1ea4 +#define regDC_I2C_DDC2_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC2_SETUP 0x1ea5 +#define regDC_I2C_DDC2_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC3_SPEED 0x1ea6 +#define regDC_I2C_DDC3_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC3_SETUP 0x1ea7 +#define regDC_I2C_DDC3_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC4_SPEED 0x1ea8 +#define regDC_I2C_DDC4_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC4_SETUP 0x1ea9 +#define regDC_I2C_DDC4_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC5_SPEED 0x1eaa +#define regDC_I2C_DDC5_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC5_SETUP 0x1eab +#define regDC_I2C_DDC5_SETUP_BASE_IDX 2 +#define regDC_I2C_TRANSACTION0 0x1eae +#define regDC_I2C_TRANSACTION0_BASE_IDX 2 +#define regDC_I2C_TRANSACTION1 0x1eaf +#define regDC_I2C_TRANSACTION1_BASE_IDX 2 +#define regDC_I2C_TRANSACTION2 0x1eb0 +#define regDC_I2C_TRANSACTION2_BASE_IDX 2 +#define regDC_I2C_TRANSACTION3 0x1eb1 +#define regDC_I2C_TRANSACTION3_BASE_IDX 2 +#define regDC_I2C_DATA 0x1eb2 +#define regDC_I2C_DATA_BASE_IDX 2 +#define regDC_I2C_EDID_DETECT_CTRL 0x1eb6 +#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 +#define regDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 +#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dio_misc_dispdec +// base address: 0x0 +#define regDIO_SCRATCH0 0x1eca +#define regDIO_SCRATCH0_BASE_IDX 2 +#define regDIO_SCRATCH1 0x1ecb +#define regDIO_SCRATCH1_BASE_IDX 2 +#define regDIO_SCRATCH2 0x1ecc +#define regDIO_SCRATCH2_BASE_IDX 2 +#define regDIO_SCRATCH3 0x1ecd +#define regDIO_SCRATCH3_BASE_IDX 2 +#define regDIO_SCRATCH4 0x1ece +#define regDIO_SCRATCH4_BASE_IDX 2 +#define regDIO_SCRATCH5 0x1ecf +#define regDIO_SCRATCH5_BASE_IDX 2 +#define regDIO_SCRATCH6 0x1ed0 +#define regDIO_SCRATCH6_BASE_IDX 2 +#define regDIO_SCRATCH7 0x1ed1 +#define regDIO_SCRATCH7_BASE_IDX 2 +#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS 0x1ed3 +#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX 2 +#define regDIO_MEM_PWR_STATUS 0x1edd +#define regDIO_MEM_PWR_STATUS_BASE_IDX 2 +#define regDIO_MEM_PWR_CTRL 0x1ede +#define regDIO_MEM_PWR_CTRL_BASE_IDX 2 +#define regDIO_MEM_PWR_CTRL2 0x1edf +#define regDIO_MEM_PWR_CTRL2_BASE_IDX 2 +#define regDIO_CLK_CNTL 0x1ee0 +#define regDIO_CLK_CNTL_BASE_IDX 2 +#define regDIO_POWER_MANAGEMENT_CNTL 0x1ee4 +#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 +#define regDIG_SOFT_RESET 0x1eee +#define regDIG_SOFT_RESET_BASE_IDX 2 +#define regDIO_CLK_CNTL2 0x1ef2 +#define regDIO_CLK_CNTL2_BASE_IDX 2 +#define regDIO_CLK_CNTL3 0x1ef3 +#define regDIO_CLK_CNTL3_BASE_IDX 2 +#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff +#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 +#define regDIO_LINKA_CNTL 0x1f04 +#define regDIO_LINKA_CNTL_BASE_IDX 2 +#define regDIO_LINKB_CNTL 0x1f05 +#define regDIO_LINKB_CNTL_BASE_IDX 2 +#define regDIO_LINKC_CNTL 0x1f06 +#define regDIO_LINKC_CNTL_BASE_IDX 2 +#define regDIO_LINKD_CNTL 0x1f07 +#define regDIO_LINKD_CNTL_BASE_IDX 2 +#define regDIO_LINKE_CNTL 0x1f08 +#define regDIO_LINKE_CNTL_BASE_IDX 2 +#define regDIO_LINKF_CNTL 0x1f09 +#define regDIO_LINKF_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_dispdec +// base address: 0x0 +#define regDC_GENERICA 0x2868 +#define regDC_GENERICA_BASE_IDX 2 +#define regDC_GENERICB 0x2869 +#define regDC_GENERICB_BASE_IDX 2 +#define regDCIO_CLOCK_CNTL 0x286a +#define regDCIO_CLOCK_CNTL_BASE_IDX 2 +#define regDC_REF_CLK_CNTL 0x286b +#define regDC_REF_CLK_CNTL_BASE_IDX 2 +#define regUNIPHYA_LINK_CNTL 0x286d +#define regUNIPHYA_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e +#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYB_LINK_CNTL 0x286f +#define regUNIPHYB_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 +#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYC_LINK_CNTL 0x2871 +#define regUNIPHYC_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 +#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYD_LINK_CNTL 0x2873 +#define regUNIPHYD_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 +#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYE_LINK_CNTL 0x2875 +#define regUNIPHYE_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 +#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regDCIO_WRCMD_DELAY 0x287e +#define regDCIO_WRCMD_DELAY_BASE_IDX 2 +#define regDC_PINSTRAPS 0x2880 +#define regDC_PINSTRAPS_BASE_IDX 2 +#define regDCIO_SPARE 0x2882 +#define regDCIO_SPARE_BASE_IDX 2 +#define regINTERCEPT_STATE 0x2884 +#define regINTERCEPT_STATE_BASE_IDX 2 +#define regDCIO_PATTERN_GEN_PAT 0x2886 +#define regDCIO_PATTERN_GEN_PAT_BASE_IDX 2 +#define regDCIO_PATTERN_GEN_EN 0x2887 +#define regDCIO_PATTERN_GEN_EN_BASE_IDX 2 +#define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b +#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 +#define regDCIO_GSL_GENLK_PAD_CNTL 0x288c +#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 +#define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d +#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 +#define regDCIO_SOFT_RESET 0x289e +#define regDCIO_SOFT_RESET_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_chip_dispdec +// base address: 0x0 +#define regDC_GPIO_GENERIC_MASK 0x28c8 +#define regDC_GPIO_GENERIC_MASK_BASE_IDX 2 +#define regDC_GPIO_GENERIC_A 0x28c9 +#define regDC_GPIO_GENERIC_A_BASE_IDX 2 +#define regDC_GPIO_GENERIC_EN 0x28ca +#define regDC_GPIO_GENERIC_EN_BASE_IDX 2 +#define regDC_GPIO_GENERIC_Y 0x28cb +#define regDC_GPIO_GENERIC_Y_BASE_IDX 2 +#define regDC_GPIO_DDC1_MASK 0x28d0 +#define regDC_GPIO_DDC1_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC1_A 0x28d1 +#define regDC_GPIO_DDC1_A_BASE_IDX 2 +#define regDC_GPIO_DDC1_EN 0x28d2 +#define regDC_GPIO_DDC1_EN_BASE_IDX 2 +#define regDC_GPIO_DDC1_Y 0x28d3 +#define regDC_GPIO_DDC1_Y_BASE_IDX 2 +#define regDC_GPIO_DDC2_MASK 0x28d4 +#define regDC_GPIO_DDC2_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC2_A 0x28d5 +#define regDC_GPIO_DDC2_A_BASE_IDX 2 +#define regDC_GPIO_DDC2_EN 0x28d6 +#define regDC_GPIO_DDC2_EN_BASE_IDX 2 +#define regDC_GPIO_DDC2_Y 0x28d7 +#define regDC_GPIO_DDC2_Y_BASE_IDX 2 +#define regDC_GPIO_DDC3_MASK 0x28d8 +#define regDC_GPIO_DDC3_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC3_A 0x28d9 +#define regDC_GPIO_DDC3_A_BASE_IDX 2 +#define regDC_GPIO_DDC3_EN 0x28da +#define regDC_GPIO_DDC3_EN_BASE_IDX 2 +#define regDC_GPIO_DDC3_Y 0x28db +#define regDC_GPIO_DDC3_Y_BASE_IDX 2 +#define regDC_GPIO_DDC4_MASK 0x28dc +#define regDC_GPIO_DDC4_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC4_A 0x28dd +#define regDC_GPIO_DDC4_A_BASE_IDX 2 +#define regDC_GPIO_DDC4_EN 0x28de +#define regDC_GPIO_DDC4_EN_BASE_IDX 2 +#define regDC_GPIO_DDC4_Y 0x28df +#define regDC_GPIO_DDC4_Y_BASE_IDX 2 +#define regDC_GPIO_DDC5_MASK 0x28e0 +#define regDC_GPIO_DDC5_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC5_A 0x28e1 +#define regDC_GPIO_DDC5_A_BASE_IDX 2 +#define regDC_GPIO_DDC5_EN 0x28e2 +#define regDC_GPIO_DDC5_EN_BASE_IDX 2 +#define regDC_GPIO_DDC5_Y 0x28e3 +#define regDC_GPIO_DDC5_Y_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_MASK 0x28e8 +#define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_A 0x28e9 +#define regDC_GPIO_DDCVGA_A_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_EN 0x28ea +#define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_Y 0x28eb +#define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 +#define regDC_GPIO_GENLK_MASK 0x28f0 +#define regDC_GPIO_GENLK_MASK_BASE_IDX 2 +#define regDC_GPIO_GENLK_A 0x28f1 +#define regDC_GPIO_GENLK_A_BASE_IDX 2 +#define regDC_GPIO_GENLK_EN 0x28f2 +#define regDC_GPIO_GENLK_EN_BASE_IDX 2 +#define regDC_GPIO_GENLK_Y 0x28f3 +#define regDC_GPIO_GENLK_Y_BASE_IDX 2 +#define regDC_GPIO_HPD_MASK 0x28f4 +#define regDC_GPIO_HPD_MASK_BASE_IDX 2 +#define regDC_GPIO_HPD_A 0x28f5 +#define regDC_GPIO_HPD_A_BASE_IDX 2 +#define regDC_GPIO_HPD_EN 0x28f6 +#define regDC_GPIO_HPD_EN_BASE_IDX 2 +#define regDC_GPIO_HPD_Y 0x28f7 +#define regDC_GPIO_HPD_Y_BASE_IDX 2 +#define regDC_GPIO_DRIVE_STRENGTH_S0 0x28f8 +#define regDC_GPIO_DRIVE_STRENGTH_S0_BASE_IDX 2 +#define regDC_GPIO_DRIVE_STRENGTH_S1 0x28f9 +#define regDC_GPIO_DRIVE_STRENGTH_S1_BASE_IDX 2 +#define regDC_GPIO_PWRSEQ0_EN 0x28fa +#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 +#define regDC_GPIO_PAD_STRENGTH_1 0x28fc +#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 +#define regDC_GPIO_PAD_STRENGTH_2 0x28fd +#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 +#define regPHY_AUX_CNTL 0x28ff +#define regPHY_AUX_CNTL_BASE_IDX 2 +#define regDC_GPIO_DRIVE_TXIMPSEL 0x2900 +#define regDC_GPIO_DRIVE_TXIMPSEL_BASE_IDX 2 +#define regDC_GPIO_TX12_EN 0x2915 +#define regDC_GPIO_TX12_EN_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_0 0x2916 +#define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_1 0x2917 +#define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_2 0x2918 +#define regDC_GPIO_AUX_CTRL_2_BASE_IDX 2 +#define regDC_GPIO_RXEN 0x2919 +#define regDC_GPIO_RXEN_BASE_IDX 2 +#define regDC_GPIO_PULLUPEN 0x291a +#define regDC_GPIO_PULLUPEN_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_3 0x291b +#define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_4 0x291c +#define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_5 0x291d +#define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 +#define regAUXI2C_PAD_ALL_PWR_OK 0x291e +#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec +// base address: 0x0 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x2928 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x2929 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x292a +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x292b +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x292c +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x292d +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x292e +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x292f +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2930 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2931 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2932 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2933 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x2934 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x2935 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x2936 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x2937 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x2938 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x2939 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x293a +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x293b +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x293c +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x293d +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x293e +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x293f +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2940 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2941 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2942 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2943 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x2944 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x2945 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x2946 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x2947 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x2948 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x2949 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x294a +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x294b +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x294c +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x294d +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x294e +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x294f +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2950 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2951 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2952 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2953 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x2954 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x2955 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x2956 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x2957 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x2958 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x2959 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x295a +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x295b +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x295c +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x295d +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x295e +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x295f +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2960 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2961 +#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec +// base address: 0x360 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec +// base address: 0x6c0 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec +// base address: 0xa20 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec +// base address: 0xd80 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x2cb8 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x2cb9 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2cba +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2cbb +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2cbc +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2cbd +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2cbe +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2cbf +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2cc0 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2cc1 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 + + +// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec +// base address: 0x0 +#define regDC_GPIO_PWRSEQ_EN 0x2f10 +#define regDC_GPIO_PWRSEQ_EN_BASE_IDX 2 +#define regDC_GPIO_PWRSEQ_CTRL 0x2f11 +#define regDC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 +#define regDC_GPIO_PWRSEQ_MASK 0x2f12 +#define regDC_GPIO_PWRSEQ_MASK_BASE_IDX 2 +#define regDC_GPIO_PWRSEQ_A_Y 0x2f13 +#define regDC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 +#define regPANEL_PWRSEQ_CNTL 0x2f14 +#define regPANEL_PWRSEQ_CNTL_BASE_IDX 2 +#define regPANEL_PWRSEQ_STATE 0x2f15 +#define regPANEL_PWRSEQ_STATE_BASE_IDX 2 +#define regPANEL_PWRSEQ_DELAY1 0x2f16 +#define regPANEL_PWRSEQ_DELAY1_BASE_IDX 2 +#define regPANEL_PWRSEQ_DELAY2 0x2f17 +#define regPANEL_PWRSEQ_DELAY2_BASE_IDX 2 +#define regPANEL_PWRSEQ_REF_DIV1 0x2f18 +#define regPANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 +#define regBL_PWM_CNTL 0x2f19 +#define regBL_PWM_CNTL_BASE_IDX 2 +#define regBL_PWM_CNTL2 0x2f1a +#define regBL_PWM_CNTL2_BASE_IDX 2 +#define regBL_PWM_PERIOD_CNTL 0x2f1b +#define regBL_PWM_PERIOD_CNTL_BASE_IDX 2 +#define regBL_PWM_GRP1_REG_LOCK 0x2f1c +#define regBL_PWM_GRP1_REG_LOCK_BASE_IDX 2 +#define regPANEL_PWRSEQ_REF_DIV2 0x2f1d +#define regPANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 +#define regPWRSEQ_SPARE 0x2f21 +#define regPWRSEQ_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec +// base address: 0x0 +#define regDSCC0_DSCC_CONFIG0 0x300a +#define regDSCC0_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC0_DSCC_CONFIG1 0x300b +#define regDSCC0_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC0_DSCC_STATUS 0x300c +#define regDSCC0_DSCC_STATUS_BASE_IDX 2 +#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d +#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG0 0x300e +#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG1 0x300f +#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG2 0x3010 +#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG3 0x3011 +#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG4 0x3012 +#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG5 0x3013 +#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG6 0x3014 +#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG7 0x3015 +#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG8 0x3016 +#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG9 0x3017 +#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG10 0x3018 +#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG11 0x3019 +#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG12 0x301a +#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG13 0x301b +#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG14 0x301c +#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG15 0x301d +#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG16 0x301e +#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG17 0x301f +#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG18 0x3020 +#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG19 0x3021 +#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG20 0x3022 +#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG21 0x3023 +#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG22 0x3024 +#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 +#define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC0_DSCC_MAX_ABS_ERROR0 0x302c +#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC0_DSCC_MAX_ABS_ERROR1 0x302d +#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e +#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f +#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 +#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 +#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec +// base address: 0x0 +#define regDSCCIF0_DSCCIF_CONFIG0 0x3005 +#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 +#define regDSCCIF0_DSCCIF_CONFIG1 0x3006 +#define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec +// base address: 0x0 +#define regDSC_TOP0_DSC_TOP_CONTROL 0x3000 +#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 +#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec +// base address: 0x170 +#define regDSCC1_DSCC_CONFIG0 0x3066 +#define regDSCC1_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC1_DSCC_CONFIG1 0x3067 +#define regDSCC1_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC1_DSCC_STATUS 0x3068 +#define regDSCC1_DSCC_STATUS_BASE_IDX 2 +#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 +#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG0 0x306a +#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG1 0x306b +#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG2 0x306c +#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG3 0x306d +#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG4 0x306e +#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG5 0x306f +#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG6 0x3070 +#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG7 0x3071 +#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG8 0x3072 +#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG9 0x3073 +#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG10 0x3074 +#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG11 0x3075 +#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG12 0x3076 +#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG13 0x3077 +#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG14 0x3078 +#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG15 0x3079 +#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG16 0x307a +#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG17 0x307b +#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG18 0x307c +#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG19 0x307d +#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG20 0x307e +#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG21 0x307f +#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG22 0x3080 +#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 +#define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 +#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 +#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a +#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b +#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c +#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d +#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec +// base address: 0x170 +#define regDSCCIF1_DSCCIF_CONFIG0 0x3061 +#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 +#define regDSCCIF1_DSCCIF_CONFIG1 0x3062 +#define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec +// base address: 0x170 +#define regDSC_TOP1_DSC_TOP_CONTROL 0x305c +#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP1_DSC_DEBUG_CONTROL 0x305d +#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec +// base address: 0x2e0 +#define regDSCC2_DSCC_CONFIG0 0x30c2 +#define regDSCC2_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC2_DSCC_CONFIG1 0x30c3 +#define regDSCC2_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC2_DSCC_STATUS 0x30c4 +#define regDSCC2_DSCC_STATUS_BASE_IDX 2 +#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5 +#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG0 0x30c6 +#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG1 0x30c7 +#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG2 0x30c8 +#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG3 0x30c9 +#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG4 0x30ca +#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG5 0x30cb +#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG6 0x30cc +#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG7 0x30cd +#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG8 0x30ce +#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG9 0x30cf +#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG10 0x30d0 +#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG11 0x30d1 +#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG12 0x30d2 +#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG13 0x30d3 +#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG14 0x30d4 +#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG15 0x30d5 +#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG16 0x30d6 +#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG17 0x30d7 +#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG18 0x30d8 +#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG19 0x30d9 +#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG20 0x30da +#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG21 0x30db +#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG22 0x30dc +#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd +#define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4 +#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5 +#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6 +#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7 +#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8 +#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9 +#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec +// base address: 0x2e0 +#define regDSCCIF2_DSCCIF_CONFIG0 0x30bd +#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 +#define regDSCCIF2_DSCCIF_CONFIG1 0x30be +#define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec +// base address: 0x2e0 +#define regDSC_TOP2_DSC_TOP_CONTROL 0x30b8 +#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 +#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec +// base address: 0x450 +#define regDSCC3_DSCC_CONFIG0 0x311e +#define regDSCC3_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC3_DSCC_CONFIG1 0x311f +#define regDSCC3_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC3_DSCC_STATUS 0x3120 +#define regDSCC3_DSCC_STATUS_BASE_IDX 2 +#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS 0x3121 +#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG0 0x3122 +#define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG1 0x3123 +#define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG2 0x3124 +#define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG3 0x3125 +#define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG4 0x3126 +#define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG5 0x3127 +#define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG6 0x3128 +#define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG7 0x3129 +#define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG8 0x312a +#define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG9 0x312b +#define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG10 0x312c +#define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG11 0x312d +#define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG12 0x312e +#define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG13 0x312f +#define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG14 0x3130 +#define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG15 0x3131 +#define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG16 0x3132 +#define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG17 0x3133 +#define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG18 0x3134 +#define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG19 0x3135 +#define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG20 0x3136 +#define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG21 0x3137 +#define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG22 0x3138 +#define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC3_DSCC_MEM_POWER_CONTROL 0x3139 +#define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313a +#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x313b +#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x313c +#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x313d +#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x313e +#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x313f +#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC3_DSCC_MAX_ABS_ERROR0 0x3140 +#define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC3_DSCC_MAX_ABS_ERROR1 0x3141 +#define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x3142 +#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x3143 +#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3144 +#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3145 +#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3146 +#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3147 +#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3148 +#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149 +#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec +// base address: 0x450 +#define regDSCCIF3_DSCCIF_CONFIG0 0x3119 +#define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2 +#define regDSCCIF3_DSCCIF_CONFIG1 0x311a +#define regDSCCIF3_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec +// base address: 0x450 +#define regDSC_TOP3_DSC_TOP_CONTROL 0x3114 +#define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP3_DSC_DEBUG_CONTROL 0x3115 +#define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_hpo_top_dispdec +// base address: 0x2790c +#define regHPO_TOP_CLOCK_CONTROL 0x0e43 +#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 +#define regHPO_TOP_HW_CONTROL 0x0e4a +#define regHPO_TOP_HW_CONTROL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec +// base address: 0x27958 +#define regDP_STREAM_MAPPER_CONTROL0 0x0e56 +#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX 3 +#define regDP_STREAM_MAPPER_CONTROL1 0x0e57 +#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX 3 +#define regDP_STREAM_MAPPER_CONTROL2 0x0e58 +#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX 3 +#define regDP_STREAM_MAPPER_CONTROL3 0x0e59 +#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec +// base address: 0x2646c +#define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c +#define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x091d +#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_INFO0 0x091e +#define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_INFO1 0x091f +#define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX 3 +#define regAFMT5_AFMT_60958_0 0x0920 +#define regAFMT5_AFMT_60958_0_BASE_IDX 3 +#define regAFMT5_AFMT_60958_1 0x0921 +#define regAFMT5_AFMT_60958_1_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_CRC_CONTROL 0x0922 +#define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 3 +#define regAFMT5_AFMT_RAMP_CONTROL0 0x0923 +#define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX 3 +#define regAFMT5_AFMT_RAMP_CONTROL1 0x0924 +#define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX 3 +#define regAFMT5_AFMT_RAMP_CONTROL2 0x0925 +#define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX 3 +#define regAFMT5_AFMT_RAMP_CONTROL3 0x0926 +#define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX 3 +#define regAFMT5_AFMT_60958_2 0x0927 +#define regAFMT5_AFMT_60958_2_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_CRC_RESULT 0x0928 +#define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 3 +#define regAFMT5_AFMT_STATUS 0x0929 +#define regAFMT5_AFMT_STATUS_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL 0x092a +#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3 +#define regAFMT5_AFMT_INFOFRAME_CONTROL0 0x092b +#define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3 +#define regAFMT5_AFMT_INTERRUPT_STATUS 0x092c +#define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_SRC_CONTROL 0x092d +#define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3 +#define regAFMT5_AFMT_MEM_PWR 0x092f +#define regAFMT5_AFMT_MEM_PWR_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec +// base address: 0x264f0 +#define regDME5_DME_CONTROL 0x093c +#define regDME5_DME_CONTROL_BASE_IDX 3 +#define regDME5_DME_MEMORY_CONTROL 0x093d +#define regDME5_DME_MEMORY_CONTROL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec +// base address: 0x264c4 +#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 +#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 +#define regVPG5_VPG_GENERIC_PACKET_DATA 0x0932 +#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 +#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 +#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 +#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 +#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 +#define regVPG5_VPG_GENERIC_STATUS 0x0935 +#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX 3 +#define regVPG5_VPG_MEM_PWR 0x0936 +#define regVPG5_VPG_MEM_PWR_BASE_IDX 3 +#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x0937 +#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3 +#define regVPG5_VPG_ISRC1_2_DATA 0x0938 +#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX 3 +#define regVPG5_VPG_MPEG_INFO0 0x0939 +#define regVPG5_VPG_MPEG_INFO0_BASE_IDX 3 +#define regVPG5_VPG_MPEG_INFO1 0x093a +#define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec +// base address: 0x1ab8c +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x3624 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL 0x3625 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x3626 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x3627 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE 0x3628 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec +// base address: 0x1abc0 +#define regAPG0_APG_CONTROL 0x3630 +#define regAPG0_APG_CONTROL_BASE_IDX 2 +#define regAPG0_APG_CONTROL2 0x3631 +#define regAPG0_APG_CONTROL2_BASE_IDX 2 +#define regAPG0_APG_DBG_GEN_CONTROL 0x3632 +#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG0_APG_PACKET_CONTROL 0x3633 +#define regAPG0_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG0_APG_AUDIO_CRC_CONTROL 0x363a +#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG0_APG_AUDIO_CRC_CONTROL2 0x363b +#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG0_APG_AUDIO_CRC_RESULT 0x363c +#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG0_APG_STATUS 0x3641 +#define regAPG0_APG_STATUS_BASE_IDX 2 +#define regAPG0_APG_STATUS2 0x3642 +#define regAPG0_APG_STATUS2_BASE_IDX 2 +#define regAPG0_APG_MEM_PWR 0x3644 +#define regAPG0_APG_MEM_PWR_BASE_IDX 2 +#define regAPG0_APG_SPARE 0x3646 +#define regAPG0_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec +// base address: 0x1ac38 +#define regDME6_DME_CONTROL 0x364e +#define regDME6_DME_CONTROL_BASE_IDX 2 +#define regDME6_DME_MEMORY_CONTROL 0x364f +#define regDME6_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec +// base address: 0x1ac44 +#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3651 +#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG6_VPG_GENERIC_PACKET_DATA 0x3652 +#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x3653 +#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3654 +#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG6_VPG_GENERIC_STATUS 0x3655 +#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG6_VPG_MEM_PWR 0x3656 +#define regVPG6_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x3657 +#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG6_VPG_ISRC1_2_DATA 0x3658 +#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG6_VPG_MPEG_INFO0 0x3659 +#define regVPG6_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG6_VPG_MPEG_INFO1 0x365a +#define regVPG6_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec +// base address: 0x1ac74 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL 0x365d +#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL 0x365e +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x365f +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3660 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3661 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 0x3662 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 0x3663 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 0x3664 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 0x3665 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 0x3666 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 0x3667 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 0x3668 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 0x3669 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 0x366a +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b +#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x366c +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x366d +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x366e +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x366f +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3670 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3671 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3672 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3673 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3674 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3675 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x3676 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x3677 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3678 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3679 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x367a +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL 0x367b +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x367c +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x367d +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x367e +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL 0x3683 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL 0x3684 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3685 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3686 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 0x3688 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 0x3689 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS 0x368a +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL 0x368b +#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE 0x368c +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec +// base address: 0x1aedc +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL 0x36f7 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x36f8 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL 0x36f9 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x36fa +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x36fb +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE 0x36fc +#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec +// base address: 0x1af10 +#define regAPG1_APG_CONTROL 0x3704 +#define regAPG1_APG_CONTROL_BASE_IDX 2 +#define regAPG1_APG_CONTROL2 0x3705 +#define regAPG1_APG_CONTROL2_BASE_IDX 2 +#define regAPG1_APG_DBG_GEN_CONTROL 0x3706 +#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG1_APG_PACKET_CONTROL 0x3707 +#define regAPG1_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG1_APG_AUDIO_CRC_CONTROL 0x370e +#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG1_APG_AUDIO_CRC_CONTROL2 0x370f +#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG1_APG_AUDIO_CRC_RESULT 0x3710 +#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG1_APG_STATUS 0x3715 +#define regAPG1_APG_STATUS_BASE_IDX 2 +#define regAPG1_APG_STATUS2 0x3716 +#define regAPG1_APG_STATUS2_BASE_IDX 2 +#define regAPG1_APG_MEM_PWR 0x3718 +#define regAPG1_APG_MEM_PWR_BASE_IDX 2 +#define regAPG1_APG_SPARE 0x371a +#define regAPG1_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec +// base address: 0x1af88 +#define regDME7_DME_CONTROL 0x3722 +#define regDME7_DME_CONTROL_BASE_IDX 2 +#define regDME7_DME_MEMORY_CONTROL 0x3723 +#define regDME7_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec +// base address: 0x1af94 +#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3725 +#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG7_VPG_GENERIC_PACKET_DATA 0x3726 +#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL 0x3727 +#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3728 +#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG7_VPG_GENERIC_STATUS 0x3729 +#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG7_VPG_MEM_PWR 0x372a +#define regVPG7_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL 0x372b +#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG7_VPG_ISRC1_2_DATA 0x372c +#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG7_VPG_MPEG_INFO0 0x372d +#define regVPG7_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG7_VPG_MPEG_INFO1 0x372e +#define regVPG7_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec +// base address: 0x1afc4 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL 0x3731 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3732 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3733 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3734 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3735 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 0x3736 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 0x3737 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 0x3738 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 0x3739 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 0x373a +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 0x373b +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 0x373c +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 0x373d +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 0x373e +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f +#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3740 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3741 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3742 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3743 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3744 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3745 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3746 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3747 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3748 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3749 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x374a +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x374b +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x374c +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x374d +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x374e +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL 0x374f +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3750 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3751 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3752 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL 0x3757 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL 0x3758 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3759 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x375a +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 0x375c +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 0x375d +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS 0x375e +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL 0x375f +#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE 0x3760 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec +// base address: 0x1b22c +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL 0x37cb +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x37cc +#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL 0x37cd +#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x37ce +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x37cf +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE 0x37d0 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec +// base address: 0x1b260 +#define regAPG2_APG_CONTROL 0x37d8 +#define regAPG2_APG_CONTROL_BASE_IDX 2 +#define regAPG2_APG_CONTROL2 0x37d9 +#define regAPG2_APG_CONTROL2_BASE_IDX 2 +#define regAPG2_APG_DBG_GEN_CONTROL 0x37da +#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG2_APG_PACKET_CONTROL 0x37db +#define regAPG2_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG2_APG_AUDIO_CRC_CONTROL 0x37e2 +#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG2_APG_AUDIO_CRC_CONTROL2 0x37e3 +#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG2_APG_AUDIO_CRC_RESULT 0x37e4 +#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG2_APG_STATUS 0x37e9 +#define regAPG2_APG_STATUS_BASE_IDX 2 +#define regAPG2_APG_STATUS2 0x37ea +#define regAPG2_APG_STATUS2_BASE_IDX 2 +#define regAPG2_APG_MEM_PWR 0x37ec +#define regAPG2_APG_MEM_PWR_BASE_IDX 2 +#define regAPG2_APG_SPARE 0x37ee +#define regAPG2_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec +// base address: 0x1b2d8 +#define regDME8_DME_CONTROL 0x37f6 +#define regDME8_DME_CONTROL_BASE_IDX 2 +#define regDME8_DME_MEMORY_CONTROL 0x37f7 +#define regDME8_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec +// base address: 0x1b2e4 +#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL 0x37f9 +#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG8_VPG_GENERIC_PACKET_DATA 0x37fa +#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL 0x37fb +#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x37fc +#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG8_VPG_GENERIC_STATUS 0x37fd +#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG8_VPG_MEM_PWR 0x37fe +#define regVPG8_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL 0x37ff +#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG8_VPG_ISRC1_2_DATA 0x3800 +#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG8_VPG_MPEG_INFO0 0x3801 +#define regVPG8_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG8_VPG_MPEG_INFO1 0x3802 +#define regVPG8_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec +// base address: 0x1b314 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL 0x3805 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3806 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3807 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3808 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3809 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 0x380a +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 0x380b +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 0x380c +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 0x380d +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 0x380e +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 0x380f +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 0x3810 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 0x3811 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 0x3812 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3814 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3815 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3816 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3817 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3818 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3819 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x381a +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x381b +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x381c +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x381d +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x381e +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x381f +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3820 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3821 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x3822 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL 0x3823 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3824 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3825 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3826 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL 0x382b +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL 0x382c +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL 0x382d +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x382e +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 0x3830 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 0x3831 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS 0x3832 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3833 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE 0x3834 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec +// base address: 0x1b57c +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL 0x389f +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x38a0 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL 0x38a1 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x38a2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x38a3 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE 0x38a4 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec +// base address: 0x1b5b0 +#define regAPG3_APG_CONTROL 0x38ac +#define regAPG3_APG_CONTROL_BASE_IDX 2 +#define regAPG3_APG_CONTROL2 0x38ad +#define regAPG3_APG_CONTROL2_BASE_IDX 2 +#define regAPG3_APG_DBG_GEN_CONTROL 0x38ae +#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG3_APG_PACKET_CONTROL 0x38af +#define regAPG3_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG3_APG_AUDIO_CRC_CONTROL 0x38b6 +#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG3_APG_AUDIO_CRC_CONTROL2 0x38b7 +#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG3_APG_AUDIO_CRC_RESULT 0x38b8 +#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG3_APG_STATUS 0x38bd +#define regAPG3_APG_STATUS_BASE_IDX 2 +#define regAPG3_APG_STATUS2 0x38be +#define regAPG3_APG_STATUS2_BASE_IDX 2 +#define regAPG3_APG_MEM_PWR 0x38c0 +#define regAPG3_APG_MEM_PWR_BASE_IDX 2 +#define regAPG3_APG_SPARE 0x38c2 +#define regAPG3_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec +// base address: 0x1b628 +#define regDME9_DME_CONTROL 0x38ca +#define regDME9_DME_CONTROL_BASE_IDX 2 +#define regDME9_DME_MEMORY_CONTROL 0x38cb +#define regDME9_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec +// base address: 0x1b634 +#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL 0x38cd +#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG9_VPG_GENERIC_PACKET_DATA 0x38ce +#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL 0x38cf +#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x38d0 +#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG9_VPG_GENERIC_STATUS 0x38d1 +#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG9_VPG_MEM_PWR 0x38d2 +#define regVPG9_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL 0x38d3 +#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG9_VPG_ISRC1_2_DATA 0x38d4 +#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG9_VPG_MPEG_INFO0 0x38d5 +#define regVPG9_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG9_VPG_MPEG_INFO1 0x38d6 +#define regVPG9_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec +// base address: 0x1b664 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL 0x38d9 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL 0x38da +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x38db +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x38dc +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x38dd +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 0x38de +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 0x38df +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 0x38e0 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 0x38e1 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 0x38e2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 0x38e3 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 0x38e4 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 0x38e5 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 0x38e6 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL 0x38e7 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x38e8 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x38e9 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x38ea +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x38eb +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x38ec +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x38ed +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x38ee +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x38ef +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x38f0 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x38f1 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x38f2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x38f3 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x38f4 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x38f5 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x38f6 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL 0x38f7 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x38f8 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x38f9 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x38fa +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL 0x38ff +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL 0x3900 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3901 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3902 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL 0x3903 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 0x3904 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 0x3905 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS 0x3906 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3907 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE 0x3908 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec +// base address: 0x1ad5c +#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL 0x3697 +#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE 0x3698 +#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec +// base address: 0x1ae00 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL 0x36c0 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS 0x36c1 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE 0x36c4 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 0x36c5 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 0x36c6 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 0x36c7 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 0x36c8 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 0x36cb +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 0x36cc +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 0x36cd +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 0x36ce +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 0x36d1 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 0x36d2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 0x36d3 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 0x36d4 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG 0x36d7 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 0x36d8 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 0x36d9 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 0x36da +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 0x36db +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE 0x36dc +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 0x36dd +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 0x36de +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 0x36df +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 0x36e0 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 0x36e1 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 0x36e2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 0x36e3 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 0x36e4 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 0x36e5 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 0x36e6 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 0x36e7 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS 0x36e8 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x36ea +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0 0x36eb +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1 0x36ec +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS 0x36ed +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT 0x36ee +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec +// base address: 0x1b0ac +#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL 0x376b +#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE 0x376c +#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec +// base address: 0x1b150 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL 0x3794 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS 0x3795 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE 0x3798 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3799 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 0x379a +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 0x379b +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 0x379c +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 0x379f +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 0x37a0 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 0x37a1 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 0x37a2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 0x37a5 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 0x37a6 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 0x37a7 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 0x37a8 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG 0x37ab +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 0x37ac +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 0x37ad +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 0x37ae +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 0x37af +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE 0x37b0 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 0x37b1 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 0x37b2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 0x37b3 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 0x37b4 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 0x37b5 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 0x37b6 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 0x37b7 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 0x37b8 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 0x37b9 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 0x37ba +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 0x37bb +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS 0x37bc +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x37be +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0 0x37bf +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1 0x37c0 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS 0x37c1 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT 0x37c2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azcontroller_azdec +// base address: 0x0 +#define regCORB_WRITE_POINTER 0x0000 +#define regCORB_WRITE_POINTER_BASE_IDX 0 +#define regCORB_READ_POINTER 0x0000 +#define regCORB_READ_POINTER_BASE_IDX 0 +#define regCORB_CONTROL 0x0001 +#define regCORB_CONTROL_BASE_IDX 0 +#define regCORB_STATUS 0x0001 +#define regCORB_STATUS_BASE_IDX 0 +#define regCORB_SIZE 0x0001 +#define regCORB_SIZE_BASE_IDX 0 +#define regRIRB_LOWER_BASE_ADDRESS 0x0002 +#define regRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regRIRB_UPPER_BASE_ADDRESS 0x0003 +#define regRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regRIRB_WRITE_POINTER 0x0004 +#define regRIRB_WRITE_POINTER_BASE_IDX 0 +#define regRESPONSE_INTERRUPT_COUNT 0x0004 +#define regRESPONSE_INTERRUPT_COUNT_BASE_IDX 0 +#define regRIRB_CONTROL 0x0005 +#define regRIRB_CONTROL_BASE_IDX 0 +#define regRIRB_STATUS 0x0005 +#define regRIRB_STATUS_BASE_IDX 0 +#define regRIRB_SIZE 0x0005 +#define regRIRB_SIZE_BASE_IDX 0 +#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 +#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 +#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 +#define regIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 +#define regIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 +#define regIMMEDIATE_COMMAND_STATUS 0x0008 +#define regIMMEDIATE_COMMAND_STATUS_BASE_IDX 0 +#define regDMA_POSITION_LOWER_BASE_ADDRESS 0x000a +#define regDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regDMA_POSITION_UPPER_BASE_ADDRESS 0x000b +#define regDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regWALL_CLOCK_COUNTER_ALIAS 0x074c +#define regWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azendpoint_azdec +// base address: 0x0 +#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +// base address: 0x0 +#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 +#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 +#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 +#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 + + +// addressBlock: dce_dc_hda_azroot_azdec +// base address: 0x0 +#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 + + +// addressBlock: dce_dc_hda_azstream0_azdec +// base address: 0x0 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761 +#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream1_azdec +// base address: 0x20 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769 +#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream2_azdec +// base address: 0x40 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771 +#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream3_azdec +// base address: 0x60 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779 +#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream4_azdec +// base address: 0x80 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781 +#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream5_azdec +// base address: 0xa0 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789 +#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream6_azdec +// base address: 0xc0 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791 +#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream7_azdec +// base address: 0xe0 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799 +#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: vga_vgaseqind +// base address: 0x0 +#define ixSEQ00 0x0000 +#define ixSEQ01 0x0001 +#define ixSEQ02 0x0002 +#define ixSEQ03 0x0003 +#define ixSEQ04 0x0004 + + +// addressBlock: vga_vgacrtind +// base address: 0x0 +#define ixCRT00 0x0000 +#define ixCRT01 0x0001 +#define ixCRT02 0x0002 +#define ixCRT03 0x0003 +#define ixCRT04 0x0004 +#define ixCRT05 0x0005 +#define ixCRT06 0x0006 +#define ixCRT07 0x0007 +#define ixCRT08 0x0008 +#define ixCRT09 0x0009 +#define ixCRT0A 0x000a +#define ixCRT0B 0x000b +#define ixCRT0C 0x000c +#define ixCRT0D 0x000d +#define ixCRT0E 0x000e +#define ixCRT0F 0x000f +#define ixCRT10 0x0010 +#define ixCRT11 0x0011 +#define ixCRT12 0x0012 +#define ixCRT13 0x0013 +#define ixCRT14 0x0014 +#define ixCRT15 0x0015 +#define ixCRT16 0x0016 +#define ixCRT17 0x0017 +#define ixCRT18 0x0018 +#define ixCRT1E 0x001e +#define ixCRT1F 0x001f +#define ixCRT22 0x0022 + + +// addressBlock: vga_vgagrphind +// base address: 0x0 +#define ixGRA00 0x0000 +#define ixGRA01 0x0001 +#define ixGRA02 0x0002 +#define ixGRA03 0x0003 +#define ixGRA04 0x0004 +#define ixGRA05 0x0005 +#define ixGRA06 0x0006 +#define ixGRA07 0x0007 +#define ixGRA08 0x0008 + + +// addressBlock: vga_vgaattrind +// base address: 0x0 +#define ixATTR00 0x0000 +#define ixATTR01 0x0001 +#define ixATTR02 0x0002 +#define ixATTR03 0x0003 +#define ixATTR04 0x0004 +#define ixATTR05 0x0005 +#define ixATTR06 0x0006 +#define ixATTR07 0x0007 +#define ixATTR08 0x0008 +#define ixATTR09 0x0009 +#define ixATTR0A 0x000a +#define ixATTR0B 0x000b +#define ixATTR0C 0x000c +#define ixATTR0D 0x000d +#define ixATTR0E 0x000e +#define ixATTR0F 0x000f +#define ixATTR10 0x0010 +#define ixATTR11 0x0011 +#define ixATTR12 0x0012 +#define ixATTR13 0x0013 +#define ixATTR14 0x0014 + + +// addressBlock: azendpoint_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e +#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e + + +// addressBlock: azendpoint_descriptorind +// base address: 0x0 +#define ixAUDIO_DESCRIPTOR0 0x0001 +#define ixAUDIO_DESCRIPTOR1 0x0002 +#define ixAUDIO_DESCRIPTOR2 0x0003 +#define ixAUDIO_DESCRIPTOR3 0x0004 +#define ixAUDIO_DESCRIPTOR4 0x0005 +#define ixAUDIO_DESCRIPTOR5 0x0006 +#define ixAUDIO_DESCRIPTOR6 0x0007 +#define ixAUDIO_DESCRIPTOR7 0x0008 +#define ixAUDIO_DESCRIPTOR8 0x0009 +#define ixAUDIO_DESCRIPTOR9 0x000a +#define ixAUDIO_DESCRIPTOR10 0x000b +#define ixAUDIO_DESCRIPTOR11 0x000c +#define ixAUDIO_DESCRIPTOR12 0x000d +#define ixAUDIO_DESCRIPTOR13 0x000e + + +// addressBlock: azendpoint_sinkinfoind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 +#define ixSINK_DESCRIPTION0 0x0005 +#define ixSINK_DESCRIPTION1 0x0006 +#define ixSINK_DESCRIPTION2 0x0007 +#define ixSINK_DESCRIPTION3 0x0008 +#define ixSINK_DESCRIPTION4 0x0009 +#define ixSINK_DESCRIPTION5 0x000a +#define ixSINK_DESCRIPTION6 0x000b +#define ixSINK_DESCRIPTION7 0x000c +#define ixSINK_DESCRIPTION8 0x000d +#define ixSINK_DESCRIPTION9 0x000e +#define ixSINK_DESCRIPTION10 0x000f +#define ixSINK_DESCRIPTION11 0x0010 +#define ixSINK_DESCRIPTION12 0x0011 +#define ixSINK_DESCRIPTION13 0x0012 +#define ixSINK_DESCRIPTION14 0x0013 +#define ixSINK_DESCRIPTION15 0x0014 +#define ixSINK_DESCRIPTION16 0x0015 +#define ixSINK_DESCRIPTION17 0x0016 + + +// addressBlock: azf0controller_azinputcrc0resultind +// base address: 0x0 +#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 +#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 +#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 +#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 +#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 +#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 +#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 +#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azinputcrc1resultind +// base address: 0x0 +#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 +#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 +#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 +#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 +#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 +#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 +#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 +#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azcrc0resultind +// base address: 0x0 +#define ixAZALIA_CRC0_CHANNEL0 0x0000 +#define ixAZALIA_CRC0_CHANNEL1 0x0001 +#define ixAZALIA_CRC0_CHANNEL2 0x0002 +#define ixAZALIA_CRC0_CHANNEL3 0x0003 +#define ixAZALIA_CRC0_CHANNEL4 0x0004 +#define ixAZALIA_CRC0_CHANNEL5 0x0005 +#define ixAZALIA_CRC0_CHANNEL6 0x0006 +#define ixAZALIA_CRC0_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azcrc1resultind +// base address: 0x0 +#define ixAZALIA_CRC1_CHANNEL0 0x0000 +#define ixAZALIA_CRC1_CHANNEL1 0x0001 +#define ixAZALIA_CRC1_CHANNEL2 0x0002 +#define ixAZALIA_CRC1_CHANNEL3 0x0003 +#define ixAZALIA_CRC1_CHANNEL4 0x0004 +#define ixAZALIA_CRC1_CHANNEL5 0x0005 +#define ixAZALIA_CRC1_CHANNEL6 0x0006 +#define ixAZALIA_CRC1_CHANNEL7 0x0007 + + +// addressBlock: azinputendpoint_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c + + +// addressBlock: azroot_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f + + +// addressBlock: azf0stream0_streamind +// base address: 0x0 +#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream1_streamind +// base address: 0x0 +#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream2_streamind +// base address: 0x0 +#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream3_streamind +// base address: 0x0 +#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream4_streamind +// base address: 0x0 +#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream5_streamind +// base address: 0x0 +#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream6_streamind +// base address: 0x0 +#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream7_streamind +// base address: 0x0 +#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream8_streamind +// base address: 0x0 +#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream9_streamind +// base address: 0x0 +#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream10_streamind +// base address: 0x0 +#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream11_streamind +// base address: 0x0 +#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream12_streamind +// base address: 0x0 +#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream13_streamind +// base address: 0x0 +#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream14_streamind +// base address: 0x0 +#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream15_streamind +// base address: 0x0 +#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0endpoint0_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint1_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint2_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint3_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint4_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint5_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint6_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint7_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0inputendpoint0_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint1_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint2_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint3_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint4_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint5_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint6_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint7_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h new file mode 100644 index 000000000000..23faa628cd59 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h @@ -0,0 +1,56578 @@ +/* + * Copyright (C) 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _dcn_3_2_1_SH_MASK_HEADER +#define _dcn_3_2_1_SH_MASK_HEADER + + +// addressBlock: dce_dc_dccg_dccg_dfs_dispdec +//DENTIST_DISPCLK_CNTL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT 0x15 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT 0x16 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK 0x00200000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK 0x00400000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L + + +// addressBlock: dce_dc_dccg_dccg_dispdec +//PHYPLLA_PIXCLK_RESYNC_CNTL +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x00000100L +//PHYPLLB_PIXCLK_RESYNC_CNTL +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK 0x00000100L +//PHYPLLC_PIXCLK_RESYNC_CNTL +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK 0x00000100L +//PHYPLLD_PIXCLK_RESYNC_CNTL +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK 0x00000100L +//DP_DTO_DBUF_EN +#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT 0x0 +#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT 0x1 +#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT 0x2 +#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT 0x3 +#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT 0x4 +#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT 0x5 +#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT 0x6 +#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT 0x7 +#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK 0x00000001L +#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK 0x00000002L +#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK 0x00000004L +#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK 0x00000008L +#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK 0x00000010L +#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK 0x00000020L +#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK 0x00000040L +#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK 0x00000080L +//DSCCLK3_DTO_PARAM +#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE__SHIFT 0x0 +#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO__SHIFT 0x10 +#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO_MASK 0x00FF0000L +//DPREFCLK_CGTT_BLK_CTRL_REG +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_GATE_DISABLE_CNTL4 +#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE_MASK 0x00020000L +//DPSTREAMCLK_CNTL +#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL__SHIFT 0x0 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN__SHIFT 0x3 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL__SHIFT 0x4 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN__SHIFT 0x7 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL__SHIFT 0x8 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN__SHIFT 0xb +#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL__SHIFT 0xc +#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN__SHIFT 0xf +#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL_MASK 0x00000007L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN_MASK 0x00000008L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL_MASK 0x00000070L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN_MASK 0x00000080L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL_MASK 0x00000700L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN_MASK 0x00000800L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL_MASK 0x00007000L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN_MASK 0x00008000L +//REFCLK_CGTT_BLK_CTRL_REG +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//PHYPLLE_PIXCLK_RESYNC_CNTL +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK 0x00000100L +//DCCG_GLOBAL_FGCG_REP_CNTL +#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS__SHIFT 0x0 +#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS_MASK 0x00000001L +//DCCG_DS_DTO_INCR +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0 +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xFFFFFFFFL +//DCCG_DS_DTO_MODULO +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0 +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xFFFFFFFFL +//DCCG_DS_CNTL +#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0 +#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT 0x4 +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8 +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9 +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10 +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18 +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19 +#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x00000001L +#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK 0x00000030L +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x00000100L +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x00000200L +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x00030000L +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x01000000L +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x02000000L +//DCCG_DS_HW_CAL_INTERVAL +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0 +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xFFFFFFFFL +//DPREFCLK_CNTL +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x00000007L +//DCE_VERSION +#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0 +#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8 +#define DCE_VERSION__MAJOR_VERSION_MASK 0x000000FFL +#define DCE_VERSION__MINOR_VERSION_MASK 0x0000FF00L +//DCCG_GTC_CNTL +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0 +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L +//DCCG_GTC_DTO_INCR +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0 +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xFFFFFFFFL +//DCCG_GTC_DTO_MODULO +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0 +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xFFFFFFFFL +//DCCG_GTC_CURRENT +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0 +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xFFFFFFFFL +//SYMCLK32_SE_CNTL +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL__SHIFT 0x0 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN__SHIFT 0x3 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL__SHIFT 0x4 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN__SHIFT 0x7 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL__SHIFT 0x8 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN__SHIFT 0xb +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL__SHIFT 0xc +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN__SHIFT 0xf +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL_MASK 0x00000007L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN_MASK 0x00000008L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL_MASK 0x00000070L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN_MASK 0x00000080L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL_MASK 0x00000700L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN_MASK 0x00000800L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL_MASK 0x00007000L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN_MASK 0x00008000L +//SYMCLK32_LE_CNTL +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL__SHIFT 0x0 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN__SHIFT 0x3 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL__SHIFT 0x4 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN__SHIFT 0x7 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL_MASK 0x00000007L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN_MASK 0x00000008L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL_MASK 0x00000070L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN_MASK 0x00000080L +//DTBCLK_P_CNTL +#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL__SHIFT 0x0 +#define DTBCLK_P_CNTL__DTBCLK_P0_EN__SHIFT 0x2 +#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL__SHIFT 0x3 +#define DTBCLK_P_CNTL__DTBCLK_P1_EN__SHIFT 0x5 +#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL__SHIFT 0x6 +#define DTBCLK_P_CNTL__DTBCLK_P2_EN__SHIFT 0x8 +#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL__SHIFT 0x9 +#define DTBCLK_P_CNTL__DTBCLK_P3_EN__SHIFT 0xb +#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL_MASK 0x00000003L +#define DTBCLK_P_CNTL__DTBCLK_P0_EN_MASK 0x00000004L +#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL_MASK 0x00000018L +#define DTBCLK_P_CNTL__DTBCLK_P1_EN_MASK 0x00000020L +#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL_MASK 0x000000C0L +#define DTBCLK_P_CNTL__DTBCLK_P2_EN_MASK 0x00000100L +#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL_MASK 0x00000600L +#define DTBCLK_P_CNTL__DTBCLK_P3_EN_MASK 0x00000800L +//DCCG_GATE_DISABLE_CNTL5 +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE__SHIFT 0x7 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE__SHIFT 0xd +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE_MASK 0x00000080L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE_MASK 0x00002000L +//DSCCLK0_DTO_PARAM +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT 0x0 +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT 0x10 +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK 0x00FF0000L +//DSCCLK1_DTO_PARAM +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT 0x0 +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT 0x10 +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK 0x00FF0000L +//DSCCLK2_DTO_PARAM +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT 0x0 +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT 0x10 +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK 0x00FF0000L +//OTG_PIXEL_RATE_DIV +#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK1__SHIFT 0x0 +#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK2__SHIFT 0x1 +#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK1__SHIFT 0x3 +#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK2__SHIFT 0x4 +#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK1__SHIFT 0x6 +#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK2__SHIFT 0x7 +#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK1__SHIFT 0x9 +#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK2__SHIFT 0xa +#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK1_MASK 0x00000001L +#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK2_MASK 0x00000006L +#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK1_MASK 0x00000008L +#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK2_MASK 0x00000030L +#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK1_MASK 0x00000040L +#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK2_MASK 0x00000180L +#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK1_MASK 0x00000200L +#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK2_MASK 0x00000C00L +//MILLISECOND_TIME_BASE_DIV +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001FFFFL +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +//DISPCLK_FREQ_CHANGE_CNTL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003FFFL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000F0000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0E000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L +//DC_MEM_GLOBAL_PWR_REQ_CNTL +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L +//DCCG_GATE_DISABLE_CNTL +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x00020000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x00040000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x00080000L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x08000000L +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000L +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000L +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000L +//DISPCLK_CGTT_BLK_CTRL_REG +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//SOCCLK_CGTT_BLK_CTRL_REG +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_CAC_STATUS +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xFFFFFFFFL +//MICROSECOND_TIME_BASE_DIV +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007FL +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007F00L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +//DCCG_GATE_DISABLE_CNTL2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE__SHIFT 0xd +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE__SHIFT 0x18 +#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE__SHIFT 0x19 +#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x00000020L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE_MASK 0x00002000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x00010000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x00020000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x00040000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x00080000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x00100000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x00200000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE_MASK 0x01000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE_MASK 0x02000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE_MASK 0x08000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE_MASK 0x10000000L +//SYMCLK_CGTT_BLK_CTRL_REG +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_DISP_CNTL_REG +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x00000100L +//OTG0_PIXEL_RATE_CNTL +#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE__SHIFT 0x3 +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 +#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS__SHIFT 0x6 +#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS__SHIFT 0x7 +#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT 0x8 +#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT 0x9 +#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL__SHIFT 0xc +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE_MASK 0x00000008L +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x00000020L +#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS_MASK 0x00000040L +#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS_MASK 0x00000080L +#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK 0x00000100L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK 0x00000200L +#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL_MASK 0x00003000L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO0_PHASE +#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 +#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xFFFFFFFFL +//DP_DTO0_MODULO +#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 +#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xFFFFFFFFL +//OTG0_PHYPLL_PIXEL_RATE_CNTL +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG1_PIXEL_RATE_CNTL +#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE__SHIFT 0x3 +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 +#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS__SHIFT 0x6 +#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS__SHIFT 0x7 +#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT 0x8 +#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT 0x9 +#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL__SHIFT 0xc +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE_MASK 0x00000008L +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x00000020L +#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS_MASK 0x00000040L +#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS_MASK 0x00000080L +#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK 0x00000100L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK 0x00000200L +#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL_MASK 0x00003000L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO1_PHASE +#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 +#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xFFFFFFFFL +//DP_DTO1_MODULO +#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 +#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xFFFFFFFFL +//OTG1_PHYPLL_PIXEL_RATE_CNTL +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG2_PIXEL_RATE_CNTL +#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE__SHIFT 0x3 +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4 +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5 +#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS__SHIFT 0x6 +#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS__SHIFT 0x7 +#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT 0x8 +#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT 0x9 +#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL__SHIFT 0xc +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE_MASK 0x00000008L +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x00000020L +#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS_MASK 0x00000040L +#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS_MASK 0x00000080L +#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK 0x00000100L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK 0x00000200L +#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL_MASK 0x00003000L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO2_PHASE +#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0 +#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xFFFFFFFFL +//DP_DTO2_MODULO +#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0 +#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xFFFFFFFFL +//OTG2_PHYPLL_PIXEL_RATE_CNTL +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG3_PIXEL_RATE_CNTL +#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE__SHIFT 0x3 +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4 +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5 +#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS__SHIFT 0x6 +#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS__SHIFT 0x7 +#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT 0x8 +#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT 0x9 +#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL__SHIFT 0xc +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE_MASK 0x00000008L +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x00000020L +#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS_MASK 0x00000040L +#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS_MASK 0x00000080L +#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK 0x00000100L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK 0x00000200L +#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL_MASK 0x00003000L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO3_PHASE +#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0 +#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xFFFFFFFFL +//DP_DTO3_MODULO +#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0 +#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xFFFFFFFFL +//OTG3_PHYPLL_PIXEL_RATE_CNTL +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//DPPCLK_CGTT_BLK_CTRL_REG +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DPPCLK0_DTO_PARAM +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT 0x0 +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT 0x10 +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK1_DTO_PARAM +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT 0x0 +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT 0x10 +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK2_DTO_PARAM +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT 0x0 +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT 0x10 +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK3_DTO_PARAM +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT 0x0 +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT 0x10 +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK 0x00FF0000L +//DCCG_CAC_STATUS2 +#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT 0x0 +#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK 0x0007FFFFL +//SYMCLKA_CLOCK_ENABLE +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKB_CLOCK_ENABLE +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKC_CLOCK_ENABLE +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKD_CLOCK_ENABLE +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKE_CLOCK_ENABLE +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x00000700L +//DCCG_SOFT_RESET +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 +#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 +#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10 +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11 +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12 +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13 +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14 +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15 +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L +#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L +#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x00000010L +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x00000100L +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x00001000L +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x00002000L +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x00004000L +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x00008000L +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x00010000L +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x00020000L +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x00040000L +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x00080000L +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x00100000L +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x00200000L +//DSCCLK_DTO_CTRL +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE__SHIFT 0x0 +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE__SHIFT 0x1 +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE__SHIFT 0x2 +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE__SHIFT 0x3 +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE__SHIFT 0x4 +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE__SHIFT 0x5 +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT 0x8 +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT 0x9 +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT 0xa +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT 0xb +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT 0xc +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT 0xd +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE_MASK 0x00000001L +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE_MASK 0x00000002L +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE_MASK 0x00000004L +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE_MASK 0x00000008L +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE_MASK 0x00000010L +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE_MASK 0x00000020L +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK 0x00000100L +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK 0x00000200L +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK 0x00000400L +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK 0x00000800L +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK 0x00001000L +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK 0x00002000L +//DCCG_AUDIO_DTO_SOURCE +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO__SHIFT 0x1d +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000070L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x00100000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x01000000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO_MASK 0x20000000L +//DCCG_AUDIO_DTO0_PHASE +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO0_MODULE +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO1_PHASE +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO1_MODULE +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG0_LATCH_VALUE +#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG1_LATCH_VALUE +#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG2_LATCH_VALUE +#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG3_LATCH_VALUE +#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG4_LATCH_VALUE +#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG5_LATCH_VALUE +#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK 0xFFFFFFFFL +//DPPCLK_DTO_CTRL +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE__SHIFT 0x0 +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT 0x1 +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE__SHIFT 0x4 +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT 0x5 +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE__SHIFT 0x8 +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT 0x9 +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE__SHIFT 0xc +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT 0xd +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE__SHIFT 0x10 +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT 0x11 +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE__SHIFT 0x14 +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT 0x15 +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE_MASK 0x00000001L +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK 0x00000002L +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE_MASK 0x00000010L +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK 0x00000020L +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE_MASK 0x00000100L +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK 0x00000200L +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE_MASK 0x00001000L +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK 0x00002000L +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE_MASK 0x00010000L +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK 0x00020000L +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE_MASK 0x00100000L +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK 0x00200000L +//DCCG_VSYNC_CNT_CTRL +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT 0x0 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT 0x2 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT 0x3 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT 0x4 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT 0x8 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT 0x10 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT 0x11 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT 0x12 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT 0x13 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT 0x14 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT 0x15 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT 0x18 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT 0x19 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT 0x1a +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT 0x1b +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT 0x1c +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT 0x1d +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK 0x00000001L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK 0x00000004L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK 0x00000008L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK 0x000000F0L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK 0x00000F00L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK 0x00010000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK 0x00020000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK 0x00040000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK 0x00080000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK 0x00100000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK 0x00200000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK 0x01000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK 0x02000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK 0x04000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK 0x08000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK 0x10000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK 0x20000000L +//DCCG_VSYNC_CNT_INT_CTRL +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT 0x0 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT 0x0 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT 0x1 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT 0x1 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT 0x2 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT 0x2 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT 0x3 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT 0x3 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT 0x4 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT 0x4 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT 0x5 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT 0x5 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT 0x8 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT 0x9 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT 0xa +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT 0xb +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT 0xc +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT 0xd +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK 0x00000001L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK 0x00000001L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK 0x00000002L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK 0x00000002L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK 0x00000004L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK 0x00000004L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK 0x00000008L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK 0x00000008L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK 0x00000010L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK 0x00000010L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK 0x00000020L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK 0x00000020L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK 0x00000100L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK 0x00000200L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK 0x00000400L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK 0x00000800L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK 0x00001000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK 0x00002000L +//FORCE_SYMCLK_DISABLE +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT 0x0 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT 0x1 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT 0x2 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT 0x3 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT 0x4 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT 0x5 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT 0x6 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK 0x00000001L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK 0x00000002L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK 0x00000004L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK 0x00000008L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK 0x00000010L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK 0x00000020L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK 0x00000040L +//DCCG_TEST_CLK_SEL +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL__SHIFT 0xe +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000001FFL +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00001000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL_MASK 0x0000C000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x01FF0000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000L +//DTBCLK_DTO0_PHASE +#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE__SHIFT 0x0 +#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE_MASK 0xFFFFFFFFL +//DTBCLK_DTO1_PHASE +#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE__SHIFT 0x0 +#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE_MASK 0xFFFFFFFFL +//DTBCLK_DTO2_PHASE +#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE__SHIFT 0x0 +#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE_MASK 0xFFFFFFFFL +//DTBCLK_DTO3_PHASE +#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE__SHIFT 0x0 +#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE_MASK 0xFFFFFFFFL +//DTBCLK_DTO0_MODULO +#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO__SHIFT 0x0 +#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO_MASK 0xFFFFFFFFL +//DTBCLK_DTO1_MODULO +#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO__SHIFT 0x0 +#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO_MASK 0xFFFFFFFFL +//DTBCLK_DTO2_MODULO +#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO__SHIFT 0x0 +#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO_MASK 0xFFFFFFFFL +//DTBCLK_DTO3_MODULO +#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO__SHIFT 0x0 +#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO_MASK 0xFFFFFFFFL +//HDMICHARCLK0_CLOCK_CNTL +#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN__SHIFT 0x0 +#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL__SHIFT 0x4 +#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN_MASK 0x00000001L +#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL_MASK 0x00000070L +//PHYASYMCLK_CLOCK_CNTL +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN__SHIFT 0x0 +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL__SHIFT 0x4 +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN_MASK 0x00000001L +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL_MASK 0x00000030L +//PHYBSYMCLK_CLOCK_CNTL +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN__SHIFT 0x0 +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL__SHIFT 0x4 +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN_MASK 0x00000001L +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL_MASK 0x00000030L +//PHYCSYMCLK_CLOCK_CNTL +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_EN__SHIFT 0x0 +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_SRC_SEL__SHIFT 0x4 +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_EN_MASK 0x00000001L +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_SRC_SEL_MASK 0x00000030L +//PHYDSYMCLK_CLOCK_CNTL +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_EN__SHIFT 0x0 +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_SRC_SEL__SHIFT 0x4 +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_EN_MASK 0x00000001L +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_SRC_SEL_MASK 0x00000030L +//PHYESYMCLK_CLOCK_CNTL +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN__SHIFT 0x0 +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL__SHIFT 0x4 +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN_MASK 0x00000001L +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL_MASK 0x00000030L +//HDMISTREAMCLK_CNTL +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL__SHIFT 0x0 +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN__SHIFT 0x3 +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_DTO_FORCE_DIS__SHIFT 0x4 +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL_MASK 0x00000007L +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN_MASK 0x00000008L +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_DTO_FORCE_DIS_MASK 0x00000010L +//DCCG_GATE_DISABLE_CNTL3 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE__SHIFT 0xd +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE__SHIFT 0xe +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE__SHIFT 0xf +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE__SHIFT 0x17 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE_MASK 0x00000020L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE_MASK 0x00002000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE_MASK 0x00004000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE_MASK 0x00008000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE_MASK 0x00100000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE_MASK 0x00200000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE_MASK 0x00800000L +//HDMISTREAMCLK0_DTO_PARAM +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE__SHIFT 0x0 +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO__SHIFT 0x8 +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN__SHIFT 0x10 +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE_MASK 0x000000FFL +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO_MASK 0x0000FF00L +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN_MASK 0x00010000L +//DCCG_AUDIO_DTBCLK_DTO_PHASE +#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTBCLK_DTO_MODULO +#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO__SHIFT 0x0 +#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO_MASK 0xFFFFFFFFL +//DTBCLK_DTO_DBUF_EN +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN__SHIFT 0x0 +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN__SHIFT 0x1 +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN__SHIFT 0x2 +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN__SHIFT 0x3 +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN_MASK 0x00000001L +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN_MASK 0x00000002L +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN_MASK 0x00000004L +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN_MASK 0x00000008L +//DMCUBCLK_CNTL +#define DMCUBCLK_CNTL__DMCUBCLK_SRC_SEL__SHIFT 0x0 +#define DMCUBCLK_CNTL__DMCUBCLK_SRC_SEL_MASK 0x00000003L + + +// addressBlock: dce_dc_dmu_rbbmif_dispdec +//RBBMIF_TIMEOUT +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14 +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0x000FFFFFL +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xFFF00000L +//RBBMIF_STATUS +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0xFFFFFFFFL +//RBBMIF_STATUS_2 +#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT 0x0 +#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK 0x0000007FL +//RBBMIF_INT_STATUS +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT 0x2 +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK 0x0003FFFCL +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000L +//RBBMIF_TIMEOUT_DIS +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0 +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1 +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2 +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3 +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4 +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5 +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6 +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7 +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8 +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9 +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe +#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT 0xf +#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT 0x10 +#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT 0x11 +#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT 0x12 +#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT 0x13 +#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT 0x14 +#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT 0x15 +#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT 0x16 +#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT 0x17 +#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT 0x18 +#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT 0x19 +#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT 0x1a +#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT 0x1b +#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT 0x1c +#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT 0x1d +#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT 0x1e +#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT 0x1f +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x00000001L +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x00000002L +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x00000004L +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x00000008L +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x00000010L +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x00000020L +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x00000040L +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x00000080L +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x00000100L +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x00000200L +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x00000400L +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x00000800L +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x00001000L +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x00002000L +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x00004000L +#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK 0x00008000L +#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK 0x00010000L +#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK 0x00020000L +#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK 0x00040000L +#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK 0x00080000L +#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK 0x00100000L +#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK 0x00200000L +#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK 0x00400000L +#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK 0x00800000L +#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK 0x01000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK 0x02000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK 0x04000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK 0x08000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK 0x10000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK 0x20000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK 0x40000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK 0x80000000L +//RBBMIF_TIMEOUT_DIS_2 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT 0x0 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT 0x1 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT 0x2 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT 0x3 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT 0x4 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT 0x5 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS__SHIFT 0x6 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK 0x00000001L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK 0x00000002L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK 0x00000004L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK 0x00000008L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK 0x00000010L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK 0x00000020L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS_MASK 0x00000040L +//RBBMIF_STATUS_FLAG +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0 +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT 0x8 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT 0x9 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT 0x10 +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x00000003L +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x00000010L +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x00000020L +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x00000040L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK 0x00000100L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK 0x00000E00L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dmu_ihc_dispdec +//DC_GPU_TIMER_START_POSITION_V_UPDATE +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_VSTARTUP +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK 0x00700000L +//DC_GPU_TIMER_READ +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xFFFFFFFFL +//DC_GPU_TIMER_READ_CNTL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000007FL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001C000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000E0000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L +//DISP_INTERRUPT_STATUS +#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE +#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE2 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE3 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE6 +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE7 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE8 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE9 +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE10 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE11 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE12 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE13 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE14 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE15 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE16 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE17 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE18 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE19 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE20 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE21 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE22 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK 0x80000000L +//DC_GPU_TIMER_START_POSITION_VREADY +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_FLIP +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT 0x18 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT 0x1c +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK 0x07000000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK 0x70000000L +//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_FLIP_AWAY +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT 0x18 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT 0x1c +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK 0x07000000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK 0x70000000L +//DISP_INTERRUPT_STATUS_CONTINUE23 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE24 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE25 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT_MASK 0x40000000L +//DCCG_INTERRUPT_DEST +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT 0x0 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT 0x1 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT 0x2 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT 0x3 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT 0x4 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT 0x5 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK 0x00000001L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK 0x00000002L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK 0x00000004L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK 0x00000008L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK 0x00000010L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK 0x00000020L +//DMU_INTERRUPT_DEST +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT 0x0 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT 0x1 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT 0x2 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT 0x3 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT 0x4 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST__SHIFT 0x5 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST__SHIFT 0x6 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST__SHIFT 0x7 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST__SHIFT 0x8 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST__SHIFT 0x9 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT 0xa +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT 0xb +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT 0xc +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT 0xd +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT 0xe +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT 0xf +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT 0x10 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT 0x11 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT 0x1a +#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1b +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK 0x00000001L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK 0x00000002L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK 0x00000004L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK 0x00000008L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK 0x00000010L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST_MASK 0x00000020L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST_MASK 0x00000040L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST_MASK 0x00000080L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST_MASK 0x00000100L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST_MASK 0x00000200L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK 0x00000400L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK 0x00000800L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK 0x00001000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK 0x00002000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK 0x00004000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK 0x00008000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK 0x00010000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK 0x00020000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK 0x04000000L +#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x08000000L +//DMU_INTERRUPT_DEST2 +#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST__SHIFT 0xc +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST__SHIFT 0xd +#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST_MASK 0x00001000L +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST_MASK 0x00002000L +//DCPG_INTERRUPT_DEST +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT 0x0 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT 0x1 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT 0x2 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT 0x3 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT 0x4 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT 0x5 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT 0x6 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT 0x7 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x10 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x11 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x12 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x13 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x14 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x15 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x16 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x17 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK 0x00000001L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK 0x00000002L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK 0x00000004L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK 0x00000008L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK 0x00000010L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK 0x00000020L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK 0x00000040L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK 0x00000080L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK 0x00010000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK 0x00020000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK 0x00040000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK 0x00080000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK 0x00100000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK 0x00200000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK 0x00400000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK 0x00800000L +//DCPG_INTERRUPT_DEST2 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT 0x0 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT 0x1 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT 0x2 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT 0x3 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT 0x4 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT 0x5 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x6 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x7 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x8 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x9 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT 0xa +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT 0xb +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK 0x00000001L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK 0x00000002L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK 0x00000004L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK 0x00000008L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK 0x00000010L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK 0x00000020L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000040L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000080L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000100L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000200L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000400L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000800L +//MMHUBBUB_INTERRUPT_DEST +#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST__SHIFT 0x0 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT 0x1 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT 0x2 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT 0x3 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT 0x4 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT 0x5 +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST__SHIFT 0x8 +#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST_MASK 0x00000001L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK 0x00000002L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK 0x00000004L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK 0x00000008L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK 0x00000010L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK 0x00000020L +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST_MASK 0x00000100L +//WB_INTERRUPT_DEST +#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0x1 +#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0x9 +#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0xb +#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000002L +#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000200L +#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000800L +//DCHUB_INTERRUPT_DEST +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x0 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x1 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x2 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x3 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x4 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x5 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x6 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x7 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x8 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x9 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0xa +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0xb +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x10 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x11 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x12 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x13 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x14 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x15 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x16 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x17 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x1a +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1b +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x1c +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x1d +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x1e +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1f +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000001L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000002L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000004L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000008L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000010L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000020L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000040L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000080L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000100L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000200L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000400L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000800L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00010000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK 0x00020000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00040000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00080000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00100000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK 0x00200000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00400000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00800000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK 0x02000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK 0x04000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x08000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK 0x10000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK 0x20000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK 0x40000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x80000000L +//DCHUB_PERFCOUNTER_INTERRUPT_DEST +//DCHUB_INTERRUPT_DEST2 +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x0 +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x1 +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x2 +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x3 +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x4 +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x5 +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x6 +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x7 +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x8 +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x9 +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xa +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xb +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST__SHIFT 0x1a +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000001L +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000002L +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000004L +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000008L +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000010L +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000020L +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000040L +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000080L +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000100L +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000200L +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000400L +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000800L +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x02000000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST_MASK 0x04000000L +//DPP_PERFCOUNTER_INTERRUPT_DEST +//MPC_INTERRUPT_DEST +#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT 0x0 +#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT 0x1 +#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT 0x2 +#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT 0x3 +#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT 0x4 +#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT 0x5 +#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT 0x6 +#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT 0x7 +#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK 0x00000001L +#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK 0x00000002L +#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK 0x00000004L +#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK 0x00000008L +#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK 0x00000010L +#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK 0x00000020L +#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK 0x00000040L +#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK 0x00000080L +//OPP_INTERRUPT_DEST +//OPTC_INTERRUPT_DEST +#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x18 +#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x19 +#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1a +#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1b +#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1c +#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1d +#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x01000000L +#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x02000000L +#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x04000000L +#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x08000000L +#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x10000000L +#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x20000000L +//OTG0_INTERRUPT_DEST +#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG1_INTERRUPT_DEST +#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG2_INTERRUPT_DEST +#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG3_INTERRUPT_DEST +#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG4_INTERRUPT_DEST +#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG5_INTERRUPT_DEST +#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//DIG_INTERRUPT_DEST +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x0 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x1 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x2 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x3 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x4 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x5 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x6 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x7 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0x8 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0x9 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xa +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xb +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xc +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xd +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xe +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xf +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000001L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000002L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000004L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000008L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000010L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000020L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000040L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000080L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000100L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000200L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000400L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000800L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00001000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00002000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00004000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00008000L +//I2C_DDC_HPD_INTERRUPT_DEST +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT 0x0 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT 0x1 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT 0x2 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT 0x3 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT 0x4 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT 0x5 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT 0x6 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT 0x7 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x10 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x11 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x12 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x13 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x14 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x15 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT 0x16 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK 0x00000001L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK 0x00000002L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK 0x00000004L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK 0x00000008L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK 0x00000010L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK 0x00000020L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK 0x00000040L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK 0x00000080L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK 0x00010000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK 0x00020000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK 0x00040000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK 0x00080000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK 0x00100000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK 0x00200000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK 0x00400000L +//DIO_INTERRUPT_DEST +#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST__SHIFT 0x4 +#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST_MASK 0x00000010L +//DCIO_INTERRUPT_DEST +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x0 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x1 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x2 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x3 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x4 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x5 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x6 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x10 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000001L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000002L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000004L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000008L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000010L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000020L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000040L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK 0x00010000L +//HPD_INTERRUPT_DEST +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT 0x0 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT 0x1 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT 0x2 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT 0x3 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT 0x4 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT 0x5 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT 0x8 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT 0x9 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT 0xa +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT 0xb +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT 0xc +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT 0xd +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK 0x00000001L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK 0x00000002L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK 0x00000004L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK 0x00000008L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK 0x00000010L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK 0x00000020L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK 0x00000100L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK 0x00000200L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK 0x00000400L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK 0x00000800L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK 0x00001000L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK 0x00002000L +//AZ_INTERRUPT_DEST +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x0 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x1 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x2 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x3 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x4 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x5 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x6 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x7 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT 0x8 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT 0x9 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT 0xa +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT 0xb +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT 0xc +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT 0xd +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT 0xe +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT 0xf +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT 0x10 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT 0x11 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT 0x12 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT 0x13 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT 0x14 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT 0x15 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT 0x16 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT 0x17 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000001L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000002L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000004L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000008L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000010L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000020L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000040L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000080L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK 0x00000100L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK 0x00000200L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK 0x00000400L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK 0x00000800L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK 0x00001000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK 0x00002000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK 0x00004000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK 0x00008000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK 0x00010000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK 0x00020000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK 0x00040000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK 0x00080000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK 0x00100000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK 0x00200000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK 0x00400000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK 0x00800000L +//AUX_INTERRUPT_DEST +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT 0x0 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT 0x1 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT 0x2 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT 0x3 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT 0x4 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT 0x5 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT 0x6 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT 0x7 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT 0x8 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT 0x9 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT 0xa +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT 0xb +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x10 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x11 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x12 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x13 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x14 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x15 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x16 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x17 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x18 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x19 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x1a +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x1b +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK 0x00000001L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK 0x00000002L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK 0x00000004L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK 0x00000008L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK 0x00000010L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK 0x00000020L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK 0x00000040L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK 0x00000080L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK 0x00000100L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK 0x00000200L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK 0x00000400L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK 0x00000800L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00010000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00020000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00040000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00080000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00100000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00200000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00400000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00800000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x01000000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x02000000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x04000000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x08000000L +//DSC_INTERRUPT_DEST +#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x0 +#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x1 +#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x4 +#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x5 +#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x8 +#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x9 +#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0xc +#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0xd +#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x10 +#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x11 +#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x14 +#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x15 +#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000001L +#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000002L +#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000010L +#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000020L +#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000100L +#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000200L +#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00001000L +#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00002000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00010000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00020000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00100000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00200000L +//HPO_INTERRUPT_DEST + + +// addressBlock: dce_dc_dmu_dmu_misc_dispdec +//CC_DC_PIPE_DIS +#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x0 +#define CC_DC_PIPE_DIS__DC_FULL_DIS__SHIFT 0xc +#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT 0x10 +#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x000000FFL +#define CC_DC_PIPE_DIS__DC_FULL_DIS_MASK 0x00001000L +#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK 0x00010000L +//DMU_CLK_CNTL +#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT 0x0 +#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT 0x4 +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT 0x6 +#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT 0x8 +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT 0xa +#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK 0x0000000FL +#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK 0x00000010L +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK 0x00000040L +#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK 0x00000100L +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK 0x00000400L +//DMCUB_SMU_INTERRUPT_CNTL +#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT__SHIFT 0x0 +#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG__SHIFT 0x10 +#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT_MASK 0x00000001L +#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_MASK 0xFFFF0000L +//SMU_INTERRUPT_CONTROL +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x00000001L +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x00000010L +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xFFFF0000L +//DMU_MISC_ALLOW_DS_FORCE +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT 0x0 +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT 0x4 +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK 0x00000001L +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK 0x00000010L + + +// addressBlock: dce_dc_dmu_dc_pg_dispdec +//DOMAIN0_PG_CONFIG +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN0_PG_STATUS +#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN1_PG_CONFIG +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN1_PG_STATUS +#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN2_PG_CONFIG +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN2_PG_STATUS +#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN3_PG_CONFIG +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN3_PG_STATUS +#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN16_PG_CONFIG +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN16_PG_STATUS +#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN17_PG_CONFIG +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN17_PG_STATUS +#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN18_PG_CONFIG +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN18_PG_STATUS +#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN19_PG_CONFIG +#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN19_PG_STATUS +#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DCPG_INTERRUPT_STATUS +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK 0x00000040L +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L +//DCPG_INTERRUPT_STATUS_2 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED_MASK 0x00000040L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L +//DCPG_INTERRUPT_CONTROL_1 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT 0xc +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT 0xe +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK 0x00000001L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK 0x00000004L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK 0x00000008L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK 0x00000010L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK 0x00000040L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK 0x00000100L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK 0x00000400L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK 0x00001000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK 0x00004000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +//DCPG_INTERRUPT_CONTROL_3 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK__SHIFT 0xc +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK__SHIFT 0xe +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK_MASK 0x00000001L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK_MASK 0x00000004L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK 0x00000008L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK_MASK 0x00000010L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK_MASK 0x00000040L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK_MASK 0x00000100L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK_MASK 0x00000400L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK_MASK 0x00001000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK_MASK 0x00004000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +//DC_IP_REQUEST_CNTL +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0 +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x00000001L + + +// addressBlock: dce_dc_dmu_dmcub_dispdec +//DMCUB_REGION0_OFFSET +#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT 0x8 +#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION0_OFFSET_HIGH +#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION1_OFFSET +#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT 0x8 +#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION1_OFFSET_HIGH +#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION2_OFFSET +#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT 0x8 +#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION2_OFFSET_HIGH +#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION4_OFFSET +#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT 0x8 +#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION4_OFFSET_HIGH +#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION5_OFFSET +#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT 0x8 +#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION5_OFFSET_HIGH +#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION6_OFFSET +#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT 0x8 +#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION6_OFFSET_HIGH +#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION7_OFFSET +#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT 0x8 +#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION7_OFFSET_HIGH +#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION0_TOP_ADDRESS +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT 0x1f +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK 0x80000000L +//DMCUB_REGION1_TOP_ADDRESS +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT 0x1f +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK 0x80000000L +//DMCUB_REGION2_TOP_ADDRESS +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT 0x1f +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK 0x80000000L +//DMCUB_REGION4_TOP_ADDRESS +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT 0x1f +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK 0x80000000L +//DMCUB_REGION5_TOP_ADDRESS +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT 0x1f +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK 0x80000000L +//DMCUB_REGION6_TOP_ADDRESS +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT 0x1f +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK 0x80000000L +//DMCUB_REGION7_TOP_ADDRESS +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT 0x1f +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW0_BASE_ADDRESS +#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW1_BASE_ADDRESS +#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW2_BASE_ADDRESS +#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW3_BASE_ADDRESS +#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW4_BASE_ADDRESS +#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW5_BASE_ADDRESS +#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW6_BASE_ADDRESS +#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW7_BASE_ADDRESS +#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW0_TOP_ADDRESS +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW1_TOP_ADDRESS +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW2_TOP_ADDRESS +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW3_TOP_ADDRESS +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW4_TOP_ADDRESS +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW5_TOP_ADDRESS +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW6_TOP_ADDRESS +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW7_TOP_ADDRESS +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW0_OFFSET +#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW0_OFFSET_HIGH +#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW1_OFFSET +#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW1_OFFSET_HIGH +#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW2_OFFSET +#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW2_OFFSET_HIGH +#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW3_OFFSET +#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW3_OFFSET_HIGH +#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW4_OFFSET +#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW4_OFFSET_HIGH +#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW5_OFFSET +#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW5_OFFSET_HIGH +#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW6_OFFSET +#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW6_OFFSET_HIGH +#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW7_OFFSET +#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW7_OFFSET_HIGH +#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_INTERRUPT_ENABLE +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT 0x0 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT 0x1 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT 0x2 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT 0x3 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT 0x4 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT 0x5 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT 0x6 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT 0x7 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT 0x8 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT 0x9 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT 0xa +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT 0xb +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT 0xc +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN__SHIFT 0xd +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN__SHIFT 0xe +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN__SHIFT 0xf +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN__SHIFT 0x10 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN__SHIFT 0x11 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT 0x12 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK 0x00000001L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK 0x00000002L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK 0x00000004L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK 0x00000008L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK 0x00000010L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK 0x00000020L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK 0x00000040L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK 0x00000080L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK 0x00000100L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK 0x00000200L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK 0x00000400L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK 0x00000800L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK 0x00001000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN_MASK 0x00002000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN_MASK 0x00004000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN_MASK 0x00008000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN_MASK 0x00010000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN_MASK 0x00020000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK 0x00040000L +//DMCUB_INTERRUPT_ACK +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT 0x0 +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT 0x1 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT 0x2 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT 0x3 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT 0x4 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT 0x5 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT 0x6 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT 0x7 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT 0x8 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT 0x9 +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT 0xa +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT 0xb +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT 0xc +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK__SHIFT 0xd +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK__SHIFT 0xe +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK__SHIFT 0xf +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK__SHIFT 0x10 +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK__SHIFT 0x11 +#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT 0x12 +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK 0x00000001L +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK 0x00000002L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK 0x00000004L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK 0x00000008L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK 0x00000010L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK 0x00000020L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK 0x00000040L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK 0x00000080L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK 0x00000100L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK 0x00000200L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK 0x00000400L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK 0x00000800L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK 0x00001000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK_MASK 0x00002000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK_MASK 0x00004000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK_MASK 0x00008000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK_MASK 0x00010000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK_MASK 0x00020000L +#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK 0x00040000L +//DMCUB_INTERRUPT_STATUS +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT 0x0 +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT 0x1 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT 0x2 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT 0x3 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT 0x4 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT 0x5 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT 0x6 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT 0x7 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT 0x8 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT 0x9 +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT 0xa +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT 0xb +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT 0xc +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT__SHIFT 0xd +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT__SHIFT 0xe +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT__SHIFT 0xf +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT__SHIFT 0x10 +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT__SHIFT 0x11 +#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT 0x12 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT 0x13 +#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT 0x14 +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK 0x00000001L +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK 0x00000002L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK 0x00000004L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK 0x00000008L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK 0x00000010L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK 0x00000020L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK 0x00000040L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK 0x00000080L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK 0x00000100L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK 0x00000200L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK 0x00000400L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK 0x00000800L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK 0x00001000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT_MASK 0x00002000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT_MASK 0x00004000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT_MASK 0x00008000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT_MASK 0x00010000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT_MASK 0x00020000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK 0x00040000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK 0x00080000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK 0x00100000L +//DMCUB_INTERRUPT_TYPE +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT 0x0 +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT 0x1 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT 0x2 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT 0x3 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT 0x4 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT 0x5 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT 0x6 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT 0x7 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT 0x8 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT 0x9 +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT 0xa +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT 0xb +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT 0xc +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE__SHIFT 0xd +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE__SHIFT 0xe +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE__SHIFT 0xf +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE__SHIFT 0x10 +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE__SHIFT 0x11 +#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT 0x12 +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK 0x00000001L +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK 0x00000002L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK 0x00000004L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK 0x00000008L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK 0x00000010L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK 0x00000020L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK 0x00000040L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK 0x00000080L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK 0x00000100L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK 0x00000200L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK 0x00000400L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK 0x00000800L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK 0x00001000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE_MASK 0x00002000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE_MASK 0x00004000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE_MASK 0x00008000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE_MASK 0x00010000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE_MASK 0x00020000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK 0x00040000L +//DMCUB_EXT_INTERRUPT_STATUS +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT 0x8 +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK 0x000000FFL +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK 0x0000FF00L +//DMCUB_EXT_INTERRUPT_CTXID +#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK 0x0FFFFFFFL +//DMCUB_EXT_INTERRUPT_ACK +#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK 0x00000001L +//DMCUB_INST_FETCH_FAULT_ADDR +#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_DATA_WRITE_FAULT_ADDR +#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_SEC_CNTL +#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL__SHIFT 0x0 +#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT 0x8 +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT 0x10 +#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT 0x11 +#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT 0x14 +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT 0x15 +#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT 0x18 +#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT 0x19 +#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL_MASK 0x00000007L +#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK 0x00003F00L +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK 0x00010000L +#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK 0x00020000L +#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK 0x00100000L +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK 0x00200000L +#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK 0x01000000L +#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK 0x02000000L +//DMCUB_MEM_CNTL +#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT 0x0 +#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT 0x4 +#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK 0x0000000FL +#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK 0x000000F0L +//DMCUB_INBOX0_BASE_ADDRESS +#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_SIZE +#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT 0x0 +#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_WPTR +#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT 0x0 +#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_RPTR +#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT 0x0 +#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_BASE_ADDRESS +#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_SIZE +#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT 0x0 +#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_WPTR +#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT 0x0 +#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_RPTR +#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT 0x0 +#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_BASE_ADDRESS +#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_SIZE +#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT 0x0 +#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_WPTR +#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT 0x0 +#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_RPTR +#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT 0x0 +#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_BASE_ADDRESS +#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_SIZE +#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT 0x0 +#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_WPTR +#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT 0x0 +#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_RPTR +#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT 0x0 +#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK 0xFFFFFFFFL +//DMCUB_TIMER_TRIGGER0 +#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT 0x0 +#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK 0xFFFFFFFFL +//DMCUB_TIMER_TRIGGER1 +#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT 0x0 +#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK 0xFFFFFFFFL +//DMCUB_TIMER_WINDOW +#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT 0x0 +#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK 0x00000007L +//DMCUB_SCRATCH0 +#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT 0x0 +#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH1 +#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT 0x0 +#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH2 +#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT 0x0 +#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH3 +#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT 0x0 +#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH4 +#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT 0x0 +#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH5 +#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT 0x0 +#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH6 +#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT 0x0 +#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH7 +#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT 0x0 +#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH8 +#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT 0x0 +#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH9 +#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT 0x0 +#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH10 +#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT 0x0 +#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH11 +#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT 0x0 +#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH12 +#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT 0x0 +#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH13 +#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT 0x0 +#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH14 +#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT 0x0 +#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH15 +#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT 0x0 +#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH16 +#define DMCUB_SCRATCH16__DMCUB_SCRATCH16__SHIFT 0x0 +#define DMCUB_SCRATCH16__DMCUB_SCRATCH16_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH17 +#define DMCUB_SCRATCH17__DMCUB_SCRATCH17__SHIFT 0x0 +#define DMCUB_SCRATCH17__DMCUB_SCRATCH17_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH18 +#define DMCUB_SCRATCH18__DMCUB_SCRATCH18__SHIFT 0x0 +#define DMCUB_SCRATCH18__DMCUB_SCRATCH18_MASK 0xFFFFFFFFL +//DMCUB_CNTL +#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT 0x0 +#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT 0x8 +#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT 0x10 +#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT 0x12 +#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT 0x13 +#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT 0x14 +#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK 0x000000FFL +#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK 0x00000100L +#define DMCUB_CNTL__DMCUB_ENABLE_MASK 0x00010000L +#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK 0x00040000L +#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK 0x00080000L +#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK 0x00100000L +//DMCUB_GPINT_DATAIN0 +#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN1 +#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAOUT +#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT 0x0 +#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK 0xFFFFFFFFL +//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR +#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_LS_WAKE_INT_ENABLE +#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT 0x0 +#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK 0xFFFFFFFFL +//DMCUB_MEM_PWR_CNTL +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT 0x1 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT 0x3 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT 0x4 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK 0x00000006L +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK 0x00000008L +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK 0x00000030L +//DMCUB_TIMER_CURRENT +#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT 0x0 +#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK 0xFFFFFFFFL +//DMCUB_PROC_ID +#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT 0x0 +#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK 0x0000FFFFL +//DMCUB_CNTL2 +#define DMCUB_CNTL2__DMCUB_SOFT_RESET__SHIFT 0x0 +#define DMCUB_CNTL2__DMCUB_SOFT_RESET_MASK 0x00000001L +//DMCUB_GPINT_DATAIN2 +#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN3 +#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN4 +#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN5 +#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN6 +#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6_MASK 0xFFFFFFFFL +//DMCUB_REGION3_TMR_AXI_SPACE +#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE__SHIFT 0x0 +#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE_MASK 0x07L +//DMCUB_SCRATCH19 +#define DMCUB_SCRATCH19__DMCUB_SCRATCH19__SHIFT 0x0 +#define DMCUB_SCRATCH19__DMCUB_SCRATCH19_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH20 +#define DMCUB_SCRATCH20__DMCUB_SCRATCH20__SHIFT 0x0 +#define DMCUB_SCRATCH20__DMCUB_SCRATCH20_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH21 +#define DMCUB_SCRATCH21__DMCUB_SCRATCH21__SHIFT 0x0 +#define DMCUB_SCRATCH21__DMCUB_SCRATCH21_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH22 +#define DMCUB_SCRATCH22__DMCUB_SCRATCH22__SHIFT 0x0 +#define DMCUB_SCRATCH22__DMCUB_SCRATCH22_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH23 +#define DMCUB_SCRATCH23__DMCUB_SCRATCH23__SHIFT 0x0 +#define DMCUB_SCRATCH23__DMCUB_SCRATCH23_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec +//DWB_ENABLE_CLK_CTRL +#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE__SHIFT 0x0 +#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS__SHIFT 0x4 +#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS__SHIFT 0x8 +#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL__SHIFT 0xc +#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE_MASK 0x00000001L +#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS_MASK 0x00000010L +#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS_MASK 0x00000100L +#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL_MASK 0x00003000L +//DWB_MEM_PWR_CTRL +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE__SHIFT 0x8 +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS__SHIFT 0xa +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE__SHIFT 0xc +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE__SHIFT 0x10 +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS__SHIFT 0x12 +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE__SHIFT 0x14 +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE_MASK 0x00000300L +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS_MASK 0x00000400L +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE_MASK 0x00003000L +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE_MASK 0x00030000L +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS_MASK 0x00040000L +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE_MASK 0x00300000L +//FC_MODE_CTRL +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN__SHIFT 0x0 +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE__SHIFT 0x4 +#define FC_MODE_CTRL__FC_WINDOW_CROP_EN__SHIFT 0x8 +#define FC_MODE_CTRL__FC_EYE_SELECTION__SHIFT 0xc +#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY__SHIFT 0x10 +#define FC_MODE_CTRL__FC_NEW_CONTENT__SHIFT 0x14 +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT__SHIFT 0x1f +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_MASK 0x00000001L +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE_MASK 0x00000030L +#define FC_MODE_CTRL__FC_WINDOW_CROP_EN_MASK 0x00000100L +#define FC_MODE_CTRL__FC_EYE_SELECTION_MASK 0x00003000L +#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY_MASK 0x00010000L +#define FC_MODE_CTRL__FC_NEW_CONTENT_MASK 0x00100000L +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT_MASK 0x80000000L +//FC_FLOW_CTRL +#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT__SHIFT 0x0 +#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT_MASK 0x00000FFFL +//FC_WINDOW_START +#define FC_WINDOW_START__FC_WINDOW_START_X__SHIFT 0x0 +#define FC_WINDOW_START__FC_WINDOW_START_Y__SHIFT 0x10 +#define FC_WINDOW_START__FC_WINDOW_START_X_MASK 0x00001FFFL +#define FC_WINDOW_START__FC_WINDOW_START_Y_MASK 0x1FFF0000L +//FC_WINDOW_SIZE +#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH__SHIFT 0x0 +#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT__SHIFT 0x10 +#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH_MASK 0x00000FFFL +#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT_MASK 0x0FFF0000L +//FC_SOURCE_SIZE +#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH__SHIFT 0x0 +#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT__SHIFT 0x10 +#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH_MASK 0x00007FFFL +#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT_MASK 0x7FFF0000L +//DWB_UPDATE_CTRL +#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK__SHIFT 0x0 +#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING__SHIFT 0x4 +#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK_MASK 0x00000001L +#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING_MASK 0x00000010L +//DWB_CRC_CTRL +#define DWB_CRC_CTRL__DWB_CRC_EN__SHIFT 0x0 +#define DWB_CRC_CTRL__DWB_CRC_CONT_EN__SHIFT 0x4 +#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL__SHIFT 0x8 +#define DWB_CRC_CTRL__DWB_CRC_EN_MASK 0x00000001L +#define DWB_CRC_CTRL__DWB_CRC_CONT_EN_MASK 0x00000010L +#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL_MASK 0x00000300L +//DWB_CRC_MASK_R_G +#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK__SHIFT 0x0 +#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK__SHIFT 0x10 +#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK_MASK 0x0000FFFFL +#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK_MASK 0xFFFF0000L +//DWB_CRC_MASK_B_A +#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK__SHIFT 0x0 +#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK__SHIFT 0x10 +#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK_MASK 0x0000FFFFL +#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK_MASK 0xFFFF0000L +//DWB_CRC_VAL_R_G +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED__SHIFT 0x0 +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN__SHIFT 0x10 +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED_MASK 0x0000FFFFL +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN_MASK 0xFFFF0000L +//DWB_CRC_VAL_B_A +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE__SHIFT 0x0 +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A__SHIFT 0x10 +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE_MASK 0x0000FFFFL +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A_MASK 0xFFFF0000L +//DWB_OUT_CTRL +#define DWB_OUT_CTRL__OUT_FORMAT__SHIFT 0x0 +#define DWB_OUT_CTRL__OUT_DENORM__SHIFT 0x4 +#define DWB_OUT_CTRL__OUT_MAX__SHIFT 0x8 +#define DWB_OUT_CTRL__OUT_MIN__SHIFT 0x14 +#define DWB_OUT_CTRL__OUT_FORMAT_MASK 0x00000003L +#define DWB_OUT_CTRL__OUT_DENORM_MASK 0x00000030L +#define DWB_OUT_CTRL__OUT_MAX_MASK 0x0003FF00L +#define DWB_OUT_CTRL__OUT_MIN_MASK 0x3FF00000L +//DWB_MMHUBBUB_BACKPRESSURE_CNT_EN +#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__SHIFT 0x0 +#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN_MASK 0x00000001L +//DWB_MMHUBBUB_BACKPRESSURE_CNT +#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE__SHIFT 0x0 +#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE_MASK 0x0000FFFFL +//DWB_HOST_READ_CONTROL +#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL_MASK 0x000000FFL +//DWB_OVERFLOW_STATUS +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG__SHIFT 0x0 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK__SHIFT 0x8 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK__SHIFT 0xc +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG_MASK 0x00000001L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK_MASK 0x00000100L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK_MASK 0x00001000L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS_MASK 0x00010000L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE_MASK 0x00100000L +//DWB_OVERFLOW_COUNTER +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE__SHIFT 0x0 +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT__SHIFT 0x4 +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT__SHIFT 0x10 +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE_MASK 0x00000003L +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT_MASK 0x0000FFF0L +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT_MASK 0x0FFF0000L +//DWB_SOFT_RESET +#define DWB_SOFT_RESET__DWB_SOFT_RESET__SHIFT 0x0 +#define DWB_SOFT_RESET__DWB_SOFT_RESET_MASK 0x00000001L + + +// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec +//DWB_HDR_MULT_COEF +#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF__SHIFT 0x0 +#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF_MASK 0x0007FFFFL +//DWB_GAMUT_REMAP_MODE +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE__SHIFT 0x0 +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x18 +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_MASK 0x00000003L +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT_MASK 0x03000000L +//DWB_GAMUT_REMAP_COEF_FORMAT +#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//DWB_GAMUT_REMAPA_C11_C12 +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C13_C14 +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C21_C22 +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C23_C24 +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C31_C32 +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C33_C34 +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C11_C12 +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C13_C14 +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C21_C22 +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C23_C24 +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C31_C32 +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C33_C34 +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34_MASK 0xFFFF0000L +//DWB_OGAM_CONTROL +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE__SHIFT 0x0 +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT__SHIFT 0x4 +#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE__SHIFT 0x8 +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT__SHIFT 0x18 +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT__SHIFT 0x1c +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_MASK 0x00000003L +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_MASK 0x00000010L +#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE_MASK 0x00000100L +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT_MASK 0x03000000L +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT_MASK 0x10000000L +//DWB_OGAM_LUT_INDEX +#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX__SHIFT 0x0 +#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX_MASK 0x000001FFL +//DWB_OGAM_LUT_DATA +#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA__SHIFT 0x0 +#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA_MASK 0x0003FFFFL +//DWB_OGAM_LUT_CONTROL +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x4 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG__SHIFT 0x8 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL__SHIFT 0xc +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE__SHIFT 0x10 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000030L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG_MASK 0x00000100L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL_MASK 0x00001000L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE_MASK 0x00010000L +//DWB_OGAM_RAMA_START_CNTL_B +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//DWB_OGAM_RAMA_START_CNTL_G +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//DWB_OGAM_RAMA_START_CNTL_R +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//DWB_OGAM_RAMA_START_BASE_CNTL_B +#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_SLOPE_CNTL_B +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_BASE_CNTL_G +#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_SLOPE_CNTL_G +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_BASE_CNTL_R +#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_SLOPE_CNTL_R +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL1_B +#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL2_B +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//DWB_OGAM_RAMA_END_CNTL1_G +#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL2_G +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//DWB_OGAM_RAMA_END_CNTL1_R +#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL2_R +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//DWB_OGAM_RAMA_OFFSET_B +#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//DWB_OGAM_RAMA_OFFSET_G +#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//DWB_OGAM_RAMA_OFFSET_R +#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//DWB_OGAM_RAMA_REGION_0_1 +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_2_3 +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_4_5 +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_6_7 +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_8_9 +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_10_11 +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_12_13 +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_14_15 +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_16_17 +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_18_19 +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_20_21 +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_22_23 +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_24_25 +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_26_27 +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_28_29 +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_30_31 +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_32_33 +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_START_CNTL_B +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//DWB_OGAM_RAMB_START_CNTL_G +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//DWB_OGAM_RAMB_START_CNTL_R +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//DWB_OGAM_RAMB_START_BASE_CNTL_B +#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_SLOPE_CNTL_B +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_BASE_CNTL_G +#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_SLOPE_CNTL_G +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_BASE_CNTL_R +#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_SLOPE_CNTL_R +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL1_B +#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL2_B +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//DWB_OGAM_RAMB_END_CNTL1_G +#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL2_G +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//DWB_OGAM_RAMB_END_CNTL1_R +#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL2_R +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//DWB_OGAM_RAMB_OFFSET_B +#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//DWB_OGAM_RAMB_OFFSET_G +#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//DWB_OGAM_RAMB_OFFSET_R +#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//DWB_OGAM_RAMB_REGION_0_1 +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_2_3 +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_4_5 +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_6_7 +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_8_9 +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_10_11 +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_12_13 +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_14_15 +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_16_17 +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_18_19 +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_20_21 +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_22_23 +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_24_25 +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_26_27 +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_28_29 +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_30_31 +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_32_33 +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec +//VGA_MEM_WRITE_PAGE_ADDR +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L +//VGA_MEM_READ_PAGE_ADDR +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L +//VGA_RENDER_CONTROL +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0 +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5 +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7 +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8 +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10 +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18 +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19 +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001FL +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x02000000L +//VGA_SEQUENCER_RESET_CONTROL +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0 +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1 +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2 +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3 +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4 +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5 +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8 +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9 +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12 +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00FC0000L +//VGA_MODE_CONTROL +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0 +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4 +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8 +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10 +#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT 0x18 +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L +#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK 0x01000000L +//VGA_SURFACE_PITCH_SELECT +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L +//VGA_MEMORY_BASE_ADDRESS +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0 +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xFFFFFFFFL +//VGA_DISPBUF1_SURFACE_ADDR +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0 +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01FFFFFFL +//VGA_DISPBUF2_SURFACE_ADDR +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0 +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01FFFFFFL +//VGA_MEMORY_BASE_ADDRESS_HIGH +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0 +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x0000FFFFL +//VGA_HDP_CONTROL +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0 +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4 +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8 +#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10 +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18 +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L +#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L +//VGA_CACHE_CONTROL +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0 +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8 +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10 +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14 +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18 +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3F000000L +//D1VGA_CONTROL +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0 +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8 +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18 +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L +//D2VGA_CONTROL +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0 +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8 +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18 +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L +//VGA_STATUS +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0 +#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1 +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2 +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3 +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L +#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L +//VGA_INTERRUPT_CONTROL +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0 +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8 +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10 +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18 +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L +//VGA_STATUS_CLEAR +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0 +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8 +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10 +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18 +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L +//VGA_INTERRUPT_STATUS +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0 +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1 +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2 +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3 +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L +//VGA_MAIN_CONTROL +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0 +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3 +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5 +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8 +#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10 +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18 +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000E0L +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L +#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0x0000F000L +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L +//VGA_TEST_CONTROL +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18 +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L +//VGA_QOS_CTRL +#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT 0x0 +#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT 0x4 +#define VGA_QOS_CTRL__VGA_READ_QOS_MASK 0x0000000FL +#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK 0x000000F0L +//CRTC8_IDX +#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0 +#define CRTC8_IDX__VCRTC_IDX_MASK 0x3FL +//CRTC8_DATA +#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0 +#define CRTC8_DATA__VCRTC_DATA_MASK 0xFFL +//GENFC_WT +#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 +#define GENFC_WT__VSYNC_SEL_W_MASK 0x08L +//GENS1 +#define GENS1__NO_DISPLAY__SHIFT 0x0 +#define GENS1__VGA_VSTATUS__SHIFT 0x3 +#define GENS1__PIXEL_READ_BACK__SHIFT 0x4 +#define GENS1__NO_DISPLAY_MASK 0x01L +#define GENS1__VGA_VSTATUS_MASK 0x08L +#define GENS1__PIXEL_READ_BACK_MASK 0x30L +//ATTRDW +#define ATTRDW__ATTR_DATA__SHIFT 0x0 +#define ATTRDW__ATTR_DATA_MASK 0xFFL +//ATTRX +#define ATTRX__ATTR_IDX__SHIFT 0x0 +#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5 +#define ATTRX__ATTR_IDX_MASK 0x1FL +#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20L +//ATTRDR +#define ATTRDR__ATTR_DATA__SHIFT 0x0 +#define ATTRDR__ATTR_DATA_MASK 0xFFL +//GENMO_WT +#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0 +#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1 +#define GENMO_WT__VGA_CKSEL__SHIFT 0x2 +#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5 +#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6 +#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7 +#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x01L +#define GENMO_WT__VGA_RAM_EN_MASK 0x02L +#define GENMO_WT__VGA_CKSEL_MASK 0x0CL +#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20L +#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40L +#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80L +//GENS0 +#define GENS0__SENSE_SWITCH__SHIFT 0x4 +#define GENS0__CRT_INTR__SHIFT 0x7 +#define GENS0__SENSE_SWITCH_MASK 0x10L +#define GENS0__CRT_INTR_MASK 0x80L +//GENENB +#define GENENB__BLK_IO_BASE__SHIFT 0x0 +#define GENENB__BLK_IO_BASE_MASK 0xFFL +//SEQ8_IDX +#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0 +#define SEQ8_IDX__SEQ_IDX_MASK 0x07L +//SEQ8_DATA +#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0 +#define SEQ8_DATA__SEQ_DATA_MASK 0xFFL +//DAC_MASK +#define DAC_MASK__DAC_MASK__SHIFT 0x0 +#define DAC_MASK__DAC_MASK_MASK 0xFFL +//DAC_R_INDEX +#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0 +#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xFFL +//DAC_W_INDEX +#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0 +#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xFFL +//DAC_DATA +#define DAC_DATA__DAC_DATA__SHIFT 0x0 +#define DAC_DATA__DAC_DATA_MASK 0x3FL +//GENFC_RD +#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3 +#define GENFC_RD__VSYNC_SEL_R_MASK 0x08L +//GENMO_RD +#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0 +#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1 +#define GENMO_RD__VGA_CKSEL__SHIFT 0x2 +#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5 +#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 +#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7 +#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x01L +#define GENMO_RD__VGA_RAM_EN_MASK 0x02L +#define GENMO_RD__VGA_CKSEL_MASK 0x0CL +#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20L +#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40L +#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80L +//GRPH8_IDX +#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0 +#define GRPH8_IDX__GRPH_IDX_MASK 0x0FL +//GRPH8_DATA +#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0 +#define GRPH8_DATA__GRPH_DATA_MASK 0xFFL +//CRTC8_IDX_1 +#define CRTC8_IDX_1__VCRTC_IDX__SHIFT 0x0 +#define CRTC8_IDX_1__VCRTC_IDX_MASK 0x3FL +//CRTC8_DATA_1 +#define CRTC8_DATA_1__VCRTC_DATA__SHIFT 0x0 +#define CRTC8_DATA_1__VCRTC_DATA_MASK 0xFFL +//GENFC_WT_1 +#define GENFC_WT_1__VSYNC_SEL_W__SHIFT 0x3 +#define GENFC_WT_1__VSYNC_SEL_W_MASK 0x08L +//GENS1_1 +#define GENS1_1__NO_DISPLAY__SHIFT 0x0 +#define GENS1_1__VGA_VSTATUS__SHIFT 0x3 +#define GENS1_1__PIXEL_READ_BACK__SHIFT 0x4 +#define GENS1_1__NO_DISPLAY_MASK 0x01L +#define GENS1_1__VGA_VSTATUS_MASK 0x08L +#define GENS1_1__PIXEL_READ_BACK_MASK 0x30L +//D3VGA_CONTROL +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0 +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18 +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L +//D4VGA_CONTROL +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0 +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8 +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18 +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L +//D5VGA_CONTROL +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0 +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8 +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18 +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L +//D6VGA_CONTROL +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0 +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8 +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18 +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L +//VGA_SOURCE_SELECT +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L + + +// addressBlock: dce_dc_mmhubbub_vgaif_dispdec +//MCIF_CONTROL +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L +//MCIF_WRITE_COMBINE_CONTROL +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0 +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000003FFL +//MCIF_PHASE0_OUTSTANDING_COUNTER +#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 +#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//MCIF_PHASE1_OUTSTANDING_COUNTER +#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 +#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//MCIF_PHASE2_OUTSTANDING_COUNTER +#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT 0x0 +#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL + + +// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec +//MCIF_WB_BUFMGR_SW_CONTROL +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L +//MCIF_WB_BUFMGR_STATUS +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L +//MCIF_WB_BUF_PITCH +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L +//MCIF_WB_BUF_1_STATUS +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_1_STATUS2 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK 0x00010000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK 0x00080000L +//MCIF_WB_BUF_2_STATUS +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_2_STATUS2 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK 0x00010000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK 0x00080000L +//MCIF_WB_BUF_3_STATUS +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_3_STATUS2 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK 0x00010000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK 0x00080000L +//MCIF_WB_BUF_4_STATUS +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_4_STATUS2 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK 0x00010000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK 0x00080000L +//MCIF_WB_ARBITRATION_CONTROL +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x14 +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFF00000L +//MCIF_WB_SCLK_CHANGE +#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0 +#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L +//MCIF_WB_TEST_DEBUG_INDEX +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//MCIF_WB_TEST_DEBUG_DATA +#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0 +#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_1_ADDR_Y +#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_1_ADDR_C +#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_2_ADDR_Y +#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_2_ADDR_C +#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_3_ADDR_Y +#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_3_ADDR_C +#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_4_ADDR_Y +#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_4_ADDR_C +#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUFMGR_VCE_CONTROL +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L +//MCIF_WB_NB_PSTATE_CONTROL +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1 +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L +//MCIF_WB_CLOCK_GATER_CONTROL +#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0 +#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L +//MCIF_WB_SELF_REFRESH_CONTROL +#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1 +#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L +//MULTI_LEVEL_QOS_CTRL +#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0 +#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL +//MCIF_WB_SECURITY_LEVEL +#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL__SHIFT 0x0 +#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE__SHIFT 0x4 +#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL_MASK 0x00000007L +#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE_MASK 0x00000070L +//MCIF_WB_BUF_LUMA_SIZE +#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0 +#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB_BUF_CHROMA_SIZE +#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0 +#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB_BUF_1_ADDR_Y_HIGH +#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_1_ADDR_C_HIGH +#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_2_ADDR_Y_HIGH +#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_2_ADDR_C_HIGH +#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_3_ADDR_Y_HIGH +#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_3_ADDR_C_HIGH +#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_4_ADDR_Y_HIGH +#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_4_ADDR_C_HIGH +#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_1_RESOLUTION +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_BUF_2_RESOLUTION +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_BUF_3_RESOLUTION +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_BUF_4_RESOLUTION +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_PSTATE_CHANGE_DURATION_VBI +#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT 0x0 +#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT 0x10 +#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI_MASK 0x0000FFFFL +#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI_MASK 0xFFFF0000L +//MCIF_WB_VMID_CONTROL +#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID__SHIFT 0x0 +#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID_MASK 0x0000000FL +//MCIF_WB_MIN_TTO +#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO__SHIFT 0x0 +#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO_MASK 0x0007FFFFL + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec +//MCIF_WB_NB_PSTATE_LATENCY_WATERMARK +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0 +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x18 +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE__SHIFT 0x1f +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x001FFFFFL +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x07000000L +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE_MASK 0x80000000L +//MCIF_WB_WATERMARK +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0 +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x18 +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x001FFFFFL +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x07000000L +//MMHUBBUB_WARMUP_CONFIG +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS__SHIFT 0x10 +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID__SHIFT 0x14 +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS_MASK 0x000F0000L +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID_MASK 0x00F00000L +//MMHUBBUB_WARMUP_CONTROL_STATUS +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN__SHIFT 0x0 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN__SHIFT 0x4 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS__SHIFT 0x5 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK__SHIFT 0x6 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR__SHIFT 0x8 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN_MASK 0x00000001L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN_MASK 0x00000010L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS_MASK 0x00000020L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK_MASK 0x00000040L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR_MASK 0x03FFFF00L +//MMHUBBUB_WARMUP_BASE_ADDR_LOW +#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW__SHIFT 0x0 +#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW_MASK 0xFFFFFFFFL +//MMHUBBUB_WARMUP_BASE_ADDR_HIGH +#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH__SHIFT 0x0 +#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH_MASK 0x000007FFL +//MMHUBBUB_WARMUP_ADDR_REGION +#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION__SHIFT 0x0 +#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION_MASK 0x07FFFFFFL +//MMHUBBUB_MIN_TTO +#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO__SHIFT 0x0 +#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO_MASK 0x0007FFFFL +//MMHUBBUB_CTRL +#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE__SHIFT 0x0 +#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE_MASK 0x00000003L +//WBIF_SMU_WM_CONTROL +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL__SHIFT 0x14 +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ__SHIFT 0x16 +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL_MASK 0x00300000L +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ_MASK 0x00400000L +//WBIF0_MISC_CTRL +#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT 0x0 +#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT 0x10 +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT 0x18 +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT 0x19 +#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK 0x000003FFL +#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK 0x00010000L +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK 0x01000000L +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK 0x02000000L +//WBIF0_PHASE0_OUTSTANDING_COUNTER +#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 +#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//WBIF0_PHASE1_OUTSTANDING_COUNTER +#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 +#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//VGA_SRC_SPLIT_CNTL +#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT 0x0 +#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK 0x00000003L +//MMHUBBUB_MEM_PWR_STATUS +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT 0x0 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT 0x2 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT 0x4 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT 0x6 +#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x1f +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK 0x00000003L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK 0x0000000CL +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK 0x00000030L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK 0x000000C0L +#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x80000000L +//MMHUBBUB_MEM_PWR_CNTL +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x0 +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x1 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT 0x2 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT 0x4 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT 0x5 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT 0x7 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT 0x8 +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x00000001L +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x00000002L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK 0x0000000CL +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK 0x00000010L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK 0x00000060L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK 0x00000080L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK 0x00000100L +//MMHUBBUB_CLOCK_CNTL +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT 0x0 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT 0x5 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS__SHIFT 0x6 +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS__SHIFT 0x7 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0x8 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT 0x9 +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT 0xa +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS__SHIFT 0x11 +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK 0x00000020L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS_MASK 0x00000040L +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS_MASK 0x00000080L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000100L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK 0x00000200L +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK 0x00000400L +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS_MASK 0x00020000L +//MMHUBBUB_SOFT_RESET +#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0 +#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET__SHIFT 0x1 +#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT 0x2 +#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT 0x8 +#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L +#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET_MASK 0x00000002L +#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK 0x00000004L +#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK 0x00000100L +//DMU_IF_ERR_STATUS +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT 0x0 +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT 0x4 +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK 0x00000001L +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK 0x00000010L +//MMHUBBUB_CLIENT_UNIT_ID +#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID__SHIFT 0x0 +#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT 0x8 +#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID_MASK 0x0000003FL +#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK 0x00003F00L +//MMHUBBUB_WARMUP_VMID_CONTROL +#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID__SHIFT 0x0 +#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID_MASK 0x0000000FL + + +// addressBlock: dce_dc_hda_azf0controller_dispdec +//AZALIA_CONTROLLER_CLOCK_GATING +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0 +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x00000001L +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x00000010L +//AZALIA_AUDIO_DTO +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000FFFFL +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xFFFF0000L +//AZALIA_AUDIO_DTO_CONTROL +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L +//AZALIA_SOCCLK_CONTROL +#define AZALIA_SOCCLK_CONTROL__DRM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT 0x0 +#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT 0x1 +#define AZALIA_SOCCLK_CONTROL__DRM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK 0x00000001L +#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK 0x00000002L +//AZALIA_UNDERFLOW_FILLER_SAMPLE +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0 +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xFFFFFFFFL +//AZALIA_DATA_DMA_CONTROL +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0x0000000CL +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0x000000C0L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L +//AZALIA_BDL_DMA_CONTROL +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0x0000000CL +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0x000000C0L +//AZALIA_RIRB_AND_DP_CONTROL +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x000001E0L +//AZALIA_CORB_DMA_CONTROL +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L +//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0 +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xFFFFFFFFL +//AZALIA_CYCLIC_BUFFER_SYNC +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0 +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L +//AZALIA_GLOBAL_CAPABILITIES +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L +//AZALIA_OUTPUT_PAYLOAD_CAPABILITY +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFF0000L +//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000FFL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0x00FF0000L +//AZALIA_INPUT_PAYLOAD_CAPABILITY +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFF0000L +//AZALIA_INPUT_CRC0_CONTROL0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC0_CONTROL1 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CONTROL2 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_INPUT_CRC0_CONTROL3 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC0_RESULT +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CONTROL0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC1_CONTROL1 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CONTROL2 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_INPUT_CRC1_CONTROL3 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC1_RESULT +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CONTROL0 +#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x00000001L +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L +//AZALIA_CRC0_CONTROL1 +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CONTROL2 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_CRC0_CONTROL3 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_CRC0_RESULT +#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CONTROL0 +#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x00000001L +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L +//AZALIA_CRC1_CONTROL1 +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CONTROL2 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_CRC1_CONTROL3 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_CRC1_RESULT +#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_MEM_PWR_CTRL +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x00000003L +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x00000004L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x00000018L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x00000020L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0x000000C0L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x00000100L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x00000600L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x00000800L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x00003000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x00004000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x00018000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x00020000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0x000C0000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x00100000L +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000L +//AZALIA_MEM_PWR_STATUS +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x00000003L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0x0000000CL +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x00000030L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0x000000C0L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x00000300L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0x00000C00L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hda_azf0root_dispdec +//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L +//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0 +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003FL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL +//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//AZALIA_F0_GTC_GROUP_OFFSET0 +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET1 +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET2 +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET3 +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET4 +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET5 +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET6 +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xFFFFFFFFL +//REG_DC_AUDIO_PORT_CONNECTIVITY +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT 0x0 +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK 0x00000007L +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK 0x00000007L +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L + + +// addressBlock: dce_dc_hda_az_misc_dispdec +//AZ_CLOCK_CNTL +#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x0 +#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8 +#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x10 +#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT 0x18 +#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x00000001L +#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000100L +#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x00010000L +#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK 0x1F000000L + + +// addressBlock: dce_dc_hda_azf0stream0_dispdec +//AZF0STREAM0_AZALIA_STREAM_INDEX +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM0_AZALIA_STREAM_DATA +#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream1_dispdec +//AZF0STREAM1_AZALIA_STREAM_INDEX +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM1_AZALIA_STREAM_DATA +#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream2_dispdec +//AZF0STREAM2_AZALIA_STREAM_INDEX +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM2_AZALIA_STREAM_DATA +#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream3_dispdec +//AZF0STREAM3_AZALIA_STREAM_INDEX +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM3_AZALIA_STREAM_DATA +#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream4_dispdec +//AZF0STREAM4_AZALIA_STREAM_INDEX +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM4_AZALIA_STREAM_DATA +#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream5_dispdec +//AZF0STREAM5_AZALIA_STREAM_INDEX +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM5_AZALIA_STREAM_DATA +#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream6_dispdec +//AZF0STREAM6_AZALIA_STREAM_INDEX +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM6_AZALIA_STREAM_DATA +#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream7_dispdec +//AZF0STREAM7_AZALIA_STREAM_INDEX +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM7_AZALIA_STREAM_DATA +#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream8_dispdec +//AZF0STREAM8_AZALIA_STREAM_INDEX +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM8_AZALIA_STREAM_DATA +#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream9_dispdec +//AZF0STREAM9_AZALIA_STREAM_INDEX +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM9_AZALIA_STREAM_DATA +#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream10_dispdec +//AZF0STREAM10_AZALIA_STREAM_INDEX +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM10_AZALIA_STREAM_DATA +#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream11_dispdec +//AZF0STREAM11_AZALIA_STREAM_INDEX +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM11_AZALIA_STREAM_DATA +#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream12_dispdec +//AZF0STREAM12_AZALIA_STREAM_INDEX +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM12_AZALIA_STREAM_DATA +#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream13_dispdec +//AZF0STREAM13_AZALIA_STREAM_INDEX +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM13_AZALIA_STREAM_DATA +#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream14_dispdec +//AZF0STREAM14_AZALIA_STREAM_INDEX +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM14_AZALIA_STREAM_DATA +#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream15_dispdec +//AZF0STREAM15_AZALIA_STREAM_INDEX +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM15_AZALIA_STREAM_DATA +#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint0_dispdec +//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint1_dispdec +//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint2_dispdec +//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint3_dispdec +//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint4_dispdec +//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint5_dispdec +//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint6_dispdec +//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint7_dispdec +//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchubbubl_hubbub_dispdec +//DCHUBBUB_ARB_DF_REQ_OUTSTAND +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT 0x0 +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT 0xa +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK 0x000003FFL +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK 0x000FFC00L +//DCHUBBUB_ARB_SAT_LEVEL +#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT 0x0 +#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK 0xFFFFFFFFL +//DCHUBBUB_ARB_QOS_FORCE +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT 0x0 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT 0x8 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST__SHIFT 0x9 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK 0x0000000FL +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK 0x00000100L +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST_MASK 0x00000200L +//DCHUBBUB_ARB_DRAM_STATE_CNTL +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT 0x0 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT 0x1 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST__SHIFT 0x2 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT 0x4 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT 0x5 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE__SHIFT 0x7 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE__SHIFT 0xc +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK 0x00000001L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK 0x00000002L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST_MASK 0x00000004L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK 0x00000010L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK 0x00000020L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE_MASK 0x00000080L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE_MASK 0x00001000L +//DCHUBBUB_ARB_USR_RETRAINING_CNTL +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING__SHIFT 0x1 +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE__SHIFT 0x8 +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE__SHIFT 0x9 +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST__SHIFT 0xa +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE__SHIFT 0xb +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST_MASK 0x00000001L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING_MASK 0x00000002L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE_MASK 0x00000100L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE_MASK 0x00000200L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST_MASK 0x00000400L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE_MASK 0x00000800L +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK 0x00003FFFL +//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK 0x000003FFL +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK 0x00003FFFL +//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK 0x000003FFL +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK 0x00003FFFL +//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_C +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK 0x000003FFL +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK 0x00003FFFL +//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_D +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK 0x000003FFL +//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT 0x0 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT 0x4 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT 0x5 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT 0x8 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE__SHIFT 0x18 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK 0x00000003L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK 0x00000010L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK 0x00000020L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK 0x00000100L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE_MASK 0x01000000L +//DCHUBBUB_ARB_MALL_CNTL +#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS__SHIFT 0x0 +#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE__SHIFT 0x4 +#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS_MASK 0x00000001L +#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE_MASK 0x00000010L +#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +//DCHUBBUB_ARB_TIMEOUT_ENABLE +#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT 0x0 +#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK 0x00000001L +//DCHUBBUB_GLOBAL_TIMER_CNTL +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT 0x0 +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT 0xc +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT 0x10 +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK 0x0000000FL +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK 0x00001000L +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK 0xFFFF0000L +//SURFACE_CHECK0_ADDRESS_LSB +#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK0_ADDRESS_MSB +#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK1_ADDRESS_LSB +#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK1_ADDRESS_MSB +#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK2_ADDRESS_LSB +#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK2_ADDRESS_MSB +#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK3_ADDRESS_LSB +#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK3_ADDRESS_MSB +#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK 0x80000000L +//VTG0_CONTROL +#define VTG0_CONTROL__VTG0_FP2__SHIFT 0x0 +#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT 0x10 +#define VTG0_CONTROL__VTG0_ENABLE__SHIFT 0x1f +#define VTG0_CONTROL__VTG0_FP2_MASK 0x00007FFFL +#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG0_CONTROL__VTG0_ENABLE_MASK 0x80000000L +//VTG1_CONTROL +#define VTG1_CONTROL__VTG1_FP2__SHIFT 0x0 +#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT 0x10 +#define VTG1_CONTROL__VTG1_ENABLE__SHIFT 0x1f +#define VTG1_CONTROL__VTG1_FP2_MASK 0x00007FFFL +#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG1_CONTROL__VTG1_ENABLE_MASK 0x80000000L +//VTG2_CONTROL +#define VTG2_CONTROL__VTG2_FP2__SHIFT 0x0 +#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT 0x10 +#define VTG2_CONTROL__VTG2_ENABLE__SHIFT 0x1f +#define VTG2_CONTROL__VTG2_FP2_MASK 0x00007FFFL +#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG2_CONTROL__VTG2_ENABLE_MASK 0x80000000L +//VTG3_CONTROL +#define VTG3_CONTROL__VTG3_FP2__SHIFT 0x0 +#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10 +#define VTG3_CONTROL__VTG3_ENABLE__SHIFT 0x1f +#define VTG3_CONTROL__VTG3_FP2_MASK 0x00007FFFL +#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG3_CONTROL__VTG3_ENABLE_MASK 0x80000000L +//DCHUBBUB_SOFT_RESET +#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT 0x0 +#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT 0x1 +#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT 0x4 +#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK 0x00000001L +#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK 0x00000002L +#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK 0x00000010L +//DCHUBBUB_CLOCK_CNTL +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT 0x0 +#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x5 +#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x6 +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS__SHIFT 0x7 +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL +#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000020L +#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000040L +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS_MASK 0x00000080L +//DCFCLK_CNTL +#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT 0x1f +#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK 0x80000000L +//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT 0x0 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN__SHIFT 0x1 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL__SHIFT 0x2 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT 0x3 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT 0x7 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT 0xa +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT 0xb +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK 0x00000001L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN_MASK 0x00000002L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL_MASK 0x00000004L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK 0x00000078L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK 0x00000380L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK 0x00000400L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK 0x007FF800L +//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT 0x0 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT 0x1 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT 0x4 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT 0xc +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT 0x13 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT 0x1f +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK 0x00000001L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK 0x0000000EL +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK 0x00000FF0L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK 0x00007000L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK 0x7FF80000L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK 0x80000000L +//DCHUBBUB_VLINE_SNAPSHOT +#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT 0x0 +#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK 0x00000001L +//DCHUBBUB_CTRL_STATUS +#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT 0x0 +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS__SHIFT 0x2 +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR__SHIFT 0x3 +#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE__SHIFT 0x1f +#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK 0x00000001L +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS_MASK 0x00000004L +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR_MASK 0x00000008L +#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE_MASK 0x80000000L +//DCHUBBUB_TIMEOUT_DETECTION_CTRL1 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT 0x6 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK 0x0000003FL +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK 0xFFFFFFC0L +//DCHUBBUB_TIMEOUT_DETECTION_CTRL2 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT 0x1b +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT 0x1c +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK 0x07FFFFFFL +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK 0x08000000L +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK 0x10000000L +//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT 0x1 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT 0x2 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT 0x3 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK 0x00000001L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK 0x00000002L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK 0x00000004L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK 0x000000F8L +//FMON_CTRL +#define FMON_CTRL__FMON_START__SHIFT 0x0 +#define FMON_CTRL__FMON_MODE__SHIFT 0x1 +#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT 0x4 +#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT 0x5 +#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT 0x6 +#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT 0x7 +#define FMON_CTRL__FMON_STATE__SHIFT 0x9 +#define FMON_CTRL__FMON_URG_FILTER__SHIFT 0xc +#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT 0xd +#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT 0x11 +#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT 0x16 +#define FMON_CTRL__FMON_SOF_SEL__SHIFT 0x1b +#define FMON_CTRL__FMON_START_MASK 0x00000001L +#define FMON_CTRL__FMON_MODE_MASK 0x00000006L +#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK 0x00000010L +#define FMON_CTRL__FMON_STATUS_IGNORE_MASK 0x00000020L +#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK 0x00000040L +#define FMON_CTRL__FMON_FILTER_UID_EN_MASK 0x00000180L +#define FMON_CTRL__FMON_STATE_MASK 0x00000600L +#define FMON_CTRL__FMON_URG_FILTER_MASK 0x00001000L +#define FMON_CTRL__FMON_URG_THRESHOLD_MASK 0x0001E000L +#define FMON_CTRL__FMON_FILTER_UID_1_MASK 0x003E0000L +#define FMON_CTRL__FMON_FILTER_UID_2_MASK 0x07C00000L +#define FMON_CTRL__FMON_SOF_SEL_MASK 0x38000000L + + +// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec +//DCHUBBUB_SDPIF_CFG0 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT 0x1 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT 0x3 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT 0x6 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT 0xa +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT 0xb +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT 0xc +#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT 0xd +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT 0xe +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT 0xf +#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT 0x19 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK 0x00000006L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK 0x00000038L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK 0x000003C0L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK 0x00000400L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK 0x00000800L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK 0x00001000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK 0x00002000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK 0x00004000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK 0x00008000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK 0x7E000000L +//DCHUBBUB_SDPIF_CFG1 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT 0x1 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT 0x2 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT 0x8 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING__SHIFT 0x9 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK 0x00000002L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK 0x00000004L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK 0x00000100L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING_MASK 0x00000200L +//DCHUBBUB_SDPIF_CFG2 +#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL__SHIFT 0x8 +#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT 0x10 +#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL_MASK 0x00000700L +#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK 0x01FF0000L +//VM_REQUEST_PHYSICAL +#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT 0x0 +#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT 0x3 +#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK 0x00000001L +#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK 0x00000008L +//DCHUBBUB_FORCE_IO_STATUS_0 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT 0x0 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT 0x1 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT 0x2 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT 0x3 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT 0x7 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT 0xa +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK 0x00000001L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK 0x00000002L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK 0x00000004L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK 0x00000078L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK 0x00000380L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK 0xFFFFFC00L +//DCHUBBUB_FORCE_IO_STATUS_1 +#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT 0x0 +#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK 0x001FFFFFL +//DCN_VM_FB_LOCATION_BASE +#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//DCN_VM_FB_LOCATION_TOP +#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//DCN_VM_FB_OFFSET +#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//DCN_VM_AGP_BOT +#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define DCN_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//DCN_VM_AGP_TOP +#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define DCN_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//DCN_VM_AGP_BASE +#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define DCN_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_START +#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK 0x000FFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_END +#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK 0x000FFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL +#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L +//DCHUBBUB_SDPIF_PIPE_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL__SHIFT 0x6 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL__SHIFT 0x9 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK 0x00000007L +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK 0x00000038L +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL_MASK 0x000001C0L +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL_MASK 0x00000E00L +//DCHUBBUB_SDPIF_PIPE_NOALLOC +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC__SHIFT 0x1 +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC__SHIFT 0x2 +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC_MASK 0x00000001L +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC_MASK 0x00000002L +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC_MASK 0x00000004L +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC_MASK 0x00000008L +//DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL__SHIFT 0x6 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL__SHIFT 0x9 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL_MASK 0x00000007L +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL_MASK 0x00000038L +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL_MASK 0x000001C0L +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL_MASK 0x00000E00L +//DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE2_DCCMETA_SEC_LVL__SHIFT 0x6 +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE3_DCCMETA_SEC_LVL__SHIFT 0x9 +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL_MASK 0x00000007L +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL_MASK 0x00000038L +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE2_DCCMETA_SEC_LVL_MASK 0x000001C0L +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE3_DCCMETA_SEC_LVL_MASK 0x00000E00L +//DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL__SHIFT 0x6 +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL__SHIFT 0x9 +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL_MASK 0x00000007L +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL_MASK 0x00000038L +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL_MASK 0x000001C0L +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL_MASK 0x00000E00L +//DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL__SHIFT 0x6 +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL__SHIFT 0x9 +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL_MASK 0x00000007L +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL_MASK 0x00000038L +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL_MASK 0x000001C0L +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL_MASK 0x00000E00L +//SDPIF_REQUEST_RATE_LIMIT +#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT__SHIFT 0x0 +#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT_MASK 0x00000FFFL +//DCHUBBUB_SDPIF_MEM_PWR_CTRL +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT 0x2 +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK 0x00000003L +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK 0x00000004L +//DCHUBBUB_SDPIF_MEM_PWR_STATUS +#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK 0x00000003L + + +// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec +//DCHUBBUB_RET_PATH_MEM_PWR_CTRL +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT 0x2 +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK 0x00000003L +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK 0x00000004L +//DCHUBBUB_RET_PATH_MEM_PWR_STATUS +#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK 0x00000003L +//DCHUBBUB_CRC_CTRL +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT 0x0 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT 0x1 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT 0x2 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT 0x3 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT 0x4 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT 0x6 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT 0x8 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT 0xc +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT 0x14 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK 0x00000001L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK 0x00000002L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK 0x00000004L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK 0x00000008L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK 0x00000030L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK 0x000000C0L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK 0x00000F00L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK 0x00001000L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK 0x00100000L +//DCHUBBUB_CRC0_VAL_R_G +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT 0x10 +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK 0x0000FFFFL +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK 0xFFFF0000L +//DCHUBBUB_CRC0_VAL_B_A +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT 0x10 +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK 0x0000FFFFL +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK 0xFFFF0000L +//DCHUBBUB_CRC1_VAL_R_G +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT 0x10 +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK 0x0000FFFFL +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK 0xFFFF0000L +//DCHUBBUB_CRC1_VAL_B_A +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT 0x10 +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK 0x0000FFFFL +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK 0xFFFF0000L +//DCHUBBUB_DCC_STAT_CNTL +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN__SHIFT 0x1 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE__SHIFT 0x2 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL__SHIFT 0x4 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT__SHIFT 0x10 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE_MASK 0x00000001L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN_MASK 0x00000002L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE_MASK 0x00000004L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL_MASK 0x000000F0L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT_MASK 0xFFFF0000L +//DCHUBBUB_DCC_STAT0 +#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ_MASK 0xFFFFFFFFL +//DCHUBBUB_DCC_STAT1 +#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ_MASK 0xFFFFFFFFL +//DCHUBBUB_DCC_STAT2 +#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ_MASK 0xFFFFFFFFL +//DCHUBBUB_COMPBUF_CTRL +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE__SHIFT 0x0 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE__SHIFT 0x10 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS__SHIFT 0x12 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR__SHIFT 0x13 +#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR__SHIFT 0x1f +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_MASK 0x0000001FL +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT_MASK 0x00001F00L +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE_MASK 0x00010000L +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS_MASK 0x00040000L +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR_MASK 0x00080000L +#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR_MASK 0x80000000L +//DCHUBBUB_DET0_CTRL +#define DCHUBBUB_DET0_CTRL__DET0_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET0_CTRL__DET0_SIZE_MASK 0x0000001FL +#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT_MASK 0x00001F00L +//DCHUBBUB_DET1_CTRL +#define DCHUBBUB_DET1_CTRL__DET1_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET1_CTRL__DET1_SIZE_MASK 0x0000001FL +#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT_MASK 0x00001F00L +//DCHUBBUB_DET2_CTRL +#define DCHUBBUB_DET2_CTRL__DET2_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET2_CTRL__DET2_SIZE_MASK 0x0000001FL +#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT_MASK 0x00001F00L +//DCHUBBUB_DET3_CTRL +#define DCHUBBUB_DET3_CTRL__DET3_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET3_CTRL__DET3_SIZE_MASK 0x0000001FL +#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT_MASK 0x00001F00L +//DCHUBBUB_MEM_PWR_MODE_CTRL +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE__SHIFT 0x0 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE__SHIFT 0x2 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE__SHIFT 0x4 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE__SHIFT 0x6 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE__SHIFT 0x8 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE__SHIFT 0xa +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x10 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE__SHIFT 0x12 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x14 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS__SHIFT 0x18 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS__SHIFT 0x19 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS__SHIFT 0x1a +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE_MASK 0x00000003L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE_MASK 0x0000000CL +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE_MASK 0x00000030L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE_MASK 0x000000C0L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE_MASK 0x00000300L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE_MASK 0x00000C00L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE_MASK 0x00030000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE_MASK 0x000C0000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00300000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS_MASK 0x01000000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS_MASK 0x02000000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS_MASK 0x04000000L +//COMPBUF_MEM_PWR_CTRL_1 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY__SHIFT 0x0 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY__SHIFT 0x8 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY__SHIFT 0x10 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY__SHIFT 0x18 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY_MASK 0x000000FFL +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY_MASK 0x0000FF00L +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY_MASK 0x00FF0000L +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY_MASK 0xFF000000L +//COMPBUF_MEM_PWR_CTRL_2 +#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY__SHIFT 0x0 +#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY_MASK 0x000000FFL +//DCHUBBUB_MEM_PWR_STATUS +#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE__SHIFT 0x2 +#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE__SHIFT 0x4 +#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE__SHIFT 0x6 +#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE__SHIFT 0x8 +#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE__SHIFT 0xa +#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE__SHIFT 0xc +#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE__SHIFT 0xe +#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE_MASK 0x00000003L +#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE_MASK 0x0000000CL +#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE_MASK 0x00000030L +#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE_MASK 0x000000C0L +#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE_MASK 0x00000300L +#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE_MASK 0x00000C00L +#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE_MASK 0x00003000L +#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE_MASK 0x0000C000L +//COMPBUF_RESERVED_SPACE +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B__SHIFT 0x0 +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS__SHIFT 0x10 +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK 0x00000FFFL +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS_MASK 0x0FFF0000L + + +// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec +//DCN_VM_CONTEXT0_CNTL +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_CNTL +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_CNTL +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_CNTL +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_CNTL +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_CNTL +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_CNTL +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_CNTL +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_CNTL +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_CNTL +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_CNTL +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_CNTL +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_CNTL +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_CNTL +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_CNTL +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_CNTL +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_DEFAULT_ADDR_MSB +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT 0x0 +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT 0x1c +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT 0x1d +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK 0x0000000FL +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK 0x10000000L +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK 0x20000000L +//DCN_VM_DEFAULT_ADDR_LSB +#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT 0x0 +#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//DCN_VM_FAULT_CNTL +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT 0x0 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT 0x1 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT 0x2 +#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT 0x8 +#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT 0x9 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK 0x00000001L +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK 0x00000002L +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK 0x00000004L +#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK 0x00000100L +#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK 0x00000200L +//DCN_VM_FAULT_STATUS +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT 0x0 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT 0x10 +#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID__SHIFT 0x14 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT 0x18 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT 0x1a +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT 0x1f +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK 0x0000FFFFL +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK 0x000F0000L +#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID_MASK 0x00F00000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK 0x03000000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK 0x3C000000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK 0x80000000L +//DCN_VM_FAULT_ADDR_MSB +#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT 0x0 +#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK 0x0000000FL +//DCN_VM_FAULT_ADDR_LSB +#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT 0x0 +#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec +//HUBP0_DCSURF_SURFACE_CONFIG +#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP0_DCSURF_ADDR_CONFIG +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP0_DCSURF_TILING_CONFIG +#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP0_DCSURF_PRI_VIEWPORT_START +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_START_C +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_START +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_START_C +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP0_DCHUBP_REQ_SIZE_CONFIG +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP0_DCHUBP_CNTL +#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP0_HUBP_CLK_CNTL +#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT 0x18 +#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK 0x01000000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP0_DCHUBP_VMPG_CONFIG +#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT 0x1 +#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT 0x2 +#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT 0x7 +#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK 0x00000002L +#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK 0x0000007CL +#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK 0x00000080L +//HUBP0_DCHUBP_MALL_CONFIG +#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT 0x0 +#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT 0x2 +#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK 0x00000003L +#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK 0x00000004L +//HUBP0_DCHUBP_MALL_SUB_VP +#define HUBP0_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT 0x0 +#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT 0x1 +#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT 0xf +#define HUBP0_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK 0x00000001L +#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK 0x00007FFEL +#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK 0x1FFF8000L +//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +//HUBP0_HUBP_MALL_STATUS +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT 0x0 +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT 0x1 +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT 0x2 +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT 0x3 +#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT 0x4 +#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT 0x6 +#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT 0x7 +#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT 0x8 +#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT 0x9 +#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT 0xa +#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT 0xb +#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT 0xc +#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT 0xd +#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT 0xe +#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT 0xf +#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT 0x10 +#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT 0x11 +#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT 0x12 +#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT 0x13 +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK 0x00000001L +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK 0x00000002L +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK 0x00000004L +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK 0x00000008L +#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE_MASK 0x00000010L +#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK 0x00000040L +#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK 0x00000080L +#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK 0x00000100L +#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK 0x00000200L +#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK 0x00000400L +#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK 0x00000800L +#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK 0x00001000L +#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK 0x00002000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK 0x00004000L +#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK 0x00008000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK 0x00010000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK 0x00020000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK 0x00040000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK 0x00080000L + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec +//HUBPREQ0_DCSURF_SURFACE_PITCH +#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ0_DCSURF_SURFACE_PITCH_C +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ0_VMID_SETTINGS_0 +#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SURFACE_CONTROL +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x2 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x5 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0xa +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xd +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x0000000CL +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00000060L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x00000C00L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x00006000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L +//HUBPREQ0_DCSURF_FLIP_CONTROL +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ0_DCSURF_FLIP_CONTROL2 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ0_DCSURF_SURFACE_INUSE +#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ0_DCSURF_SURFACE_INUSE_C +#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ0_DCN_EXPANSION_MODE +#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ0_DCN_TTU_QOS_WM +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ0_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ0_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_DMDATA_VM_CNTL +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ0_BLANK_OFFSET_0 +#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ0_BLANK_OFFSET_1 +#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ0_DST_DIMENSIONS +#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ0_DST_AFTER_SCALER +#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ0_PREFETCH_SETTINGS +#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ0_PREFETCH_SETTINGS_C +#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_0 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ0_VBLANK_PARAMETERS_1 +#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_2 +#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_3 +#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_4 +#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_0 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ0_FLIP_PARAMETERS_1 +#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_2 +#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_0 +#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_1 +#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_2 +#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_3 +#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_4 +#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_5 +#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_6 +#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_7 +#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ0_PER_LINE_DELIVERY_PRE +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ0_PER_LINE_DELIVERY +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ0_CURSOR_SETTINGS +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ0_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +//HUBPREQ0_VBLANK_PARAMETERS_5 +#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_6 +#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_3 +#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_4 +#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_5 +#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_6 +#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ0_UCLK_PSTATE_FORCE +#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT 0x0 +#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x1 +#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT 0x2 +#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x3 +#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK 0x00000001L +#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000002L +#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK 0x00000004L +#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000008L +//HUBPREQ0_HUBPREQ_STATUS_REG0 +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT 0x8 +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT 0x10 +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK 0x0000001FL +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK 0x00001F00L +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK 0x7FFF0000L +//HUBPREQ0_HUBPREQ_STATUS_REG1 +#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT 0x10 +#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK 0x00003FFFL +#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK 0x3FFF0000L +//HUBPREQ0_HUBPREQ_STATUS_REG2 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT 0x1 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT 0x3 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT 0x5 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT 0x8 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT 0x9 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT 0xa +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT 0xb +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT 0xc +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT 0xd +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT 0x10 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT 0x11 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT 0x12 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT 0x13 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT 0x14 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT 0x15 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT 0x1a +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT 0x1b +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT 0x1c +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT 0x1d +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT 0x1e +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT 0x1f +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK 0x00000001L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK 0x00000002L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK 0x00000004L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK 0x00000008L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK 0x00000010L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK 0x00000020L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK 0x00000100L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK 0x00000200L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK 0x00000400L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK 0x00000800L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK 0x00001000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK 0x00002000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK 0x00010000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK 0x00020000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK 0x00040000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK 0x00080000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK 0x00100000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK 0x00200000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK 0x04000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK 0x08000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK 0x10000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK 0x20000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK 0x40000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK 0x80000000L + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec +//HUBPRET0_HUBPRET_CONTROL +#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00007FF0L +#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET0_HUBPRET_MEM_PWR_CTRL +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET0_HUBPRET_MEM_PWR_STATUS +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET0_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET0_HUBPRET_READ_LINE0 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE1 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_INTERRUPT +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET0_HUBPRET_READ_LINE_VALUE +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE_STATUS +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec +//CURSOR0_0_CURSOR_CONTROL +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +//CURSOR0_0_CURSOR_SURFACE_ADDRESS +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_0_CURSOR_SIZE +#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_0_CURSOR_POSITION +#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_0_CURSOR_HOT_SPOT +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_0_CURSOR_STEREO_CONTROL +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_0_CURSOR_DST_OFFSET +#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_0_CURSOR_MEM_PWR_CTRL +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_0_CURSOR_MEM_PWR_STATUS +#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_0_DMDATA_ADDRESS_HIGH +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_0_DMDATA_ADDRESS_LOW +#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_0_DMDATA_CNTL +#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_0_DMDATA_QOS_CNTL +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_0_DMDATA_STATUS +#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_0_DMDATA_SW_CNTL +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_0_DMDATA_SW_DATA +#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec +//HUBP1_DCSURF_SURFACE_CONFIG +#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP1_DCSURF_ADDR_CONFIG +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP1_DCSURF_TILING_CONFIG +#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP1_DCSURF_PRI_VIEWPORT_START +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_START_C +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_START +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_START_C +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP1_DCHUBP_REQ_SIZE_CONFIG +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP1_DCHUBP_CNTL +#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP1_HUBP_CLK_CNTL +#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT 0x18 +#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK 0x01000000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP1_DCHUBP_VMPG_CONFIG +#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT 0x1 +#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT 0x2 +#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT 0x7 +#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK 0x00000002L +#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK 0x0000007CL +#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK 0x00000080L +//HUBP1_DCHUBP_MALL_CONFIG +#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT 0x0 +#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT 0x2 +#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK 0x00000003L +#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK 0x00000004L +//HUBP1_DCHUBP_MALL_SUB_VP +#define HUBP1_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT 0x0 +#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT 0x1 +#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT 0xf +#define HUBP1_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK 0x00000001L +#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK 0x00007FFEL +#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK 0x1FFF8000L +//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +//HUBP1_HUBP_MALL_STATUS +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT 0x0 +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT 0x1 +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT 0x2 +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT 0x3 +#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT 0x4 +#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT 0x6 +#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT 0x7 +#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT 0x8 +#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT 0x9 +#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT 0xa +#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT 0xb +#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT 0xc +#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT 0xd +#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT 0xe +#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT 0xf +#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT 0x10 +#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT 0x11 +#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT 0x12 +#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT 0x13 +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK 0x00000001L +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK 0x00000002L +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK 0x00000004L +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK 0x00000008L +#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE_MASK 0x00000010L +#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK 0x00000040L +#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK 0x00000080L +#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK 0x00000100L +#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK 0x00000200L +#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK 0x00000400L +#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK 0x00000800L +#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK 0x00001000L +#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK 0x00002000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK 0x00004000L +#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK 0x00008000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK 0x00010000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK 0x00020000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK 0x00040000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK 0x00080000L + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec +//HUBPREQ1_DCSURF_SURFACE_PITCH +#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ1_DCSURF_SURFACE_PITCH_C +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ1_VMID_SETTINGS_0 +#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SURFACE_CONTROL +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x2 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x5 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0xa +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xd +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x0000000CL +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00000060L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x00000C00L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x00006000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L +//HUBPREQ1_DCSURF_FLIP_CONTROL +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ1_DCSURF_FLIP_CONTROL2 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ1_DCSURF_SURFACE_INUSE +#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ1_DCSURF_SURFACE_INUSE_C +#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ1_DCN_EXPANSION_MODE +#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ1_DCN_TTU_QOS_WM +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ1_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ1_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_DMDATA_VM_CNTL +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ1_BLANK_OFFSET_0 +#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ1_BLANK_OFFSET_1 +#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ1_DST_DIMENSIONS +#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ1_DST_AFTER_SCALER +#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ1_PREFETCH_SETTINGS +#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ1_PREFETCH_SETTINGS_C +#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_0 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ1_VBLANK_PARAMETERS_1 +#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_2 +#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_3 +#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_4 +#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_0 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ1_FLIP_PARAMETERS_1 +#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_2 +#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_0 +#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_1 +#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_2 +#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_3 +#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_4 +#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_5 +#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_6 +#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_7 +#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ1_PER_LINE_DELIVERY_PRE +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ1_PER_LINE_DELIVERY +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ1_CURSOR_SETTINGS +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ1_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +//HUBPREQ1_VBLANK_PARAMETERS_5 +#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_6 +#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_3 +#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_4 +#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_5 +#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_6 +#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ1_UCLK_PSTATE_FORCE +#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT 0x0 +#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x1 +#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT 0x2 +#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x3 +#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK 0x00000001L +#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000002L +#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK 0x00000004L +#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000008L +//HUBPREQ1_HUBPREQ_STATUS_REG0 +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT 0x8 +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT 0x10 +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK 0x0000001FL +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK 0x00001F00L +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK 0x7FFF0000L +//HUBPREQ1_HUBPREQ_STATUS_REG1 +#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT 0x10 +#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK 0x00003FFFL +#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK 0x3FFF0000L +//HUBPREQ1_HUBPREQ_STATUS_REG2 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT 0x1 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT 0x3 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT 0x5 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT 0x8 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT 0x9 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT 0xa +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT 0xb +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT 0xc +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT 0xd +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT 0x10 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT 0x11 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT 0x12 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT 0x13 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT 0x14 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT 0x15 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT 0x1a +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT 0x1b +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT 0x1c +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT 0x1d +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT 0x1e +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT 0x1f +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK 0x00000001L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK 0x00000002L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK 0x00000004L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK 0x00000008L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK 0x00000010L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK 0x00000020L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK 0x00000100L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK 0x00000200L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK 0x00000400L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK 0x00000800L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK 0x00001000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK 0x00002000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK 0x00010000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK 0x00020000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK 0x00040000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK 0x00080000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK 0x00100000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK 0x00200000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK 0x04000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK 0x08000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK 0x10000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK 0x20000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK 0x40000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK 0x80000000L + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec +//HUBPRET1_HUBPRET_CONTROL +#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00007FF0L +#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET1_HUBPRET_MEM_PWR_CTRL +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET1_HUBPRET_MEM_PWR_STATUS +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET1_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET1_HUBPRET_READ_LINE0 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE1 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_INTERRUPT +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET1_HUBPRET_READ_LINE_VALUE +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE_STATUS +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec +//CURSOR0_1_CURSOR_CONTROL +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +//CURSOR0_1_CURSOR_SURFACE_ADDRESS +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_1_CURSOR_SIZE +#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_1_CURSOR_POSITION +#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_1_CURSOR_HOT_SPOT +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_1_CURSOR_STEREO_CONTROL +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_1_CURSOR_DST_OFFSET +#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_1_CURSOR_MEM_PWR_CTRL +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_1_CURSOR_MEM_PWR_STATUS +#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_1_DMDATA_ADDRESS_HIGH +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_1_DMDATA_ADDRESS_LOW +#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_1_DMDATA_CNTL +#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_1_DMDATA_QOS_CNTL +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_1_DMDATA_STATUS +#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_1_DMDATA_SW_CNTL +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_1_DMDATA_SW_DATA +#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec +//HUBP2_DCSURF_SURFACE_CONFIG +#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP2_DCSURF_ADDR_CONFIG +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP2_DCSURF_TILING_CONFIG +#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP2_DCSURF_PRI_VIEWPORT_START +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_START_C +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_START +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_START_C +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP2_DCHUBP_REQ_SIZE_CONFIG +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP2_DCHUBP_CNTL +#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP2_HUBP_CLK_CNTL +#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT 0x18 +#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK 0x01000000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP2_DCHUBP_VMPG_CONFIG +#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT 0x1 +#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT 0x2 +#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT 0x7 +#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK 0x00000002L +#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK 0x0000007CL +#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK 0x00000080L +//HUBP2_DCHUBP_MALL_CONFIG +#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT 0x0 +#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT 0x2 +#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK 0x00000003L +#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK 0x00000004L +//HUBP2_DCHUBP_MALL_SUB_VP +#define HUBP2_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT 0x0 +#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT 0x1 +#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT 0xf +#define HUBP2_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK 0x00000001L +#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK 0x00007FFEL +#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK 0x1FFF8000L +//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +//HUBP2_HUBP_MALL_STATUS +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT 0x0 +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT 0x1 +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT 0x2 +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT 0x3 +#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT 0x4 +#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT 0x6 +#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT 0x7 +#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT 0x8 +#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT 0x9 +#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT 0xa +#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT 0xb +#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT 0xc +#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT 0xd +#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT 0xe +#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT 0xf +#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT 0x10 +#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT 0x11 +#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT 0x12 +#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT 0x13 +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK 0x00000001L +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK 0x00000002L +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK 0x00000004L +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK 0x00000008L +#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE_MASK 0x00000010L +#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK 0x00000040L +#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK 0x00000080L +#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK 0x00000100L +#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK 0x00000200L +#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK 0x00000400L +#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK 0x00000800L +#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK 0x00001000L +#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK 0x00002000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK 0x00004000L +#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK 0x00008000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK 0x00010000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK 0x00020000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK 0x00040000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK 0x00080000L + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec +//HUBPREQ2_DCSURF_SURFACE_PITCH +#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ2_DCSURF_SURFACE_PITCH_C +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ2_VMID_SETTINGS_0 +#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SURFACE_CONTROL +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x2 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x5 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0xa +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xd +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x0000000CL +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00000060L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x00000C00L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x00006000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L +//HUBPREQ2_DCSURF_FLIP_CONTROL +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ2_DCSURF_FLIP_CONTROL2 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ2_DCSURF_SURFACE_INUSE +#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ2_DCSURF_SURFACE_INUSE_C +#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ2_DCN_EXPANSION_MODE +#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ2_DCN_TTU_QOS_WM +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ2_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ2_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_DMDATA_VM_CNTL +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ2_BLANK_OFFSET_0 +#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ2_BLANK_OFFSET_1 +#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ2_DST_DIMENSIONS +#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ2_DST_AFTER_SCALER +#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ2_PREFETCH_SETTINGS +#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ2_PREFETCH_SETTINGS_C +#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_0 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ2_VBLANK_PARAMETERS_1 +#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_2 +#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_3 +#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_4 +#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_0 +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ2_FLIP_PARAMETERS_1 +#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_2 +#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_0 +#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_1 +#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_2 +#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_3 +#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_4 +#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_5 +#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_6 +#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_7 +#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ2_PER_LINE_DELIVERY_PRE +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ2_PER_LINE_DELIVERY +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ2_CURSOR_SETTINGS +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ2_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +//HUBPREQ2_VBLANK_PARAMETERS_5 +#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_6 +#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_3 +#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_4 +#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_5 +#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_6 +#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ2_UCLK_PSTATE_FORCE +#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT 0x0 +#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x1 +#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT 0x2 +#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x3 +#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK 0x00000001L +#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000002L +#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK 0x00000004L +#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000008L +//HUBPREQ2_HUBPREQ_STATUS_REG0 +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT 0x8 +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT 0x10 +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK 0x0000001FL +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK 0x00001F00L +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK 0x7FFF0000L +//HUBPREQ2_HUBPREQ_STATUS_REG1 +#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT 0x10 +#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK 0x00003FFFL +#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK 0x3FFF0000L +//HUBPREQ2_HUBPREQ_STATUS_REG2 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT 0x1 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT 0x2 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT 0x3 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT 0x4 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT 0x5 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT 0x8 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT 0x9 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT 0xa +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT 0xb +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT 0xc +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT 0xd +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT 0x10 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT 0x11 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT 0x12 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT 0x13 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT 0x14 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT 0x15 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT 0x1a +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT 0x1b +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT 0x1c +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT 0x1d +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT 0x1e +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT 0x1f +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK 0x00000001L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK 0x00000002L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK 0x00000004L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK 0x00000008L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK 0x00000010L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK 0x00000020L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK 0x00000100L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK 0x00000200L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK 0x00000400L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK 0x00000800L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK 0x00001000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK 0x00002000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK 0x00010000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK 0x00020000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK 0x00040000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK 0x00080000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK 0x00100000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK 0x00200000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK 0x04000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK 0x08000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK 0x10000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK 0x20000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK 0x40000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK 0x80000000L + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec +//HUBPRET2_HUBPRET_CONTROL +#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00007FF0L +#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET2_HUBPRET_MEM_PWR_CTRL +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET2_HUBPRET_MEM_PWR_STATUS +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET2_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET2_HUBPRET_READ_LINE0 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE1 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_INTERRUPT +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET2_HUBPRET_READ_LINE_VALUE +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE_STATUS +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec +//CURSOR0_2_CURSOR_CONTROL +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +//CURSOR0_2_CURSOR_SURFACE_ADDRESS +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_2_CURSOR_SIZE +#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_2_CURSOR_POSITION +#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_2_CURSOR_HOT_SPOT +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_2_CURSOR_STEREO_CONTROL +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_2_CURSOR_DST_OFFSET +#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_2_CURSOR_MEM_PWR_CTRL +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_2_CURSOR_MEM_PWR_STATUS +#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_2_DMDATA_ADDRESS_HIGH +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_2_DMDATA_ADDRESS_LOW +#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_2_DMDATA_CNTL +#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_2_DMDATA_QOS_CNTL +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_2_DMDATA_STATUS +#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_2_DMDATA_SW_CNTL +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_2_DMDATA_SW_DATA +#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec +//HUBP3_DCSURF_SURFACE_CONFIG +#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP3_DCSURF_ADDR_CONFIG +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP3_DCSURF_TILING_CONFIG +#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP3_DCSURF_PRI_VIEWPORT_START +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_START_C +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_START +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_START_C +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP3_DCHUBP_REQ_SIZE_CONFIG +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP3_DCHUBP_CNTL +#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP3_HUBP_CLK_CNTL +#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT 0x18 +#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK 0x01000000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP3_DCHUBP_VMPG_CONFIG +#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT 0x1 +#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT 0x2 +#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT 0x7 +#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK 0x00000002L +#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK 0x0000007CL +#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK 0x00000080L +//HUBP3_DCHUBP_MALL_CONFIG +#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT 0x0 +#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT 0x2 +#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK 0x00000003L +#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK 0x00000004L +//HUBP3_DCHUBP_MALL_SUB_VP +#define HUBP3_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT 0x0 +#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT 0x1 +#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT 0xf +#define HUBP3_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK 0x00000001L +#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK 0x00007FFEL +#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK 0x1FFF8000L +//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +//HUBP3_HUBP_MALL_STATUS +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT 0x0 +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT 0x1 +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT 0x2 +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT 0x3 +#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT 0x4 +#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT 0x6 +#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT 0x7 +#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT 0x8 +#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT 0x9 +#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT 0xa +#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT 0xb +#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT 0xc +#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT 0xd +#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT 0xe +#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT 0xf +#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT 0x10 +#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT 0x11 +#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT 0x12 +#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT 0x13 +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK 0x00000001L +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK 0x00000002L +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK 0x00000004L +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK 0x00000008L +#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE_MASK 0x00000010L +#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK 0x00000040L +#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK 0x00000080L +#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK 0x00000100L +#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK 0x00000200L +#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK 0x00000400L +#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK 0x00000800L +#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK 0x00001000L +#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK 0x00002000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK 0x00004000L +#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK 0x00008000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK 0x00010000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK 0x00020000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK 0x00040000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK 0x00080000L + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec +//HUBPREQ3_DCSURF_SURFACE_PITCH +#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ3_DCSURF_SURFACE_PITCH_C +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ3_VMID_SETTINGS_0 +#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SURFACE_CONTROL +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x2 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x5 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0xa +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xd +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x0000000CL +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00000060L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x00000C00L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x00006000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L +//HUBPREQ3_DCSURF_FLIP_CONTROL +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ3_DCSURF_FLIP_CONTROL2 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ3_DCSURF_SURFACE_INUSE +#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ3_DCSURF_SURFACE_INUSE_C +#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ3_DCN_EXPANSION_MODE +#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ3_DCN_TTU_QOS_WM +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ3_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ3_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_DMDATA_VM_CNTL +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ3_BLANK_OFFSET_0 +#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ3_BLANK_OFFSET_1 +#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ3_DST_DIMENSIONS +#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ3_DST_AFTER_SCALER +#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ3_PREFETCH_SETTINGS +#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ3_PREFETCH_SETTINGS_C +#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_0 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ3_VBLANK_PARAMETERS_1 +#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_2 +#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_3 +#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_4 +#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_0 +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ3_FLIP_PARAMETERS_1 +#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_2 +#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_0 +#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_1 +#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_2 +#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_3 +#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_4 +#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_5 +#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_6 +#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_7 +#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ3_PER_LINE_DELIVERY_PRE +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ3_PER_LINE_DELIVERY +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ3_CURSOR_SETTINGS +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ3_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +//HUBPREQ3_VBLANK_PARAMETERS_5 +#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_6 +#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_3 +#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_4 +#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_5 +#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_6 +#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ3_UCLK_PSTATE_FORCE +#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT 0x0 +#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x1 +#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT 0x2 +#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x3 +#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK 0x00000001L +#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000002L +#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK 0x00000004L +#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000008L +//HUBPREQ3_HUBPREQ_STATUS_REG0 +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT 0x8 +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT 0x10 +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK 0x0000001FL +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK 0x00001F00L +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK 0x7FFF0000L +//HUBPREQ3_HUBPREQ_STATUS_REG1 +#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT 0x10 +#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK 0x00003FFFL +#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK 0x3FFF0000L +//HUBPREQ3_HUBPREQ_STATUS_REG2 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT 0x1 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT 0x2 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT 0x3 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT 0x4 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT 0x5 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT 0x8 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT 0x9 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT 0xa +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT 0xb +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT 0xc +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT 0xd +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT 0x10 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT 0x11 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT 0x12 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT 0x13 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT 0x14 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT 0x15 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT 0x1a +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT 0x1b +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT 0x1c +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT 0x1d +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT 0x1e +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT 0x1f +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK 0x00000001L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK 0x00000002L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK 0x00000004L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK 0x00000008L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK 0x00000010L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK 0x00000020L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK 0x00000100L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK 0x00000200L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK 0x00000400L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK 0x00000800L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK 0x00001000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK 0x00002000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK 0x00010000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK 0x00020000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK 0x00040000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK 0x00080000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK 0x00100000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK 0x00200000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK 0x04000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK 0x08000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK 0x10000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK 0x20000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK 0x40000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK 0x80000000L + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec +//HUBPRET3_HUBPRET_CONTROL +#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00007FF0L +#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET3_HUBPRET_MEM_PWR_CTRL +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET3_HUBPRET_MEM_PWR_STATUS +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET3_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET3_HUBPRET_READ_LINE0 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE1 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_INTERRUPT +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET3_HUBPRET_READ_LINE_VALUE +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE_STATUS +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec +//CURSOR0_3_CURSOR_CONTROL +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +//CURSOR0_3_CURSOR_SURFACE_ADDRESS +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_3_CURSOR_SIZE +#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_3_CURSOR_POSITION +#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_3_CURSOR_HOT_SPOT +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_3_CURSOR_STEREO_CONTROL +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_3_CURSOR_DST_OFFSET +#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_3_CURSOR_MEM_PWR_CTRL +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_3_CURSOR_MEM_PWR_STATUS +#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_3_DMDATA_ADDRESS_HIGH +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_3_DMDATA_ADDRESS_LOW +#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_3_DMDATA_CNTL +#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_3_DMDATA_QOS_CNTL +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_3_DMDATA_STATUS +#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_3_DMDATA_SW_CNTL +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_3_DMDATA_SW_DATA +#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec +//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG0_FORMAT_CONTROL +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG0_FCNV_FP_BIAS_R +#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_BIAS_G +#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_BIAS_B +#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_R +#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_G +#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_B +#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG0_COLOR_KEYER_CONTROL +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG0_COLOR_KEYER_ALPHA +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_RED +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_GREEN +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_BLUE +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_ALPHA_2BIT_LUT +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L +//CNVC_CFG0_PRE_DEALPHA +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG0_PRE_CSC_MODE +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG0_PRE_CSC_C11_C12 +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C13_C14 +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C21_C22 +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C23_C24 +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C31_C32 +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C33_C34 +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C11_C12 +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C13_C14 +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C21_C22 +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C23_C24 +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C31_C32 +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C33_C34 +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG0_CNVC_COEF_FORMAT +#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG0_PRE_DEGAM +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG0_PRE_REALPHA +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec +//CNVC_CUR0_CURSOR0_CONTROL +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CNVC_CUR0_CURSOR0_COLOR0 +#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR0_CURSOR0_COLOR1 +#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR0_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec +//DSCL0_SCL_COEF_RAM_TAP_SELECT +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L +//DSCL0_SCL_COEF_RAM_TAP_DATA +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL0_SCL_MODE +#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL0_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL0_SCL_TAP_CONTROL +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL0_DSCL_CONTROL +#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL0_DSCL_2TAP_CONTROL +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL0_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL0_SCL_HORZ_FILTER_INIT +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL0_SCL_HORZ_FILTER_INIT_C +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL0_SCL_VERT_FILTER_INIT +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_INIT_BOT +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL0_SCL_VERT_FILTER_INIT_C +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL0_SCL_BLACK_COLOR +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL0_DSCL_UPDATE +#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL0_DSCL_AUTOCAL +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL0_OTG_H_BLANK +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL0_OTG_V_BLANK +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL0_RECOUT_START +#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL0_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL0_RECOUT_SIZE +#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL0_MPC_SIZE +#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL0_LB_DATA_FORMAT +#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL0_LB_MEMORY_CTRL +#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL0_LB_V_COUNTER +#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL0_DSCL_MEM_PWR_CTRL +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL0_DSCL_MEM_PWR_STATUS +#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL0_OBUF_CONTROL +#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL0_OBUF_MEM_PWR_CTRL +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec +//CM0_CM_CONTROL +#define CM0_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM0_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM0_CM_POST_CSC_CONTROL +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM0_CM_POST_CSC_C11_C12 +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C13_C14 +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C21_C22 +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C23_C24 +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C31_C32 +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C33_C34 +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C11_C12 +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C13_C14 +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C21_C22 +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C23_C24 +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C31_C32 +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C33_C34 +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_CONTROL +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x2 +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK 0x0000000CL +//CM0_CM_GAMUT_REMAP_C11_C12 +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C13_C14 +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C21_C22 +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C23_C24 +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C31_C32 +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C33_C34 +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C11_C12 +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C13_C14 +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C21_C22 +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C23_C24 +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C31_C32 +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C33_C34 +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L +//CM0_CM_BIAS_CR_R +#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM0_CM_BIAS_Y_G_CB_B +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_CONTROL +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM0_CM_GAMCOR_LUT_INDEX +#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM0_CM_GAMCOR_LUT_DATA +#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_LUT_CONTROL +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM0_CM_GAMCOR_RAMA_START_CNTL_B +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMA_START_CNTL_G +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMA_START_CNTL_R +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMA_OFFSET_B +#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMA_OFFSET_G +#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMA_OFFSET_R +#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMA_REGION_0_1 +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_2_3 +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_4_5 +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_6_7 +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_8_9 +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_10_11 +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_12_13 +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_14_15 +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_16_17 +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_18_19 +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_20_21 +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_22_23 +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_24_25 +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_26_27 +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_28_29 +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_30_31 +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_32_33 +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_START_CNTL_B +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMB_START_CNTL_G +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMB_START_CNTL_R +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMB_OFFSET_B +#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMB_OFFSET_G +#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMB_OFFSET_R +#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMB_REGION_0_1 +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_2_3 +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_4_5 +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_6_7 +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_8_9 +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_10_11 +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_12_13 +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_14_15 +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_16_17 +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_18_19 +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_20_21 +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_22_23 +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_24_25 +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_26_27 +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_28_29 +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_30_31 +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_32_33 +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_HDR_MULT_COEF +#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM0_CM_MEM_PWR_CTRL +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +//CM0_CM_MEM_PWR_STATUS +#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +//CM0_CM_DEALPHA +#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM0_CM_COEF_FORMAT +#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec +//DPP_TOP0_DPP_CONTROL +#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT 0x18 +#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK 0x01000000L +#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP0_DPP_SOFT_RESET +#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP0_DPP_CRC_VAL_R_G +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP0_DPP_CRC_VAL_B_A +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP0_DPP_CRC_CTRL +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xe +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x0000C000L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP0_HOST_READ_CONTROL +#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec +//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG1_FORMAT_CONTROL +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG1_FCNV_FP_BIAS_R +#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_BIAS_G +#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_BIAS_B +#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_R +#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_G +#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_B +#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG1_COLOR_KEYER_CONTROL +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG1_COLOR_KEYER_ALPHA +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_RED +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_GREEN +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_BLUE +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_ALPHA_2BIT_LUT +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L +//CNVC_CFG1_PRE_DEALPHA +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG1_PRE_CSC_MODE +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG1_PRE_CSC_C11_C12 +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C13_C14 +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C21_C22 +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C23_C24 +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C31_C32 +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C33_C34 +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C11_C12 +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C13_C14 +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C21_C22 +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C23_C24 +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C31_C32 +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C33_C34 +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG1_CNVC_COEF_FORMAT +#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG1_PRE_DEGAM +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG1_PRE_REALPHA +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec +//CNVC_CUR1_CURSOR0_CONTROL +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CNVC_CUR1_CURSOR0_COLOR0 +#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR1_CURSOR0_COLOR1 +#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR1_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec +//DSCL1_SCL_COEF_RAM_TAP_SELECT +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L +//DSCL1_SCL_COEF_RAM_TAP_DATA +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL1_SCL_MODE +#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL1_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL1_SCL_TAP_CONTROL +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL1_DSCL_CONTROL +#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL1_DSCL_2TAP_CONTROL +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL1_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL1_SCL_HORZ_FILTER_INIT +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL1_SCL_HORZ_FILTER_INIT_C +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL1_SCL_VERT_FILTER_INIT +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_INIT_BOT +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL1_SCL_VERT_FILTER_INIT_C +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL1_SCL_BLACK_COLOR +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL1_DSCL_UPDATE +#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL1_DSCL_AUTOCAL +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL1_OTG_H_BLANK +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL1_OTG_V_BLANK +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL1_RECOUT_START +#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL1_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL1_RECOUT_SIZE +#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL1_MPC_SIZE +#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL1_LB_DATA_FORMAT +#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL1_LB_MEMORY_CTRL +#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL1_LB_V_COUNTER +#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL1_DSCL_MEM_PWR_CTRL +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL1_DSCL_MEM_PWR_STATUS +#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL1_OBUF_CONTROL +#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL1_OBUF_MEM_PWR_CTRL +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec +//CM1_CM_CONTROL +#define CM1_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM1_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM1_CM_POST_CSC_CONTROL +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM1_CM_POST_CSC_C11_C12 +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C13_C14 +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C21_C22 +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C23_C24 +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C31_C32 +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C33_C34 +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C11_C12 +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C13_C14 +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C21_C22 +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C23_C24 +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C31_C32 +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C33_C34 +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_CONTROL +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x2 +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK 0x0000000CL +//CM1_CM_GAMUT_REMAP_C11_C12 +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C13_C14 +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C21_C22 +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C23_C24 +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C31_C32 +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C33_C34 +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C11_C12 +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C13_C14 +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C21_C22 +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C23_C24 +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C31_C32 +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C33_C34 +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L +//CM1_CM_BIAS_CR_R +#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM1_CM_BIAS_Y_G_CB_B +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_CONTROL +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM1_CM_GAMCOR_LUT_INDEX +#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM1_CM_GAMCOR_LUT_DATA +#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_LUT_CONTROL +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM1_CM_GAMCOR_RAMA_START_CNTL_B +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMA_START_CNTL_G +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMA_START_CNTL_R +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMA_OFFSET_B +#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMA_OFFSET_G +#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMA_OFFSET_R +#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMA_REGION_0_1 +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_2_3 +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_4_5 +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_6_7 +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_8_9 +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_10_11 +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_12_13 +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_14_15 +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_16_17 +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_18_19 +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_20_21 +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_22_23 +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_24_25 +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_26_27 +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_28_29 +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_30_31 +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_32_33 +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_START_CNTL_B +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMB_START_CNTL_G +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMB_START_CNTL_R +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMB_OFFSET_B +#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMB_OFFSET_G +#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMB_OFFSET_R +#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMB_REGION_0_1 +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_2_3 +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_4_5 +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_6_7 +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_8_9 +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_10_11 +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_12_13 +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_14_15 +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_16_17 +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_18_19 +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_20_21 +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_22_23 +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_24_25 +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_26_27 +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_28_29 +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_30_31 +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_32_33 +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_HDR_MULT_COEF +#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM1_CM_MEM_PWR_CTRL +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +//CM1_CM_MEM_PWR_STATUS +#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +//CM1_CM_DEALPHA +#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM1_CM_COEF_FORMAT +#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec +//DPP_TOP1_DPP_CONTROL +#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT 0x18 +#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK 0x01000000L +#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP1_DPP_SOFT_RESET +#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP1_DPP_CRC_VAL_R_G +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP1_DPP_CRC_VAL_B_A +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP1_DPP_CRC_CTRL +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xe +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x0000C000L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP1_HOST_READ_CONTROL +#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec +//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG2_FORMAT_CONTROL +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG2_FCNV_FP_BIAS_R +#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_BIAS_G +#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_BIAS_B +#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_SCALE_R +#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_SCALE_G +#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_SCALE_B +#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG2_COLOR_KEYER_CONTROL +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG2_COLOR_KEYER_ALPHA +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_RED +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_GREEN +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_BLUE +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_ALPHA_2BIT_LUT +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L +//CNVC_CFG2_PRE_DEALPHA +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG2_PRE_CSC_MODE +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG2_PRE_CSC_C11_C12 +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C13_C14 +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C21_C22 +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C23_C24 +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C31_C32 +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C33_C34 +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C11_C12 +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C13_C14 +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C21_C22 +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C23_C24 +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C31_C32 +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C33_C34 +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG2_CNVC_COEF_FORMAT +#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG2_PRE_DEGAM +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG2_PRE_REALPHA +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec +//CNVC_CUR2_CURSOR0_CONTROL +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CNVC_CUR2_CURSOR0_COLOR0 +#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR2_CURSOR0_COLOR1 +#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR2_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec +//DSCL2_SCL_COEF_RAM_TAP_SELECT +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L +//DSCL2_SCL_COEF_RAM_TAP_DATA +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL2_SCL_MODE +#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL2_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL2_SCL_TAP_CONTROL +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL2_DSCL_CONTROL +#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL2_DSCL_2TAP_CONTROL +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL2_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL2_SCL_HORZ_FILTER_INIT +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL2_SCL_HORZ_FILTER_INIT_C +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL2_SCL_VERT_FILTER_INIT +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_INIT_BOT +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL2_SCL_VERT_FILTER_INIT_C +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL2_SCL_BLACK_COLOR +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL2_DSCL_UPDATE +#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL2_DSCL_AUTOCAL +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL2_OTG_H_BLANK +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL2_OTG_V_BLANK +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL2_RECOUT_START +#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL2_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL2_RECOUT_SIZE +#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL2_MPC_SIZE +#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL2_LB_DATA_FORMAT +#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL2_LB_MEMORY_CTRL +#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL2_LB_V_COUNTER +#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL2_DSCL_MEM_PWR_CTRL +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL2_DSCL_MEM_PWR_STATUS +#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL2_OBUF_CONTROL +#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL2_OBUF_MEM_PWR_CTRL +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec +//CM2_CM_CONTROL +#define CM2_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM2_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM2_CM_POST_CSC_CONTROL +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM2_CM_POST_CSC_C11_C12 +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C13_C14 +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C21_C22 +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C23_C24 +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C31_C32 +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C33_C34 +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C11_C12 +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C13_C14 +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C21_C22 +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C23_C24 +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C31_C32 +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C33_C34 +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_CONTROL +#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x2 +#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK 0x0000000CL +//CM2_CM_GAMUT_REMAP_C11_C12 +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C13_C14 +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C21_C22 +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C23_C24 +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C31_C32 +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C33_C34 +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C11_C12 +#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C13_C14 +#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C21_C22 +#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C23_C24 +#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C31_C32 +#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C33_C34 +#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L +//CM2_CM_BIAS_CR_R +#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM2_CM_BIAS_Y_G_CB_B +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_CONTROL +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM2_CM_GAMCOR_LUT_INDEX +#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM2_CM_GAMCOR_LUT_DATA +#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_LUT_CONTROL +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM2_CM_GAMCOR_RAMA_START_CNTL_B +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMA_START_CNTL_G +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMA_START_CNTL_R +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMA_OFFSET_B +#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMA_OFFSET_G +#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMA_OFFSET_R +#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMA_REGION_0_1 +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_2_3 +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_4_5 +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_6_7 +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_8_9 +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_10_11 +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_12_13 +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_14_15 +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_16_17 +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_18_19 +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_20_21 +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_22_23 +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_24_25 +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_26_27 +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_28_29 +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_30_31 +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_32_33 +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_START_CNTL_B +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMB_START_CNTL_G +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMB_START_CNTL_R +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMB_OFFSET_B +#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMB_OFFSET_G +#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMB_OFFSET_R +#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMB_REGION_0_1 +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_2_3 +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_4_5 +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_6_7 +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_8_9 +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_10_11 +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_12_13 +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_14_15 +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_16_17 +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_18_19 +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_20_21 +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_22_23 +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_24_25 +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_26_27 +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_28_29 +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_30_31 +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_32_33 +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_HDR_MULT_COEF +#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM2_CM_MEM_PWR_CTRL +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +//CM2_CM_MEM_PWR_STATUS +#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +//CM2_CM_DEALPHA +#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM2_CM_COEF_FORMAT +#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec +//DPP_TOP2_DPP_CONTROL +#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT 0x18 +#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK 0x01000000L +#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP2_DPP_SOFT_RESET +#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP2_DPP_CRC_VAL_R_G +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP2_DPP_CRC_VAL_B_A +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP2_DPP_CRC_CTRL +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xe +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x0000C000L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP2_HOST_READ_CONTROL +#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec +//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG3_FORMAT_CONTROL +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG3_FCNV_FP_BIAS_R +#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_BIAS_G +#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_BIAS_B +#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_SCALE_R +#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_SCALE_G +#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_SCALE_B +#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG3_COLOR_KEYER_CONTROL +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG3_COLOR_KEYER_ALPHA +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_RED +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_GREEN +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_BLUE +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_ALPHA_2BIT_LUT +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L +//CNVC_CFG3_PRE_DEALPHA +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG3_PRE_CSC_MODE +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG3_PRE_CSC_C11_C12 +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C13_C14 +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C21_C22 +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C23_C24 +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C31_C32 +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C33_C34 +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C11_C12 +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C13_C14 +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C21_C22 +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C23_C24 +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C31_C32 +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C33_C34 +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG3_CNVC_COEF_FORMAT +#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG3_PRE_DEGAM +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG3_PRE_REALPHA +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec +//CNVC_CUR3_CURSOR0_CONTROL +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CNVC_CUR3_CURSOR0_COLOR0 +#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR3_CURSOR0_COLOR1 +#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR3_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec +//DSCL3_SCL_COEF_RAM_TAP_SELECT +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L +//DSCL3_SCL_COEF_RAM_TAP_DATA +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL3_SCL_MODE +#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL3_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL3_SCL_TAP_CONTROL +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL3_DSCL_CONTROL +#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL3_DSCL_2TAP_CONTROL +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL3_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL3_SCL_HORZ_FILTER_INIT +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL3_SCL_HORZ_FILTER_INIT_C +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL3_SCL_VERT_FILTER_INIT +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_INIT_BOT +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL3_SCL_VERT_FILTER_INIT_C +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL3_SCL_BLACK_COLOR +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL3_DSCL_UPDATE +#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL3_DSCL_AUTOCAL +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL3_OTG_H_BLANK +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL3_OTG_V_BLANK +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL3_RECOUT_START +#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL3_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL3_RECOUT_SIZE +#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL3_MPC_SIZE +#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL3_LB_DATA_FORMAT +#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL3_LB_MEMORY_CTRL +#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL3_LB_V_COUNTER +#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL3_DSCL_MEM_PWR_CTRL +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL3_DSCL_MEM_PWR_STATUS +#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL3_OBUF_CONTROL +#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL3_OBUF_MEM_PWR_CTRL +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec +//CM3_CM_CONTROL +#define CM3_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM3_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM3_CM_POST_CSC_CONTROL +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM3_CM_POST_CSC_C11_C12 +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C13_C14 +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C21_C22 +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C23_C24 +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C31_C32 +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C33_C34 +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C11_C12 +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C13_C14 +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C21_C22 +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C23_C24 +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C31_C32 +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C33_C34 +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_CONTROL +#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x2 +#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK 0x0000000CL +//CM3_CM_GAMUT_REMAP_C11_C12 +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C13_C14 +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C21_C22 +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C23_C24 +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C31_C32 +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C33_C34 +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C11_C12 +#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C13_C14 +#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C21_C22 +#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C23_C24 +#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C31_C32 +#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C33_C34 +#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L +//CM3_CM_BIAS_CR_R +#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM3_CM_BIAS_Y_G_CB_B +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_CONTROL +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM3_CM_GAMCOR_LUT_INDEX +#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM3_CM_GAMCOR_LUT_DATA +#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_LUT_CONTROL +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM3_CM_GAMCOR_RAMA_START_CNTL_B +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMA_START_CNTL_G +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMA_START_CNTL_R +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMA_OFFSET_B +#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMA_OFFSET_G +#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMA_OFFSET_R +#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMA_REGION_0_1 +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_2_3 +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_4_5 +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_6_7 +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_8_9 +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_10_11 +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_12_13 +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_14_15 +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_16_17 +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_18_19 +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_20_21 +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_22_23 +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_24_25 +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_26_27 +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_28_29 +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_30_31 +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_32_33 +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_START_CNTL_B +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMB_START_CNTL_G +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMB_START_CNTL_R +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMB_OFFSET_B +#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMB_OFFSET_G +#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMB_OFFSET_R +#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMB_REGION_0_1 +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_2_3 +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_4_5 +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_6_7 +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_8_9 +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_10_11 +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_12_13 +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_14_15 +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_16_17 +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_18_19 +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_20_21 +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_22_23 +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_24_25 +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_26_27 +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_28_29 +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_30_31 +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_32_33 +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_HDR_MULT_COEF +#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM3_CM_MEM_PWR_CTRL +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +//CM3_CM_MEM_PWR_STATUS +#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +//CM3_CM_DEALPHA +#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM3_CM_COEF_FORMAT +#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec +//DPP_TOP3_DPP_CONTROL +#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT 0x18 +#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK 0x01000000L +#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP3_DPP_SOFT_RESET +#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP3_DPP_CRC_VAL_R_G +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP3_DPP_CRC_VAL_B_A +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP3_DPP_CRC_CTRL +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xe +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x0000C000L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP3_HOST_READ_CONTROL +#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_mpc_mpcc0_dispdec +//MPCC0_MPCC_TOP_SEL +#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC0_MPCC_BOT_SEL +#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC0_MPCC_OPP_ID +#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC0_MPCC_CONTROL +#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC0_MPCC_SM_CONTROL +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC0_MPCC_UPDATE_LOCK_SEL +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC0_MPCC_TOP_GAIN +#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC0_MPCC_BOT_GAIN_INSIDE +#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC0_MPCC_BOT_GAIN_OUTSIDE +#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL +#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 +#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 +#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L +#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L +//MPCC0_MPCC_BG_R_CR +#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC0_MPCC_BG_G_Y +#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC0_MPCC_BG_B_CB +#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC0_MPCC_MEM_PWR_CTRL +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC0_MPCC_STATUS +#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc1_dispdec +//MPCC1_MPCC_TOP_SEL +#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC1_MPCC_BOT_SEL +#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC1_MPCC_OPP_ID +#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC1_MPCC_CONTROL +#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC1_MPCC_SM_CONTROL +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC1_MPCC_UPDATE_LOCK_SEL +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC1_MPCC_TOP_GAIN +#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC1_MPCC_BOT_GAIN_INSIDE +#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC1_MPCC_BOT_GAIN_OUTSIDE +#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL +#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 +#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 +#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L +#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L +//MPCC1_MPCC_BG_R_CR +#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC1_MPCC_BG_G_Y +#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC1_MPCC_BG_B_CB +#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC1_MPCC_MEM_PWR_CTRL +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC1_MPCC_STATUS +#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc2_dispdec +//MPCC2_MPCC_TOP_SEL +#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC2_MPCC_BOT_SEL +#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC2_MPCC_OPP_ID +#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC2_MPCC_CONTROL +#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC2_MPCC_SM_CONTROL +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC2_MPCC_UPDATE_LOCK_SEL +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC2_MPCC_TOP_GAIN +#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC2_MPCC_BOT_GAIN_INSIDE +#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC2_MPCC_BOT_GAIN_OUTSIDE +#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL +#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 +#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 +#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L +#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L +//MPCC2_MPCC_BG_R_CR +#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC2_MPCC_BG_G_Y +#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC2_MPCC_BG_B_CB +#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC2_MPCC_MEM_PWR_CTRL +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC2_MPCC_STATUS +#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc3_dispdec +//MPCC3_MPCC_TOP_SEL +#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC3_MPCC_BOT_SEL +#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC3_MPCC_OPP_ID +#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC3_MPCC_CONTROL +#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC3_MPCC_SM_CONTROL +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC3_MPCC_UPDATE_LOCK_SEL +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC3_MPCC_TOP_GAIN +#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC3_MPCC_BOT_GAIN_INSIDE +#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC3_MPCC_BOT_GAIN_OUTSIDE +#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL +#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 +#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 +#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L +#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L +//MPCC3_MPCC_BG_R_CR +#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC3_MPCC_BG_G_Y +#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC3_MPCC_BG_B_CB +#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC3_MPCC_MEM_PWR_CTRL +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC3_MPCC_STATUS +#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpc_cfg_dispdec +//MPC_CLOCK_CONTROL +#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x1 +#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT 0x4 +#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00000002L +#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK 0x00000030L +//MPC_SOFT_RESET +#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT 0x0 +#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT 0x1 +#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT 0x2 +#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT 0x3 +#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT 0xa +#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT 0xb +#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT 0xc +#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT 0xd +#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT 0x14 +#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT 0x15 +#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT 0x16 +#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT 0x17 +#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x1f +#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK 0x00000001L +#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK 0x00000002L +#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK 0x00000004L +#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK 0x00000008L +#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK 0x00000400L +#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK 0x00000800L +#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK 0x00001000L +#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK 0x00002000L +#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK 0x00100000L +#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK 0x00200000L +#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK 0x00400000L +#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK 0x00800000L +#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK 0x80000000L +//MPC_CRC_CTRL +#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT 0x0 +#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT 0x4 +#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT 0x8 +#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT 0xa +#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT 0xc +#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT 0x18 +#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT 0x1e +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT 0x1f +#define MPC_CRC_CTRL__MPC_CRC_EN_MASK 0x00000001L +#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK 0x00000010L +#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK 0x00000300L +#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK 0x00000400L +#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK 0x00003000L +#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK 0x03000000L +#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK 0x40000000L +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK 0x80000000L +//MPC_CRC_SEL_CONTROL +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT 0x0 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT 0x4 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL__SHIFT 0x8 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT 0x10 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK 0x0000000FL +#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK 0x000000F0L +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL_MASK 0x00000300L +#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK 0xFFFF0000L +//MPC_CRC_RESULT_AR +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT 0x0 +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT 0x10 +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK 0x0000FFFFL +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK 0xFFFF0000L +//MPC_CRC_RESULT_GB +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT 0x0 +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT 0x10 +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK 0x0000FFFFL +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK 0xFFFF0000L +//MPC_CRC_RESULT_C +#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT 0x0 +#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK 0x0000FFFFL +//MPC_BYPASS_BG_AR +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT 0x0 +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT 0x10 +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK 0x0000FFFFL +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK 0xFFFF0000L +//MPC_BYPASS_BG_GB +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT 0x0 +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT 0x10 +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK 0x0000FFFFL +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK 0xFFFF0000L +//MPC_HOST_READ_CONTROL +#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL +//MPC_DPP_PENDING_STATUS +#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT 0x0 +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT 0x1 +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT 0x2 +#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT 0x4 +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT 0x5 +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT 0x6 +#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT 0x8 +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT 0x9 +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT 0xa +#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT 0xc +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT 0xd +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT 0xe +#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING_MASK 0x00000001L +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING_MASK 0x00000002L +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING_MASK 0x00000004L +#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING_MASK 0x00000010L +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING_MASK 0x00000020L +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING_MASK 0x00000040L +#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING_MASK 0x00000100L +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING_MASK 0x00000200L +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING_MASK 0x00000400L +#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING_MASK 0x00001000L +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING_MASK 0x00002000L +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING_MASK 0x00004000L +//MPC_PENDING_STATUS_MISC +#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT 0x0 +#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT 0x1 +#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT 0x2 +#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT 0x3 +#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING__SHIFT 0x8 +#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING__SHIFT 0x9 +#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING__SHIFT 0xa +#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING__SHIFT 0xb +#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING__SHIFT 0x10 +#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK 0x00000001L +#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK 0x00000002L +#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK 0x00000004L +#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK 0x00000008L +#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING_MASK 0x00000100L +#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING_MASK 0x00000200L +#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING_MASK 0x00000400L +#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING_MASK 0x00000800L +#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING_MASK 0x00010000L +//ADR_CFG_CUR_VUPDATE_LOCK_SET0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET0 +#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET0 +#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET0 +#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET0 +#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET1 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET1 +#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET1 +#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET1 +#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET1 +#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET2 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET2 +#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET2 +#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET2 +#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET2 +#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET3 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET3 +#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET3 +#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET3 +#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET3 +#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//MPC_DWB0_MUX +#define MPC_DWB0_MUX__MPC_DWB0_MUX__SHIFT 0x0 +#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS__SHIFT 0x4 +#define MPC_DWB0_MUX__MPC_DWB0_MUX_MASK 0x0000000FL +#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS_MASK 0x000000F0L + + +// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec +//MPCC_OGAM0_MPCC_OGAM_CONTROL +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM0_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec +//MPCC_OGAM1_MPCC_OGAM_CONTROL +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM1_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec +//MPCC_OGAM2_MPCC_OGAM_CONTROL +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM2_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM2_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec +//MPCC_OGAM3_MPCC_OGAM_CONTROL +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM3_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM3_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpcc_mcm0_dispdec +//MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL +#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_3DLUT_MODE +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK 0x00000010L +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPCC_MCM0_MPCC_MCM_3DLUT_INDEX +#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL +//MPCC_MCM0_MPCC_MCM_3DLUT_DATA +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT 0x2 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK 0x00000004L +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L +//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL +//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L + + +// addressBlock: dce_dc_mpc_mpcc_mcm1_dispdec +//MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL +#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_3DLUT_MODE +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK 0x00000010L +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPCC_MCM1_MPCC_MCM_3DLUT_INDEX +#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL +//MPCC_MCM1_MPCC_MCM_3DLUT_DATA +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT 0x2 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK 0x00000004L +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L +//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL +//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L + + +// addressBlock: dce_dc_mpc_mpcc_mcm2_dispdec +//MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL +#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_3DLUT_MODE +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK 0x00000010L +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPCC_MCM2_MPCC_MCM_3DLUT_INDEX +#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL +//MPCC_MCM2_MPCC_MCM_3DLUT_DATA +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT 0x2 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK 0x00000004L +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L +//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL +//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L + + +// addressBlock: dce_dc_mpc_mpcc_mcm3_dispdec +//MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL +#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_3DLUT_MODE +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK 0x00000010L +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPCC_MCM3_MPCC_MCM_3DLUT_INDEX +#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL +//MPCC_MCM3_MPCC_MCM_3DLUT_DATA +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT 0x2 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK 0x00000004L +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L +//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL +//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L + + +// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec +//MPC_OUT0_MUX +#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT0_DENORM_CONTROL +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT0_DENORM_CLAMP_G_Y +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT0_DENORM_CLAMP_B_CB +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT1_MUX +#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT1_DENORM_CONTROL +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT1_DENORM_CLAMP_G_Y +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT1_DENORM_CLAMP_B_CB +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT2_MUX +#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT2_DENORM_CONTROL +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT2_DENORM_CLAMP_G_Y +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT2_DENORM_CLAMP_B_CB +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT3_MUX +#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT3_DENORM_CONTROL +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT3_DENORM_CLAMP_G_Y +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT3_DENORM_CLAMP_B_CB +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT_CSC_COEF_FORMAT +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT 0x0 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT 0x1 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT 0x2 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT 0x3 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK 0x00000001L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK 0x00000002L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK 0x00000004L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK 0x00000008L +//MPC_OUT0_CSC_MODE +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT0_CSC_C11_C12_A +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C13_C14_A +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C21_C22_A +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C23_C24_A +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C31_C32_A +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C33_C34_A +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C11_C12_B +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C13_C14_B +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C21_C22_B +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C23_C24_B +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C31_C32_B +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C33_C34_B +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_MODE +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT1_CSC_C11_C12_A +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C13_C14_A +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C21_C22_A +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C23_C24_A +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C31_C32_A +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C33_C34_A +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C11_C12_B +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C13_C14_B +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C21_C22_B +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C23_C24_B +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C31_C32_B +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C33_C34_B +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_MODE +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT2_CSC_C11_C12_A +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C13_C14_A +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C21_C22_A +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C23_C24_A +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C31_C32_A +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C33_C34_A +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C11_C12_B +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C13_C14_B +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C21_C22_B +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C23_C24_B +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C31_C32_B +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C33_C34_B +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_MODE +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT3_CSC_C11_C12_A +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C13_C14_A +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C21_C22_A +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C23_C24_A +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C31_C32_A +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C33_C34_A +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C11_C12_B +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C13_C14_B +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C21_C22_B +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C23_C24_B +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C31_C32_B +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C33_C34_B +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_opp_abm0_dispdec +//ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_USER_LEVEL +#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_TARGET_ABM_LEVEL +#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM0_BL1_PWM_ABM_CNTL +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_BL1_PWM_GRP2_REG_LOCK +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//ABM0_DC_ABM1_CNTL +#define ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM0_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM0_DC_ABM1_IPCSC_COEFF_SEL +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_THRES_12 +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_THRES_34 +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_CNTL_MISC +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM0_DC_ABM1_HG_MISC_CTRL +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_LS_SUM_OF_LUMA +#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L +//ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L +//ABM0_DC_ABM1_LS_PIXEL_COUNT +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L +//ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM0_DC_ABM1_HG_SAMPLE_RATE +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_LS_SAMPLE_RATE +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_1 +#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_2 +#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_3 +#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_4 +#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_5 +#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_6 +#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_7 +#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_8 +#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_9 +#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_10 +#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_11 +#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_12 +#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_13 +#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_14 +#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_15 +#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_16 +#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_17 +#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_18 +#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_19 +#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_20 +#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_21 +#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_22 +#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_23 +#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_24 +#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_BL_MASTER_LOCK +#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_opp_abm1_dispdec +//ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_USER_LEVEL +#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_TARGET_ABM_LEVEL +#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM1_BL1_PWM_ABM_CNTL +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_BL1_PWM_GRP2_REG_LOCK +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//ABM1_DC_ABM1_CNTL +#define ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM1_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM1_DC_ABM1_IPCSC_COEFF_SEL +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_THRES_12 +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_THRES_34 +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_CNTL_MISC +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM1_DC_ABM1_HG_MISC_CTRL +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_LS_SUM_OF_LUMA +#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L +//ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L +//ABM1_DC_ABM1_LS_PIXEL_COUNT +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L +//ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM1_DC_ABM1_HG_SAMPLE_RATE +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_LS_SAMPLE_RATE +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_1 +#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_2 +#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_3 +#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_4 +#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_5 +#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_6 +#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_7 +#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_8 +#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_9 +#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_10 +#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_11 +#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_12 +#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_13 +#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_14 +#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_15 +#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_16 +#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_17 +#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_18 +#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_19 +#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_20 +#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_21 +#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_22 +#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_23 +#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_24 +#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_BL_MASTER_LOCK +#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_opp_abm2_dispdec +//ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_USER_LEVEL +#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_TARGET_ABM_LEVEL +#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM2_BL1_PWM_ABM_CNTL +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM2_BL1_PWM_GRP2_REG_LOCK +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//ABM2_DC_ABM1_CNTL +#define ABM2_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM2_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM2_DC_ABM1_IPCSC_COEFF_SEL +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_THRES_12 +#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL +#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L +#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_THRES_34 +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_CNTL_MISC +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM2_DC_ABM1_HG_MISC_CTRL +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_LS_SUM_OF_LUMA +#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L +//ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L +//ABM2_DC_ABM1_LS_PIXEL_COUNT +#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 +#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L +//ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM2_DC_ABM1_HG_SAMPLE_RATE +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_LS_SAMPLE_RATE +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_1 +#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_2 +#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_3 +#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_4 +#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_5 +#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_6 +#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_7 +#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_8 +#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_9 +#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_10 +#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_11 +#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_12 +#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_13 +#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_14 +#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_15 +#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_16 +#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_17 +#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_18 +#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_19 +#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_20 +#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_21 +#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_22 +#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_23 +#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_24 +#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_BL_MASTER_LOCK +#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_opp_abm3_dispdec +//ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_USER_LEVEL +#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_TARGET_ABM_LEVEL +#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM3_BL1_PWM_ABM_CNTL +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM3_BL1_PWM_GRP2_REG_LOCK +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//ABM3_DC_ABM1_CNTL +#define ABM3_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM3_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM3_DC_ABM1_IPCSC_COEFF_SEL +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_THRES_12 +#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL +#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L +#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_THRES_34 +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_CNTL_MISC +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM3_DC_ABM1_HG_MISC_CTRL +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_LS_SUM_OF_LUMA +#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L +//ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L +//ABM3_DC_ABM1_LS_PIXEL_COUNT +#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 +#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L +//ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM3_DC_ABM1_HG_SAMPLE_RATE +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_LS_SAMPLE_RATE +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_1 +#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_2 +#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_3 +#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_4 +#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_5 +#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_6 +#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_7 +#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_8 +#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_9 +#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_10 +#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_11 +#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_12 +#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_13 +#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_14 +#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_15 +#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_16 +#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_17 +#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_18 +#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_19 +#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_20 +#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_21 +#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_22 +#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_23 +#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_24 +#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_BL_MASTER_LOCK +#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_opp_dpg0_dispdec +//DPG0_DPG_CONTROL +#define DPG0_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG0_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG0_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG0_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG0_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG0_DPG_RAMP_CONTROL +#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG0_DPG_DIMENSIONS +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG0_DPG_COLOUR_R_CR +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG0_DPG_COLOUR_G_Y +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG0_DPG_COLOUR_B_CB +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG0_DPG_OFFSET_SEGMENT +#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG0_DPG_STATUS +#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_fmt0_dispdec +//FMT0_FMT_CLAMP_COMPONENT_R +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_COMPONENT_G +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_COMPONENT_B +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT0_FMT_DYNAMIC_EXP_CNTL +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT0_FMT_CONTROL +#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT0_FMT_BIT_DEPTH_CONTROL +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT0_FMT_DITHER_RAND_R_SEED +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT0_FMT_DITHER_RAND_G_SEED +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT0_FMT_DITHER_RAND_B_SEED +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_CNTL +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT0_FMT_MAP420_MEMORY_CONTROL +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT0_FMT_422_CONTROL +#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf0_dispdec +//OPPBUF0_OPPBUF_CONTROL +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF0_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF0_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF0_OPPBUF_CONTROL1 +#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe0_dispdec +//OPP_PIPE0_OPP_PIPE_CONTROL +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec +//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_dpg1_dispdec +//DPG1_DPG_CONTROL +#define DPG1_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG1_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG1_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG1_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG1_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG1_DPG_RAMP_CONTROL +#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG1_DPG_DIMENSIONS +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG1_DPG_COLOUR_R_CR +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG1_DPG_COLOUR_G_Y +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG1_DPG_COLOUR_B_CB +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG1_DPG_OFFSET_SEGMENT +#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG1_DPG_STATUS +#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_fmt1_dispdec +//FMT1_FMT_CLAMP_COMPONENT_R +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_COMPONENT_G +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_COMPONENT_B +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT1_FMT_DYNAMIC_EXP_CNTL +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT1_FMT_CONTROL +#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT1_FMT_BIT_DEPTH_CONTROL +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT1_FMT_DITHER_RAND_R_SEED +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT1_FMT_DITHER_RAND_G_SEED +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT1_FMT_DITHER_RAND_B_SEED +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_CNTL +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT1_FMT_MAP420_MEMORY_CONTROL +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT1_FMT_422_CONTROL +#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf1_dispdec +//OPPBUF1_OPPBUF_CONTROL +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF1_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF1_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF1_OPPBUF_CONTROL1 +#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe1_dispdec +//OPP_PIPE1_OPP_PIPE_CONTROL +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec +//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_dpg2_dispdec +//DPG2_DPG_CONTROL +#define DPG2_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG2_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG2_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG2_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG2_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG2_DPG_RAMP_CONTROL +#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG2_DPG_DIMENSIONS +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG2_DPG_COLOUR_R_CR +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG2_DPG_COLOUR_G_Y +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG2_DPG_COLOUR_B_CB +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG2_DPG_OFFSET_SEGMENT +#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG2_DPG_STATUS +#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_fmt2_dispdec +//FMT2_FMT_CLAMP_COMPONENT_R +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_COMPONENT_G +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_COMPONENT_B +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT2_FMT_DYNAMIC_EXP_CNTL +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT2_FMT_CONTROL +#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT2_FMT_BIT_DEPTH_CONTROL +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT2_FMT_DITHER_RAND_R_SEED +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT2_FMT_DITHER_RAND_G_SEED +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT2_FMT_DITHER_RAND_B_SEED +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_CNTL +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT2_FMT_MAP420_MEMORY_CONTROL +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT2_FMT_422_CONTROL +#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf2_dispdec +//OPPBUF2_OPPBUF_CONTROL +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF2_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF2_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF2_OPPBUF_CONTROL1 +#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe2_dispdec +//OPP_PIPE2_OPP_PIPE_CONTROL +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec +//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_dpg3_dispdec +//DPG3_DPG_CONTROL +#define DPG3_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG3_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG3_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG3_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG3_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG3_DPG_RAMP_CONTROL +#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG3_DPG_DIMENSIONS +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG3_DPG_COLOUR_R_CR +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG3_DPG_COLOUR_G_Y +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG3_DPG_COLOUR_B_CB +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG3_DPG_OFFSET_SEGMENT +#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG3_DPG_STATUS +#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_fmt3_dispdec +//FMT3_FMT_CLAMP_COMPONENT_R +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_COMPONENT_G +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_COMPONENT_B +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT3_FMT_DYNAMIC_EXP_CNTL +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT3_FMT_CONTROL +#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT3_FMT_BIT_DEPTH_CONTROL +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT3_FMT_DITHER_RAND_R_SEED +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT3_FMT_DITHER_RAND_G_SEED +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT3_FMT_DITHER_RAND_B_SEED +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_CNTL +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT3_FMT_MAP420_MEMORY_CONTROL +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT3_FMT_422_CONTROL +#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf3_dispdec +//OPPBUF3_OPPBUF_CONTROL +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF3_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF3_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF3_OPPBUF_CONTROL1 +#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe3_dispdec +//OPP_PIPE3_OPP_PIPE_CONTROL +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec +//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_dscrm0_dispdec +//DSCRM0_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_dscrm1_dispdec +//DSCRM1_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_dscrm2_dispdec +//DSCRM2_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_dscrm3_dispdec +//DSCRM3_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_opp_top_dispdec +//OPP_TOP_CLK_CONTROL +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT 0x4 +#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT 0x8 +#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT 0xc +#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT 0xd +#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON__SHIFT 0xe +#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON__SHIFT 0xf +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK 0x00000010L +#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK 0x00000F00L +#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK 0x00001000L +#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK 0x00002000L +#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON_MASK 0x00004000L +#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON_MASK 0x00008000L +//OPP_ABM_CONTROL +#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL__SHIFT 0x0 +#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL_MASK 0x00000007L + + +// addressBlock: dce_dc_optc_odm0_dispdec +//ODM0_OPTC_INPUT_GLOBAL_CONTROL +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM0_OPTC_DATA_SOURCE_SELECT +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM0_OPTC_DATA_FORMAT_CONTROL +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM0_OPTC_BYTES_PER_PIXEL +#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM0_OPTC_WIDTH_CONTROL +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM0_OPTC_INPUT_CLOCK_CONTROL +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM0_OPTC_MEMORY_CONFIG +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM0_OPTC_INPUT_SPARE_REGISTER +#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm1_dispdec +//ODM1_OPTC_INPUT_GLOBAL_CONTROL +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM1_OPTC_DATA_SOURCE_SELECT +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM1_OPTC_DATA_FORMAT_CONTROL +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM1_OPTC_BYTES_PER_PIXEL +#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM1_OPTC_WIDTH_CONTROL +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM1_OPTC_INPUT_CLOCK_CONTROL +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM1_OPTC_MEMORY_CONFIG +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM1_OPTC_INPUT_SPARE_REGISTER +#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm2_dispdec +//ODM2_OPTC_INPUT_GLOBAL_CONTROL +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM2_OPTC_DATA_SOURCE_SELECT +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM2_OPTC_DATA_FORMAT_CONTROL +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM2_OPTC_BYTES_PER_PIXEL +#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM2_OPTC_WIDTH_CONTROL +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM2_OPTC_INPUT_CLOCK_CONTROL +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM2_OPTC_MEMORY_CONFIG +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM2_OPTC_INPUT_SPARE_REGISTER +#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm3_dispdec +//ODM3_OPTC_INPUT_GLOBAL_CONTROL +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM3_OPTC_DATA_SOURCE_SELECT +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM3_OPTC_DATA_FORMAT_CONTROL +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM3_OPTC_BYTES_PER_PIXEL +#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM3_OPTC_WIDTH_CONTROL +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM3_OPTC_INPUT_CLOCK_CONTROL +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM3_OPTC_MEMORY_CONFIG +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM3_OPTC_INPUT_SPARE_REGISTER +#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg0_dispdec +//OTG0_OTG_H_TOTAL +#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG0_OTG_H_BLANK_START_END +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG0_OTG_H_SYNC_A +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG0_OTG_H_SYNC_A_CNTL +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG0_OTG_H_TIMING_CNTL +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT 0x8 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT 0x10 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK 0x00000100L +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK 0x00030000L +//OTG0_OTG_V_TOTAL +#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MIN +#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MAX +#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MID +#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_CONTROL +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG0_OTG_V_TOTAL_INT_STATUS +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG0_OTG_VSYNC_NOM_INT_STATUS +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG0_OTG_V_BLANK_START_END +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG0_OTG_V_SYNC_A +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG0_OTG_V_SYNC_A_CNTL +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG0_OTG_TRIGA_CNTL +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG0_OTG_TRIGA_MANUAL_TRIG +#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG0_OTG_TRIGB_CNTL +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG0_OTG_TRIGB_MANUAL_TRIG +#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG0_OTG_FORCE_COUNT_NOW_CNTL +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG0_OTG_FLOW_CONTROL +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG0_OTG_STEREO_FORCE_NEXT_EYE +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG0_OTG_CONTROL +#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG0_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG0_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG0_OTG_INTERLACE_CONTROL +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG0_OTG_INTERLACE_STATUS +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG0_OTG_PIXEL_DATA_READBACK0 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG0_OTG_PIXEL_DATA_READBACK1 +#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG0_OTG_STATUS +#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG0_OTG_STATUS_POSITION +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG0_OTG_NOM_VERT_POSITION +#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG0_OTG_STATUS_FRAME_COUNT +#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG0_OTG_STATUS_VF_COUNT +#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG0_OTG_STATUS_HV_COUNT +#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG0_OTG_COUNT_CONTROL +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG0_OTG_COUNT_RESET +#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG0_OTG_VERT_SYNC_CONTROL +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG0_OTG_STEREO_STATUS +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG0_OTG_STEREO_CONTROL +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG0_OTG_SNAPSHOT_STATUS +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG0_OTG_SNAPSHOT_CONTROL +#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG0_OTG_SNAPSHOT_POSITION +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG0_OTG_SNAPSHOT_FRAME +#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG0_OTG_INTERRUPT_CONTROL +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG0_OTG_UPDATE_LOCK +#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG0_OTG_DOUBLE_BUFFER_CONTROL +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG0_OTG_MASTER_EN +#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_CRC_CNTL +#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT 0xa +#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK 0x00000400L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG0_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_DATA_RG +#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC0_DATA_B +#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_DATA_RG +#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC1_DATA_B +#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC2_DATA_RG +#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC2_DATA_B +#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC3_DATA_RG +#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC3_DATA_B +#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG0_OTG_STATIC_SCREEN_CONTROL +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG0_OTG_3D_STRUCTURE_CONTROL +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG0_OTG_GSL_VSYNC_GAP +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG0_OTG_MASTER_UPDATE_MODE +#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG0_OTG_CLOCK_CONTROL +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG0_OTG_VSTARTUP_PARAM +#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG0_OTG_VUPDATE_PARAM +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG0_OTG_VREADY_PARAM +#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG0_OTG_GLOBAL_SYNC_STATUS +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG0_OTG_MASTER_UPDATE_LOCK +#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG0_OTG_GSL_CONTROL +#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG0_OTG_GSL_WINDOW_X +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG0_OTG_GSL_WINDOW_Y +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG0_OTG_VUPDATE_KEEPOUT +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL0 +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL1 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL2 +#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL3 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG0_OTG_GLOBAL_CONTROL4 +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG0_OTG_TRIG_MANUAL_CONTROL +#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG0_OTG_MANUAL_FLOW_CONTROL +#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG0_OTG_DRR_TIMING_INT_STATUS +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG0_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG0_OTG_DRR_V_TOTAL_CHANGE +#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG0_OTG_DRR_TRIGGER_WINDOW +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG0_OTG_DRR_CONTROL +#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG0_OTG_M_CONST_DTO0 +#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG0_OTG_M_CONST_DTO1 +#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG0_OTG_REQUEST_CONTROL +#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG0_OTG_DSC_START_POSITION +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG0_OTG_PIPE_UPDATE_STATUS +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG0_OTG_SPARE_REGISTER +#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg1_dispdec +//OTG1_OTG_H_TOTAL +#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG1_OTG_H_BLANK_START_END +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG1_OTG_H_SYNC_A +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG1_OTG_H_SYNC_A_CNTL +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG1_OTG_H_TIMING_CNTL +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT 0x8 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT 0x10 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK 0x00000100L +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK 0x00030000L +//OTG1_OTG_V_TOTAL +#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MIN +#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MAX +#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MID +#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_CONTROL +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG1_OTG_V_TOTAL_INT_STATUS +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG1_OTG_VSYNC_NOM_INT_STATUS +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG1_OTG_V_BLANK_START_END +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG1_OTG_V_SYNC_A +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG1_OTG_V_SYNC_A_CNTL +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG1_OTG_TRIGA_CNTL +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG1_OTG_TRIGA_MANUAL_TRIG +#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG1_OTG_TRIGB_CNTL +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG1_OTG_TRIGB_MANUAL_TRIG +#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG1_OTG_FORCE_COUNT_NOW_CNTL +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG1_OTG_FLOW_CONTROL +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG1_OTG_STEREO_FORCE_NEXT_EYE +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG1_OTG_CONTROL +#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG1_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG1_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG1_OTG_INTERLACE_CONTROL +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG1_OTG_INTERLACE_STATUS +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG1_OTG_PIXEL_DATA_READBACK0 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG1_OTG_PIXEL_DATA_READBACK1 +#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG1_OTG_STATUS +#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG1_OTG_STATUS_POSITION +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG1_OTG_NOM_VERT_POSITION +#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG1_OTG_STATUS_FRAME_COUNT +#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG1_OTG_STATUS_VF_COUNT +#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG1_OTG_STATUS_HV_COUNT +#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG1_OTG_COUNT_CONTROL +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG1_OTG_COUNT_RESET +#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG1_OTG_VERT_SYNC_CONTROL +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG1_OTG_STEREO_STATUS +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG1_OTG_STEREO_CONTROL +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG1_OTG_SNAPSHOT_STATUS +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG1_OTG_SNAPSHOT_CONTROL +#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG1_OTG_SNAPSHOT_POSITION +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG1_OTG_SNAPSHOT_FRAME +#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG1_OTG_INTERRUPT_CONTROL +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG1_OTG_UPDATE_LOCK +#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG1_OTG_DOUBLE_BUFFER_CONTROL +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG1_OTG_MASTER_EN +#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_CRC_CNTL +#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT 0xa +#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK 0x00000400L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG1_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_DATA_RG +#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC0_DATA_B +#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_DATA_RG +#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC1_DATA_B +#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC2_DATA_RG +#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC2_DATA_B +#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC3_DATA_RG +#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC3_DATA_B +#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG1_OTG_STATIC_SCREEN_CONTROL +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG1_OTG_3D_STRUCTURE_CONTROL +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG1_OTG_GSL_VSYNC_GAP +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG1_OTG_MASTER_UPDATE_MODE +#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG1_OTG_CLOCK_CONTROL +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG1_OTG_VSTARTUP_PARAM +#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG1_OTG_VUPDATE_PARAM +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG1_OTG_VREADY_PARAM +#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG1_OTG_GLOBAL_SYNC_STATUS +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG1_OTG_MASTER_UPDATE_LOCK +#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG1_OTG_GSL_CONTROL +#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG1_OTG_GSL_WINDOW_X +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG1_OTG_GSL_WINDOW_Y +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG1_OTG_VUPDATE_KEEPOUT +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL0 +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL1 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL2 +#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL3 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG1_OTG_GLOBAL_CONTROL4 +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG1_OTG_TRIG_MANUAL_CONTROL +#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG1_OTG_MANUAL_FLOW_CONTROL +#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG1_OTG_DRR_TIMING_INT_STATUS +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG1_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG1_OTG_DRR_V_TOTAL_CHANGE +#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG1_OTG_DRR_TRIGGER_WINDOW +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG1_OTG_DRR_CONTROL +#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG1_OTG_M_CONST_DTO0 +#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG1_OTG_M_CONST_DTO1 +#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG1_OTG_REQUEST_CONTROL +#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG1_OTG_DSC_START_POSITION +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG1_OTG_PIPE_UPDATE_STATUS +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG1_OTG_SPARE_REGISTER +#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg2_dispdec +//OTG2_OTG_H_TOTAL +#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG2_OTG_H_BLANK_START_END +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG2_OTG_H_SYNC_A +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG2_OTG_H_SYNC_A_CNTL +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG2_OTG_H_TIMING_CNTL +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT 0x8 +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT 0x10 +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK 0x00000100L +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK 0x00030000L +//OTG2_OTG_V_TOTAL +#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MIN +#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MAX +#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MID +#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_CONTROL +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG2_OTG_V_TOTAL_INT_STATUS +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG2_OTG_VSYNC_NOM_INT_STATUS +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG2_OTG_V_BLANK_START_END +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG2_OTG_V_SYNC_A +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG2_OTG_V_SYNC_A_CNTL +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG2_OTG_TRIGA_CNTL +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG2_OTG_TRIGA_MANUAL_TRIG +#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG2_OTG_TRIGB_CNTL +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG2_OTG_TRIGB_MANUAL_TRIG +#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG2_OTG_FORCE_COUNT_NOW_CNTL +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG2_OTG_FLOW_CONTROL +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG2_OTG_STEREO_FORCE_NEXT_EYE +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG2_OTG_CONTROL +#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG2_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG2_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG2_OTG_INTERLACE_CONTROL +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG2_OTG_INTERLACE_STATUS +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG2_OTG_PIXEL_DATA_READBACK0 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG2_OTG_PIXEL_DATA_READBACK1 +#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG2_OTG_STATUS +#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG2_OTG_STATUS_POSITION +#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG2_OTG_NOM_VERT_POSITION +#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG2_OTG_STATUS_FRAME_COUNT +#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG2_OTG_STATUS_VF_COUNT +#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG2_OTG_STATUS_HV_COUNT +#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG2_OTG_COUNT_CONTROL +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG2_OTG_COUNT_RESET +#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG2_OTG_VERT_SYNC_CONTROL +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG2_OTG_STEREO_STATUS +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG2_OTG_STEREO_CONTROL +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG2_OTG_SNAPSHOT_STATUS +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG2_OTG_SNAPSHOT_CONTROL +#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG2_OTG_SNAPSHOT_POSITION +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG2_OTG_SNAPSHOT_FRAME +#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG2_OTG_INTERRUPT_CONTROL +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG2_OTG_UPDATE_LOCK +#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG2_OTG_DOUBLE_BUFFER_CONTROL +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG2_OTG_MASTER_EN +#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG2_OTG_CRC_CNTL +#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT 0xa +#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK 0x00000400L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG2_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_DATA_RG +#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC0_DATA_B +#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_DATA_RG +#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC1_DATA_B +#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC2_DATA_RG +#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC2_DATA_B +#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC3_DATA_RG +#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC3_DATA_B +#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG2_OTG_STATIC_SCREEN_CONTROL +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG2_OTG_3D_STRUCTURE_CONTROL +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG2_OTG_GSL_VSYNC_GAP +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG2_OTG_MASTER_UPDATE_MODE +#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG2_OTG_CLOCK_CONTROL +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG2_OTG_VSTARTUP_PARAM +#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG2_OTG_VUPDATE_PARAM +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG2_OTG_VREADY_PARAM +#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG2_OTG_GLOBAL_SYNC_STATUS +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG2_OTG_MASTER_UPDATE_LOCK +#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG2_OTG_GSL_CONTROL +#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG2_OTG_GSL_WINDOW_X +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG2_OTG_GSL_WINDOW_Y +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG2_OTG_VUPDATE_KEEPOUT +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL0 +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL1 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL2 +#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL3 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG2_OTG_GLOBAL_CONTROL4 +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG2_OTG_TRIG_MANUAL_CONTROL +#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG2_OTG_MANUAL_FLOW_CONTROL +#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG2_OTG_DRR_TIMING_INT_STATUS +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG2_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG2_OTG_DRR_V_TOTAL_CHANGE +#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG2_OTG_DRR_TRIGGER_WINDOW +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG2_OTG_DRR_CONTROL +#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG2_OTG_M_CONST_DTO0 +#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG2_OTG_M_CONST_DTO1 +#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG2_OTG_REQUEST_CONTROL +#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG2_OTG_DSC_START_POSITION +#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG2_OTG_PIPE_UPDATE_STATUS +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG2_OTG_SPARE_REGISTER +#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg3_dispdec +//OTG3_OTG_H_TOTAL +#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG3_OTG_H_BLANK_START_END +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG3_OTG_H_SYNC_A +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG3_OTG_H_SYNC_A_CNTL +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG3_OTG_H_TIMING_CNTL +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT 0x8 +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT 0x10 +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK 0x00000100L +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK 0x00030000L +//OTG3_OTG_V_TOTAL +#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MIN +#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MAX +#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MID +#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_CONTROL +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG3_OTG_V_TOTAL_INT_STATUS +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG3_OTG_VSYNC_NOM_INT_STATUS +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG3_OTG_V_BLANK_START_END +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG3_OTG_V_SYNC_A +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG3_OTG_V_SYNC_A_CNTL +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG3_OTG_TRIGA_CNTL +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG3_OTG_TRIGA_MANUAL_TRIG +#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG3_OTG_TRIGB_CNTL +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG3_OTG_TRIGB_MANUAL_TRIG +#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG3_OTG_FORCE_COUNT_NOW_CNTL +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG3_OTG_FLOW_CONTROL +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG3_OTG_STEREO_FORCE_NEXT_EYE +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG3_OTG_CONTROL +#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG3_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG3_OTG_INTERLACE_CONTROL +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG3_OTG_INTERLACE_STATUS +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG3_OTG_PIXEL_DATA_READBACK0 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG3_OTG_PIXEL_DATA_READBACK1 +#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG3_OTG_STATUS +#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG3_OTG_STATUS_POSITION +#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG3_OTG_NOM_VERT_POSITION +#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG3_OTG_STATUS_FRAME_COUNT +#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG3_OTG_STATUS_VF_COUNT +#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG3_OTG_STATUS_HV_COUNT +#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG3_OTG_COUNT_CONTROL +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG3_OTG_COUNT_RESET +#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG3_OTG_VERT_SYNC_CONTROL +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG3_OTG_STEREO_STATUS +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG3_OTG_STEREO_CONTROL +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG3_OTG_SNAPSHOT_STATUS +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG3_OTG_SNAPSHOT_CONTROL +#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG3_OTG_SNAPSHOT_POSITION +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG3_OTG_SNAPSHOT_FRAME +#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG3_OTG_INTERRUPT_CONTROL +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG3_OTG_UPDATE_LOCK +#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG3_OTG_DOUBLE_BUFFER_CONTROL +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG3_OTG_MASTER_EN +#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG3_OTG_CRC_CNTL +#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT 0xa +#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK 0x00000400L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG3_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_DATA_RG +#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC0_DATA_B +#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_DATA_RG +#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC1_DATA_B +#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC2_DATA_RG +#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC2_DATA_B +#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC3_DATA_RG +#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC3_DATA_B +#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG3_OTG_STATIC_SCREEN_CONTROL +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG3_OTG_3D_STRUCTURE_CONTROL +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG3_OTG_GSL_VSYNC_GAP +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG3_OTG_MASTER_UPDATE_MODE +#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG3_OTG_CLOCK_CONTROL +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG3_OTG_VSTARTUP_PARAM +#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG3_OTG_VUPDATE_PARAM +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG3_OTG_VREADY_PARAM +#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG3_OTG_GLOBAL_SYNC_STATUS +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG3_OTG_MASTER_UPDATE_LOCK +#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG3_OTG_GSL_CONTROL +#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG3_OTG_GSL_WINDOW_X +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG3_OTG_GSL_WINDOW_Y +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG3_OTG_VUPDATE_KEEPOUT +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL0 +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL1 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL2 +#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL3 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG3_OTG_GLOBAL_CONTROL4 +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG3_OTG_TRIG_MANUAL_CONTROL +#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG3_OTG_MANUAL_FLOW_CONTROL +#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG3_OTG_DRR_TIMING_INT_STATUS +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG3_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG3_OTG_DRR_V_TOTAL_CHANGE +#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG3_OTG_DRR_TRIGGER_WINDOW +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG3_OTG_DRR_CONTROL +#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG3_OTG_M_CONST_DTO0 +#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG3_OTG_M_CONST_DTO1 +#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG3_OTG_REQUEST_CONTROL +#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG3_OTG_DSC_START_POSITION +#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG3_OTG_PIPE_UPDATE_STATUS +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG3_OTG_SPARE_REGISTER +#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_optc_misc_dispdec +//GSL_SOURCE_SELECT +#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT 0x0 +#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT 0x4 +#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT 0x8 +#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT 0x10 +#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK 0x00000007L +#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK 0x00000070L +#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK 0x00000700L +#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK 0x00070000L +//OPTC_CLOCK_CONTROL +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT 0x1 +#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT 0x8 +#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS__SHIFT 0xf +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK 0x00000002L +#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK 0x00000F00L +#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS_MASK 0x00008000L +//ODM_MEM_PWR_CTRL +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT 0x0 +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT 0x2 +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT 0x4 +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT 0x6 +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT 0x8 +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT 0xa +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT 0xc +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT 0xe +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT 0x10 +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT 0x12 +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT 0x14 +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT 0x16 +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT 0x18 +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT 0x1a +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT 0x1c +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT 0x1e +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK 0x00000003L +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK 0x00000004L +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK 0x00000030L +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK 0x00000040L +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK 0x00000300L +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK 0x00000400L +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK 0x00003000L +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK 0x00004000L +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK 0x00030000L +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK 0x00040000L +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK 0x00300000L +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK 0x00400000L +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK 0x03000000L +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK 0x04000000L +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK 0x30000000L +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK 0x40000000L +//ODM_MEM_PWR_CTRL3 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT 0x0 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT 0x2 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK 0x00000003L +#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK 0x0000000CL +//ODM_MEM_PWR_STATUS +#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT 0x0 +#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT 0x2 +#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT 0x4 +#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT 0x6 +#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT 0x8 +#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT 0xa +#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT 0xc +#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT 0xe +#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK 0x00000003L +#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK 0x0000000CL +#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK 0x00000030L +#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK 0x000000C0L +#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK 0x00000300L +#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK 0x00000C00L +#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK 0x00003000L +#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK 0x0000C000L +//OPTC_MISC_SPARE_REGISTER +#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT 0x0 +#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK 0x000000FFL + + +// addressBlock: dce_dc_dio_hpd0_dispdec +//HPD0_DC_HPD_INT_STATUS +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD0_DC_HPD_INT_CONTROL +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD0_DC_HPD_CONTROL +#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD0_DC_HPD_FAST_TRAIN_CNTL +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD0_DC_HPD_TOGGLE_FILT_CNTL +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_hpd1_dispdec +//HPD1_DC_HPD_INT_STATUS +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD1_DC_HPD_INT_CONTROL +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD1_DC_HPD_CONTROL +#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD1_DC_HPD_FAST_TRAIN_CNTL +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD1_DC_HPD_TOGGLE_FILT_CNTL +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_hpd2_dispdec +//HPD2_DC_HPD_INT_STATUS +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD2_DC_HPD_INT_CONTROL +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD2_DC_HPD_CONTROL +#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD2_DC_HPD_FAST_TRAIN_CNTL +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD2_DC_HPD_TOGGLE_FILT_CNTL +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_hpd3_dispdec +//HPD3_DC_HPD_INT_STATUS +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD3_DC_HPD_INT_CONTROL +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD3_DC_HPD_CONTROL +#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD3_DC_HPD_FAST_TRAIN_CNTL +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD3_DC_HPD_TOGGLE_FILT_CNTL +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_hpd4_dispdec +//HPD4_DC_HPD_INT_STATUS +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD4_DC_HPD_INT_CONTROL +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD4_DC_HPD_CONTROL +#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD4_DC_HPD_FAST_TRAIN_CNTL +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD4_DC_HPD_TOGGLE_FILT_CNTL +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_dp0_dispdec +//DP0_DP_LINK_CNTL +#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP0_DP_PIXEL_FORMAT +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT 0x1e +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK 0x40000000L +//DP0_DP_MSA_COLORIMETRY +#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP0_DP_CONFIG +#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP0_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP0_DP_VID_STREAM_CNTL +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP0_DP_STEER_FIFO +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP0_DP_STEER_FIFO__DP_TU_SIZE__SHIFT 0x18 +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP0_DP_STEER_FIFO__DP_TU_SIZE_MASK 0x3F000000L +//DP0_DP_MSA_MISC +#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP0_DP_DPHY_INTERNAL_CTRL +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP0_DP_VID_TIMING +#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP0_DP_VID_N +#define DP0_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP0_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP0_DP_VID_M +#define DP0_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP0_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP0_DP_LINK_FRAMING_CNTL +#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP0_DP_HBR2_EYE_PATTERN +#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP0_DP_VID_MSA_VBID +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP0_DP_VID_INTERRUPT_CNTL +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP0_DP_DPHY_CNTL +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP0_DP_DPHY_TRAINING_PATTERN_SEL +#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP0_DP_DPHY_SYM0 +#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP0_DP_DPHY_SYM1 +#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP0_DP_DPHY_SYM2 +#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP0_DP_DPHY_8B10B_CNTL +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP0_DP_DPHY_PRBS_CNTL +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP0_DP_DPHY_SCRAM_CNTL +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP0_DP_DPHY_CRC_EN +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP0_DP_DPHY_CRC_CNTL +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP0_DP_DPHY_CRC_RESULT +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP0_DP_DPHY_CRC_MST_CNTL +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP0_DP_DPHY_CRC_MST_STATUS +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP0_DP_DPHY_FAST_TRAINING +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP0_DP_DPHY_FAST_TRAINING_STATUS +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP0_DP_SEC_CNTL +#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP0_DP_SEC_CNTL1 +#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING1 +#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING2 +#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING3 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING4 +#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP0_DP_SEC_AUD_N +#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_N_READBACK +#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_M +#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_M_READBACK +#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP0_DP_SEC_TIMESTAMP +#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP0_DP_SEC_PACKET_CNTL +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP0_DP_MSE_RATE_CNTL +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP0_DP_MSE_RATE_UPDATE +#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP0_DP_MSE_SAT0 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP0_DP_MSE_SAT1 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP0_DP_MSE_SAT2 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP0_DP_MSE_SAT_UPDATE +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP0_DP_MSE_LINK_TIMING +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP0_DP_MSE_MISC_CNTL +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP0_DP_DPHY_BS_SR_SWAP_CNTL +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP0_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP0_DP_MSE_SAT0_STATUS +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP0_DP_MSE_SAT1_STATUS +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP0_DP_MSE_SAT2_STATUS +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP0_DP_DPIA_SPARE +#define DP0_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT 0x0 +#define DP0_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK 0x00000003L +//DP0_DP_MSA_TIMING_PARAM1 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP0_DP_MSA_TIMING_PARAM2 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP0_DP_MSA_TIMING_PARAM3 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP0_DP_MSA_TIMING_PARAM4 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP0_DP_MSO_CNTL +#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP0_DP_MSO_CNTL1 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP0_DP_DSC_CNTL +#define DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000001L +//DP0_DP_SEC_CNTL2 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP0_DP_SEC_CNTL3 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL4 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL5 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL6 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP0_DP_SEC_CNTL7 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP0_DP_DB_CNTL +#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP0_DP_MSA_VBID_MISC +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_METADATA_TRANSMISSION +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP0_DP_ALPM_CNTL +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP8_CNTL +#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP9_CNTL +#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP10_CNTL +#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP11_CNTL +#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP_EN_DB_STATUS +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP0_DP_AUXLESS_ALPM_CNTL1 +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +//DP0_DP_AUXLESS_ALPM_CNTL2 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT 0x8 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0xf +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT 0x10 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x16 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x17 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT 0x18 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK 0x00003F00L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00008000L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK 0x000F0000L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00400000L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00800000L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK 0xFF000000L +//DP0_DP_AUXLESS_ALPM_CNTL3 +#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_AUXLESS_ALPM_CNTL4 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x0 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x8 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x9 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0xa +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0xb +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x0000007FL +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000100L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000200L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000400L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000800L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP0_DP_AUXLESS_ALPM_CNTL5 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dio_dig0_dispdec +//DIG0_DIG_FE_CNTL +#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG0_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT 0xf +#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG0_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK 0x00008000L +#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG0_DIG_OUTPUT_CRC_CNTL +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG0_DIG_OUTPUT_CRC_RESULT +#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG0_DIG_CLOCK_PATTERN +#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG0_DIG_TEST_PATTERN +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG0_DIG_RANDOM_PATTERN_SEED +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG0_DIG_FIFO_CTRL0 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x7 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT 0x8 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x0000007CL +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000080L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK 0x00000100L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG0_DIG_FIFO_CTRL1 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG0_HDMI_METADATA_PACKET_CONTROL +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_CONTROL +#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG0_HDMI_STATUS +#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG0_HDMI_AUDIO_PACKET_CONTROL +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG0_HDMI_ACR_PACKET_CONTROL +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG0_HDMI_VBI_PACKET_CONTROL +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG0_HDMI_INFOFRAME_CONTROL0 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG0_HDMI_INFOFRAME_CONTROL1 +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG0_HDMI_GC +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG0_HDMI_DB_CONTROL +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG0_HDMI_ACR_32_0 +#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_32_1 +#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_44_0 +#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_44_1 +#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_48_0 +#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_48_1 +#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_STATUS_0 +#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_STATUS_1 +#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG0_AFMT_CNTL +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG0_DIG_BE_CNTL +#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG0_DIG_BE_EN_CNTL +#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG0_TMDS_CNTL +#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG0_TMDS_CONTROL_CHAR +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG0_TMDS_CONTROL0_FEEDBACK +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG0_TMDS_STEREOSYNC_CTL_SEL +#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG0_TMDS_CTL_BITS +#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG0_TMDS_DCBALANCER_CONTROL +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG0_TMDS_SYNC_DCBALANCE_CHAR +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG0_TMDS_CTL0_1_GEN_CNTL +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG0_TMDS_CTL2_3_GEN_CNTL +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG0_DIG_VERSION +#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG0_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG0_FORCE_DIG_DISABLE +#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp1_dispdec +//DP1_DP_LINK_CNTL +#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP1_DP_PIXEL_FORMAT +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT 0x1e +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK 0x40000000L +//DP1_DP_MSA_COLORIMETRY +#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP1_DP_CONFIG +#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP1_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP1_DP_VID_STREAM_CNTL +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP1_DP_STEER_FIFO +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP1_DP_STEER_FIFO__DP_TU_SIZE__SHIFT 0x18 +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP1_DP_STEER_FIFO__DP_TU_SIZE_MASK 0x3F000000L +//DP1_DP_MSA_MISC +#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP1_DP_DPHY_INTERNAL_CTRL +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP1_DP_VID_TIMING +#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP1_DP_VID_N +#define DP1_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP1_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP1_DP_VID_M +#define DP1_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP1_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP1_DP_LINK_FRAMING_CNTL +#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP1_DP_HBR2_EYE_PATTERN +#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP1_DP_VID_MSA_VBID +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP1_DP_VID_INTERRUPT_CNTL +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP1_DP_DPHY_CNTL +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP1_DP_DPHY_TRAINING_PATTERN_SEL +#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP1_DP_DPHY_SYM0 +#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP1_DP_DPHY_SYM1 +#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP1_DP_DPHY_SYM2 +#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP1_DP_DPHY_8B10B_CNTL +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP1_DP_DPHY_PRBS_CNTL +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP1_DP_DPHY_SCRAM_CNTL +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP1_DP_DPHY_CRC_EN +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP1_DP_DPHY_CRC_CNTL +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP1_DP_DPHY_CRC_RESULT +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP1_DP_DPHY_CRC_MST_CNTL +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP1_DP_DPHY_CRC_MST_STATUS +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP1_DP_DPHY_FAST_TRAINING +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP1_DP_DPHY_FAST_TRAINING_STATUS +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP1_DP_SEC_CNTL +#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP1_DP_SEC_CNTL1 +#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING1 +#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING2 +#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING3 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING4 +#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP1_DP_SEC_AUD_N +#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_N_READBACK +#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_M +#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_M_READBACK +#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP1_DP_SEC_TIMESTAMP +#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP1_DP_SEC_PACKET_CNTL +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP1_DP_MSE_RATE_CNTL +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP1_DP_MSE_RATE_UPDATE +#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP1_DP_MSE_SAT0 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP1_DP_MSE_SAT1 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP1_DP_MSE_SAT2 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP1_DP_MSE_SAT_UPDATE +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP1_DP_MSE_LINK_TIMING +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP1_DP_MSE_MISC_CNTL +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP1_DP_DPHY_BS_SR_SWAP_CNTL +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP1_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP1_DP_MSE_SAT0_STATUS +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP1_DP_MSE_SAT1_STATUS +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP1_DP_MSE_SAT2_STATUS +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP1_DP_DPIA_SPARE +#define DP1_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT 0x0 +#define DP1_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK 0x00000003L +//DP1_DP_MSA_TIMING_PARAM1 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP1_DP_MSA_TIMING_PARAM2 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP1_DP_MSA_TIMING_PARAM3 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP1_DP_MSA_TIMING_PARAM4 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP1_DP_MSO_CNTL +#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP1_DP_MSO_CNTL1 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP1_DP_DSC_CNTL +#define DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000001L +//DP1_DP_SEC_CNTL2 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP1_DP_SEC_CNTL3 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL4 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL5 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL6 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP1_DP_SEC_CNTL7 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP1_DP_DB_CNTL +#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP1_DP_MSA_VBID_MISC +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_METADATA_TRANSMISSION +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP1_DP_ALPM_CNTL +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP8_CNTL +#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP9_CNTL +#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP10_CNTL +#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP11_CNTL +#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP_EN_DB_STATUS +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP1_DP_AUXLESS_ALPM_CNTL1 +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +//DP1_DP_AUXLESS_ALPM_CNTL2 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT 0x8 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0xf +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT 0x10 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x16 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x17 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT 0x18 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK 0x00003F00L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00008000L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK 0x000F0000L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00400000L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00800000L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK 0xFF000000L +//DP1_DP_AUXLESS_ALPM_CNTL3 +#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_AUXLESS_ALPM_CNTL4 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x0 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x8 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x9 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0xa +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0xb +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x0000007FL +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000100L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000200L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000400L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000800L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP1_DP_AUXLESS_ALPM_CNTL5 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dio_dig1_dispdec +//DIG1_DIG_FE_CNTL +#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG1_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT 0xf +#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG1_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK 0x00008000L +#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG1_DIG_OUTPUT_CRC_CNTL +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG1_DIG_OUTPUT_CRC_RESULT +#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG1_DIG_CLOCK_PATTERN +#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG1_DIG_TEST_PATTERN +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG1_DIG_RANDOM_PATTERN_SEED +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG1_DIG_FIFO_CTRL0 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x7 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT 0x8 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x0000007CL +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000080L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK 0x00000100L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG1_DIG_FIFO_CTRL1 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG1_HDMI_METADATA_PACKET_CONTROL +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_CONTROL +#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG1_HDMI_STATUS +#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG1_HDMI_AUDIO_PACKET_CONTROL +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG1_HDMI_ACR_PACKET_CONTROL +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG1_HDMI_VBI_PACKET_CONTROL +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG1_HDMI_INFOFRAME_CONTROL0 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG1_HDMI_INFOFRAME_CONTROL1 +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG1_HDMI_GC +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG1_HDMI_DB_CONTROL +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG1_HDMI_ACR_32_0 +#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_32_1 +#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_44_0 +#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_44_1 +#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_48_0 +#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_48_1 +#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_STATUS_0 +#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_STATUS_1 +#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG1_AFMT_CNTL +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG1_DIG_BE_CNTL +#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG1_DIG_BE_EN_CNTL +#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG1_TMDS_CNTL +#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG1_TMDS_CONTROL_CHAR +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG1_TMDS_CONTROL0_FEEDBACK +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG1_TMDS_STEREOSYNC_CTL_SEL +#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG1_TMDS_CTL_BITS +#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG1_TMDS_DCBALANCER_CONTROL +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG1_TMDS_SYNC_DCBALANCE_CHAR +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG1_TMDS_CTL0_1_GEN_CNTL +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG1_TMDS_CTL2_3_GEN_CNTL +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG1_DIG_VERSION +#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG1_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG1_FORCE_DIG_DISABLE +#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp2_dispdec +//DP2_DP_LINK_CNTL +#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP2_DP_PIXEL_FORMAT +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT 0x1e +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK 0x40000000L +//DP2_DP_MSA_COLORIMETRY +#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP2_DP_CONFIG +#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP2_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP2_DP_VID_STREAM_CNTL +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP2_DP_STEER_FIFO +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP2_DP_STEER_FIFO__DP_TU_SIZE__SHIFT 0x18 +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP2_DP_STEER_FIFO__DP_TU_SIZE_MASK 0x3F000000L +//DP2_DP_MSA_MISC +#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP2_DP_DPHY_INTERNAL_CTRL +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP2_DP_VID_TIMING +#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP2_DP_VID_N +#define DP2_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP2_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP2_DP_VID_M +#define DP2_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP2_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP2_DP_LINK_FRAMING_CNTL +#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP2_DP_HBR2_EYE_PATTERN +#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP2_DP_VID_MSA_VBID +#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP2_DP_VID_INTERRUPT_CNTL +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP2_DP_DPHY_CNTL +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP2_DP_DPHY_TRAINING_PATTERN_SEL +#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP2_DP_DPHY_SYM0 +#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP2_DP_DPHY_SYM1 +#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP2_DP_DPHY_SYM2 +#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP2_DP_DPHY_8B10B_CNTL +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP2_DP_DPHY_PRBS_CNTL +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP2_DP_DPHY_SCRAM_CNTL +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP2_DP_DPHY_CRC_EN +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP2_DP_DPHY_CRC_CNTL +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP2_DP_DPHY_CRC_RESULT +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP2_DP_DPHY_CRC_MST_CNTL +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP2_DP_DPHY_CRC_MST_STATUS +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP2_DP_DPHY_FAST_TRAINING +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP2_DP_DPHY_FAST_TRAINING_STATUS +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP2_DP_SEC_CNTL +#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP2_DP_SEC_CNTL1 +#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING1 +#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING2 +#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING3 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING4 +#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP2_DP_SEC_AUD_N +#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_N_READBACK +#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_M +#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_M_READBACK +#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP2_DP_SEC_TIMESTAMP +#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP2_DP_SEC_PACKET_CNTL +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP2_DP_MSE_RATE_CNTL +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP2_DP_MSE_RATE_UPDATE +#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP2_DP_MSE_SAT0 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP2_DP_MSE_SAT1 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP2_DP_MSE_SAT2 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP2_DP_MSE_SAT_UPDATE +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP2_DP_MSE_LINK_TIMING +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP2_DP_MSE_MISC_CNTL +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP2_DP_DPHY_BS_SR_SWAP_CNTL +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP2_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP2_DP_MSE_SAT0_STATUS +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP2_DP_MSE_SAT1_STATUS +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP2_DP_MSE_SAT2_STATUS +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP2_DP_DPIA_SPARE +#define DP2_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT 0x0 +#define DP2_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK 0x00000003L +//DP2_DP_MSA_TIMING_PARAM1 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP2_DP_MSA_TIMING_PARAM2 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP2_DP_MSA_TIMING_PARAM3 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP2_DP_MSA_TIMING_PARAM4 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP2_DP_MSO_CNTL +#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP2_DP_MSO_CNTL1 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP2_DP_DSC_CNTL +#define DP2_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP2_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000001L +//DP2_DP_SEC_CNTL2 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP2_DP_SEC_CNTL3 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL4 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL5 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL6 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP2_DP_SEC_CNTL7 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP2_DP_DB_CNTL +#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP2_DP_MSA_VBID_MISC +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_METADATA_TRANSMISSION +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP2_DP_ALPM_CNTL +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP8_CNTL +#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP9_CNTL +#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP10_CNTL +#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP11_CNTL +#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP_EN_DB_STATUS +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP2_DP_AUXLESS_ALPM_CNTL1 +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +//DP2_DP_AUXLESS_ALPM_CNTL2 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT 0x8 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0xf +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT 0x10 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x16 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x17 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT 0x18 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK 0x00003F00L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00008000L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK 0x000F0000L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00400000L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00800000L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK 0xFF000000L +//DP2_DP_AUXLESS_ALPM_CNTL3 +#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_AUXLESS_ALPM_CNTL4 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x0 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x8 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x9 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0xa +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0xb +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x0000007FL +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000100L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000200L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000400L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000800L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP2_DP_AUXLESS_ALPM_CNTL5 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dio_dig2_dispdec +//DIG2_DIG_FE_CNTL +#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG2_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT 0xf +#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG2_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK 0x00008000L +#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG2_DIG_OUTPUT_CRC_CNTL +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG2_DIG_OUTPUT_CRC_RESULT +#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG2_DIG_CLOCK_PATTERN +#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG2_DIG_TEST_PATTERN +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG2_DIG_RANDOM_PATTERN_SEED +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG2_DIG_FIFO_CTRL0 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x7 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT 0x8 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x0000007CL +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000080L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK 0x00000100L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG2_DIG_FIFO_CTRL1 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG2_HDMI_METADATA_PACKET_CONTROL +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_CONTROL +#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG2_HDMI_STATUS +#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG2_HDMI_AUDIO_PACKET_CONTROL +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG2_HDMI_ACR_PACKET_CONTROL +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG2_HDMI_VBI_PACKET_CONTROL +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG2_HDMI_INFOFRAME_CONTROL0 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG2_HDMI_INFOFRAME_CONTROL1 +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG2_HDMI_GC +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG2_HDMI_DB_CONTROL +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG2_HDMI_ACR_32_0 +#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_32_1 +#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_44_0 +#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_44_1 +#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_48_0 +#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_48_1 +#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_STATUS_0 +#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_STATUS_1 +#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG2_AFMT_CNTL +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG2_DIG_BE_CNTL +#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG2_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG2_DIG_BE_EN_CNTL +#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG2_TMDS_CNTL +#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG2_TMDS_CONTROL_CHAR +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG2_TMDS_CONTROL0_FEEDBACK +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG2_TMDS_STEREOSYNC_CTL_SEL +#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG2_TMDS_CTL_BITS +#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG2_TMDS_DCBALANCER_CONTROL +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG2_TMDS_SYNC_DCBALANCE_CHAR +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG2_TMDS_CTL0_1_GEN_CNTL +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG2_TMDS_CTL2_3_GEN_CNTL +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG2_DIG_VERSION +#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG2_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG2_FORCE_DIG_DISABLE +#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp3_dispdec +//DP3_DP_LINK_CNTL +#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP3_DP_PIXEL_FORMAT +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT 0x1e +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK 0x40000000L +//DP3_DP_MSA_COLORIMETRY +#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP3_DP_CONFIG +#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP3_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP3_DP_VID_STREAM_CNTL +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP3_DP_STEER_FIFO +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP3_DP_STEER_FIFO__DP_TU_SIZE__SHIFT 0x18 +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP3_DP_STEER_FIFO__DP_TU_SIZE_MASK 0x3F000000L +//DP3_DP_MSA_MISC +#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP3_DP_DPHY_INTERNAL_CTRL +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP3_DP_VID_TIMING +#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP3_DP_VID_N +#define DP3_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP3_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP3_DP_VID_M +#define DP3_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP3_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP3_DP_LINK_FRAMING_CNTL +#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP3_DP_HBR2_EYE_PATTERN +#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP3_DP_VID_MSA_VBID +#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP3_DP_VID_INTERRUPT_CNTL +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP3_DP_DPHY_CNTL +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP3_DP_DPHY_TRAINING_PATTERN_SEL +#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP3_DP_DPHY_SYM0 +#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP3_DP_DPHY_SYM1 +#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP3_DP_DPHY_SYM2 +#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP3_DP_DPHY_8B10B_CNTL +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP3_DP_DPHY_PRBS_CNTL +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP3_DP_DPHY_SCRAM_CNTL +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP3_DP_DPHY_CRC_EN +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP3_DP_DPHY_CRC_CNTL +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP3_DP_DPHY_CRC_RESULT +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP3_DP_DPHY_CRC_MST_CNTL +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP3_DP_DPHY_CRC_MST_STATUS +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP3_DP_DPHY_FAST_TRAINING +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP3_DP_DPHY_FAST_TRAINING_STATUS +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP3_DP_SEC_CNTL +#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP3_DP_SEC_CNTL1 +#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING1 +#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING2 +#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING3 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING4 +#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP3_DP_SEC_AUD_N +#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_N_READBACK +#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_M +#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_M_READBACK +#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP3_DP_SEC_TIMESTAMP +#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP3_DP_SEC_PACKET_CNTL +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP3_DP_MSE_RATE_CNTL +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP3_DP_MSE_RATE_UPDATE +#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP3_DP_MSE_SAT0 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP3_DP_MSE_SAT1 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP3_DP_MSE_SAT2 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP3_DP_MSE_SAT_UPDATE +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP3_DP_MSE_LINK_TIMING +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP3_DP_MSE_MISC_CNTL +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP3_DP_DPHY_BS_SR_SWAP_CNTL +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP3_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP3_DP_MSE_SAT0_STATUS +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP3_DP_MSE_SAT1_STATUS +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP3_DP_MSE_SAT2_STATUS +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP3_DP_DPIA_SPARE +#define DP3_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT 0x0 +#define DP3_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK 0x00000003L +//DP3_DP_MSA_TIMING_PARAM1 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP3_DP_MSA_TIMING_PARAM2 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP3_DP_MSA_TIMING_PARAM3 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP3_DP_MSA_TIMING_PARAM4 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP3_DP_MSO_CNTL +#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP3_DP_MSO_CNTL1 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP3_DP_DSC_CNTL +#define DP3_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP3_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000001L +//DP3_DP_SEC_CNTL2 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP3_DP_SEC_CNTL3 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL4 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL5 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL6 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP3_DP_SEC_CNTL7 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP3_DP_DB_CNTL +#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP3_DP_MSA_VBID_MISC +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_METADATA_TRANSMISSION +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP3_DP_ALPM_CNTL +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP8_CNTL +#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP9_CNTL +#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP10_CNTL +#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP11_CNTL +#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP_EN_DB_STATUS +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP3_DP_AUXLESS_ALPM_CNTL1 +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +//DP3_DP_AUXLESS_ALPM_CNTL2 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT 0x8 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0xf +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT 0x10 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x16 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x17 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT 0x18 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK 0x00003F00L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00008000L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK 0x000F0000L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00400000L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00800000L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK 0xFF000000L +//DP3_DP_AUXLESS_ALPM_CNTL3 +#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_AUXLESS_ALPM_CNTL4 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x0 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x8 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x9 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0xa +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0xb +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x0000007FL +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000100L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000200L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000400L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000800L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP3_DP_AUXLESS_ALPM_CNTL5 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dio_dig3_dispdec +//DIG3_DIG_FE_CNTL +#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG3_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT 0xf +#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG3_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK 0x00008000L +#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG3_DIG_OUTPUT_CRC_CNTL +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG3_DIG_OUTPUT_CRC_RESULT +#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG3_DIG_CLOCK_PATTERN +#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG3_DIG_TEST_PATTERN +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG3_DIG_RANDOM_PATTERN_SEED +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG3_DIG_FIFO_CTRL0 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x7 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT 0x8 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x0000007CL +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000080L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK 0x00000100L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG3_DIG_FIFO_CTRL1 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG3_HDMI_METADATA_PACKET_CONTROL +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_CONTROL +#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG3_HDMI_STATUS +#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG3_HDMI_AUDIO_PACKET_CONTROL +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG3_HDMI_ACR_PACKET_CONTROL +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG3_HDMI_VBI_PACKET_CONTROL +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG3_HDMI_INFOFRAME_CONTROL0 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG3_HDMI_INFOFRAME_CONTROL1 +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG3_HDMI_GC +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG3_HDMI_DB_CONTROL +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG3_HDMI_ACR_32_0 +#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_32_1 +#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_44_0 +#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_44_1 +#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_48_0 +#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_48_1 +#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_STATUS_0 +#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_STATUS_1 +#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG3_AFMT_CNTL +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG3_DIG_BE_CNTL +#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG3_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG3_DIG_BE_EN_CNTL +#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG3_TMDS_CNTL +#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG3_TMDS_CONTROL_CHAR +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG3_TMDS_CONTROL0_FEEDBACK +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG3_TMDS_STEREOSYNC_CTL_SEL +#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG3_TMDS_CTL_BITS +#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG3_TMDS_DCBALANCER_CONTROL +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG3_TMDS_SYNC_DCBALANCE_CHAR +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG3_TMDS_CTL0_1_GEN_CNTL +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG3_TMDS_CTL2_3_GEN_CNTL +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG3_DIG_VERSION +#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG3_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG3_FORCE_DIG_DISABLE +#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp4_dispdec +//DP4_DP_LINK_CNTL +#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP4_DP_PIXEL_FORMAT +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT 0x1e +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK 0x40000000L +//DP4_DP_MSA_COLORIMETRY +#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP4_DP_CONFIG +#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP4_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP4_DP_VID_STREAM_CNTL +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP4_DP_STEER_FIFO +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP4_DP_STEER_FIFO__DP_TU_SIZE__SHIFT 0x18 +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP4_DP_STEER_FIFO__DP_TU_SIZE_MASK 0x3F000000L +//DP4_DP_MSA_MISC +#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP4_DP_DPHY_INTERNAL_CTRL +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP4_DP_VID_TIMING +#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP4_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP4_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP4_DP_VID_N +#define DP4_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP4_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP4_DP_VID_M +#define DP4_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP4_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP4_DP_LINK_FRAMING_CNTL +#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP4_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP4_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP4_DP_HBR2_EYE_PATTERN +#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP4_DP_VID_MSA_VBID +#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP4_DP_VID_INTERRUPT_CNTL +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP4_DP_DPHY_CNTL +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP4_DP_DPHY_TRAINING_PATTERN_SEL +#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP4_DP_DPHY_SYM0 +#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP4_DP_DPHY_SYM1 +#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP4_DP_DPHY_SYM2 +#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP4_DP_DPHY_8B10B_CNTL +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP4_DP_DPHY_PRBS_CNTL +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP4_DP_DPHY_SCRAM_CNTL +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP4_DP_DPHY_CRC_EN +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP4_DP_DPHY_CRC_CNTL +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP4_DP_DPHY_CRC_RESULT +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP4_DP_DPHY_CRC_MST_CNTL +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP4_DP_DPHY_CRC_MST_STATUS +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP4_DP_DPHY_FAST_TRAINING +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP4_DP_DPHY_FAST_TRAINING_STATUS +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP4_DP_SEC_CNTL +#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP4_DP_SEC_CNTL1 +#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING1 +#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING2 +#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING3 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING4 +#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP4_DP_SEC_AUD_N +#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_N_READBACK +#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_M +#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_M_READBACK +#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP4_DP_SEC_TIMESTAMP +#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP4_DP_SEC_PACKET_CNTL +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP4_DP_MSE_RATE_CNTL +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP4_DP_MSE_RATE_UPDATE +#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP4_DP_MSE_SAT0 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP4_DP_MSE_SAT1 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP4_DP_MSE_SAT2 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP4_DP_MSE_SAT_UPDATE +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP4_DP_MSE_LINK_TIMING +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP4_DP_MSE_MISC_CNTL +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP4_DP_DPHY_BS_SR_SWAP_CNTL +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP4_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP4_DP_MSE_SAT0_STATUS +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP4_DP_MSE_SAT1_STATUS +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP4_DP_MSE_SAT2_STATUS +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP4_DP_DPIA_SPARE +#define DP4_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT 0x0 +#define DP4_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK 0x00000003L +//DP4_DP_MSA_TIMING_PARAM1 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP4_DP_MSA_TIMING_PARAM2 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP4_DP_MSA_TIMING_PARAM3 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP4_DP_MSA_TIMING_PARAM4 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP4_DP_MSO_CNTL +#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP4_DP_MSO_CNTL1 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP4_DP_DSC_CNTL +#define DP4_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP4_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000001L +//DP4_DP_SEC_CNTL2 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP4_DP_SEC_CNTL3 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL4 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL5 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL6 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP4_DP_SEC_CNTL7 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP4_DP_DB_CNTL +#define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP4_DP_MSA_VBID_MISC +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_METADATA_TRANSMISSION +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP4_DP_ALPM_CNTL +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP4_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP4_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP8_CNTL +#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP9_CNTL +#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP10_CNTL +#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP11_CNTL +#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP_EN_DB_STATUS +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP4_DP_AUXLESS_ALPM_CNTL1 +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +//DP4_DP_AUXLESS_ALPM_CNTL2 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT 0x8 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0xf +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT 0x10 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x16 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x17 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT 0x18 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK 0x00003F00L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00008000L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK 0x000F0000L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00400000L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00800000L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK 0xFF000000L +//DP4_DP_AUXLESS_ALPM_CNTL3 +#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_AUXLESS_ALPM_CNTL4 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x0 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x8 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x9 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0xa +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0xb +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x0000007FL +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000100L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000200L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000400L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000800L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP4_DP_AUXLESS_ALPM_CNTL5 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dio_dig4_dispdec +//DIG4_DIG_FE_CNTL +#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG4_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT 0xf +#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG4_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK 0x00008000L +#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG4_DIG_OUTPUT_CRC_CNTL +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG4_DIG_OUTPUT_CRC_RESULT +#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG4_DIG_CLOCK_PATTERN +#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG4_DIG_TEST_PATTERN +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG4_DIG_RANDOM_PATTERN_SEED +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG4_DIG_FIFO_CTRL0 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x7 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT 0x8 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x0000007CL +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000080L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK 0x00000100L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG4_DIG_FIFO_CTRL1 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG4_HDMI_METADATA_PACKET_CONTROL +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_CONTROL +#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG4_HDMI_STATUS +#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG4_HDMI_AUDIO_PACKET_CONTROL +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG4_HDMI_ACR_PACKET_CONTROL +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG4_HDMI_VBI_PACKET_CONTROL +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG4_HDMI_INFOFRAME_CONTROL0 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG4_HDMI_INFOFRAME_CONTROL1 +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG4_HDMI_GC +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG4_HDMI_DB_CONTROL +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG4_HDMI_ACR_32_0 +#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_32_1 +#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_44_0 +#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_44_1 +#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_48_0 +#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_48_1 +#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_STATUS_0 +#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_STATUS_1 +#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG4_AFMT_CNTL +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG4_DIG_BE_CNTL +#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG4_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG4_DIG_BE_EN_CNTL +#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG4_TMDS_CNTL +#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG4_TMDS_CONTROL_CHAR +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG4_TMDS_CONTROL0_FEEDBACK +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG4_TMDS_STEREOSYNC_CTL_SEL +#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG4_TMDS_CTL_BITS +#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG4_TMDS_DCBALANCER_CONTROL +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG4_TMDS_SYNC_DCBALANCE_CHAR +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG4_TMDS_CTL0_1_GEN_CNTL +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG4_TMDS_CTL2_3_GEN_CNTL +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG4_DIG_VERSION +#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG4_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG4_FORCE_DIG_DISABLE +#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec +//AFMT0_AFMT_VBI_PACKET_CONTROL +#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT0_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT0_AFMT_AUDIO_INFO0 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT0_AFMT_AUDIO_INFO1 +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT0_AFMT_60958_0 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT0_AFMT_60958_1 +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT0_AFMT_AUDIO_CRC_CONTROL +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT0_AFMT_RAMP_CONTROL0 +#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT0_AFMT_RAMP_CONTROL1 +#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT0_AFMT_RAMP_CONTROL2 +#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT0_AFMT_RAMP_CONTROL3 +#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT0_AFMT_60958_2 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT0_AFMT_AUDIO_CRC_RESULT +#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT0_AFMT_STATUS +#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT0_AFMT_AUDIO_PACKET_CONTROL +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT0_AFMT_INFOFRAME_CONTROL0 +#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT0_AFMT_INTERRUPT_STATUS +//AFMT0_AFMT_AUDIO_SRC_CONTROL +#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT0_AFMT_MEM_PWR +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec +//AFMT1_AFMT_VBI_PACKET_CONTROL +#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT1_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT1_AFMT_AUDIO_INFO0 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT1_AFMT_AUDIO_INFO1 +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT1_AFMT_60958_0 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT1_AFMT_60958_1 +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT1_AFMT_AUDIO_CRC_CONTROL +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT1_AFMT_RAMP_CONTROL0 +#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT1_AFMT_RAMP_CONTROL1 +#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT1_AFMT_RAMP_CONTROL2 +#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT1_AFMT_RAMP_CONTROL3 +#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT1_AFMT_60958_2 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT1_AFMT_AUDIO_CRC_RESULT +#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT1_AFMT_STATUS +#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT1_AFMT_AUDIO_PACKET_CONTROL +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT1_AFMT_INFOFRAME_CONTROL0 +#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT1_AFMT_INTERRUPT_STATUS +//AFMT1_AFMT_AUDIO_SRC_CONTROL +#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT1_AFMT_MEM_PWR +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec +//AFMT2_AFMT_VBI_PACKET_CONTROL +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT2_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT2_AFMT_AUDIO_INFO0 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT2_AFMT_AUDIO_INFO1 +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT2_AFMT_60958_0 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT2_AFMT_60958_1 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT2_AFMT_AUDIO_CRC_CONTROL +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT2_AFMT_RAMP_CONTROL0 +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT2_AFMT_RAMP_CONTROL1 +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT2_AFMT_RAMP_CONTROL2 +#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT2_AFMT_RAMP_CONTROL3 +#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT2_AFMT_60958_2 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT2_AFMT_AUDIO_CRC_RESULT +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT2_AFMT_STATUS +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT2_AFMT_AUDIO_PACKET_CONTROL +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT2_AFMT_INFOFRAME_CONTROL0 +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT2_AFMT_INTERRUPT_STATUS +//AFMT2_AFMT_AUDIO_SRC_CONTROL +#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT2_AFMT_MEM_PWR +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec +//AFMT3_AFMT_VBI_PACKET_CONTROL +#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT3_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT3_AFMT_AUDIO_INFO0 +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT3_AFMT_AUDIO_INFO1 +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT3_AFMT_60958_0 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT3_AFMT_60958_1 +#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT3_AFMT_AUDIO_CRC_CONTROL +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT3_AFMT_RAMP_CONTROL0 +#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT3_AFMT_RAMP_CONTROL1 +#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT3_AFMT_RAMP_CONTROL2 +#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT3_AFMT_RAMP_CONTROL3 +#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT3_AFMT_60958_2 +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT3_AFMT_AUDIO_CRC_RESULT +#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT3_AFMT_STATUS +#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT3_AFMT_AUDIO_PACKET_CONTROL +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT3_AFMT_INFOFRAME_CONTROL0 +#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT3_AFMT_INTERRUPT_STATUS +//AFMT3_AFMT_AUDIO_SRC_CONTROL +#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT3_AFMT_MEM_PWR +#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec +//AFMT4_AFMT_VBI_PACKET_CONTROL +#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT4_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT4_AFMT_AUDIO_INFO0 +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT4_AFMT_AUDIO_INFO1 +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT4_AFMT_60958_0 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT4_AFMT_60958_1 +#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT4_AFMT_AUDIO_CRC_CONTROL +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT4_AFMT_RAMP_CONTROL0 +#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT4_AFMT_RAMP_CONTROL1 +#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT4_AFMT_RAMP_CONTROL2 +#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT4_AFMT_RAMP_CONTROL3 +#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT4_AFMT_60958_2 +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT4_AFMT_AUDIO_CRC_RESULT +#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT4_AFMT_STATUS +#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT4_AFMT_AUDIO_PACKET_CONTROL +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT4_AFMT_INFOFRAME_CONTROL0 +#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT4_AFMT_INTERRUPT_STATUS +//AFMT4_AFMT_AUDIO_SRC_CONTROL +#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT4_AFMT_MEM_PWR +#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec +//DME0_DME_CONTROL +#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME0_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME0_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME0_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME0_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME0_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME0_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME0_DME_MEMORY_CONTROL +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec +//VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG0_VPG_GENERIC_PACKET_DATA +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG0_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG0_VPG_GENERIC_STATUS +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG0_VPG_MEM_PWR +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG0_VPG_ISRC1_2_ACCESS_CTRL +#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG0_VPG_ISRC1_2_DATA +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG0_VPG_MPEG_INFO0 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG0_VPG_MPEG_INFO1 +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec +//DME1_DME_CONTROL +#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME1_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME1_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME1_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME1_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME1_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME1_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME1_DME_MEMORY_CONTROL +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec +//VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG1_VPG_GENERIC_PACKET_DATA +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG1_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG1_VPG_GENERIC_STATUS +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG1_VPG_MEM_PWR +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG1_VPG_ISRC1_2_ACCESS_CTRL +#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG1_VPG_ISRC1_2_DATA +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG1_VPG_MPEG_INFO0 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG1_VPG_MPEG_INFO1 +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec +//DME2_DME_CONTROL +#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME2_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME2_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME2_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME2_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME2_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME2_DME_MEMORY_CONTROL +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec +//VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG2_VPG_GENERIC_PACKET_DATA +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG2_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG2_VPG_GENERIC_STATUS +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG2_VPG_MEM_PWR +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG2_VPG_ISRC1_2_ACCESS_CTRL +#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG2_VPG_ISRC1_2_DATA +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG2_VPG_MPEG_INFO0 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG2_VPG_MPEG_INFO1 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec +//DME3_DME_CONTROL +#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME3_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME3_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME3_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME3_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME3_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME3_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME3_DME_MEMORY_CONTROL +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec +//VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG3_VPG_GENERIC_PACKET_DATA +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG3_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG3_VPG_GENERIC_STATUS +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG3_VPG_MEM_PWR +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG3_VPG_ISRC1_2_ACCESS_CTRL +#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG3_VPG_ISRC1_2_DATA +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG3_VPG_MPEG_INFO0 +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG3_VPG_MPEG_INFO1 +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec +//DME4_DME_CONTROL +#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME4_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME4_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME4_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME4_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME4_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME4_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME4_DME_MEMORY_CONTROL +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec +//VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG4_VPG_GENERIC_PACKET_DATA +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG4_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG4_VPG_GENERIC_STATUS +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG4_VPG_MEM_PWR +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG4_VPG_ISRC1_2_ACCESS_CTRL +#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG4_VPG_ISRC1_2_DATA +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG4_VPG_MPEG_INFO0 +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG4_VPG_MPEG_INFO1 +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_dio_dp_aux0_dispdec +//DP_AUX0_AUX_CONTROL +#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX0_AUX_SW_CONTROL +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX0_AUX_ARB_CONTROL +#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX0_AUX_INTERRUPT_CONTROL +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX0_AUX_SW_STATUS +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX0_AUX_LS_STATUS +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX0_AUX_SW_DATA +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX0_AUX_LS_DATA +#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX0_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX0_AUX_DPHY_TX_CONTROL +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX0_AUX_DPHY_RX_CONTROL0 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX0_AUX_DPHY_RX_CONTROL1 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX0_AUX_DPHY_TX_STATUS +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX0_AUX_DPHY_RX_STATUS +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX0_AUX_GTC_SYNC_CONTROL +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX0_AUX_GTC_SYNC_STATUS +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX0_AUX_PHY_WAKE_CNTL +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dce_dc_dio_dp_aux1_dispdec +//DP_AUX1_AUX_CONTROL +#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX1_AUX_SW_CONTROL +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX1_AUX_ARB_CONTROL +#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX1_AUX_INTERRUPT_CONTROL +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX1_AUX_SW_STATUS +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX1_AUX_LS_STATUS +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX1_AUX_SW_DATA +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX1_AUX_LS_DATA +#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX1_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX1_AUX_DPHY_TX_CONTROL +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX1_AUX_DPHY_RX_CONTROL0 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX1_AUX_DPHY_RX_CONTROL1 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX1_AUX_DPHY_TX_STATUS +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX1_AUX_DPHY_RX_STATUS +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX1_AUX_GTC_SYNC_CONTROL +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX1_AUX_GTC_SYNC_STATUS +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX1_AUX_PHY_WAKE_CNTL +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dce_dc_dio_dp_aux2_dispdec +//DP_AUX2_AUX_CONTROL +#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX2_AUX_SW_CONTROL +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX2_AUX_ARB_CONTROL +#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX2_AUX_INTERRUPT_CONTROL +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX2_AUX_SW_STATUS +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX2_AUX_LS_STATUS +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX2_AUX_SW_DATA +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX2_AUX_LS_DATA +#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX2_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX2_AUX_DPHY_TX_CONTROL +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX2_AUX_DPHY_RX_CONTROL0 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX2_AUX_DPHY_RX_CONTROL1 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX2_AUX_DPHY_TX_STATUS +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX2_AUX_DPHY_RX_STATUS +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX2_AUX_GTC_SYNC_CONTROL +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX2_AUX_GTC_SYNC_STATUS +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX2_AUX_PHY_WAKE_CNTL +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dce_dc_dio_dp_aux3_dispdec +//DP_AUX3_AUX_CONTROL +#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX3_AUX_SW_CONTROL +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX3_AUX_ARB_CONTROL +#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX3_AUX_INTERRUPT_CONTROL +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX3_AUX_SW_STATUS +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX3_AUX_LS_STATUS +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX3_AUX_SW_DATA +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX3_AUX_LS_DATA +#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX3_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX3_AUX_DPHY_TX_CONTROL +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX3_AUX_DPHY_RX_CONTROL0 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX3_AUX_DPHY_RX_CONTROL1 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX3_AUX_DPHY_TX_STATUS +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX3_AUX_DPHY_RX_STATUS +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX3_AUX_GTC_SYNC_CONTROL +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX3_AUX_GTC_SYNC_STATUS +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX3_AUX_PHY_WAKE_CNTL +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dce_dc_dio_dp_aux4_dispdec +//DP_AUX4_AUX_CONTROL +#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX4_AUX_SW_CONTROL +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX4_AUX_ARB_CONTROL +#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX4_AUX_INTERRUPT_CONTROL +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX4_AUX_SW_STATUS +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX4_AUX_LS_STATUS +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX4_AUX_SW_DATA +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX4_AUX_LS_DATA +#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX4_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX4_AUX_DPHY_TX_CONTROL +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX4_AUX_DPHY_RX_CONTROL0 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX4_AUX_DPHY_RX_CONTROL1 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX4_AUX_DPHY_TX_STATUS +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX4_AUX_DPHY_RX_STATUS +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX4_AUX_GTC_SYNC_CONTROL +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX4_AUX_GTC_SYNC_STATUS +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX4_AUX_PHY_WAKE_CNTL +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dce_dc_dio_dout_i2c_dispdec +//DC_I2C_CONTROL +#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3 +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14 +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f +#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000L +//DC_I2C_ARBITRATION +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0 +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19 +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L +//DC_I2C_INTERRUPT_CONTROL +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L +//DC_I2C_SW_STATUS +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L +//DC_I2C_DDC1_HW_STATUS +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC2_HW_STATUS +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC3_HW_STATUS +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC4_HW_STATUS +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC5_HW_STATUS +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC1_SPEED +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC1_SETUP +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC2_SPEED +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC2_SETUP +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC3_SPEED +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC3_SETUP +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC4_SPEED +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC4_SETUP +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC5_SPEED +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC5_SETUP +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_TRANSACTION0 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8 +#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L +#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x03FF0000L +//DC_I2C_TRANSACTION1 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8 +#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L +#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x03FF0000L +//DC_I2C_TRANSACTION2 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8 +#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L +#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x03FF0000L +//DC_I2C_TRANSACTION3 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8 +#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L +#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x03FF0000L +//DC_I2C_DATA +#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0 +#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8 +#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f +#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L +#define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000FF00L +#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x03FF0000L +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L +//DC_I2C_EDID_DETECT_CTRL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000FFFFL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00F00000L +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L +//DC_I2C_READ_REQUEST_INTERRUPT +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x00000001L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x00000002L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x00000004L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x00000008L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x00000010L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x00000020L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x00000040L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x00000080L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x00000100L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x00000200L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x00000400L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x00000800L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x00001000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x00002000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x00004000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x00008000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x00010000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x00020000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x00040000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x00080000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x00100000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x00200000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x00400000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x00800000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x01000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x02000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x04000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x08000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000L + + +// addressBlock: dce_dc_dio_dio_misc_dispdec +//DIO_SCRATCH0 +#define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT 0x0 +#define DIO_SCRATCH0__DIO_SCRATCH0_MASK 0xFFFFFFFFL +//DIO_SCRATCH1 +#define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT 0x0 +#define DIO_SCRATCH1__DIO_SCRATCH1_MASK 0xFFFFFFFFL +//DIO_SCRATCH2 +#define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT 0x0 +#define DIO_SCRATCH2__DIO_SCRATCH2_MASK 0xFFFFFFFFL +//DIO_SCRATCH3 +#define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT 0x0 +#define DIO_SCRATCH3__DIO_SCRATCH3_MASK 0xFFFFFFFFL +//DIO_SCRATCH4 +#define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT 0x0 +#define DIO_SCRATCH4__DIO_SCRATCH4_MASK 0xFFFFFFFFL +//DIO_SCRATCH5 +#define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT 0x0 +#define DIO_SCRATCH5__DIO_SCRATCH5_MASK 0xFFFFFFFFL +//DIO_SCRATCH6 +#define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT 0x0 +#define DIO_SCRATCH6__DIO_SCRATCH6_MASK 0xFFFFFFFFL +//DIO_SCRATCH7 +#define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT 0x0 +#define DIO_SCRATCH7__DIO_SCRATCH7_MASK 0xFFFFFFFFL +//DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x0 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x1 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x3 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x4 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x5 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x6 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000001L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000002L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000008L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000010L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000020L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000040L +//DIO_MEM_PWR_STATUS +#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0 +#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3 +#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4 +#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5 +#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6 +#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7 +#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8 +#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9 +#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x00000001L +#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x00000008L +#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x00000010L +#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x00000020L +#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x00000040L +#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x00000080L +#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x00000100L +#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x00000200L +//DIO_MEM_PWR_CTRL +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0 +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1 +#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4 +#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5 +#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6 +#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7 +#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8 +#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9 +#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000001L +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x00000002L +#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x00000010L +#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x00000020L +#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x00000040L +#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x00000080L +#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x00000100L +#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x00000200L +#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x00000400L +//DIO_MEM_PWR_CTRL2 +#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT 0x18 +#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT 0x19 +#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT 0x1a +#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT 0x1b +#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT 0x1c +#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT 0x1d +#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT 0x1e +#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK 0x01000000L +#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK 0x02000000L +#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK 0x04000000L +#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK 0x08000000L +#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK 0x10000000L +#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK 0x20000000L +#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK 0x40000000L +//DIO_CLK_CNTL +#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS__SHIFT 0x5 +#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18 +#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19 +#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a +#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b +#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c +#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d +#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e +#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS_MASK 0x00000020L +#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x01000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x02000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x04000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x08000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000L +//DIO_POWER_MANAGEMENT_CNTL +#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0 +#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8 +#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L +#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L +//DIG_SOFT_RESET +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0 +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1 +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4 +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5 +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8 +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9 +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10 +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11 +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14 +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15 +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18 +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19 +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x01000000L +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x02000000L +//DIO_CLK_CNTL2 +#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT 0x0 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT 0x7 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT 0x8 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT 0x9 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT 0xb +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT 0xc +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT 0xd +#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT 0x11 +#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT 0x12 +#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT 0x13 +#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT 0x14 +#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT 0x15 +#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT 0x16 +#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT 0x17 +#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS__SHIFT 0x18 +#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS__SHIFT 0x19 +#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS__SHIFT 0x1a +#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS__SHIFT 0x1b +#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS__SHIFT 0x1c +#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS__SHIFT 0x1d +#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS__SHIFT 0x1e +#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK 0x0000007FL +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK 0x00000080L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK 0x00000100L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK 0x00000200L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK 0x00000800L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK 0x00001000L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK 0x00002000L +#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK 0x00020000L +#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK 0x00040000L +#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK 0x00080000L +#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK 0x00100000L +#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK 0x00200000L +#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK 0x00400000L +#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK 0x00800000L +#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS_MASK 0x01000000L +#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS_MASK 0x02000000L +#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS_MASK 0x04000000L +#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS_MASK 0x08000000L +#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS_MASK 0x10000000L +#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS_MASK 0x20000000L +#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS_MASK 0x40000000L +//DIO_CLK_CNTL3 +#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT 0x0 +#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT 0x1 +#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT 0x2 +#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT 0x3 +#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT 0x4 +#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT 0x5 +#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT 0x6 +#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT 0xb +#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT 0xc +#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT 0xd +#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT 0xe +#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT 0xf +#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT 0x10 +#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK 0x00000001L +#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK 0x00000002L +#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK 0x00000004L +#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK 0x00000008L +#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK 0x00000010L +#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK 0x00000020L +#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK 0x00000040L +#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK 0x00000800L +#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK 0x00001000L +#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK 0x00002000L +#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK 0x00004000L +#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK 0x00008000L +#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK 0x00010000L +//DIO_HDMI_RXSTATUS_TIMER_CONTROL +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT 0x0 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT 0x4 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT 0x8 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT 0xc +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT 0x10 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK 0x00000001L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK 0x00000010L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK 0x00000100L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK 0x00001000L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK 0x0FFF0000L +//DIO_LINKA_CNTL +#define DIO_LINKA_CNTL__ENC_TYPE_SEL__SHIFT 0x0 +#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define DIO_LINKA_CNTL__ENC_TYPE_SEL_MASK 0x00000003L +#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL_MASK 0x00000700L +//DIO_LINKB_CNTL +#define DIO_LINKB_CNTL__ENC_TYPE_SEL__SHIFT 0x0 +#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define DIO_LINKB_CNTL__ENC_TYPE_SEL_MASK 0x00000003L +#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL_MASK 0x00000700L +//DIO_LINKC_CNTL +#define DIO_LINKC_CNTL__ENC_TYPE_SEL__SHIFT 0x0 +#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define DIO_LINKC_CNTL__ENC_TYPE_SEL_MASK 0x00000003L +#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL_MASK 0x00000700L +//DIO_LINKD_CNTL +#define DIO_LINKD_CNTL__ENC_TYPE_SEL__SHIFT 0x0 +#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define DIO_LINKD_CNTL__ENC_TYPE_SEL_MASK 0x00000003L +#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL_MASK 0x00000700L +//DIO_LINKE_CNTL +#define DIO_LINKE_CNTL__ENC_TYPE_SEL__SHIFT 0x0 +#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define DIO_LINKE_CNTL__ENC_TYPE_SEL_MASK 0x00000003L +#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL_MASK 0x00000700L +//DIO_LINKF_CNTL +#define DIO_LINKF_CNTL__ENC_TYPE_SEL__SHIFT 0x0 +#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define DIO_LINKF_CNTL__ENC_TYPE_SEL_MASK 0x00000003L +#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL_MASK 0x00000700L + + +// addressBlock: dce_dc_dcio_dcio_dispdec +//DC_GENERICA +#define DC_GENERICA__GENERICA_EN__SHIFT 0x0 +#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7 +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_GENERICA__GENERICA_EN_MASK 0x00000001L +#define DC_GENERICA__GENERICA_SEL_MASK 0x00000F80L +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L +//DC_GENERICB +#define DC_GENERICB__GENERICB_EN__SHIFT 0x0 +#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_GENERICB__GENERICB_EN_MASK 0x00000001L +#define DC_GENERICB__GENERICB_SEL_MASK 0x00000F00L +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L +//DCIO_CLOCK_CNTL +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0 +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5 +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x0000001FL +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x00000020L +//DC_REF_CLK_CNTL +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L +//UNIPHYA_LINK_CNTL +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +//UNIPHYA_CHANNEL_XBAR_CNTL +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//UNIPHYB_LINK_CNTL +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +//UNIPHYB_CHANNEL_XBAR_CNTL +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//UNIPHYC_LINK_CNTL +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +//UNIPHYC_CHANNEL_XBAR_CNTL +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//UNIPHYD_LINK_CNTL +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +//UNIPHYD_CHANNEL_XBAR_CNTL +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//UNIPHYE_LINK_CNTL +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +//UNIPHYE_CHANNEL_XBAR_CNTL +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//DCIO_WRCMD_DELAY +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x18 +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xFF000000L +//DC_PINSTRAPS +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10 +#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11 +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x00002000L +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000C000L +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x00010000L +#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0x000E0000L +//DCIO_SPARE +#define DCIO_SPARE__DCIO_SPARE__SHIFT 0x0 +#define DCIO_SPARE__DCIO_SPARE_MASK 0xFFFFFFFFL +//INTERCEPT_STATE +#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT 0x0 +#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE__SHIFT 0x1 +#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE__SHIFT 0x4 +#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE__SHIFT 0x5 +#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE__SHIFT 0x6 +#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE__SHIFT 0x7 +#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE__SHIFT 0x8 +#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE__SHIFT 0x9 +#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE__SHIFT 0xa +#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK 0x00000001L +#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE_MASK 0x00000002L +#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE_MASK 0x00000010L +#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE_MASK 0x00000020L +#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE_MASK 0x00000040L +#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE_MASK 0x00000080L +#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE_MASK 0x00000100L +#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE_MASK 0x00000200L +#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE_MASK 0x00000400L +//DCIO_PATTERN_GEN_PAT +#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT__SHIFT 0x0 +#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT_MASK 0xFFFFFFFFL +//DCIO_PATTERN_GEN_EN +#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN__SHIFT 0x0 +#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN_MASK 0x00000001L +//DCIO_BL_PWM_FRAME_START_DISP_SEL +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT 0x0 +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL__SHIFT 0x4 +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK 0x00000007L +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL_MASK 0x00000070L +//DCIO_GSL_GENLK_PAD_CNTL +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT 0x4 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT 0x14 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK 0x00000030L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK 0x00300000L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L +//DCIO_GSL_SWAPLOCK_PAD_CNTL +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT 0x4 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT 0x14 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK 0x00000030L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK 0x00300000L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L +//DCIO_SOFT_RESET +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0 +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x1 +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x2 +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x3 +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x4 +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0x5 +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0x6 +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x8 +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x9 +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0xa +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0xb +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0xc +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xd +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xe +#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT 0x10 +#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET__SHIFT 0x11 +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x00000001L +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x00000002L +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x00000004L +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x00000008L +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x00000010L +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x00000020L +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x00000040L +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000100L +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000200L +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000400L +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000800L +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00001000L +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00002000L +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x00004000L +#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK 0x00010000L +#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET_MASK 0x00020000L + + +// addressBlock: dce_dc_dcio_dcio_chip_dispdec +//DC_GPIO_GENERIC_MASK +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN__SHIFT 0x1c +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x0000000CL +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x000000C0L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000C00L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x0000C000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x000C0000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00C00000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x0C000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN_MASK 0xF0000000L +//DC_GPIO_GENERIC_A +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L +//DC_GPIO_GENERIC_EN +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L +//DC_GPIO_GENERIC_Y +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L +//DC_GPIO_DDC1_MASK +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 +#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L +#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC1_A +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L +//DC_GPIO_DDC1_EN +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC1_Y +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC2_MASK +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 +#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L +#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC2_A +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L +//DC_GPIO_DDC2_EN +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC2_Y +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC3_MASK +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 +#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L +#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC3_A +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L +//DC_GPIO_DDC3_EN +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC3_Y +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC4_MASK +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 +#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L +#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC4_A +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L +//DC_GPIO_DDC4_EN +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC4_Y +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC5_MASK +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 +#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L +#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC5_A +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L +//DC_GPIO_DDC5_EN +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC5_Y +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L +//DC_GPIO_DDCVGA_MASK +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY__SHIFT 0x4 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10 +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY_MASK 0x00000010L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xF0000000L +//DC_GPIO_DDCVGA_A +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L +//DC_GPIO_DDCVGA_EN +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L +//DC_GPIO_DDCVGA_Y +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L +//DC_GPIO_GENLK_MASK +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x4 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xc +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x14 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1c +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000030L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00003000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00300000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x30000000L +//DC_GPIO_GENLK_A +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L +//DC_GPIO_GENLK_EN +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L +//DC_GPIO_GENLK_Y +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L +//DC_GPIO_HPD_MASK +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x000000C0L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000C00L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x000C0000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00C00000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x0C000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0xC0000000L +//DC_GPIO_HPD_A +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0 +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8 +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10 +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18 +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L +//DC_GPIO_HPD_EN +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0 +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1 +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2 +#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5 +#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8 +#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9 +#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10 +#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11 +#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14 +#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15 +#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18 +#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19 +#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c +#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d +#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x00000002L +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x00000004L +#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x00000020L +#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x00000040L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L +#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x00000200L +#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x00000400L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L +#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x00020000L +#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x00040000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x00100000L +#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x00200000L +#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x00400000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x01000000L +#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x02000000L +#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x04000000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L +#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000L +#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000L +//DC_GPIO_HPD_Y +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L +//DC_GPIO_DRIVE_STRENGTH_S0 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICA_S0__SHIFT 0x0 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICB_S0__SHIFT 0x1 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICC_S0__SHIFT 0x2 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICD_S0__SHIFT 0x3 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICE_S0__SHIFT 0x4 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICF_S0__SHIFT 0x5 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICG_S0__SHIFT 0x6 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_CLK_S0__SHIFT 0x8 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_VSYNC_S0__SHIFT 0x9 +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_A_S0__SHIFT 0xa +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_B_S0__SHIFT 0xb +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICA_S0_MASK 0x00000001L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICB_S0_MASK 0x00000002L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICC_S0_MASK 0x00000004L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICD_S0_MASK 0x00000008L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICE_S0_MASK 0x00000010L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICF_S0_MASK 0x00000020L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICG_S0_MASK 0x00000040L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_CLK_S0_MASK 0x00000100L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_VSYNC_S0_MASK 0x00000200L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_A_S0_MASK 0x00000400L +#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_B_S0_MASK 0x00000800L +//DC_GPIO_DRIVE_STRENGTH_S1 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICA_S1__SHIFT 0x0 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICB_S1__SHIFT 0x1 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICC_S1__SHIFT 0x2 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICD_S1__SHIFT 0x3 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICE_S1__SHIFT 0x4 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICF_S1__SHIFT 0x5 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICG_S1__SHIFT 0x6 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_CLK_S1__SHIFT 0x8 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_VSYNC_S1__SHIFT 0x9 +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_A_S1__SHIFT 0xa +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_B_S1__SHIFT 0xb +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICA_S1_MASK 0x00000001L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICB_S1_MASK 0x00000002L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICC_S1_MASK 0x00000004L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICD_S1_MASK 0x00000008L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICE_S1_MASK 0x00000010L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICF_S1_MASK 0x00000020L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICG_S1_MASK 0x00000040L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_CLK_S1_MASK 0x00000100L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_VSYNC_S1_MASK 0x00000200L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_A_S1_MASK 0x00000400L +#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_B_S1_MASK 0x00000800L +//DC_GPIO_PWRSEQ0_EN +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT 0x14 +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT 0x15 +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT 0x19 +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT 0x1a +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1d +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK 0x00100000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK 0x00E00000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK 0x02000000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK 0x1C000000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x20000000L +//DC_GPIO_PAD_STRENGTH_1 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10 +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000FL +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000F0L +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0x000F0000L +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0x00F00000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0F000000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xF0000000L +//DC_GPIO_PAD_STRENGTH_2 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000FL +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000F0L +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x00000700L +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x00007000L +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xC0000000L +//PHY_AUX_CNTL +#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0x9 +#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT 0xa +#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT 0xc +#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT 0xe +#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT 0x10 +#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT 0x12 +#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT 0x14 +#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00000200L +#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK 0x00000C00L +#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK 0x00003000L +#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK 0x0000C000L +#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK 0x00030000L +#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK 0x000C0000L +#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK 0x00300000L +//DC_GPIO_DRIVE_TXIMPSEL +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICA_TXIMPSEL__SHIFT 0x0 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICB_TXIMPSEL__SHIFT 0x1 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICC_TXIMPSEL__SHIFT 0x2 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICD_TXIMPSEL__SHIFT 0x3 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICE_TXIMPSEL__SHIFT 0x4 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICF_TXIMPSEL__SHIFT 0x5 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICG_TXIMPSEL__SHIFT 0x6 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_CLK_TXIMPSEL__SHIFT 0x8 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_VSYNC_TXIMPSEL__SHIFT 0x9 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_A_TXIMPSEL__SHIFT 0xa +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_B_TXIMPSEL__SHIFT 0xb +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD1_TXIMPSEL__SHIFT 0xc +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD2_TXIMPSEL__SHIFT 0xd +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD3_TXIMPSEL__SHIFT 0xe +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD4_TXIMPSEL__SHIFT 0xf +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD5_TXIMPSEL__SHIFT 0x10 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD6_TXIMPSEL__SHIFT 0x11 +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICA_TXIMPSEL_MASK 0x00000001L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICB_TXIMPSEL_MASK 0x00000002L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICC_TXIMPSEL_MASK 0x00000004L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICD_TXIMPSEL_MASK 0x00000008L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICE_TXIMPSEL_MASK 0x00000010L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICF_TXIMPSEL_MASK 0x00000020L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICG_TXIMPSEL_MASK 0x00000040L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_CLK_TXIMPSEL_MASK 0x00000100L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_VSYNC_TXIMPSEL_MASK 0x00000200L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_A_TXIMPSEL_MASK 0x00000400L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_B_TXIMPSEL_MASK 0x00000800L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD1_TXIMPSEL_MASK 0x00001000L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD2_TXIMPSEL_MASK 0x00002000L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD3_TXIMPSEL_MASK 0x00004000L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD4_TXIMPSEL_MASK 0x00008000L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD5_TXIMPSEL_MASK 0x00010000L +#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD6_TXIMPSEL_MASK 0x00020000L +//DC_GPIO_TX12_EN +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT 0x3 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT 0x4 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT 0x5 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT 0x6 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT 0x7 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT 0x8 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT 0x9 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK 0x00000008L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK 0x00000010L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK 0x00000020L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK 0x00000040L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK 0x00000080L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK 0x00000100L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK 0x00000200L +//DC_GPIO_AUX_CTRL_0 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT 0x15 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK 0x000000C0L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK 0x00000300L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK 0x00000C00L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK 0x00003000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK 0x00200000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK 0x00C00000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK 0xC0000000L +//DC_GPIO_AUX_CTRL_1 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT 0x1 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT 0x3 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT 0x7 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT 0xb +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK 0x00000001L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK 0x00000002L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK 0x00000004L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK 0x00000008L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK 0x00000010L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK 0x00000020L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK 0x00000040L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK 0x00000080L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK 0x00001800L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK 0x0000C000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK 0x00030000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK 0x000C0000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK 0x00300000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK 0xC0000000L +//DC_GPIO_AUX_CTRL_2 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK 0x00004000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK 0x40000000L +//DC_GPIO_RXEN +#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT 0x0 +#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT 0x1 +#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT 0x2 +#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT 0x3 +#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT 0x4 +#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT 0x5 +#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT 0x6 +#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT 0x8 +#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT 0x9 +#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT 0xa +#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT 0xb +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT 0xc +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT 0xd +#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT 0xe +#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT 0xf +#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT 0x10 +#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT 0x11 +#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT 0x12 +#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT 0x13 +#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK 0x00000001L +#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK 0x00000002L +#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK 0x00000004L +#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK 0x00000008L +#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK 0x00000010L +#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK 0x00000020L +#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK 0x00000040L +#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK 0x00000100L +#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK 0x00000200L +#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK 0x00000400L +#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK 0x00000800L +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK 0x00001000L +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK 0x00002000L +#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK 0x00004000L +#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK 0x00008000L +#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK 0x00010000L +#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK 0x00020000L +#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK 0x00040000L +#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK 0x00080000L +//DC_GPIO_PULLUPEN +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT 0x0 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT 0x1 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT 0x2 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT 0x3 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT 0x4 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT 0x5 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT 0x6 +#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT 0x8 +#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT 0x9 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT 0xe +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT 0xf +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT 0x10 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT 0x11 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT 0x12 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT 0x13 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK 0x00000001L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK 0x00000002L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK 0x00000004L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK 0x00000008L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK 0x00000010L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK 0x00000020L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK 0x00000040L +#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK 0x00000100L +#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK 0x00000200L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK 0x00004000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK 0x00008000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK 0x00010000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK 0x00020000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK 0x00040000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK 0x00080000L +//DC_GPIO_AUX_CTRL_3 +#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT 0x1 +#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT 0x3 +#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT 0xb +#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK 0x00000001L +#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK 0x00000002L +#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK 0x00000004L +#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK 0x00000008L +#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK 0x00000010L +#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK 0x00000020L +#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK 0x00000800L +#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK 0x00030000L +#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK 0x000C0000L +#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK 0x00300000L +#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK 0x00C00000L +#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK 0x03000000L +#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK 0x0C000000L +//DC_GPIO_AUX_CTRL_4 +#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK 0x0000000FL +#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK 0x000000F0L +#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK 0x00000F00L +#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK 0x0000F000L +#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK 0x000F0000L +#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK 0x00F00000L +//DC_GPIO_AUX_CTRL_5 +#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT 0xf +#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT 0x15 +#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT 0x17 +#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK 0x000000C0L +#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK 0x00000300L +#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK 0x00000C00L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK 0x00004000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK 0x00008000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK 0x00200000L +#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK 0x00400000L +#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK 0x00800000L +#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK 0x20000000L +//AUXI2C_PAD_ALL_PWR_OK +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT 0x0 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT 0x1 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT 0x2 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT 0x3 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT 0x4 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT 0x5 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK 0x00000001L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK 0x00000002L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK 0x00000004L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK 0x00000008L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK 0x00000010L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK 0x00000020L + + +// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec +//DC_GPIO_PWRSEQ_EN +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00010000L +//DC_GPIO_PWRSEQ_CTRL +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL__SHIFT 0x1 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL__SHIFT 0x2 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT 0x3 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT 0x4 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT 0x5 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT 0x6 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT 0x7 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1__SHIFT 0x14 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1__SHIFT 0x15 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1__SHIFT 0x16 +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL_MASK 0x00000002L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL_MASK 0x00000004L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK 0x00000008L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK 0x00000010L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK 0x00000020L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK 0x00000040L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK 0x00000080L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1_MASK 0x00100000L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1_MASK 0x00200000L +#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1_MASK 0x00400000L +//DC_GPIO_PWRSEQ_MASK +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT 0x4 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT 0x6 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x14 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x16 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK 0x00000010L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK 0x000000C0L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x0000C000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00100000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x00C00000L +//DC_GPIO_PWRSEQ_A_Y +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT 0x1 +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT 0x9 +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT 0x11 +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK 0x00000002L +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK 0x00000200L +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK 0x00020000L +//PANEL_PWRSEQ_CNTL +#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT 0x0 +#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT 0x4 +#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT 0x8 +#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT 0x9 +#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT 0xa +#define PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT 0x10 +#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT 0x11 +#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT 0x12 +#define PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT 0x18 +#define PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT 0x19 +#define PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT 0x1a +#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK 0x00000001L +#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK 0x00000010L +#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK 0x00000100L +#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK 0x00000200L +#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK 0x00000400L +#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK 0x00010000L +#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK 0x00020000L +#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK 0x00040000L +#define PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK 0x01000000L +#define PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK 0x02000000L +#define PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK 0x04000000L +//PANEL_PWRSEQ_STATE +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT 0x1 +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT 0x2 +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT 0x3 +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT 0x4 +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT 0x8 +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK 0x00000002L +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK 0x00000004L +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK 0x00000008L +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK 0x00000010L +#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK 0x00000F00L +//PANEL_PWRSEQ_DELAY1 +#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT 0x0 +#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT 0x8 +#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT 0x10 +#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT 0x18 +#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK 0x000000FFL +#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK 0x0000FF00L +#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK 0x00FF0000L +#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK 0xFF000000L +//PANEL_PWRSEQ_DELAY2 +#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT 0x0 +#define PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT 0x8 +#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT 0x10 +#define PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT 0x18 +#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK 0x000000FFL +#define PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK 0x0000FF00L +#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK 0x00FF0000L +#define PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK 0x01000000L +//PANEL_PWRSEQ_REF_DIV1 +#define PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT 0x0 +#define PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT 0x10 +#define PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK 0x00000FFFL +#define PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK 0xFFFF0000L +//BL_PWM_CNTL +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 +#define BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT 0x13 +#define BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT 0x14 +#define BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x15 +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e +#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000FFFFL +#define BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK 0x00080000L +#define BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK 0x00100000L +#define BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x00200000L +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L +#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L +//BL_PWM_CNTL2 +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT 0x1f +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000FFFFL +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000L +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK 0x80000000L +//BL_PWM_PERIOD_CNTL +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000FFFFL +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000F0000L +//BL_PWM_GRP1_REG_LOCK +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//PANEL_PWRSEQ_REF_DIV2 +#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT 0x0 +#define PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT 0x8 +#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT 0x10 +#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK 0x0000007FL +#define PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK 0x00007F00L +#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK 0x00010000L +//PWRSEQ_SPARE +#define PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT 0x0 +#define PWRSEQ_SPARE__PWRSEQ_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec +//DSCC0_DSCC_CONFIG0 +#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC0_DSCC_CONFIG1 +#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC0_DSCC_STATUS +#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC0_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT 0xc +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT 0x1c +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK 0x00001000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK 0x10000000L +//DSCC0_DSCC_PPS_CONFIG0 +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC0_DSCC_PPS_CONFIG1 +#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG2 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG3 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG4 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG5 +#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG6 +#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC0_DSCC_PPS_CONFIG7 +#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG8 +#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG9 +#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG10 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG11 +#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC0_DSCC_PPS_CONFIG12 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG13 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG14 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG15 +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG16 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG17 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG18 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG19 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG20 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG21 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG22 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC0_DSCC_MEM_POWER_CONTROL +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_MAX_ABS_ERROR0 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC0_DSCC_MAX_ABS_ERROR1 +#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL + + +// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec +//DSCCIF0_DSCCIF_CONFIG0 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF0_DSCCIF_CONFIG1 +#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec +//DSC_TOP0_DSC_TOP_CONTROL +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +//DSC_TOP0_DSC_DEBUG_CONTROL +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L + + +// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec +//DSCC1_DSCC_CONFIG0 +#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC1_DSCC_CONFIG1 +#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC1_DSCC_STATUS +#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC1_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT 0xc +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT 0x1c +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK 0x00001000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK 0x10000000L +//DSCC1_DSCC_PPS_CONFIG0 +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC1_DSCC_PPS_CONFIG1 +#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG2 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG3 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG4 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG5 +#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG6 +#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC1_DSCC_PPS_CONFIG7 +#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG8 +#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG9 +#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG10 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG11 +#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC1_DSCC_PPS_CONFIG12 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG13 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG14 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG15 +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG16 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG17 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG18 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG19 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG20 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG21 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG22 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC1_DSCC_MEM_POWER_CONTROL +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_MAX_ABS_ERROR0 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC1_DSCC_MAX_ABS_ERROR1 +#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL + + +// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec +//DSCCIF1_DSCCIF_CONFIG0 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF1_DSCCIF_CONFIG1 +#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec +//DSC_TOP1_DSC_TOP_CONTROL +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L + + +// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec +//DSCC2_DSCC_CONFIG0 +#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC2_DSCC_CONFIG1 +#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC2_DSCC_STATUS +#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC2_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT 0xc +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT 0x1c +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK 0x00001000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK 0x10000000L +//DSCC2_DSCC_PPS_CONFIG0 +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC2_DSCC_PPS_CONFIG1 +#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG2 +#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG3 +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG4 +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG5 +#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG6 +#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC2_DSCC_PPS_CONFIG7 +#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG8 +#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG9 +#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG10 +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG11 +#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC2_DSCC_PPS_CONFIG12 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC2_DSCC_PPS_CONFIG13 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC2_DSCC_PPS_CONFIG14 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC2_DSCC_PPS_CONFIG15 +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG16 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG17 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG18 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG19 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG20 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG21 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG22 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC2_DSCC_MEM_POWER_CONTROL +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_MAX_ABS_ERROR0 +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC2_DSCC_MAX_ABS_ERROR1 +#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL + + +// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec +//DSCCIF2_DSCCIF_CONFIG0 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF2_DSCCIF_CONFIG1 +#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec +//DSC_TOP2_DSC_TOP_CONTROL +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L + + +// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec +//DSCC3_DSCC_CONFIG0 +#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC3_DSCC_CONFIG1 +#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC3_DSCC_STATUS +#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC3_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT 0xc +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT 0x1c +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK 0x00001000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK 0x10000000L +//DSCC3_DSCC_PPS_CONFIG0 +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC3_DSCC_PPS_CONFIG1 +#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG2 +#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG3 +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG4 +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG5 +#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG6 +#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC3_DSCC_PPS_CONFIG7 +#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG8 +#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG9 +#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG10 +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG11 +#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC3_DSCC_PPS_CONFIG12 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC3_DSCC_PPS_CONFIG13 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC3_DSCC_PPS_CONFIG14 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC3_DSCC_PPS_CONFIG15 +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG16 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG17 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG18 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG19 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG20 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG21 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG22 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC3_DSCC_MEM_POWER_CONTROL +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_MAX_ABS_ERROR0 +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC3_DSCC_MAX_ABS_ERROR1 +#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL + + +// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec +//DSCCIF3_DSCCIF_CONFIG0 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF3_DSCCIF_CONFIG1 +#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec +//DSC_TOP3_DSC_TOP_CONTROL +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L + + +// addressBlock: dce_dc_hpo_hpo_top_dispdec +//HPO_TOP_CLOCK_CONTROL +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT 0x1 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT 0x4 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT 0x5 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT 0x8 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS__SHIFT 0x9 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT 0xc +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS__SHIFT 0xd +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS__SHIFT 0x10 +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS__SHIFT 0x11 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS__SHIFT 0x12 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS__SHIFT 0x13 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS__SHIFT 0x14 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS__SHIFT 0x15 +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT 0x18 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK 0x00000002L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK 0x00000010L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK 0x00000020L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK 0x00000100L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS_MASK 0x00000200L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK 0x00001000L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS_MASK 0x00002000L +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS_MASK 0x00010000L +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS_MASK 0x00020000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS_MASK 0x00040000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS_MASK 0x00080000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS_MASK 0x00100000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS_MASK 0x00200000L +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK 0xFF000000L +//HPO_TOP_HW_CONTROL +#define HPO_TOP_HW_CONTROL__HPO_IO_EN__SHIFT 0x0 +#define HPO_TOP_HW_CONTROL__HPO_IO_EN_MASK 0x00000001L + + +// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec +//DP_STREAM_MAPPER_CONTROL0 +#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET_MASK 0x00000007L +//DP_STREAM_MAPPER_CONTROL1 +#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET_MASK 0x00000007L +//DP_STREAM_MAPPER_CONTROL2 +#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET_MASK 0x00000007L +//DP_STREAM_MAPPER_CONTROL3 +#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET_MASK 0x00000007L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec +//AFMT5_AFMT_VBI_PACKET_CONTROL +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT5_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT5_AFMT_AUDIO_INFO0 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT5_AFMT_AUDIO_INFO1 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT5_AFMT_60958_0 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT5_AFMT_60958_1 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT5_AFMT_AUDIO_CRC_CONTROL +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT5_AFMT_RAMP_CONTROL0 +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT5_AFMT_RAMP_CONTROL1 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT5_AFMT_RAMP_CONTROL2 +#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT5_AFMT_RAMP_CONTROL3 +#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT5_AFMT_60958_2 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT5_AFMT_AUDIO_CRC_RESULT +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT5_AFMT_STATUS +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT5_AFMT_AUDIO_PACKET_CONTROL +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT5_AFMT_INFOFRAME_CONTROL0 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT5_AFMT_INTERRUPT_STATUS +//AFMT5_AFMT_AUDIO_SRC_CONTROL +#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT5_AFMT_MEM_PWR +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec +//DME5_DME_CONTROL +#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME5_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME5_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME5_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME5_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME5_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME5_DME_MEMORY_CONTROL +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec +//VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG5_VPG_GENERIC_PACKET_DATA +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG5_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG5_VPG_GENERIC_STATUS +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG5_VPG_MEM_PWR +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG5_VPG_ISRC1_2_ACCESS_CTRL +#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG5_VPG_ISRC1_2_DATA +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG5_VPG_MPEG_INFO0 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG5_VPG_MPEG_INFO1 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec +//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +//DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00001F00L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC0_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec +//APG0_APG_CONTROL +#define APG0_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG0_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG0_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG0_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG0_APG_CONTROL2 +#define APG0_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG0_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG0_APG_DBG_GEN_CONTROL +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG0_APG_PACKET_CONTROL +#define APG0_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT 0x0 +#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT 0x1 +#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG0_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK 0x00000001L +#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK 0x00000002L +#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG0_APG_AUDIO_CRC_CONTROL +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG0_APG_AUDIO_CRC_CONTROL2 +#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG0_APG_AUDIO_CRC_RESULT +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG0_APG_STATUS +#define APG0_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG0_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG0_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG0_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG0_APG_STATUS2 +#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG0_APG_MEM_PWR +#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG0_APG_SPARE +#define APG0_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG0_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec +//DME6_DME_CONTROL +#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME6_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME6_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME6_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME6_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME6_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME6_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME6_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME6_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME6_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME6_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME6_DME_MEMORY_CONTROL +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec +//VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG6_VPG_GENERIC_PACKET_DATA +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG6_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG6_VPG_GENERIC_STATUS +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG6_VPG_MEM_PWR +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG6_VPG_ISRC1_2_ACCESS_CTRL +#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG6_VPG_ISRC1_2_DATA +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG6_VPG_MPEG_INFO0 +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG6_VPG_MPEG_INFO1 +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec +//DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK 0x0000FFFFL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK 0x0000FFFFL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +//DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec +//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +//DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00001F00L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC1_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec +//APG1_APG_CONTROL +#define APG1_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG1_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG1_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG1_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG1_APG_CONTROL2 +#define APG1_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG1_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG1_APG_DBG_GEN_CONTROL +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG1_APG_PACKET_CONTROL +#define APG1_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT 0x0 +#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT 0x1 +#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG1_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK 0x00000001L +#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK 0x00000002L +#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG1_APG_AUDIO_CRC_CONTROL +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG1_APG_AUDIO_CRC_CONTROL2 +#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG1_APG_AUDIO_CRC_RESULT +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG1_APG_STATUS +#define APG1_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG1_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG1_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG1_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG1_APG_STATUS2 +#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG1_APG_MEM_PWR +#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG1_APG_SPARE +#define APG1_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG1_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec +//DME7_DME_CONTROL +#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME7_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME7_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME7_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME7_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME7_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME7_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME7_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME7_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME7_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME7_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME7_DME_MEMORY_CONTROL +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec +//VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG7_VPG_GENERIC_PACKET_DATA +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG7_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG7_VPG_GENERIC_STATUS +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG7_VPG_MEM_PWR +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG7_VPG_ISRC1_2_ACCESS_CTRL +#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG7_VPG_ISRC1_2_DATA +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG7_VPG_MPEG_INFO0 +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG7_VPG_MPEG_INFO1 +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec +//DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK 0x0000FFFFL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK 0x0000FFFFL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +//DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec +//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +//DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00001F00L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC2_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec +//APG2_APG_CONTROL +#define APG2_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG2_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG2_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG2_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG2_APG_CONTROL2 +#define APG2_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG2_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG2_APG_DBG_GEN_CONTROL +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG2_APG_PACKET_CONTROL +#define APG2_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT 0x0 +#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT 0x1 +#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG2_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK 0x00000001L +#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK 0x00000002L +#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG2_APG_AUDIO_CRC_CONTROL +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG2_APG_AUDIO_CRC_CONTROL2 +#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG2_APG_AUDIO_CRC_RESULT +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG2_APG_STATUS +#define APG2_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG2_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG2_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG2_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG2_APG_STATUS2 +#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG2_APG_MEM_PWR +#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG2_APG_SPARE +#define APG2_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG2_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec +//DME8_DME_CONTROL +#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME8_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME8_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME8_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME8_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME8_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME8_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME8_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME8_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME8_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME8_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME8_DME_MEMORY_CONTROL +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec +//VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG8_VPG_GENERIC_PACKET_DATA +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG8_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG8_VPG_GENERIC_STATUS +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG8_VPG_MEM_PWR +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG8_VPG_ISRC1_2_ACCESS_CTRL +#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG8_VPG_ISRC1_2_DATA +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG8_VPG_MPEG_INFO0 +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG8_VPG_MPEG_INFO1 +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec +//DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK 0x0000FFFFL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK 0x0000FFFFL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +//DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec +//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +//DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00001F00L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC3_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec +//APG3_APG_CONTROL +#define APG3_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG3_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG3_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG3_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG3_APG_CONTROL2 +#define APG3_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG3_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG3_APG_DBG_GEN_CONTROL +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG3_APG_PACKET_CONTROL +#define APG3_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT 0x0 +#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT 0x1 +#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG3_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK 0x00000001L +#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK 0x00000002L +#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG3_APG_AUDIO_CRC_CONTROL +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG3_APG_AUDIO_CRC_CONTROL2 +#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG3_APG_AUDIO_CRC_RESULT +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG3_APG_STATUS +#define APG3_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG3_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG3_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG3_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG3_APG_STATUS2 +#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG3_APG_MEM_PWR +#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG3_APG_SPARE +#define APG3_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG3_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec +//DME9_DME_CONTROL +#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME9_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME9_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME9_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME9_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME9_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME9_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME9_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME9_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME9_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME9_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME9_DME_MEMORY_CONTROL +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec +//VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG9_VPG_GENERIC_PACKET_DATA +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG9_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG9_VPG_GENERIC_STATUS +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG9_VPG_MEM_PWR +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG9_VPG_ISRC1_2_ACCESS_CTRL +#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG9_VPG_ISRC1_2_DATA +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG9_VPG_MPEG_INFO0 +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG9_VPG_MPEG_INFO1 +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec +//DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK 0x0000FFFFL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK 0x0000FFFFL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +//DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec +//DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x4 +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK 0x00000010L +//DP_LINK_ENC0_DP_LINK_ENC_SPARE +#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec +//DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE_MASK 0x00000030L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK 0x00000300L +//DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT 0xc +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT 0x10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK 0x00000030L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK 0x00001000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK 0x00030000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK 0x00000003L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT 0xc +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT 0x10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT 0x14 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT 0x18 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT 0x1c +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK 0x00000070L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK 0x00000700L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK 0x00007000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK 0x00070000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK 0x00700000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK 0x07000000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK 0x70000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK 0x000000FFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT 0x2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT 0x3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT 0x6 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT 0x7 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK 0x00000004L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK 0x00000008L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK 0x00000040L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK 0x00000080L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK 0x00000100L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT 0x2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT 0xa +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT 0xc +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT 0x10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT 0x12 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT 0x14 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT 0x18 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT 0x1a +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT 0x1c +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK 0x00000003L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK 0x00000004L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK 0x000000F0L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK 0x00000300L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK 0x00000400L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK 0x0000F000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK 0x00030000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK 0x00040000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK 0x00F00000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK 0x03000000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK 0x04000000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK 0xF0000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT 0x6 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT 0x10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT 0x11 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT 0x14 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT 0x15 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK 0x00000030L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK 0x000000C0L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK 0x00003F00L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK 0x00010000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK 0x000E0000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK 0x00100000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK 0x00600000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK 0x00FFFF00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec +//DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x4 +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK 0x00000010L +//DP_LINK_ENC1_DP_LINK_ENC_SPARE +#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec +//DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE_MASK 0x00000030L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK 0x00000300L +//DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT 0xc +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT 0x10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK 0x00000030L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK 0x00001000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK 0x00030000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK 0x00000003L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT 0xc +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT 0x10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT 0x14 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT 0x18 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT 0x1c +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK 0x00000070L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK 0x00000700L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK 0x00007000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK 0x00070000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK 0x00700000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK 0x07000000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK 0x70000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK 0x000000FFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT 0x2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT 0x3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT 0x6 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT 0x7 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK 0x00000004L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK 0x00000008L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK 0x00000040L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK 0x00000080L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK 0x00000100L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT 0x2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT 0xa +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT 0xc +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT 0x10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT 0x12 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT 0x14 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT 0x18 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT 0x1a +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT 0x1c +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK 0x00000003L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK 0x00000004L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK 0x000000F0L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK 0x00000300L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK 0x00000400L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK 0x0000F000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK 0x00030000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK 0x00040000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK 0x00F00000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK 0x03000000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK 0x04000000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK 0xF0000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT 0x6 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT 0x10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT 0x11 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT 0x14 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT 0x15 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK 0x00000030L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK 0x000000C0L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK 0x00003F00L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK 0x00010000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK 0x000E0000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK 0x00100000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK 0x00600000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK 0x00FFFF00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azcontroller_azdec +//CORB_WRITE_POINTER +#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 +#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL +//CORB_READ_POINTER +#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 +#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf +#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL +#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L +//CORB_CONTROL +#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 +#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 +#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L +#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L +//CORB_STATUS +#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 +#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x01L +//CORB_SIZE +#define CORB_SIZE__CORB_SIZE__SHIFT 0x0 +#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 +#define CORB_SIZE__CORB_SIZE_MASK 0x0003L +#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0x00F0L +//RIRB_LOWER_BASE_ADDRESS +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//RIRB_UPPER_BASE_ADDRESS +#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//RIRB_WRITE_POINTER +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0x00FFL +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000L +//RESPONSE_INTERRUPT_COUNT +#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 +#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0x00FFL +//RIRB_CONTROL +#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 +#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 +#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 +#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x01L +#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x02L +#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x04L +//RIRB_STATUS +#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 +#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 +#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x01L +#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x04L +//RIRB_SIZE +#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 +#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 +#define RIRB_SIZE__RIRB_SIZE_MASK 0x0003L +#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0x00F0L +//IMMEDIATE_COMMAND_OUTPUT_INTERFACE +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0x0FFFFFFFL +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xF0000000L +//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0000FFFFL +//IMMEDIATE_RESPONSE_INPUT_INTERFACE +#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 +#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xFFFFFFFFL +//IMMEDIATE_COMMAND_STATUS +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x00000001L +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x00000002L +//DMA_POSITION_LOWER_BASE_ADDRESS +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x00000001L +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007EL +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//DMA_POSITION_UPPER_BASE_ADDRESS +#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//WALL_CLOCK_COUNTER_ALIAS +#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 +#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azendpoint_azdec +//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azroot_azdec +//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azstream0_azdec +//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream1_azdec +//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream2_azdec +//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream3_azdec +//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream4_azdec +//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream5_azdec +//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream6_azdec +//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream7_azdec +//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: vga_vgaseqind +//SEQ00 +#define SEQ00__SEQ_RST0B__SHIFT 0x0 +#define SEQ00__SEQ_RST1B__SHIFT 0x1 +#define SEQ00__SEQ_RST0B_MASK 0x01L +#define SEQ00__SEQ_RST1B_MASK 0x02L +//SEQ01 +#define SEQ01__SEQ_DOT8__SHIFT 0x0 +#define SEQ01__SEQ_SHIFT2__SHIFT 0x2 +#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3 +#define SEQ01__SEQ_SHIFT4__SHIFT 0x4 +#define SEQ01__SEQ_MAXBW__SHIFT 0x5 +#define SEQ01__SEQ_DOT8_MASK 0x01L +#define SEQ01__SEQ_SHIFT2_MASK 0x04L +#define SEQ01__SEQ_PCLKBY2_MASK 0x08L +#define SEQ01__SEQ_SHIFT4_MASK 0x10L +#define SEQ01__SEQ_MAXBW_MASK 0x20L +//SEQ02 +#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0 +#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1 +#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2 +#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3 +#define SEQ02__SEQ_MAP0_EN_MASK 0x01L +#define SEQ02__SEQ_MAP1_EN_MASK 0x02L +#define SEQ02__SEQ_MAP2_EN_MASK 0x04L +#define SEQ02__SEQ_MAP3_EN_MASK 0x08L +//SEQ03 +#define SEQ03__SEQ_FONT_B1__SHIFT 0x0 +#define SEQ03__SEQ_FONT_B2__SHIFT 0x1 +#define SEQ03__SEQ_FONT_A1__SHIFT 0x2 +#define SEQ03__SEQ_FONT_A2__SHIFT 0x3 +#define SEQ03__SEQ_FONT_B0__SHIFT 0x4 +#define SEQ03__SEQ_FONT_A0__SHIFT 0x5 +#define SEQ03__SEQ_FONT_B1_MASK 0x01L +#define SEQ03__SEQ_FONT_B2_MASK 0x02L +#define SEQ03__SEQ_FONT_A1_MASK 0x04L +#define SEQ03__SEQ_FONT_A2_MASK 0x08L +#define SEQ03__SEQ_FONT_B0_MASK 0x10L +#define SEQ03__SEQ_FONT_A0_MASK 0x20L +//SEQ04 +#define SEQ04__SEQ_256K__SHIFT 0x1 +#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2 +#define SEQ04__SEQ_CHAIN__SHIFT 0x3 +#define SEQ04__SEQ_256K_MASK 0x02L +#define SEQ04__SEQ_ODDEVEN_MASK 0x04L +#define SEQ04__SEQ_CHAIN_MASK 0x08L + + +// addressBlock: vga_vgacrtind +//CRT00 +#define CRT00__H_TOTAL__SHIFT 0x0 +#define CRT00__H_TOTAL_MASK 0xFFL +//CRT01 +#define CRT01__H_DISP_END__SHIFT 0x0 +#define CRT01__H_DISP_END_MASK 0xFFL +//CRT02 +#define CRT02__H_BLANK_START__SHIFT 0x0 +#define CRT02__H_BLANK_START_MASK 0xFFL +//CRT03 +#define CRT03__H_BLANK_END__SHIFT 0x0 +#define CRT03__H_DE_SKEW__SHIFT 0x5 +#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7 +#define CRT03__H_BLANK_END_MASK 0x1FL +#define CRT03__H_DE_SKEW_MASK 0x60L +#define CRT03__CR10CR11_R_DIS_B_MASK 0x80L +//CRT04 +#define CRT04__H_SYNC_START__SHIFT 0x0 +#define CRT04__H_SYNC_START_MASK 0xFFL +//CRT05 +#define CRT05__H_SYNC_END__SHIFT 0x0 +#define CRT05__H_SYNC_SKEW__SHIFT 0x5 +#define CRT05__H_BLANK_END_B5__SHIFT 0x7 +#define CRT05__H_SYNC_END_MASK 0x1FL +#define CRT05__H_SYNC_SKEW_MASK 0x60L +#define CRT05__H_BLANK_END_B5_MASK 0x80L +//CRT06 +#define CRT06__V_TOTAL__SHIFT 0x0 +#define CRT06__V_TOTAL_MASK 0xFFL +//CRT07 +#define CRT07__V_TOTAL_B8__SHIFT 0x0 +#define CRT07__V_DISP_END_B8__SHIFT 0x1 +#define CRT07__V_SYNC_START_B8__SHIFT 0x2 +#define CRT07__V_BLANK_START_B8__SHIFT 0x3 +#define CRT07__LINE_CMP_B8__SHIFT 0x4 +#define CRT07__V_TOTAL_B9__SHIFT 0x5 +#define CRT07__V_DISP_END_B9__SHIFT 0x6 +#define CRT07__V_SYNC_START_B9__SHIFT 0x7 +#define CRT07__V_TOTAL_B8_MASK 0x01L +#define CRT07__V_DISP_END_B8_MASK 0x02L +#define CRT07__V_SYNC_START_B8_MASK 0x04L +#define CRT07__V_BLANK_START_B8_MASK 0x08L +#define CRT07__LINE_CMP_B8_MASK 0x10L +#define CRT07__V_TOTAL_B9_MASK 0x20L +#define CRT07__V_DISP_END_B9_MASK 0x40L +#define CRT07__V_SYNC_START_B9_MASK 0x80L +//CRT08 +#define CRT08__ROW_SCAN_START__SHIFT 0x0 +#define CRT08__BYTE_PAN__SHIFT 0x5 +#define CRT08__ROW_SCAN_START_MASK 0x1FL +#define CRT08__BYTE_PAN_MASK 0x60L +//CRT09 +#define CRT09__MAX_ROW_SCAN__SHIFT 0x0 +#define CRT09__V_BLANK_START_B9__SHIFT 0x5 +#define CRT09__LINE_CMP_B9__SHIFT 0x6 +#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7 +#define CRT09__MAX_ROW_SCAN_MASK 0x1FL +#define CRT09__V_BLANK_START_B9_MASK 0x20L +#define CRT09__LINE_CMP_B9_MASK 0x40L +#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80L +//CRT0A +#define CRT0A__CURSOR_START__SHIFT 0x0 +#define CRT0A__CURSOR_DISABLE__SHIFT 0x5 +#define CRT0A__CURSOR_START_MASK 0x1FL +#define CRT0A__CURSOR_DISABLE_MASK 0x20L +//CRT0B +#define CRT0B__CURSOR_END__SHIFT 0x0 +#define CRT0B__CURSOR_SKEW__SHIFT 0x5 +#define CRT0B__CURSOR_END_MASK 0x1FL +#define CRT0B__CURSOR_SKEW_MASK 0x60L +//CRT0C +#define CRT0C__DISP_START__SHIFT 0x0 +#define CRT0C__DISP_START_MASK 0xFFL +//CRT0D +#define CRT0D__DISP_START__SHIFT 0x0 +#define CRT0D__DISP_START_MASK 0xFFL +//CRT0E +#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0 +#define CRT0E__CURSOR_LOC_HI_MASK 0xFFL +//CRT0F +#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0 +#define CRT0F__CURSOR_LOC_LO_MASK 0xFFL +//CRT10 +#define CRT10__V_SYNC_START__SHIFT 0x0 +#define CRT10__V_SYNC_START_MASK 0xFFL +//CRT11 +#define CRT11__V_SYNC_END__SHIFT 0x0 +#define CRT11__V_INTR_CLR__SHIFT 0x4 +#define CRT11__V_INTR_EN__SHIFT 0x5 +#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6 +#define CRT11__C0T7_WR_ONLY__SHIFT 0x7 +#define CRT11__V_SYNC_END_MASK 0x0FL +#define CRT11__V_INTR_CLR_MASK 0x10L +#define CRT11__V_INTR_EN_MASK 0x20L +#define CRT11__SEL5_REFRESH_CYC_MASK 0x40L +#define CRT11__C0T7_WR_ONLY_MASK 0x80L +//CRT12 +#define CRT12__V_DISP_END__SHIFT 0x0 +#define CRT12__V_DISP_END_MASK 0xFFL +//CRT13 +#define CRT13__DISP_PITCH__SHIFT 0x0 +#define CRT13__DISP_PITCH_MASK 0xFFL +//CRT14 +#define CRT14__UNDRLN_LOC__SHIFT 0x0 +#define CRT14__ADDR_CNT_BY4__SHIFT 0x5 +#define CRT14__DOUBLE_WORD__SHIFT 0x6 +#define CRT14__UNDRLN_LOC_MASK 0x1FL +#define CRT14__ADDR_CNT_BY4_MASK 0x20L +#define CRT14__DOUBLE_WORD_MASK 0x40L +//CRT15 +#define CRT15__V_BLANK_START__SHIFT 0x0 +#define CRT15__V_BLANK_START_MASK 0xFFL +//CRT16 +#define CRT16__V_BLANK_END__SHIFT 0x0 +#define CRT16__V_BLANK_END_MASK 0xFFL +//CRT17 +#define CRT17__RA0_AS_A13B__SHIFT 0x0 +#define CRT17__RA1_AS_A14B__SHIFT 0x1 +#define CRT17__VCOUNT_BY2__SHIFT 0x2 +#define CRT17__ADDR_CNT_BY2__SHIFT 0x3 +#define CRT17__WRAP_A15TOA0__SHIFT 0x5 +#define CRT17__BYTE_MODE__SHIFT 0x6 +#define CRT17__CRTC_SYNC_EN__SHIFT 0x7 +#define CRT17__RA0_AS_A13B_MASK 0x01L +#define CRT17__RA1_AS_A14B_MASK 0x02L +#define CRT17__VCOUNT_BY2_MASK 0x04L +#define CRT17__ADDR_CNT_BY2_MASK 0x08L +#define CRT17__WRAP_A15TOA0_MASK 0x20L +#define CRT17__BYTE_MODE_MASK 0x40L +#define CRT17__CRTC_SYNC_EN_MASK 0x80L +//CRT18 +#define CRT18__LINE_CMP__SHIFT 0x0 +#define CRT18__LINE_CMP_MASK 0xFFL +//CRT1E +#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1 +#define CRT1E__GRPH_DEC_RD1_MASK 0x02L +//CRT1F +#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0 +#define CRT1F__GRPH_DEC_RD0_MASK 0xFFL +//CRT22 +#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0 +#define CRT22__GRPH_LATCH_DATA_MASK 0xFFL + + +// addressBlock: vga_vgagrphind +//GRA00 +#define GRA00__GRPH_SET_RESET0__SHIFT 0x0 +#define GRA00__GRPH_SET_RESET1__SHIFT 0x1 +#define GRA00__GRPH_SET_RESET2__SHIFT 0x2 +#define GRA00__GRPH_SET_RESET3__SHIFT 0x3 +#define GRA00__GRPH_SET_RESET0_MASK 0x01L +#define GRA00__GRPH_SET_RESET1_MASK 0x02L +#define GRA00__GRPH_SET_RESET2_MASK 0x04L +#define GRA00__GRPH_SET_RESET3_MASK 0x08L +//GRA01 +#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0 +#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1 +#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2 +#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3 +#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x01L +#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x02L +#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x04L +#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x08L +//GRA02 +#define GRA02__GRPH_CCOMP__SHIFT 0x0 +#define GRA02__GRPH_CCOMP_MASK 0x0FL +//GRA03 +#define GRA03__GRPH_ROTATE__SHIFT 0x0 +#define GRA03__GRPH_FN_SEL__SHIFT 0x3 +#define GRA03__GRPH_ROTATE_MASK 0x07L +#define GRA03__GRPH_FN_SEL_MASK 0x18L +//GRA04 +#define GRA04__GRPH_RMAP__SHIFT 0x0 +#define GRA04__GRPH_RMAP_MASK 0x03L +//GRA05 +#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0 +#define GRA05__GRPH_READ1__SHIFT 0x3 +#define GRA05__CGA_ODDEVEN__SHIFT 0x4 +#define GRA05__GRPH_OES__SHIFT 0x5 +#define GRA05__GRPH_PACK__SHIFT 0x6 +#define GRA05__GRPH_WRITE_MODE_MASK 0x03L +#define GRA05__GRPH_READ1_MASK 0x08L +#define GRA05__CGA_ODDEVEN_MASK 0x10L +#define GRA05__GRPH_OES_MASK 0x20L +#define GRA05__GRPH_PACK_MASK 0x40L +//GRA06 +#define GRA06__GRPH_GRAPHICS__SHIFT 0x0 +#define GRA06__GRPH_ODDEVEN__SHIFT 0x1 +#define GRA06__GRPH_ADRSEL__SHIFT 0x2 +#define GRA06__GRPH_GRAPHICS_MASK 0x01L +#define GRA06__GRPH_ODDEVEN_MASK 0x02L +#define GRA06__GRPH_ADRSEL_MASK 0x0CL +//GRA07 +#define GRA07__GRPH_XCARE0__SHIFT 0x0 +#define GRA07__GRPH_XCARE1__SHIFT 0x1 +#define GRA07__GRPH_XCARE2__SHIFT 0x2 +#define GRA07__GRPH_XCARE3__SHIFT 0x3 +#define GRA07__GRPH_XCARE0_MASK 0x01L +#define GRA07__GRPH_XCARE1_MASK 0x02L +#define GRA07__GRPH_XCARE2_MASK 0x04L +#define GRA07__GRPH_XCARE3_MASK 0x08L +//GRA08 +#define GRA08__GRPH_BMSK__SHIFT 0x0 +#define GRA08__GRPH_BMSK_MASK 0xFFL + + +// addressBlock: vga_vgaattrind +//ATTR00 +#define ATTR00__ATTR_PAL__SHIFT 0x0 +#define ATTR00__ATTR_PAL_MASK 0x3FL +//ATTR01 +#define ATTR01__ATTR_PAL__SHIFT 0x0 +#define ATTR01__ATTR_PAL_MASK 0x3FL +//ATTR02 +#define ATTR02__ATTR_PAL__SHIFT 0x0 +#define ATTR02__ATTR_PAL_MASK 0x3FL +//ATTR03 +#define ATTR03__ATTR_PAL__SHIFT 0x0 +#define ATTR03__ATTR_PAL_MASK 0x3FL +//ATTR04 +#define ATTR04__ATTR_PAL__SHIFT 0x0 +#define ATTR04__ATTR_PAL_MASK 0x3FL +//ATTR05 +#define ATTR05__ATTR_PAL__SHIFT 0x0 +#define ATTR05__ATTR_PAL_MASK 0x3FL +//ATTR06 +#define ATTR06__ATTR_PAL__SHIFT 0x0 +#define ATTR06__ATTR_PAL_MASK 0x3FL +//ATTR07 +#define ATTR07__ATTR_PAL__SHIFT 0x0 +#define ATTR07__ATTR_PAL_MASK 0x3FL +//ATTR08 +#define ATTR08__ATTR_PAL__SHIFT 0x0 +#define ATTR08__ATTR_PAL_MASK 0x3FL +//ATTR09 +#define ATTR09__ATTR_PAL__SHIFT 0x0 +#define ATTR09__ATTR_PAL_MASK 0x3FL +//ATTR0A +#define ATTR0A__ATTR_PAL__SHIFT 0x0 +#define ATTR0A__ATTR_PAL_MASK 0x3FL +//ATTR0B +#define ATTR0B__ATTR_PAL__SHIFT 0x0 +#define ATTR0B__ATTR_PAL_MASK 0x3FL +//ATTR0C +#define ATTR0C__ATTR_PAL__SHIFT 0x0 +#define ATTR0C__ATTR_PAL_MASK 0x3FL +//ATTR0D +#define ATTR0D__ATTR_PAL__SHIFT 0x0 +#define ATTR0D__ATTR_PAL_MASK 0x3FL +//ATTR0E +#define ATTR0E__ATTR_PAL__SHIFT 0x0 +#define ATTR0E__ATTR_PAL_MASK 0x3FL +//ATTR0F +#define ATTR0F__ATTR_PAL__SHIFT 0x0 +#define ATTR0F__ATTR_PAL_MASK 0x3FL +//ATTR10 +#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0 +#define ATTR10__ATTR_MONO_EN__SHIFT 0x1 +#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2 +#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3 +#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5 +#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6 +#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7 +#define ATTR10__ATTR_GRPH_MODE_MASK 0x01L +#define ATTR10__ATTR_MONO_EN_MASK 0x02L +#define ATTR10__ATTR_LGRPH_EN_MASK 0x04L +#define ATTR10__ATTR_BLINK_EN_MASK 0x08L +#define ATTR10__ATTR_PANTOPONLY_MASK 0x20L +#define ATTR10__ATTR_PCLKBY2_MASK 0x40L +#define ATTR10__ATTR_CSEL_EN_MASK 0x80L +//ATTR11 +#define ATTR11__ATTR_OVSC__SHIFT 0x0 +#define ATTR11__ATTR_OVSC_MASK 0xFFL +//ATTR12 +#define ATTR12__ATTR_MAP_EN__SHIFT 0x0 +#define ATTR12__ATTR_VSMUX__SHIFT 0x4 +#define ATTR12__ATTR_MAP_EN_MASK 0x0FL +#define ATTR12__ATTR_VSMUX_MASK 0x30L +//ATTR13 +#define ATTR13__ATTR_PPAN__SHIFT 0x0 +#define ATTR13__ATTR_PPAN_MASK 0x0FL +//ATTR14 +#define ATTR14__ATTR_CSEL1__SHIFT 0x0 +#define ATTR14__ATTR_CSEL2__SHIFT 0x2 +#define ATTR14__ATTR_CSEL1_MASK 0x03L +#define ATTR14__ATTR_CSEL2_MASK 0x0CL + + +// addressBlock: azendpoint_f2codecind +//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007FL +//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000FC00L +//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x00000003L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZALIA_F2_CODEC_PIN_CONTROL_HBR +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xFFFFFFFFL + + +// addressBlock: azendpoint_descriptorind +//AUDIO_DESCRIPTOR0 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR1 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR2 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR3 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR4 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR5 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR6 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR7 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR8 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR9 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR10 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR11 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR12 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR13 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L + + +// addressBlock: azendpoint_sinkinfoind +//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000FFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000FFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xFFFFFFFFL +//SINK_DESCRIPTION0 +#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION1 +#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION2 +#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION3 +#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION4 +#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION5 +#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION6 +#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION7 +#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION8 +#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION9 +#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION10 +#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION11 +#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION12 +#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION13 +#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION14 +#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION15 +#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION16 +#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION17 +#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000FFL + + +// addressBlock: azf0controller_azinputcrc0resultind +//AZALIA_INPUT_CRC0_CHANNEL0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL1 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL2 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL3 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL4 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL5 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL6 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL7 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azinputcrc1resultind +//AZALIA_INPUT_CRC1_CHANNEL0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL1 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL2 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL3 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL4 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL5 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL6 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL7 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azcrc0resultind +//AZALIA_CRC0_CHANNEL0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL1 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL2 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL3 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL4 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL5 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL6 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL7 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azcrc1resultind +//AZALIA_CRC1_CHANNEL0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL1 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL2 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL3 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL4 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL5 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL6 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL7 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azinputendpoint_f2codecind +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L + + +// addressBlock: azroot_f2codecind +//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L + + +// addressBlock: azf0stream0_streamind +//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream1_streamind +//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream2_streamind +//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream3_streamind +//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream4_streamind +//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream5_streamind +//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream6_streamind +//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream7_streamind +//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream8_streamind +//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream9_streamind +//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream10_streamind +//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream11_streamind +//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream12_streamind +//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream13_streamind +//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream14_streamind +//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream15_streamind +//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0endpoint0_endpointind +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint1_endpointind +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint2_endpointind +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint3_endpointind +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint4_endpointind +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint5_endpointind +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint6_endpointind +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint7_endpointind +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0inputendpoint0_inputendpointind +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint1_inputendpointind +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint2_inputendpointind +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint3_inputendpointind +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint4_inputendpointind +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint5_inputendpointind +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint6_inputendpointind +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint7_inputendpointind +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +#endif -- cgit v1.2.3 From ac2e555e0a7fe571d46f7dcb1529b4bee00095d6 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Mon, 21 Feb 2022 16:03:58 -0500 Subject: drm/amd/display: Add DMCUB source files and changes for DCN32/321 DMCUB is the display engine microcontroller which aids in modesetting and other display related features. Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 31 ++ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 2 + drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 6 + drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 26 +- drivers/gpu/drm/amd/display/dmub/src/Makefile | 1 + drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 488 ++++++++++++++++++++++ drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h | 256 ++++++++++++ drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 51 ++- 8 files changed, 859 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index 541376fabbef..11597bca966a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -250,6 +250,37 @@ void dc_dmub_trace_event_control(struct dc *dc, bool enable) dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable); } +void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub) +{ + union dmub_rb_cmd cmd = { 0 }; + enum dmub_status status; + + if (!dmub) { + return; + } + + memset(&cmd, 0, sizeof(cmd)); + + /* Prepare fw command */ + cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS; + cmd.query_feature_caps.header.sub_type = 0; + cmd.query_feature_caps.header.ret_status = 1; + cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data); + + /* Send command to fw */ + status = dmub_srv_cmd_with_reply_data(dmub, &cmd); + + ASSERT(status == DMUB_STATUS_OK); + + /* If command was processed, copy feature caps to dmub srv */ + if (status == DMUB_STATUS_OK && + cmd.query_feature_caps.header.ret_status == 0) { + memcpy(&dmub->feature_caps, + &cmd.query_feature_caps.query_feature_caps_data, + sizeof(struct dmub_feature_caps)); + } +} + bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data) { if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h index 7e4e2ec5915d..50e44b53f14c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h @@ -68,6 +68,8 @@ bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_bu void dc_dmub_trace_event_control(struct dc *dc, bool enable); +void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub); + void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv); void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv); void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data); diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index 7dbc9fb55459..04049dc5d9df 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -246,6 +246,7 @@ struct dmub_srv_hw_params { bool dpia_supported; bool disable_dpia; bool usb4_cm_version; + bool fw_in_system_memory; }; /** @@ -310,6 +311,9 @@ struct dmub_srv_hw_funcs { const struct dmub_window *cw0, const struct dmub_window *cw1); + void (*backdoor_load_zfb_mode)(struct dmub_srv *dmub, + const struct dmub_window *cw0, + const struct dmub_window *cw1); void (*setup_windows)(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, @@ -365,6 +369,7 @@ struct dmub_srv_hw_funcs { uint32_t (*get_gpint_dataout)(struct dmub_srv *dmub); + void (*configure_dmub_in_system_memory)(struct dmub_srv *dmub); void (*clear_inbox0_ack_register)(struct dmub_srv *dmub); uint32_t (*read_inbox0_ack_register)(struct dmub_srv *dmub); void (*send_inbox0_cmd)(struct dmub_srv *dmub, union dmub_inbox0_data_register data); @@ -412,6 +417,7 @@ struct dmub_srv { /* private: internal use only */ const struct dmub_srv_common_regs *regs; const struct dmub_srv_dcn31_regs *regs_dcn31; + const struct dmub_srv_dcn32_regs *regs_dcn32; struct dmub_srv_base_funcs funcs; struct dmub_srv_hw_funcs hw_funcs; diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 385c28238beb..8fc1846f0708 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -641,7 +641,10 @@ enum dmub_cmd_type { * Command type used for all panel control commands. */ DMUB_CMD__PANEL_CNTL = 74, - + /** + * Command type used for + */ + DMUB_CMD__CAB_FOR_SS = 75, /** * Command type used for interfacing with DPIA. */ @@ -878,6 +881,23 @@ struct dmub_rb_cmd_mall { uint8_t reserved2; /**< Reserved bits */ }; +/** + * enum dmub_cmd_cab_type - TODO: + */ +enum dmub_cmd_cab_type { + DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, + DMUB_CMD__CAB_NO_DCN_REQ = 1, + DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, +}; + +/** + * struct dmub_rb_cmd_cab_for_ss - TODO: + */ +struct dmub_rb_cmd_cab_for_ss { + struct dmub_cmd_header header; + uint8_t cab_alloc_ways; /* total number of ways */ + uint8_t debug_bits; /* debug bits */ +}; /** * enum dmub_cmd_idle_opt_type - Idle optimization command type. */ @@ -2693,6 +2713,10 @@ union dmub_rb_cmd { * Definition of a DMUB_CMD__MALL command. */ struct dmub_rb_cmd_mall mall; + /** + * Definition of a DMUB_CMD__CAB command. + */ + struct dmub_rb_cmd_cab_for_ss cab; /** * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. */ diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile index 856c7f48de7a..0589ad4778ee 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/Makefile +++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile @@ -23,6 +23,7 @@ DMUB = dmub_srv.o dmub_srv_stat.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o DMUB += dmub_dcn30.o dmub_dcn301.o dmub_dcn302.o dmub_dcn303.o DMUB += dmub_dcn31.o dmub_dcn315.o dmub_dcn316.o +DMUB += dmub_dcn32.o AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB)) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c new file mode 100644 index 000000000000..0a498082ccc6 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c @@ -0,0 +1,488 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "../dmub_srv.h" +#include "dmub_reg.h" +#include "dmub_dcn32.h" + +#include "dcn/dcn_3_2_0_offset.h" +#include "dcn/dcn_3_2_0_sh_mask.h" + +#define DCN_BASE__INST0_SEG2 0x000034C0 + +#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg +#define CTX dmub +#define REGS dmub->regs_dcn32 +#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name) + +const struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs = { +#define DMUB_SR(reg) REG_OFFSET_EXP(reg), + { DMUB_DCN32_REGS() }, +#undef DMUB_SR + +#define DMUB_SF(reg, field) FD_MASK(reg, field), + { DMUB_DCN32_FIELDS() }, +#undef DMUB_SF + +#define DMUB_SF(reg, field) FD_SHIFT(reg, field), + { DMUB_DCN32_FIELDS() }, +#undef DMUB_SF +}; + +static void dmub_dcn32_get_fb_base_offset(struct dmub_srv *dmub, + uint64_t *fb_base, + uint64_t *fb_offset) +{ + uint32_t tmp; + + if (dmub->fb_base || dmub->fb_offset) { + *fb_base = dmub->fb_base; + *fb_offset = dmub->fb_offset; + return; + } + + REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); + *fb_base = (uint64_t)tmp << 24; + + REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); + *fb_offset = (uint64_t)tmp << 24; +} + +static inline void dmub_dcn32_translate_addr(const union dmub_addr *addr_in, + uint64_t fb_base, + uint64_t fb_offset, + union dmub_addr *addr_out) +{ + addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; +} + +void dmub_dcn32_reset(struct dmub_srv *dmub) +{ + union dmub_gpint_data_register cmd; + const uint32_t timeout = 30; + uint32_t in_reset, scratch, i; + + REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); + + if (in_reset == 0) { + cmd.bits.status = 1; + cmd.bits.command_code = DMUB_GPINT__STOP_FW; + cmd.bits.param = 0; + + dmub->hw_funcs.set_gpint(dmub, cmd); + + /** + * Timeout covers both the ACK and the wait + * for remaining work to finish. + * + * This is mostly bound by the PHY disable sequence. + * Each register check will be greater than 1us, so + * don't bother using udelay. + */ + + for (i = 0; i < timeout; ++i) { + if (dmub->hw_funcs.is_gpint_acked(dmub, cmd)) + break; + } + + for (i = 0; i < timeout; ++i) { + scratch = dmub->hw_funcs.get_gpint_response(dmub); + if (scratch == DMUB_GPINT__STOP_FW_RESPONSE) + break; + } + + /* Clear the GPINT command manually so we don't reset again. */ + cmd.all = 0; + dmub->hw_funcs.set_gpint(dmub, cmd); + + /* Force reset in case we timed out, DMCUB is likely hung. */ + } + + REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1); + REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); + REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1); + REG_WRITE(DMCUB_INBOX1_RPTR, 0); + REG_WRITE(DMCUB_INBOX1_WPTR, 0); + REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); + REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); + REG_WRITE(DMCUB_SCRATCH0, 0); +} + +void dmub_dcn32_reset_release(struct dmub_srv *dmub) +{ + REG_WRITE(DMCUB_GPINT_DATAIN1, 0); + REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0); + REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); + REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1); + REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0); +} + +void dmub_dcn32_backdoor_load(struct dmub_srv *dmub, + const struct dmub_window *cw0, + const struct dmub_window *cw1) +{ + union dmub_addr offset; + uint64_t fb_base, fb_offset; + + dmub_dcn32_get_fb_base_offset(dmub, &fb_base, &fb_offset); + + REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); + + dmub_dcn32_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); + + REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); + REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, + DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, + DMCUB_REGION3_CW0_ENABLE, 1); + + dmub_dcn32_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); + + REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); + REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, + DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, + DMCUB_REGION3_CW1_ENABLE, 1); + + REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, + 0x20); +} + +void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub, + const struct dmub_window *cw0, + const struct dmub_window *cw1) +{ + union dmub_addr offset; + + REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); + + offset = cw0->offset; + + REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); + REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, + DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, + DMCUB_REGION3_CW0_ENABLE, 1); + + offset = cw1->offset; + + REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); + REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, + DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, + DMCUB_REGION3_CW1_ENABLE, 1); + + REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, + 0x20); +} + +void dmub_dcn32_setup_windows(struct dmub_srv *dmub, + const struct dmub_window *cw2, + const struct dmub_window *cw3, + const struct dmub_window *cw4, + const struct dmub_window *cw5, + const struct dmub_window *cw6) +{ + union dmub_addr offset; + + offset = cw3->offset; + + REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); + REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, + DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, + DMCUB_REGION3_CW3_ENABLE, 1); + + offset = cw4->offset; + + REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); + REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, + DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, + DMCUB_REGION3_CW4_ENABLE, 1); + + offset = cw5->offset; + + REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); + REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, + DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, + DMCUB_REGION3_CW5_ENABLE, 1); + + REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); + REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, + DMCUB_REGION5_TOP_ADDRESS, + cw5->region.top - cw5->region.base - 1, + DMCUB_REGION5_ENABLE, 1); + + offset = cw6->offset; + + REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); + REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, + DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, + DMCUB_REGION3_CW6_ENABLE, 1); +} + +void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub, + const struct dmub_region *inbox1) +{ + REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base); + REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); +} + +uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_INBOX1_RPTR); +} + +void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) +{ + REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); +} + +void dmub_dcn32_setup_out_mailbox(struct dmub_srv *dmub, + const struct dmub_region *outbox1) +{ + REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base); + REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base); +} + +uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub) +{ + /** + * outbox1 wptr register is accessed without locks (dal & dc) + * and to be called only by dmub_srv_stat_get_notification() + */ + return REG_READ(DMCUB_OUTBOX1_WPTR); +} + +void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) +{ + /** + * outbox1 rptr register is accessed without locks (dal & dc) + * and to be called only by dmub_srv_stat_get_notification() + */ + REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); +} + +bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub) +{ + uint32_t is_hw_init; + + REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); + + return is_hw_init != 0; +} + +bool dmub_dcn32_is_supported(struct dmub_srv *dmub) +{ + uint32_t supported = 0; + + REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); + + return supported; +} + +void dmub_dcn32_set_gpint(struct dmub_srv *dmub, + union dmub_gpint_data_register reg) +{ + REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all); +} + +bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub, + union dmub_gpint_data_register reg) +{ + union dmub_gpint_data_register test; + + reg.bits.status = 0; + test.all = REG_READ(DMCUB_GPINT_DATAIN1); + + return test.all == reg.all; +} + +uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_SCRATCH7); +} + +uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub) +{ + uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT); + + REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0); + + REG_WRITE(DMCUB_GPINT_DATAOUT, 0); + REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1); + REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0); + + REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1); + + return dataout; +} + +union dmub_fw_boot_status dmub_dcn32_get_fw_boot_status(struct dmub_srv *dmub) +{ + union dmub_fw_boot_status status; + + status.all = REG_READ(DMCUB_SCRATCH0); + return status; +} + +void dmub_dcn32_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params) +{ + union dmub_fw_boot_options boot_options = {0}; + + boot_options.bits.z10_disable = params->disable_z10; + + REG_WRITE(DMCUB_SCRATCH14, boot_options.all); +} + +void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip) +{ + union dmub_fw_boot_options boot_options; + boot_options.all = REG_READ(DMCUB_SCRATCH14); + boot_options.bits.skip_phy_init_panel_sequence = skip; + REG_WRITE(DMCUB_SCRATCH14, boot_options.all); +} + +void dmub_dcn32_setup_outbox0(struct dmub_srv *dmub, + const struct dmub_region *outbox0) +{ + REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base); + + REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base); +} + +uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_OUTBOX0_WPTR); +} + +void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) +{ + REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); +} + +uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_TIMER_CURRENT); +} + +void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) +{ + uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset; + uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled; + + if (!dmub || !diag_data) + return; + + memset(diag_data, 0, sizeof(*diag_data)); + + diag_data->dmcub_version = dmub->fw_version; + + diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0); + diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1); + diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2); + diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3); + diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4); + diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5); + diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6); + diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7); + diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8); + diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9); + diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10); + diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11); + diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12); + diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13); + diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14); + diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15); + + diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); + diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); + diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); + + diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); + diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); + diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); + + diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); + diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); + diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); + + REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); + diag_data->is_dmcub_enabled = is_dmub_enabled; + + REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); + diag_data->is_dmcub_soft_reset = is_soft_reset; + + REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); + diag_data->is_dmcub_secure_reset = is_sec_reset; + + REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); + diag_data->is_traceport_en = is_traceport_enabled; + + REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); + diag_data->is_cw0_enabled = is_cw0_enabled; + + REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); + diag_data->is_cw6_enabled = is_cw6_enabled; +} +void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub) +{ + /* DMCUB_REGION3_TMR_AXI_SPACE values: + * 0b011 (0x3) - FB physical address + * 0b100 (0x4) - GPU virtual address + * + * Default value is 0x3 (FB Physical address for TMR). When programming + * DMUB to be in system memory, change to 0x4. The system memory allocated + * is accessible by both GPU and CPU, so we use GPU virtual address. + */ + REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4); +} + +void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data) +{ + REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all); +} + +void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub) +{ + REG_WRITE(DMCUB_SCRATCH17, 0); +} + +uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_SCRATCH17); +} diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h new file mode 100644 index 000000000000..7d1a6eb4d665 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h @@ -0,0 +1,256 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _DMUB_DCN32_H_ +#define _DMUB_DCN32_H_ + +#include "dmub_dcn31.h" + +struct dmub_srv; + +/* DCN32 register definitions. */ + +#define DMUB_DCN32_REGS() \ + DMUB_SR(DMCUB_CNTL) \ + DMUB_SR(DMCUB_CNTL2) \ + DMUB_SR(DMCUB_SEC_CNTL) \ + DMUB_SR(DMCUB_INBOX0_SIZE) \ + DMUB_SR(DMCUB_INBOX0_RPTR) \ + DMUB_SR(DMCUB_INBOX0_WPTR) \ + DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \ + DMUB_SR(DMCUB_INBOX1_SIZE) \ + DMUB_SR(DMCUB_INBOX1_RPTR) \ + DMUB_SR(DMCUB_INBOX1_WPTR) \ + DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \ + DMUB_SR(DMCUB_OUTBOX0_SIZE) \ + DMUB_SR(DMCUB_OUTBOX0_RPTR) \ + DMUB_SR(DMCUB_OUTBOX0_WPTR) \ + DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \ + DMUB_SR(DMCUB_OUTBOX1_SIZE) \ + DMUB_SR(DMCUB_OUTBOX1_RPTR) \ + DMUB_SR(DMCUB_OUTBOX1_WPTR) \ + DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \ + DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \ + DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \ + DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \ + DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \ + DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \ + DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \ + DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \ + DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION4_OFFSET) \ + DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION5_OFFSET) \ + DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \ + DMUB_SR(DMCUB_SCRATCH0) \ + DMUB_SR(DMCUB_SCRATCH1) \ + DMUB_SR(DMCUB_SCRATCH2) \ + DMUB_SR(DMCUB_SCRATCH3) \ + DMUB_SR(DMCUB_SCRATCH4) \ + DMUB_SR(DMCUB_SCRATCH5) \ + DMUB_SR(DMCUB_SCRATCH6) \ + DMUB_SR(DMCUB_SCRATCH7) \ + DMUB_SR(DMCUB_SCRATCH8) \ + DMUB_SR(DMCUB_SCRATCH9) \ + DMUB_SR(DMCUB_SCRATCH10) \ + DMUB_SR(DMCUB_SCRATCH11) \ + DMUB_SR(DMCUB_SCRATCH12) \ + DMUB_SR(DMCUB_SCRATCH13) \ + DMUB_SR(DMCUB_SCRATCH14) \ + DMUB_SR(DMCUB_SCRATCH15) \ + DMUB_SR(DMCUB_SCRATCH16) \ + DMUB_SR(DMCUB_SCRATCH17) \ + DMUB_SR(DMCUB_GPINT_DATAIN1) \ + DMUB_SR(DMCUB_GPINT_DATAOUT) \ + DMUB_SR(CC_DC_PIPE_DIS) \ + DMUB_SR(MMHUBBUB_SOFT_RESET) \ + DMUB_SR(DCN_VM_FB_LOCATION_BASE) \ + DMUB_SR(DCN_VM_FB_OFFSET) \ + DMUB_SR(DMCUB_TIMER_CURRENT) \ + DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \ + DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \ + DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR) \ + DMUB_SR(DMCUB_REGION3_TMR_AXI_SPACE) \ + DMUB_SR(DMCUB_INTERRUPT_ENABLE) \ + DMUB_SR(DMCUB_INTERRUPT_ACK) + +#define DMUB_DCN32_FIELDS() \ + DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \ + DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \ + DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \ + DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \ + DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \ + DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \ + DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \ + DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \ + DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \ + DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \ + DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \ + DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \ + DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \ + DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \ + DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \ + DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \ + DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \ + DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \ + DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \ + DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \ + DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR) \ + DMUB_SF(DMCUB_REGION3_TMR_AXI_SPACE, DMCUB_REGION3_TMR_AXI_SPACE) \ + DMUB_SF(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN) \ + DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK) + +struct dmub_srv_dcn32_reg_offset { +#define DMUB_SR(reg) uint32_t reg; + DMUB_DCN32_REGS() + DMCUB_INTERNAL_REGS() +#undef DMUB_SR +}; + +struct dmub_srv_dcn32_reg_shift { +#define DMUB_SF(reg, field) uint8_t reg##__##field; + DMUB_DCN32_FIELDS() +#undef DMUB_SF +}; + +struct dmub_srv_dcn32_reg_mask { +#define DMUB_SF(reg, field) uint32_t reg##__##field; + DMUB_DCN32_FIELDS() +#undef DMUB_SF +}; + +struct dmub_srv_dcn32_regs { + const struct dmub_srv_dcn32_reg_offset offset; + const struct dmub_srv_dcn32_reg_mask mask; + const struct dmub_srv_dcn32_reg_shift shift; +}; + +extern const struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs; + +void dmub_dcn32_reset(struct dmub_srv *dmub); + +void dmub_dcn32_reset_release(struct dmub_srv *dmub); + +void dmub_dcn32_backdoor_load(struct dmub_srv *dmub, + const struct dmub_window *cw0, + const struct dmub_window *cw1); + +void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub, + const struct dmub_window *cw0, + const struct dmub_window *cw1); + +void dmub_dcn32_setup_windows(struct dmub_srv *dmub, + const struct dmub_window *cw2, + const struct dmub_window *cw3, + const struct dmub_window *cw4, + const struct dmub_window *cw5, + const struct dmub_window *cw6); + +void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub, + const struct dmub_region *inbox1); + +uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub); + +void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset); + +void dmub_dcn32_setup_out_mailbox(struct dmub_srv *dmub, + const struct dmub_region *outbox1); + +uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub); + +void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset); + +bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub); + +bool dmub_dcn32_is_supported(struct dmub_srv *dmub); + +void dmub_dcn32_set_gpint(struct dmub_srv *dmub, + union dmub_gpint_data_register reg); + +bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub, + union dmub_gpint_data_register reg); + +uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub); + +uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub); + +void dmub_dcn32_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params); + +void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip); + +union dmub_fw_boot_status dmub_dcn32_get_fw_boot_status(struct dmub_srv *dmub); + +void dmub_dcn32_setup_outbox0(struct dmub_srv *dmub, + const struct dmub_region *outbox0); + +uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub); + +void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset); + +uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub); + +void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data); + +void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub); +void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data); +void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub); +uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub); + +#endif /* _DMUB_DCN32_H_ */ diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c index 66db5e538c7f..4c6a624f04a7 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c @@ -34,6 +34,7 @@ #include "dmub_dcn31.h" #include "dmub_dcn315.h" #include "dmub_dcn316.h" +#include "dmub_dcn32.h" #include "os_types.h" /* * Note: the DMUB service is standalone. No additional headers should be @@ -260,6 +261,43 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) break; + case DMUB_ASIC_DCN32: + case DMUB_ASIC_DCN321: + dmub->regs_dcn32 = &dmub_srv_dcn32_regs; + funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory; + funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd; + funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register; + funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register; + funcs->reset = dmub_dcn32_reset; + funcs->reset_release = dmub_dcn32_reset_release; + funcs->backdoor_load = dmub_dcn32_backdoor_load; + funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode; + funcs->setup_windows = dmub_dcn32_setup_windows; + funcs->setup_mailbox = dmub_dcn32_setup_mailbox; + funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr; + funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr; + funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox; + funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr; + funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr; + funcs->is_supported = dmub_dcn32_is_supported; + funcs->is_hw_init = dmub_dcn32_is_hw_init; + funcs->set_gpint = dmub_dcn32_set_gpint; + funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked; + funcs->get_gpint_response = dmub_dcn32_get_gpint_response; + funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout; + funcs->get_fw_status = dmub_dcn32_get_fw_boot_status; + funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options; + funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence; + + /* outbox0 call stacks */ + funcs->setup_outbox0 = dmub_dcn32_setup_outbox0; + funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr; + funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr; + funcs->get_current_time = dmub_dcn32_get_current_time; + funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data; + + break; + default: return false; } @@ -501,6 +539,9 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, cw1.region.base = DMUB_CW1_BASE; cw1.region.top = cw1.region.base + stack_fb->size - 1; + if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory) + dmub->hw_funcs.configure_dmub_in_system_memory(dmub); + if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { /** * Read back all the instruction memory so we don't hang the @@ -508,7 +549,11 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, * flushed yet. This only occurs in backdoor loading. */ dmub_flush_buffer_mem(inst_fb); - dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); + + if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode) + dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1); + else + dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); } cw2.offset.quad_part = data_fb->gpu_addr; @@ -583,6 +628,10 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, if (dmub->hw_funcs.enable_dmub_boot_options) dmub->hw_funcs.enable_dmub_boot_options(dmub, params); + if (dmub->hw_funcs.skip_dmub_panel_power_sequence) + dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, + params->skip_panel_power_sequence); + if (dmub->hw_funcs.reset_release) dmub->hw_funcs.reset_release(dmub); -- cgit v1.2.3 From 0efd4374f6b41650863947a7528d45e8ad0f7ae0 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Mon, 21 Feb 2022 16:41:46 -0500 Subject: drm/amd/display: add dcn32 IRQ changes Add DCN3.2.x interrupt support. Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 +- .../amd/display/dc/irq/dcn32/irq_service_dcn32.c | 369 +++++++++++++++++++++ .../amd/display/dc/irq/dcn32/irq_service_dcn32.h | 35 ++ 3 files changed, 413 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.h diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile index 5f49048dde47..41da81c85fdc 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/Makefile +++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile @@ -135,7 +135,6 @@ IRQ_DCN31 = irq_service_dcn31.o AMD_DAL_IRQ_DCN31= $(addprefix $(AMDDALPATH)/dc/irq/dcn31/,$(IRQ_DCN31)) AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN31) - ############################################################################### # DCN 315 ############################################################################### @@ -144,3 +143,12 @@ IRQ_DCN315 = irq_service_dcn315.o AMD_DAL_IRQ_DCN315= $(addprefix $(AMDDALPATH)/dc/irq/dcn315/,$(IRQ_DCN315)) AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN315) + +############################################################################### +# DCN 32 +############################################################################### +IRQ_DCN32 = irq_service_dcn32.o + +AMD_DAL_IRQ_DCN32= $(addprefix $(AMDDALPATH)/dc/irq/dcn32/,$(IRQ_DCN32)) + +AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN32) diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c new file mode 100644 index 000000000000..3f9d6531c563 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c @@ -0,0 +1,369 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" +#include "include/logger_interface.h" +#include "../dce110/irq_service_dce110.h" + +#include "dcn/dcn_3_2_0_offset.h" +#include "dcn/dcn_3_2_0_sh_mask.h" + +#include "irq_service_dcn32.h" + +#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" + +#define DCN_BASE__INST0_SEG2 0x000034C0 + +enum dc_irq_source to_dal_irq_source_dcn32( + struct irq_service *irq_service, + uint32_t src_id, + uint32_t ext_id) +{ + switch (src_id) { + case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK1; + case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK2; + case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK3; + case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK4; + case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK5; + case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK6; + case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP1; + case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP2; + case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP3; + case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP4; + case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP5; + case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP6; + case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE1; + case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE2; + case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE3; + case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE4; + case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE5; + case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE6; + + case DCN_1_0__SRCID__DC_HPD1_INT: + /* generic src_id for all HPD and HPDRX interrupts */ + switch (ext_id) { + case DCN_1_0__CTXID__DC_HPD1_INT: + return DC_IRQ_SOURCE_HPD1; + case DCN_1_0__CTXID__DC_HPD2_INT: + return DC_IRQ_SOURCE_HPD2; + case DCN_1_0__CTXID__DC_HPD3_INT: + return DC_IRQ_SOURCE_HPD3; + case DCN_1_0__CTXID__DC_HPD4_INT: + return DC_IRQ_SOURCE_HPD4; + case DCN_1_0__CTXID__DC_HPD5_INT: + return DC_IRQ_SOURCE_HPD5; + case DCN_1_0__CTXID__DC_HPD6_INT: + return DC_IRQ_SOURCE_HPD6; + case DCN_1_0__CTXID__DC_HPD1_RX_INT: + return DC_IRQ_SOURCE_HPD1RX; + case DCN_1_0__CTXID__DC_HPD2_RX_INT: + return DC_IRQ_SOURCE_HPD2RX; + case DCN_1_0__CTXID__DC_HPD3_RX_INT: + return DC_IRQ_SOURCE_HPD3RX; + case DCN_1_0__CTXID__DC_HPD4_RX_INT: + return DC_IRQ_SOURCE_HPD4RX; + case DCN_1_0__CTXID__DC_HPD5_RX_INT: + return DC_IRQ_SOURCE_HPD5RX; + case DCN_1_0__CTXID__DC_HPD6_RX_INT: + return DC_IRQ_SOURCE_HPD6RX; + default: + return DC_IRQ_SOURCE_INVALID; + } + break; + + default: + return DC_IRQ_SOURCE_INVALID; + } +} + +static bool hpd_ack( + struct irq_service *irq_service, + const struct irq_source_info *info) +{ + uint32_t addr = info->status_reg; + uint32_t value = dm_read_reg(irq_service->ctx, addr); + uint32_t current_status = + get_reg_field_value( + value, + HPD0_DC_HPD_INT_STATUS, + DC_HPD_SENSE_DELAYED); + + dal_irq_service_ack_generic(irq_service, info); + + value = dm_read_reg(irq_service->ctx, info->enable_reg); + + set_reg_field_value( + value, + current_status ? 0 : 1, + HPD0_DC_HPD_INT_CONTROL, + DC_HPD_INT_POLARITY); + + dm_write_reg(irq_service->ctx, info->enable_reg, value); + + return true; +} + +static const struct irq_source_info_funcs hpd_irq_info_funcs = { + .set = NULL, + .ack = hpd_ack +}; + +static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static const struct irq_source_info_funcs pflip_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static const struct irq_source_info_funcs vblank_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +#undef BASE_INNER +#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg + +/* compile time expand base address. */ +#define BASE(seg) \ + BASE_INNER(seg) + +#define SRI(reg_name, block, id)\ + BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name + +#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ + .enable_reg = SRI(reg1, block, reg_num),\ + .enable_mask = \ + block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ + .enable_value = {\ + block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ + ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ + },\ + .ack_reg = SRI(reg2, block, reg_num),\ + .ack_mask = \ + block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ + .ack_value = \ + block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ + +#define hpd_int_entry(reg_num)\ + [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ + IRQ_REG_ENTRY(HPD, reg_num,\ + DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ + DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ + .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ + .funcs = &hpd_irq_info_funcs\ + } + +#define hpd_rx_int_entry(reg_num)\ + [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ + IRQ_REG_ENTRY(HPD, reg_num,\ + DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ + DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ + .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ + .funcs = &hpd_rx_irq_info_funcs\ + } +#define pflip_int_entry(reg_num)\ + [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ + IRQ_REG_ENTRY(HUBPREQ, reg_num,\ + DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ + DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ + .funcs = &pflip_irq_info_funcs\ + } + +/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic + * of DCE's DC_IRQ_SOURCE_VUPDATEx. + */ +#define vupdate_no_lock_int_entry(reg_num)\ + [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ + OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ + .funcs = &vupdate_no_lock_irq_info_funcs\ + } + +#define vblank_int_entry(reg_num)\ + [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ + OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ + .funcs = &vblank_irq_info_funcs\ +} + +#define dummy_irq_entry() \ + {\ + .funcs = &dummy_irq_info_funcs\ + } + +#define i2c_int_entry(reg_num) \ + [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() + +#define dp_sink_int_entry(reg_num) \ + [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() + +#define gpio_pad_int_entry(reg_num) \ + [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() + +#define dc_underflow_int_entry(reg_num) \ + [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() + +static const struct irq_source_info_funcs dummy_irq_info_funcs = { + .set = dal_irq_service_dummy_set, + .ack = dal_irq_service_dummy_ack +}; + +static const struct irq_source_info +irq_source_info_dcn32[DAL_IRQ_SOURCES_NUMBER] = { + [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), + hpd_int_entry(0), + hpd_int_entry(1), + hpd_int_entry(2), + hpd_int_entry(3), + hpd_int_entry(4), + hpd_rx_int_entry(0), + hpd_rx_int_entry(1), + hpd_rx_int_entry(2), + hpd_rx_int_entry(3), + hpd_rx_int_entry(4), + i2c_int_entry(1), + i2c_int_entry(2), + i2c_int_entry(3), + i2c_int_entry(4), + i2c_int_entry(5), + i2c_int_entry(6), + dp_sink_int_entry(1), + dp_sink_int_entry(2), + dp_sink_int_entry(3), + dp_sink_int_entry(4), + dp_sink_int_entry(5), + dp_sink_int_entry(6), + [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), + pflip_int_entry(0), + pflip_int_entry(1), + pflip_int_entry(2), + pflip_int_entry(3), + [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(), + [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(), + [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), + gpio_pad_int_entry(0), + gpio_pad_int_entry(1), + gpio_pad_int_entry(2), + gpio_pad_int_entry(3), + gpio_pad_int_entry(4), + gpio_pad_int_entry(5), + gpio_pad_int_entry(6), + gpio_pad_int_entry(7), + gpio_pad_int_entry(8), + gpio_pad_int_entry(9), + gpio_pad_int_entry(10), + gpio_pad_int_entry(11), + gpio_pad_int_entry(12), + gpio_pad_int_entry(13), + gpio_pad_int_entry(14), + gpio_pad_int_entry(15), + gpio_pad_int_entry(16), + gpio_pad_int_entry(17), + gpio_pad_int_entry(18), + gpio_pad_int_entry(19), + gpio_pad_int_entry(20), + gpio_pad_int_entry(21), + gpio_pad_int_entry(22), + gpio_pad_int_entry(23), + gpio_pad_int_entry(24), + gpio_pad_int_entry(25), + gpio_pad_int_entry(26), + gpio_pad_int_entry(27), + gpio_pad_int_entry(28), + gpio_pad_int_entry(29), + gpio_pad_int_entry(30), + dc_underflow_int_entry(1), + dc_underflow_int_entry(2), + dc_underflow_int_entry(3), + dc_underflow_int_entry(4), + dc_underflow_int_entry(5), + dc_underflow_int_entry(6), + [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), + [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), + vupdate_no_lock_int_entry(0), + vupdate_no_lock_int_entry(1), + vupdate_no_lock_int_entry(2), + vupdate_no_lock_int_entry(3), + vblank_int_entry(0), + vblank_int_entry(1), + vblank_int_entry(2), + vblank_int_entry(3), +}; + +static const struct irq_service_funcs irq_service_funcs_dcn32 = { + .to_dal_irq_source = to_dal_irq_source_dcn32 +}; + +static void dcn32_irq_construct( + struct irq_service *irq_service, + struct irq_service_init_data *init_data) +{ + dal_irq_service_construct(irq_service, init_data); + + irq_service->info = irq_source_info_dcn32; + irq_service->funcs = &irq_service_funcs_dcn32; +} + +struct irq_service *dal_irq_service_dcn32_create( + struct irq_service_init_data *init_data) +{ + struct irq_service *irq_service = kzalloc(sizeof(*irq_service), + GFP_KERNEL); + + if (!irq_service) + return NULL; + + dcn32_irq_construct(irq_service, init_data); + return irq_service; +} diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.h b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.h new file mode 100644 index 000000000000..a0d9c9e4e17f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.h @@ -0,0 +1,35 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + + +#ifndef __DAL_IRQ_SERVICE_DCN32_H__ +#define __DAL_IRQ_SERVICE_DCN32_H__ + +#include "../irq_service.h" + +struct irq_service *dal_irq_service_dcn32_create( + struct irq_service_init_data *init_data); + +#endif /* __DAL_IRQ_SERVICE_DCN32_H__ */ -- cgit v1.2.3 From 58efeea32d5e32fa340c7ee3f52d5f986b240e39 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Mon, 21 Feb 2022 16:55:55 -0500 Subject: drm/amd/display: add GPIO changes for DCN32/321 Add support for the GPIO changes for DCN3.2.x. Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/gpio/Makefile | 8 +- .../amd/display/dc/gpio/dcn32/hw_factory_dcn32.c | 255 +++++++++++++++ .../amd/display/dc/gpio/dcn32/hw_factory_dcn32.h | 31 ++ .../amd/display/dc/gpio/dcn32/hw_translate_dcn32.c | 349 +++++++++++++++++++++ .../amd/display/dc/gpio/dcn32/hw_translate_dcn32.h | 33 ++ .../display/dc/gpio/diagnostics/hw_factory_diag.c | 62 ---- .../display/dc/gpio/diagnostics/hw_factory_diag.h | 34 -- .../dc/gpio/diagnostics/hw_translate_diag.c | 41 --- .../dc/gpio/diagnostics/hw_translate_diag.h | 34 -- drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 16 +- drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 13 +- 11 files changed, 682 insertions(+), 194 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.h create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.h delete mode 100644 drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c delete mode 100644 drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.h delete mode 100644 drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.c delete mode 100644 drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.h diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile index 0f4a22be8c40..bc47481a158e 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile +++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile @@ -115,10 +115,10 @@ AMD_DAL_GPIO_DCN315 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn315/,$(GPIO_DCN315)) AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN315) ############################################################################### -# Diagnostics on FPGA +# DCN 3.2 ############################################################################### -GPIO_DIAG_FPGA = hw_translate_diag.o hw_factory_diag.o +GPIO_DCN32 = hw_translate_dcn32.o hw_factory_dcn32.o -AMD_DAL_GPIO_DIAG_FPGA = $(addprefix $(AMDDALPATH)/dc/gpio/diagnostics/,$(GPIO_DIAG_FPGA)) +AMD_DAL_GPIO_DCN32 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn32/,$(GPIO_DCN32)) -AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DIAG_FPGA) +AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN32) diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c new file mode 100644 index 000000000000..d635b73af46f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c @@ -0,0 +1,255 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "dm_services.h" +#include "include/gpio_types.h" +#include "../hw_factory.h" + + +#include "../hw_gpio.h" +#include "../hw_ddc.h" +#include "../hw_hpd.h" +#include "../hw_generic.h" + +#include "hw_factory_dcn32.h" + +#include "dcn/dcn_3_2_0_offset.h" +#include "dcn/dcn_3_2_0_sh_mask.h" + +#include "reg_helper.h" +#include "../hpd_regs.h" + +#define DCN_BASE__INST0_SEG2 0x000034C0 + +/* begin ********************* + * macros to expend register list macro defined in HW object header file */ + +/* DCN */ +#define block HPD +#define reg_num 0 + +#undef BASE_INNER +#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg + +#define BASE(seg) BASE_INNER(seg) + + + +#define REG(reg_name)\ + BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name + +#define SF_HPD(reg_name, field_name, post_fix)\ + .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix + +#define REGI(reg_name, block, id)\ + BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name + +#define SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + +/* macros to expend register list macro defined in HW object header file + * end *********************/ + + + +#define hpd_regs(id) \ +{\ + HPD_REG_LIST(id)\ +} + +static const struct hpd_registers hpd_regs[] = { + hpd_regs(0), + hpd_regs(1), + hpd_regs(2), + hpd_regs(3), + hpd_regs(4), +}; + +static const struct hpd_sh_mask hpd_shift = { + HPD_MASK_SH_LIST(__SHIFT) +}; + +static const struct hpd_sh_mask hpd_mask = { + HPD_MASK_SH_LIST(_MASK) +}; + +#include "../ddc_regs.h" + + /* set field name */ +#define SF_DDC(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + +static const struct ddc_registers ddc_data_regs_dcn[] = { + ddc_data_regs_dcn2(1), + ddc_data_regs_dcn2(2), + ddc_data_regs_dcn2(3), + ddc_data_regs_dcn2(4), + ddc_data_regs_dcn2(5), + { + DDC_GPIO_VGA_REG_LIST(DATA), + .ddc_setup = 0, + .phy_aux_cntl = 0, + .dc_gpio_aux_ctrl_5 = 0 + } +}; + +static const struct ddc_registers ddc_clk_regs_dcn[] = { + ddc_clk_regs_dcn2(1), + ddc_clk_regs_dcn2(2), + ddc_clk_regs_dcn2(3), + ddc_clk_regs_dcn2(4), + ddc_clk_regs_dcn2(5), + { + DDC_GPIO_VGA_REG_LIST(CLK), + .ddc_setup = 0, + .phy_aux_cntl = 0, + .dc_gpio_aux_ctrl_5 = 0 + } +}; + +static const struct ddc_sh_mask ddc_shift[] = { + DDC_MASK_SH_LIST_DCN2(__SHIFT, 1), + DDC_MASK_SH_LIST_DCN2(__SHIFT, 2), + DDC_MASK_SH_LIST_DCN2(__SHIFT, 3), + DDC_MASK_SH_LIST_DCN2(__SHIFT, 4), + DDC_MASK_SH_LIST_DCN2(__SHIFT, 5), + DDC_MASK_SH_LIST_DCN2(__SHIFT, 6) +}; + +static const struct ddc_sh_mask ddc_mask[] = { + DDC_MASK_SH_LIST_DCN2(_MASK, 1), + DDC_MASK_SH_LIST_DCN2(_MASK, 2), + DDC_MASK_SH_LIST_DCN2(_MASK, 3), + DDC_MASK_SH_LIST_DCN2(_MASK, 4), + DDC_MASK_SH_LIST_DCN2(_MASK, 5), + DDC_MASK_SH_LIST_DCN2(_MASK, 6) +}; + +#include "../generic_regs.h" + +/* set field name */ +#define SF_GENERIC(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + +#define generic_regs(id) \ +{\ + GENERIC_REG_LIST(id)\ +} + +static const struct generic_registers generic_regs[] = { + generic_regs(A), + generic_regs(B), +}; + +static const struct generic_sh_mask generic_shift[] = { + GENERIC_MASK_SH_LIST(__SHIFT, A), + GENERIC_MASK_SH_LIST(__SHIFT, B), +}; + +static const struct generic_sh_mask generic_mask[] = { + GENERIC_MASK_SH_LIST(_MASK, A), + GENERIC_MASK_SH_LIST(_MASK, B), +}; + +static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en) +{ + struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin); + + generic->regs = &generic_regs[en]; + generic->shifts = &generic_shift[en]; + generic->masks = &generic_mask[en]; + generic->base.regs = &generic_regs[en].gpio; +} + +static void define_ddc_registers( + struct hw_gpio_pin *pin, + uint32_t en) +{ + struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); + + switch (pin->id) { + case GPIO_ID_DDC_DATA: + ddc->regs = &ddc_data_regs_dcn[en]; + ddc->base.regs = &ddc_data_regs_dcn[en].gpio; + break; + case GPIO_ID_DDC_CLOCK: + ddc->regs = &ddc_clk_regs_dcn[en]; + ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; + break; + default: + ASSERT_CRITICAL(false); + return; + } + + ddc->shifts = &ddc_shift[en]; + ddc->masks = &ddc_mask[en]; + +} + +static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en) +{ + struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin); + + hpd->regs = &hpd_regs[en]; + hpd->shifts = &hpd_shift; + hpd->masks = &hpd_mask; + hpd->base.regs = &hpd_regs[en].gpio; +} + + +/* fucntion table */ +static const struct hw_factory_funcs funcs = { + .init_ddc_data = dal_hw_ddc_init, + .init_generic = dal_hw_generic_init, + .init_hpd = dal_hw_hpd_init, + .get_ddc_pin = dal_hw_ddc_get_pin, + .get_hpd_pin = dal_hw_hpd_get_pin, + .get_generic_pin = dal_hw_generic_get_pin, + .define_hpd_registers = define_hpd_registers, + .define_ddc_registers = define_ddc_registers, + .define_generic_registers = define_generic_registers +}; +/* + * dal_hw_factory_dcn32_init + * + * @brief + * Initialize HW factory function pointers and pin info + * + * @param + * struct hw_factory *factory - [out] struct of function pointers + */ +void dal_hw_factory_dcn32_init(struct hw_factory *factory) +{ + factory->number_of_pins[GPIO_ID_DDC_DATA] = 6; + factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 6; + factory->number_of_pins[GPIO_ID_GENERIC] = 4; + factory->number_of_pins[GPIO_ID_HPD] = 5; + factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28; + factory->number_of_pins[GPIO_ID_VIP_PAD] = 0; + factory->number_of_pins[GPIO_ID_SYNC] = 0; + factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/ + + factory->funcs = &funcs; +} diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.h new file mode 100644 index 000000000000..71138d0e192b --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.h @@ -0,0 +1,31 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#ifndef __DAL_HW_FACTORY_DCN32_H__ +#define __DAL_HW_FACTORY_DCN32_H__ + +/* Initialize HW factory function pointers and pin info */ +void dal_hw_factory_dcn32_init(struct hw_factory *factory); + +#endif /* __DAL_HW_FACTORY_DCN32_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c new file mode 100644 index 000000000000..8493b9981f9e --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c @@ -0,0 +1,349 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +/* + * Pre-requisites: headers required by header of this unit + */ +#include "hw_translate_dcn32.h" + +#include "dm_services.h" +#include "include/gpio_types.h" +#include "../hw_translate.h" + +#include "dcn/dcn_3_2_0_offset.h" +#include "dcn/dcn_3_2_0_sh_mask.h" + +#define DCN_BASE__INST0_SEG2 0x000034C0 + +/* begin ********************* + * macros to expend register list macro defined in HW object header file */ + +/* DCN */ +#define block HPD +#define reg_num 0 + +#undef BASE_INNER +#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg + +#define BASE(seg) BASE_INNER(seg) + +#undef REG +#define REG(reg_name)\ + BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name +#define SF_HPD(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + + +/* macros to expend register list macro defined in HW object header file + * end *********************/ + + +static bool offset_to_id( + uint32_t offset, + uint32_t mask, + enum gpio_id *id, + uint32_t *en) +{ + switch (offset) { + /* GENERIC */ + case REG(DC_GPIO_GENERIC_A): + *id = GPIO_ID_GENERIC; + switch (mask) { + case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK: + *en = GPIO_GENERIC_A; + return true; + case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK: + *en = GPIO_GENERIC_B; + return true; + case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK: + *en = GPIO_GENERIC_C; + return true; + case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK: + *en = GPIO_GENERIC_D; + return true; + case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK: + *en = GPIO_GENERIC_E; + return true; + case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK: + *en = GPIO_GENERIC_F; + return true; + default: + ASSERT_CRITICAL(false); + return false; + } + break; + /* HPD */ + case REG(DC_GPIO_HPD_A): + *id = GPIO_ID_HPD; + switch (mask) { + case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK: + *en = GPIO_HPD_1; + return true; + case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK: + *en = GPIO_HPD_2; + return true; + case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK: + *en = GPIO_HPD_3; + return true; + case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK: + *en = GPIO_HPD_4; + return true; + case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK: + *en = GPIO_HPD_5; + return true; + default: + ASSERT_CRITICAL(false); + return false; + } + break; + /* REG(DC_GPIO_GENLK_MASK */ + case REG(DC_GPIO_GENLK_A): + *id = GPIO_ID_GSL; + switch (mask) { + case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK: + *en = GPIO_GSL_GENLOCK_CLOCK; + return true; + case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK: + *en = GPIO_GSL_GENLOCK_VSYNC; + return true; + case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK: + *en = GPIO_GSL_SWAPLOCK_A; + return true; + case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK: + *en = GPIO_GSL_SWAPLOCK_B; + return true; + default: + ASSERT_CRITICAL(false); + return false; + } + break; + /* DDC */ + /* we don't care about the GPIO_ID for DDC + * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK + * directly in the create method */ + case REG(DC_GPIO_DDC1_A): + *en = GPIO_DDC_LINE_DDC1; + return true; + case REG(DC_GPIO_DDC2_A): + *en = GPIO_DDC_LINE_DDC2; + return true; + case REG(DC_GPIO_DDC3_A): + *en = GPIO_DDC_LINE_DDC3; + return true; + case REG(DC_GPIO_DDC4_A): + *en = GPIO_DDC_LINE_DDC4; + return true; + case REG(DC_GPIO_DDC5_A): + *en = GPIO_DDC_LINE_DDC5; + return true; + case REG(DC_GPIO_DDCVGA_A): + *en = GPIO_DDC_LINE_DDC_VGA; + return true; + default: + ASSERT_CRITICAL(false); + return false; + } +} + +static bool id_to_offset( + enum gpio_id id, + uint32_t en, + struct gpio_pin_info *info) +{ + bool result = true; + + switch (id) { + case GPIO_ID_DDC_DATA: + info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK; + switch (en) { + case GPIO_DDC_LINE_DDC1: + info->offset = REG(DC_GPIO_DDC1_A); + break; + case GPIO_DDC_LINE_DDC2: + info->offset = REG(DC_GPIO_DDC2_A); + break; + case GPIO_DDC_LINE_DDC3: + info->offset = REG(DC_GPIO_DDC3_A); + break; + case GPIO_DDC_LINE_DDC4: + info->offset = REG(DC_GPIO_DDC4_A); + break; + case GPIO_DDC_LINE_DDC5: + info->offset = REG(DC_GPIO_DDC5_A); + break; + case GPIO_DDC_LINE_DDC_VGA: + info->offset = REG(DC_GPIO_DDCVGA_A); + break; + case GPIO_DDC_LINE_I2C_PAD: + default: + ASSERT_CRITICAL(false); + result = false; + } + break; + case GPIO_ID_DDC_CLOCK: + info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK; + switch (en) { + case GPIO_DDC_LINE_DDC1: + info->offset = REG(DC_GPIO_DDC1_A); + break; + case GPIO_DDC_LINE_DDC2: + info->offset = REG(DC_GPIO_DDC2_A); + break; + case GPIO_DDC_LINE_DDC3: + info->offset = REG(DC_GPIO_DDC3_A); + break; + case GPIO_DDC_LINE_DDC4: + info->offset = REG(DC_GPIO_DDC4_A); + break; + case GPIO_DDC_LINE_DDC5: + info->offset = REG(DC_GPIO_DDC5_A); + break; + case GPIO_DDC_LINE_DDC_VGA: + info->offset = REG(DC_GPIO_DDCVGA_A); + break; + case GPIO_DDC_LINE_I2C_PAD: + default: + ASSERT_CRITICAL(false); + result = false; + } + break; + case GPIO_ID_GENERIC: + info->offset = REG(DC_GPIO_GENERIC_A); + switch (en) { + case GPIO_GENERIC_A: + info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK; + break; + case GPIO_GENERIC_B: + info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK; + break; + case GPIO_GENERIC_C: + info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK; + break; + case GPIO_GENERIC_D: + info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK; + break; + case GPIO_GENERIC_E: + info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK; + break; + case GPIO_GENERIC_F: + info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK; + break; + default: + ASSERT_CRITICAL(false); + result = false; + } + break; + case GPIO_ID_HPD: + info->offset = REG(DC_GPIO_HPD_A); + switch (en) { + case GPIO_HPD_1: + info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK; + break; + case GPIO_HPD_2: + info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK; + break; + case GPIO_HPD_3: + info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK; + break; + case GPIO_HPD_4: + info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK; + break; + case GPIO_HPD_5: + info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK; + break; + default: + ASSERT_CRITICAL(false); + result = false; + } + break; + case GPIO_ID_GSL: + switch (en) { + case GPIO_GSL_GENLOCK_CLOCK: + /*not implmented*/ + ASSERT_CRITICAL(false); + result = false; + break; + case GPIO_GSL_GENLOCK_VSYNC: + /*not implmented*/ + ASSERT_CRITICAL(false); + result = false; + break; + case GPIO_GSL_SWAPLOCK_A: + /*not implmented*/ + ASSERT_CRITICAL(false); + result = false; + break; + case GPIO_GSL_SWAPLOCK_B: + /*not implmented*/ + ASSERT_CRITICAL(false); + result = false; + + break; + default: + ASSERT_CRITICAL(false); + result = false; + } + break; + case GPIO_ID_SYNC: + case GPIO_ID_VIP_PAD: + default: + ASSERT_CRITICAL(false); + result = false; + } + + if (result) { + info->offset_y = info->offset + 2; + info->offset_en = info->offset + 1; + info->offset_mask = info->offset - 1; + + info->mask_y = info->mask; + info->mask_en = info->mask; + info->mask_mask = info->mask; + } + + return result; +} + +/* function table */ +static const struct hw_translate_funcs funcs = { + .offset_to_id = offset_to_id, + .id_to_offset = id_to_offset, +}; + +/* + * dal_hw_translate_dcn32_init + * + * @brief + * Initialize Hw translate function pointers. + * + * @param + * struct hw_translate *tr - [out] struct of function pointers + * + */ +void dal_hw_translate_dcn32_init(struct hw_translate *tr) +{ + tr->funcs = &funcs; +} + diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.h new file mode 100644 index 000000000000..af64e104d84c --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.h @@ -0,0 +1,33 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#ifndef __DAL_HW_TRANSLATE_DCN32_H__ +#define __DAL_HW_TRANSLATE_DCN32_H__ + +struct hw_translate; + +/* Initialize Hw translate function pointers */ +void dal_hw_translate_dcn32_init(struct hw_translate *tr); + +#endif /* __DAL_HW_TRANSLATE_DCN32_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c b/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c deleted file mode 100644 index c6e28f6bf1a2..000000000000 --- a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright 2013-16 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -/* - * Pre-requisites: headers required by header of this unit - */ - -#include "dm_services.h" -#include "hw_factory_diag.h" -#include "include/gpio_types.h" -#include "../hw_factory.h" - -/* - * Header of this unit - */ - -#include "../hw_gpio.h" -#include "../hw_ddc.h" -#include "../hw_hpd.h" -#include "../hw_generic.h" - -/* function table */ -static const struct hw_factory_funcs funcs = { - .init_ddc_data = NULL, - .init_generic = NULL, - .init_hpd = NULL, -}; - -void dal_hw_factory_diag_fpga_init(struct hw_factory *factory) -{ - factory->number_of_pins[GPIO_ID_DDC_DATA] = 8; - factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8; - factory->number_of_pins[GPIO_ID_GENERIC] = 7; - factory->number_of_pins[GPIO_ID_HPD] = 6; - factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31; - factory->number_of_pins[GPIO_ID_VIP_PAD] = 0; - factory->number_of_pins[GPIO_ID_SYNC] = 2; - factory->number_of_pins[GPIO_ID_GSL] = 4; - factory->funcs = &funcs; -} diff --git a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.h b/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.h deleted file mode 100644 index bf68eb1d9a1d..000000000000 --- a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright 2013-16 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DAL_HW_FACTORY_DIAG_FPGA_H__ -#define __DAL_HW_FACTORY_DIAG_FPGA_H__ - -struct hw_factory; - -/* Initialize HW factory function pointers and pin info */ -void dal_hw_factory_diag_fpga_init(struct hw_factory *factory); - -#endif /* __DAL_HW_FACTORY_DIAG_FPGA_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.c b/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.c deleted file mode 100644 index e5138a5a8eb5..000000000000 --- a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2013-16 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "hw_translate_diag.h" -#include "include/gpio_types.h" - -#include "../hw_translate.h" - -/* function table */ -static const struct hw_translate_funcs funcs = { - .offset_to_id = NULL, - .id_to_offset = NULL, -}; - -void dal_hw_translate_diag_fpga_init(struct hw_translate *tr) -{ - tr->funcs = &funcs; -} diff --git a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.h b/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.h deleted file mode 100644 index 4f053241fe96..000000000000 --- a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright 2013-16 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DAL_HW_TRANSLATE_DIAG_FPGA_H__ -#define __DAL_HW_TRANSLATE_DIAG_FPGA_H__ - -struct hw_translate; - -/* Initialize Hw translate function pointers */ -void dal_hw_translate_diag_fpga_init(struct hw_translate *tr); - -#endif /* __DAL_HW_TRANSLATE_DIAG_FPGA_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c index ef4f69612097..9756640411b9 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c @@ -53,23 +53,13 @@ #include "dcn21/hw_factory_dcn21.h" #include "dcn30/hw_factory_dcn30.h" #include "dcn315/hw_factory_dcn315.h" - -#include "diagnostics/hw_factory_diag.h" - -/* - * This unit - */ +#include "dcn32/hw_factory_dcn32.h" bool dal_hw_factory_init( struct hw_factory *factory, enum dce_version dce_version, enum dce_environment dce_environment) { - if (IS_FPGA_MAXIMUS_DC(dce_environment)) { - dal_hw_factory_diag_fpga_init(factory); - return true; - } - switch (dce_version) { #if defined(CONFIG_DRM_AMD_DC_SI) case DCE_VERSION_6_0: @@ -118,6 +108,10 @@ bool dal_hw_factory_init( case DCN_VERSION_3_15: dal_hw_factory_dcn315_init(factory); return true; + case DCN_VERSION_3_2: + case DCN_VERSION_3_21: + dal_hw_factory_dcn32_init(factory); + return true; default: ASSERT_CRITICAL(false); return false; diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c index 1db4f1414d7e..82aad7bc0300 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c @@ -51,8 +51,7 @@ #include "dcn21/hw_translate_dcn21.h" #include "dcn30/hw_translate_dcn30.h" #include "dcn315/hw_translate_dcn315.h" - -#include "diagnostics/hw_translate_diag.h" +#include "dcn32/hw_translate_dcn32.h" /* * This unit @@ -63,11 +62,6 @@ bool dal_hw_translate_init( enum dce_version dce_version, enum dce_environment dce_environment) { - if (IS_FPGA_MAXIMUS_DC(dce_environment)) { - dal_hw_translate_diag_fpga_init(translate); - return true; - } - switch (dce_version) { #if defined(CONFIG_DRM_AMD_DC_SI) case DCE_VERSION_6_0: @@ -113,7 +107,10 @@ bool dal_hw_translate_init( case DCN_VERSION_3_15: dal_hw_translate_dcn315_init(translate); return true; - + case DCN_VERSION_3_2: + case DCN_VERSION_3_21: + dal_hw_translate_dcn32_init(translate); + return true; default: BREAK_TO_DEBUGGER(); return false; -- cgit v1.2.3 From dda4fb85e433f761eedaed0005a2bc20d705d504 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Mon, 21 Feb 2022 16:58:49 -0500 Subject: drm/amd/display: DML changes for DCN32/321 DML is required for display configuration modelling for things like bandwidth management and validation. Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dml/Makefile | 7 + .../amd/display/dc/dml/dcn30/display_mode_vba_30.c | 8 +- .../amd/display/dc/dml/dcn31/display_mode_vba_31.c | 2 +- .../amd/display/dc/dml/dcn32/display_mode_vba_32.c | 3835 ++++++++++++ .../amd/display/dc/dml/dcn32/display_mode_vba_32.h | 57 + .../dc/dml/dcn32/display_mode_vba_util_32.c | 6254 ++++++++++++++++++++ .../dc/dml/dcn32/display_mode_vba_util_32.h | 1175 ++++ .../display/dc/dml/dcn32/display_rq_dlg_calc_32.c | 616 ++ .../display/dc/dml/dcn32/display_rq_dlg_calc_32.h | 70 + .../drm/amd/display/dc/dml/display_mode_enums.h | 88 +- .../gpu/drm/amd/display/dc/dml/display_mode_lib.c | 12 + .../gpu/drm/amd/display/dc/dml/display_mode_lib.h | 15 + .../drm/amd/display/dc/dml/display_mode_structs.h | 132 + .../gpu/drm/amd/display/dc/dml/display_mode_vba.c | 171 + .../gpu/drm/amd/display/dc/dml/display_mode_vba.h | 242 +- drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c | 71 +- 16 files changed, 12710 insertions(+), 45 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.h diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile index a64b88ca01a9..c48688cdd7f7 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile @@ -72,6 +72,9 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_ccflags) $(frame_warn_flag) CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/dcn30_fpu.o := $(dml_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_32.o := $(dml_ccflags) $(frame_warn_flag) +CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_rq_dlg_calc_32.o := $(dml_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_util_32.o := $(dml_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/dcn31_fpu.o := $(dml_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml/dcn302/dcn302_fpu.o := $(dml_ccflags) @@ -93,6 +96,9 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_32.o := $(dml_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_rq_dlg_calc_32.o := $(dml_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_util_32.o := $(dml_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dsc/rc_calc_fpu.o := $(dml_rcflags) @@ -116,6 +122,7 @@ DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o DML += dcn30/dcn30_fpu.o dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o DML += dcn31/display_mode_vba_31.o dcn31/display_rq_dlg_calc_31.o +DML += dcn32/display_mode_vba_32.o dcn32/display_rq_dlg_calc_32.o dcn32/display_mode_vba_util_32.o DML += dcn31/dcn31_fpu.o DML += dcn301/dcn301_fpu.o DML += dcn302/dcn302_fpu.o diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index f47d82da115c..fb4aa4c800bf 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -438,8 +438,8 @@ static void UseMinimumDCFCLK( int dpte_group_bytes[], double PrefetchLinesY[][2][DC__NUM_DPP__MAX], double PrefetchLinesC[][2][DC__NUM_DPP__MAX], - int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX], - int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX], + unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX], + unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX], int BytePerPixelY[], int BytePerPixelC[], int HTotal[], @@ -6696,8 +6696,8 @@ static void UseMinimumDCFCLK( int dpte_group_bytes[], double PrefetchLinesY[][2][DC__NUM_DPP__MAX], double PrefetchLinesC[][2][DC__NUM_DPP__MAX], - int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX], - int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX], + unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX], + unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX], int BytePerPixelY[], int BytePerPixelC[], int HTotal[], diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c index e4b9fd31223c..448fbbcdf88a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c @@ -2996,7 +2996,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->ImmediateFlipSupported)) ? true : false; #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: PrefetchModeSupported %d\n", __func__, v->PrefetchModeSupported); - dml_print("DML::%s: ImmediateFlipRequirement %d\n", __func__, v->ImmediateFlipRequirement == dm_immediate_flip_required); + dml_print("DML::%s: ImmediateFlipRequirement[0] %d\n", __func__, v->ImmediateFlipRequirement[0] == dm_immediate_flip_required); dml_print("DML::%s: ImmediateFlipSupported %d\n", __func__, v->ImmediateFlipSupported); dml_print("DML::%s: ImmediateFlipSupport %d\n", __func__, v->ImmediateFlipSupport); dml_print("DML::%s: HostVMEnable %d\n", __func__, v->HostVMEnable); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c new file mode 100644 index 000000000000..b77a1ae792d1 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -0,0 +1,3835 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dc.h" +#include "dc_link.h" +#include "../display_mode_lib.h" +#include "display_mode_vba_32.h" +#include "../dml_inline_defs.h" +#include "display_mode_vba_util_32.h" + +static const unsigned int NumberOfStates = DC__VOLTAGE_STATES; + +void dml32_recalculate(struct display_mode_lib *mode_lib); +static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation( + struct display_mode_lib *mode_lib); +void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib); + +void dml32_recalculate(struct display_mode_lib *mode_lib) +{ + ModeSupportAndSystemConfiguration(mode_lib); + + dml32_CalculateMaxDETAndMinCompressedBufferSize(mode_lib->vba.ConfigReturnBufferSizeInKByte, + mode_lib->vba.ROBBufferSizeInKByte, + DC__NUM_DPP, + false, //mode_lib->vba.override_setting.nomDETInKByteOverrideEnable, + 0, //mode_lib->vba.override_setting.nomDETInKByteOverrideValue, + + /* Output */ + &mode_lib->vba.MaxTotalDETInKByte, &mode_lib->vba.nomDETInKByte, + &mode_lib->vba.MinCompressedBufferSizeInKByte); + + PixelClockAdjustmentForProgressiveToInterlaceUnit(mode_lib); +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: Calling DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation\n", __func__); +#endif + DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(mode_lib); +} + +static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation( + struct display_mode_lib *mode_lib) +{ + struct vba_vars_st *v = &mode_lib->vba; + unsigned int j, k; + bool ImmediateFlipRequirementFinal; + int iteration; + double MaxTotalRDBandwidth; + unsigned int NextPrefetchMode; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: --- START ---\n", __func__); + dml_print("DML::%s: mode_lib->vba.PrefetchMode = %d\n", __func__, mode_lib->vba.PrefetchMode); + dml_print("DML::%s: mode_lib->vba.ImmediateFlipSupport = %d\n", __func__, mode_lib->vba.ImmediateFlipSupport); + dml_print("DML::%s: mode_lib->vba.VoltageLevel = %d\n", __func__, mode_lib->vba.VoltageLevel); +#endif + + v->WritebackDISPCLK = 0.0; + v->GlobalDPPCLK = 0.0; + + // DISPCLK and DPPCLK Calculation + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.WritebackEnable[k]) { + v->WritebackDISPCLK = dml_max(v->WritebackDISPCLK, + dml32_CalculateWriteBackDISPCLK( + mode_lib->vba.WritebackPixelFormat[k], + mode_lib->vba.PixelClock[k], mode_lib->vba.WritebackHRatio[k], + mode_lib->vba.WritebackVRatio[k], + mode_lib->vba.WritebackHTaps[k], + mode_lib->vba.WritebackVTaps[k], + mode_lib->vba.WritebackSourceWidth[k], + mode_lib->vba.WritebackDestinationWidth[k], + mode_lib->vba.HTotal[k], mode_lib->vba.WritebackLineBufferSize, + mode_lib->vba.DISPCLKDPPCLKVCOSpeed)); + } + } + + v->DISPCLK_calculated = v->WritebackDISPCLK; + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.BlendingAndTiming[k] == k) { + v->DISPCLK_calculated = dml_max(v->DISPCLK_calculated, + dml32_CalculateRequiredDispclk( + mode_lib->vba.ODMCombineEnabled[k], + mode_lib->vba.PixelClock[k], + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading, + mode_lib->vba.DISPCLKRampingMargin, + mode_lib->vba.DISPCLKDPPCLKVCOSpeed, + mode_lib->vba.MaxDppclk[v->soc.num_states - 1])); + } + } + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(mode_lib->vba.HRatio[k], + mode_lib->vba.HRatioChroma[k], + mode_lib->vba.VRatio[k], + mode_lib->vba.VRatioChroma[k], + mode_lib->vba.MaxDCHUBToPSCLThroughput, + mode_lib->vba.MaxPSCLToLBThroughput, + mode_lib->vba.PixelClock[k], + mode_lib->vba.SourcePixelFormat[k], + mode_lib->vba.htaps[k], + mode_lib->vba.HTAPsChroma[k], + mode_lib->vba.vtaps[k], + mode_lib->vba.VTAPsChroma[k], + + /* Output */ + &v->PSCL_THROUGHPUT_LUMA[k], &v->PSCL_THROUGHPUT_CHROMA[k], + &v->DPPCLKUsingSingleDPP[k]); + } + + dml32_CalculateDPPCLK(mode_lib->vba.NumberOfActiveSurfaces, mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading, + mode_lib->vba.DISPCLKDPPCLKVCOSpeed, v->DPPCLKUsingSingleDPP, mode_lib->vba.DPPPerPlane, + /* Output */ + &v->GlobalDPPCLK, v->DPPCLK); + + for (k = 0; k < v->NumberOfActiveSurfaces; ++k) { + v->DPPCLK_calculated[k] = v->DPPCLK[k]; + } + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + dml32_CalculateBytePerPixelAndBlockSizes( + mode_lib->vba.SourcePixelFormat[k], + mode_lib->vba.SurfaceTiling[k], + + /* Output */ + &v->BytePerPixelY[k], + &v->BytePerPixelC[k], + &v->BytePerPixelDETY[k], + &v->BytePerPixelDETC[k], + &v->BlockHeight256BytesY[k], + &v->BlockHeight256BytesC[k], + &v->BlockWidth256BytesY[k], + &v->BlockWidth256BytesC[k], + &v->BlockHeightY[k], + &v->BlockHeightC[k], + &v->BlockWidthY[k], + &v->BlockWidthC[k]); + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: %d\n", __func__, __LINE__); +#endif + dml32_CalculateSwathWidth( + false, // ForceSingleDPP + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.SourcePixelFormat, + mode_lib->vba.SourceRotation, + mode_lib->vba.ViewportStationary, + mode_lib->vba.ViewportWidth, + mode_lib->vba.ViewportHeight, + mode_lib->vba.ViewportXStartY, + mode_lib->vba.ViewportYStartY, + mode_lib->vba.ViewportXStartC, + mode_lib->vba.ViewportYStartC, + mode_lib->vba.SurfaceWidthY, + mode_lib->vba.SurfaceWidthC, + mode_lib->vba.SurfaceHeightY, + mode_lib->vba.SurfaceHeightC, + mode_lib->vba.ODMCombineEnabled, + v->BytePerPixelY, + v->BytePerPixelC, + v->BlockHeight256BytesY, + v->BlockHeight256BytesC, + v->BlockWidth256BytesY, + v->BlockWidth256BytesC, + mode_lib->vba.BlendingAndTiming, + mode_lib->vba.HActive, + mode_lib->vba.HRatio, + mode_lib->vba.DPPPerPlane, + + /* Output */ + v->SwathWidthSingleDPPY, v->SwathWidthSingleDPPC, v->SwathWidthY, v->SwathWidthC, + v->dummy_vars + .DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation + .dummy_integer_array[0], // Integer MaximumSwathHeightY[] + v->dummy_vars + .DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation + .dummy_integer_array[1], // Integer MaximumSwathHeightC[] + v->swath_width_luma_ub, v->swath_width_chroma_ub); + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + v->ReadBandwidthSurfaceLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k] + / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; + v->ReadBandwidthSurfaceChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k] + / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) + * mode_lib->vba.VRatioChroma[k]; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: ReadBandwidthSurfaceLuma[%i] = %fBps\n", + __func__, k, v->ReadBandwidthSurfaceLuma[k]); + dml_print("DML::%s: ReadBandwidthSurfaceChroma[%i] = %fBps\n", + __func__, k, v->ReadBandwidthSurfaceChroma[k]); +#endif + } + + { + // VBA_DELTA + // Calculate DET size, swath height + dml32_CalculateSwathAndDETConfiguration( + mode_lib->vba.DETSizeOverride, + mode_lib->vba.UsesMALLForPStateChange, + mode_lib->vba.ConfigReturnBufferSizeInKByte, + mode_lib->vba.MaxTotalDETInKByte, + mode_lib->vba.MinCompressedBufferSizeInKByte, + false, /* ForceSingleDPP */ + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.nomDETInKByte, + mode_lib->vba.UseUnboundedRequesting, + mode_lib->vba.CompressedBufferSegmentSizeInkByteFinal, + v->dummy_vars + .DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation + .dummy_output_encoder_array, /* output_encoder_class Output[] */ + v->ReadBandwidthSurfaceLuma, + v->ReadBandwidthSurfaceChroma, + v->dummy_vars + .DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation + .dummy_single_array[0], /* Single MaximumSwathWidthLuma[] */ + v->dummy_vars + .DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation + .dummy_single_array[1], /* Single MaximumSwathWidthChroma[] */ + mode_lib->vba.SourceRotation, + mode_lib->vba.ViewportStationary, + mode_lib->vba.SourcePixelFormat, + mode_lib->vba.SurfaceTiling, + mode_lib->vba.ViewportWidth, + mode_lib->vba.ViewportHeight, + mode_lib->vba.ViewportXStartY, + mode_lib->vba.ViewportYStartY, + mode_lib->vba.ViewportXStartC, + mode_lib->vba.ViewportYStartC, + mode_lib->vba.SurfaceWidthY, + mode_lib->vba.SurfaceWidthC, + mode_lib->vba.SurfaceHeightY, + mode_lib->vba.SurfaceHeightC, + v->BlockHeight256BytesY, + v->BlockHeight256BytesC, + v->BlockWidth256BytesY, + v->BlockWidth256BytesC, + mode_lib->vba.ODMCombineEnabled, + mode_lib->vba.BlendingAndTiming, + v->BytePerPixelY, + v->BytePerPixelC, + v->BytePerPixelDETY, + v->BytePerPixelDETC, + mode_lib->vba.HActive, + mode_lib->vba.HRatio, + mode_lib->vba.HRatioChroma, + mode_lib->vba.DPPPerPlane, + + /* Output */ + v->dummy_vars + .DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation + .dummy_long_array[0], /* Long swath_width_luma_ub[] */ + v->dummy_vars + .DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation + .dummy_long_array[1], /* Long swath_width_chroma_ub[] */ + v->dummy_vars + .DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation + .dummy_double_array[0], /* Long SwathWidth[] */ + v->dummy_vars + .DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation + .dummy_double_array[1], /* Long SwathWidthChroma[] */ + mode_lib->vba.SwathHeightY, + mode_lib->vba.SwathHeightC, + mode_lib->vba.DETBufferSizeInKByte, + mode_lib->vba.DETBufferSizeY, + mode_lib->vba.DETBufferSizeC, + &v->UnboundedRequestEnabled, + &v->CompressedBufferSizeInkByte, + v->dummy_vars + .DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation + .dummy_boolean_array, /* bool ViewportSizeSupportPerSurface[] */ + &v->dummy_vars + .DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation + .dummy_boolean); /* bool *ViewportSizeSupport */ + } + + // DCFCLK Deep Sleep + dml32_CalculateDCFCLKDeepSleep( + mode_lib->vba.NumberOfActiveSurfaces, + v->BytePerPixelY, + v->BytePerPixelC, + mode_lib->vba.VRatio, + mode_lib->vba.VRatioChroma, + v->SwathWidthY, + v->SwathWidthC, + mode_lib->vba.DPPPerPlane, + mode_lib->vba.HRatio, + mode_lib->vba.HRatioChroma, + mode_lib->vba.PixelClock, + v->PSCL_THROUGHPUT_LUMA, + v->PSCL_THROUGHPUT_CHROMA, + mode_lib->vba.DPPCLK, + v->ReadBandwidthSurfaceLuma, + v->ReadBandwidthSurfaceChroma, + mode_lib->vba.ReturnBusWidth, + + /* Output */ + &v->DCFCLKDeepSleep); + + // DSCCLK + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) { + v->DSCCLK_calculated[k] = 0.0; + } else { + if (mode_lib->vba.OutputFormat[k] == dm_420) + mode_lib->vba.DSCFormatFactor = 2; + else if (mode_lib->vba.OutputFormat[k] == dm_444) + mode_lib->vba.DSCFormatFactor = 1; + else if (mode_lib->vba.OutputFormat[k] == dm_n422) + mode_lib->vba.DSCFormatFactor = 2; + else + mode_lib->vba.DSCFormatFactor = 1; + if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_4to1) + v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 12 + / mode_lib->vba.DSCFormatFactor + / (1 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100); + else if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) + v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 6 + / mode_lib->vba.DSCFormatFactor + / (1 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100); + else + v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 3 + / mode_lib->vba.DSCFormatFactor + / (1 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100); + } + } + + // DSC Delay + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + v->DSCDelay[k] = dml32_DSCDelayRequirement(mode_lib->vba.DSCEnabled[k], + mode_lib->vba.ODMCombineEnabled[k], mode_lib->vba.DSCInputBitPerComponent[k], + mode_lib->vba.OutputBpp[k], mode_lib->vba.HActive[k], mode_lib->vba.HTotal[k], + mode_lib->vba.NumberOfDSCSlices[k], mode_lib->vba.OutputFormat[k], + mode_lib->vba.Output[k], mode_lib->vba.PixelClock[k], + mode_lib->vba.PixelClockBackEnd[k]); + } + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) + for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; ++j) // NumberOfSurfaces + if (j != k && mode_lib->vba.BlendingAndTiming[k] == j && mode_lib->vba.DSCEnabled[j]) + v->DSCDelay[k] = v->DSCDelay[j]; + + //Immediate Flip + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + v->ImmediateFlipSupportedSurface[k] = mode_lib->vba.ImmediateFlipSupport + && (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required); + } + + // Prefetch + dml32_CalculateSurfaceSizeInMall( + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.MALLAllocatedForDCNFinal, + mode_lib->vba.UseMALLForStaticScreen, + mode_lib->vba.DCCEnable, + mode_lib->vba.ViewportStationary, + mode_lib->vba.ViewportXStartY, + mode_lib->vba.ViewportYStartY, + mode_lib->vba.ViewportXStartC, + mode_lib->vba.ViewportYStartC, + mode_lib->vba.ViewportWidth, + mode_lib->vba.ViewportHeight, + v->BytePerPixelY, + mode_lib->vba.ViewportWidthChroma, + mode_lib->vba.ViewportHeightChroma, + v->BytePerPixelC, + mode_lib->vba.SurfaceWidthY, + mode_lib->vba.SurfaceWidthC, + mode_lib->vba.SurfaceHeightY, + mode_lib->vba.SurfaceHeightC, + v->BlockWidth256BytesY, + v->BlockWidth256BytesC, + v->BlockHeight256BytesY, + v->BlockHeight256BytesC, + v->BlockWidthY, + v->BlockWidthC, + v->BlockHeightY, + v->BlockHeightC, + + /* Output */ + v->SurfaceSizeInMALL, + &v->dummy_vars. + DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation + .dummy_boolean2); /* Boolean *ExceededMALLSize */ + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].PixelClock = mode_lib->vba.PixelClock[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DPPPerSurface = mode_lib->vba.DPPPerPlane[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SourceRotation = mode_lib->vba.SourceRotation[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportHeight = mode_lib->vba.ViewportHeight[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportHeightChroma = mode_lib->vba.ViewportHeightChroma[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidth256BytesY = v->BlockWidth256BytesY[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeight256BytesY = v->BlockHeight256BytesY[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidth256BytesC = v->BlockWidth256BytesC[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeight256BytesC = v->BlockHeight256BytesC[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidthY = v->BlockWidthY[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeightY = v->BlockHeightY[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidthC = v->BlockWidthC[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeightC = v->BlockHeightC[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].HTotal = mode_lib->vba.HTotal[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCEnable = mode_lib->vba.DCCEnable[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SurfaceTiling = mode_lib->vba.SurfaceTiling[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BytePerPixelY = v->BytePerPixelY[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BytePerPixelC = v->BytePerPixelC[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ProgressiveToInterlaceUnitInOPP = mode_lib->vba.ProgressiveToInterlaceUnitInOPP; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VRatio = mode_lib->vba.VRatio[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VRatioChroma = mode_lib->vba.VRatioChroma[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VTaps = mode_lib->vba.vtaps[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VTapsChroma = mode_lib->vba.VTAPsChroma[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].PitchY = mode_lib->vba.PitchY[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCMetaPitchY = mode_lib->vba.DCCMetaPitchY[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].PitchC = mode_lib->vba.PitchC[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCMetaPitchC = mode_lib->vba.DCCMetaPitchC[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportStationary = mode_lib->vba.ViewportStationary[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportXStart = mode_lib->vba.ViewportXStartY[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportYStart = mode_lib->vba.ViewportYStartY[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportXStartC = mode_lib->vba.ViewportXStartC[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportYStartC = mode_lib->vba.ViewportYStartC[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->vba.ForceOneRowForFrame[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SwathHeightY = mode_lib->vba.SwathHeightY[k]; + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SwathHeightC = mode_lib->vba.SwathHeightC[k]; + } + + { + + dml32_CalculateVMRowAndSwath( + mode_lib->vba.NumberOfActiveSurfaces, + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters, + v->SurfaceSizeInMALL, + mode_lib->vba.PTEBufferSizeInRequestsLuma, + mode_lib->vba.PTEBufferSizeInRequestsChroma, + mode_lib->vba.DCCMetaBufferSizeBytes, + mode_lib->vba.UseMALLForStaticScreen, + mode_lib->vba.UsesMALLForPStateChange, + mode_lib->vba.MALLAllocatedForDCNFinal, + v->SwathWidthY, + v->SwathWidthC, + mode_lib->vba.GPUVMEnable, + mode_lib->vba.HostVMEnable, + mode_lib->vba.HostVMMaxNonCachedPageTableLevels, + mode_lib->vba.GPUVMMaxPageTableLevels, + mode_lib->vba.GPUVMMinPageSizeKBytes, + mode_lib->vba.HostVMMinPageSize, + + /* Output */ + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_boolean_array2[0], // Boolean PTEBufferSizeNotExceeded[] + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_boolean_array2[1], // Boolean DCCMetaBufferSizeNotExceeded[] + v->dpte_row_width_luma_ub, + v->dpte_row_width_chroma_ub, + v->dpte_row_height, + v->dpte_row_height_chroma, + v->dpte_row_height_linear, + v->dpte_row_height_linear_chroma, + v->meta_req_width, + v->meta_req_width_chroma, + v->meta_req_height, + v->meta_req_height_chroma, + v->meta_row_width, + v->meta_row_width_chroma, + v->meta_row_height, + v->meta_row_height_chroma, + v->vm_group_bytes, + v->dpte_group_bytes, + v->PixelPTEReqWidthY, + v->PixelPTEReqHeightY, + v->PTERequestSizeY, + v->PixelPTEReqWidthC, + v->PixelPTEReqHeightC, + v->PTERequestSizeC, + v->dpde0_bytes_per_frame_ub_l, + v->meta_pte_bytes_per_frame_ub_l, + v->dpde0_bytes_per_frame_ub_c, + v->meta_pte_bytes_per_frame_ub_c, + v->PrefetchSourceLinesY, + v->PrefetchSourceLinesC, + v->VInitPreFillY, v->VInitPreFillC, + v->MaxNumSwathY, + v->MaxNumSwathC, + v->meta_row_bw, + v->dpte_row_bw, + v->PixelPTEBytesPerRow, + v->PDEAndMetaPTEBytesFrame, + v->MetaRowByte, + v->Use_One_Row_For_Frame, + v->Use_One_Row_For_Frame_Flip, + v->UsesMALLForStaticScreen, + v->PTE_BUFFER_MODE, + v->BIGK_FRAGMENT_SIZE); + } + + + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.ReorderBytes = mode_lib->vba.NumberOfChannels + * dml_max3(mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly, + mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, + mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly); + + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.VMDataOnlyReturnBW = dml32_get_return_bw_mbps_vm_only( + &mode_lib->vba.soc, + mode_lib->vba.VoltageLevel, + mode_lib->vba.DCFCLK, + mode_lib->vba.FabricClock, + mode_lib->vba.DRAMSpeed); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: mode_lib->vba.ReturnBusWidth = %f\n", __func__, mode_lib->vba.ReturnBusWidth); + dml_print("DML::%s: mode_lib->vba.DCFCLK = %f\n", __func__, mode_lib->vba.DCFCLK); + dml_print("DML::%s: mode_lib->vba.FabricClock = %f\n", __func__, mode_lib->vba.FabricClock); + dml_print("DML::%s: mode_lib->vba.FabricDatapathToDCNDataReturn = %f\n", __func__, + mode_lib->vba.FabricDatapathToDCNDataReturn); + dml_print("DML::%s: mode_lib->vba.PercentOfIdealSDPPortBWReceivedAfterUrgLatency = %f\n", + __func__, mode_lib->vba.PercentOfIdealSDPPortBWReceivedAfterUrgLatency); + dml_print("DML::%s: mode_lib->vba.DRAMSpeed = %f\n", __func__, mode_lib->vba.DRAMSpeed); + dml_print("DML::%s: mode_lib->vba.NumberOfChannels = %f\n", __func__, mode_lib->vba.NumberOfChannels); + dml_print("DML::%s: mode_lib->vba.DRAMChannelWidth = %f\n", __func__, mode_lib->vba.DRAMChannelWidth); + dml_print("DML::%s: mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly = %f\n", + __func__, mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly); + dml_print("DML::%s: VMDataOnlyReturnBW = %f\n", __func__, VMDataOnlyReturnBW); + dml_print("DML::%s: ReturnBW = %f\n", __func__, mode_lib->vba.ReturnBW); +#endif + + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor = 1.0; + + if (mode_lib->vba.GPUVMEnable && mode_lib->vba.HostVMEnable) + v->dummy_vars + .DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation + .HostVMInefficiencyFactor = + mode_lib->vba.ReturnBW / v->dummy_vars + .DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation + .VMDataOnlyReturnBW; + + mode_lib->vba.TotalDCCActiveDPP = 0; + mode_lib->vba.TotalActiveDPP = 0; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP + mode_lib->vba.DPPPerPlane[k]; + if (mode_lib->vba.DCCEnable[k]) + mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP + + mode_lib->vba.DPPPerPlane[k]; + } + + v->UrgentExtraLatency = dml32_CalculateExtraLatency( + mode_lib->vba.RoundTripPingLatencyCycles, + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.ReorderBytes, + mode_lib->vba.DCFCLK, + mode_lib->vba.TotalActiveDPP, + mode_lib->vba.PixelChunkSizeInKByte, + mode_lib->vba.TotalDCCActiveDPP, + mode_lib->vba.MetaChunkSize, + mode_lib->vba.ReturnBW, + mode_lib->vba.GPUVMEnable, + mode_lib->vba.HostVMEnable, + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.DPPPerPlane, + v->dpte_group_bytes, + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor, + mode_lib->vba.HostVMMinPageSize, + mode_lib->vba.HostVMMaxNonCachedPageTableLevels); + + mode_lib->vba.TCalc = 24.0 / v->DCFCLKDeepSleep; + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.BlendingAndTiming[k] == k) { + if (mode_lib->vba.WritebackEnable[k] == true) { + v->WritebackDelay[mode_lib->vba.VoltageLevel][k] = mode_lib->vba.WritebackLatency + + dml32_CalculateWriteBackDelay( + mode_lib->vba.WritebackPixelFormat[k], + mode_lib->vba.WritebackHRatio[k], + mode_lib->vba.WritebackVRatio[k], + mode_lib->vba.WritebackVTaps[k], + mode_lib->vba.WritebackDestinationWidth[k], + mode_lib->vba.WritebackDestinationHeight[k], + mode_lib->vba.WritebackSourceHeight[k], + mode_lib->vba.HTotal[k]) / mode_lib->vba.DISPCLK; + } else + v->WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0; + for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; ++j) { + if (mode_lib->vba.BlendingAndTiming[j] == k && + mode_lib->vba.WritebackEnable[j] == true) { + v->WritebackDelay[mode_lib->vba.VoltageLevel][k] = + dml_max(v->WritebackDelay[mode_lib->vba.VoltageLevel][k], + mode_lib->vba.WritebackLatency + + dml32_CalculateWriteBackDelay( + mode_lib->vba.WritebackPixelFormat[j], + mode_lib->vba.WritebackHRatio[j], + mode_lib->vba.WritebackVRatio[j], + mode_lib->vba.WritebackVTaps[j], + mode_lib->vba.WritebackDestinationWidth[j], + mode_lib->vba.WritebackDestinationHeight[j], + mode_lib->vba.WritebackSourceHeight[j], + mode_lib->vba.HTotal[k]) / mode_lib->vba.DISPCLK); + } + } + } + } + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) + for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; ++j) + if (mode_lib->vba.BlendingAndTiming[k] == j) + v->WritebackDelay[mode_lib->vba.VoltageLevel][k] = + v->WritebackDelay[mode_lib->vba.VoltageLevel][j]; + + v->UrgentLatency = dml32_CalculateUrgentLatency(mode_lib->vba.UrgentLatencyPixelDataOnly, + mode_lib->vba.UrgentLatencyPixelMixedWithVMData, + mode_lib->vba.UrgentLatencyVMDataOnly, + mode_lib->vba.DoUrgentLatencyAdjustment, + mode_lib->vba.UrgentLatencyAdjustmentFabricClockComponent, + mode_lib->vba.UrgentLatencyAdjustmentFabricClockReference, + mode_lib->vba.FabricClock); + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + dml32_CalculateUrgentBurstFactor(mode_lib->vba.UsesMALLForPStateChange[k], + v->swath_width_luma_ub[k], + v->swath_width_chroma_ub[k], + mode_lib->vba.SwathHeightY[k], + mode_lib->vba.SwathHeightC[k], + mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], + v->UrgentLatency, + mode_lib->vba.CursorBufferSize, + mode_lib->vba.CursorWidth[k][0], + mode_lib->vba.CursorBPP[k][0], + mode_lib->vba.VRatio[k], + mode_lib->vba.VRatioChroma[k], + v->BytePerPixelDETY[k], + v->BytePerPixelDETC[k], + mode_lib->vba.DETBufferSizeY[k], + mode_lib->vba.DETBufferSizeC[k], + + /* output */ + &v->UrgBurstFactorCursor[k], + &v->UrgBurstFactorLuma[k], + &v->UrgBurstFactorChroma[k], + &v->NoUrgentLatencyHiding[k]); + + v->cursor_bw[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0] / 8 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; + } + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + v->MaxVStartupLines[k] = ((mode_lib->vba.Interlace[k] && + !mode_lib->vba.ProgressiveToInterlaceUnitInOPP) ? + dml_floor((mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]) / 2.0, 1.0) : + mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]) - dml_max(1.0, + dml_ceil((double) v->WritebackDelay[mode_lib->vba.VoltageLevel][k] + / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1)); + + // Clamp to max OTG vstartup register limit + if (v->MaxVStartupLines[k] > 1023) + v->MaxVStartupLines[k] = 1023; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]); + dml_print("DML::%s: k=%d VoltageLevel = %d\n", __func__, k, mode_lib->vba.VoltageLevel); + dml_print("DML::%s: k=%d WritebackDelay = %f\n", __func__, + k, v->WritebackDelay[mode_lib->vba.VoltageLevel][k]); +#endif + } + + v->MaximumMaxVStartupLines = 0; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) + v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]); + + ImmediateFlipRequirementFinal = false; + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + ImmediateFlipRequirementFinal = ImmediateFlipRequirementFinal + || (mode_lib->vba.ImmediateFlipRequirement[k] == dm_immediate_flip_required); + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: ImmediateFlipRequirementFinal = %d\n", __func__, ImmediateFlipRequirementFinal); +#endif + // ModeProgramming will not repeat the schedule calculation using different prefetch mode, + //it is just calcualated once with given prefetch mode + dml32_CalculateMinAndMaxPrefetchMode( + mode_lib->vba.AllowForPStateChangeOrStutterInVBlankFinal, + &mode_lib->vba.MinPrefetchMode, + &mode_lib->vba.MaxPrefetchMode); + + v->VStartupLines = __DML_VBA_MIN_VSTARTUP__; + + iteration = 0; + MaxTotalRDBandwidth = 0; + NextPrefetchMode = mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb]; + + do { + double MaxTotalRDBandwidthNoUrgentBurst = 0.0; + bool DestinationLineTimesForPrefetchLessThan2 = false; + bool VRatioPrefetchMoreThanMax = false; + double dummy_unit_vector[DC__NUM_DPP__MAX]; + + MaxTotalRDBandwidth = 0; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: Start loop: VStartup = %d\n", __func__, mode_lib->vba.VStartupLines); +#endif + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + /* NOTE PerfetchMode variable is invalid in DAL as per the input received. + * Hence the direction is to use PrefetchModePerState. + */ + double TWait = dml32_CalculateTWait( + mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], + mode_lib->vba.UsesMALLForPStateChange[k], + mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal, + mode_lib->vba.DRRDisplay[k], + mode_lib->vba.DRAMClockChangeLatency, + mode_lib->vba.FCLKChangeLatency, v->UrgentLatency, + mode_lib->vba.SREnterPlusExitTime); + + DmlPipe myPipe; + + myPipe.Dppclk = mode_lib->vba.DPPCLK[k]; + myPipe.Dispclk = mode_lib->vba.DISPCLK; + myPipe.PixelClock = mode_lib->vba.PixelClock[k]; + myPipe.DCFClkDeepSleep = v->DCFCLKDeepSleep; + myPipe.DPPPerSurface = mode_lib->vba.DPPPerPlane[k]; + myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k]; + myPipe.SourceRotation = mode_lib->vba.SourceRotation[k]; + myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k]; + myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k]; + myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k]; + myPipe.BlockHeight256BytesC = v->BlockHeight256BytesC[k]; + myPipe.InterlaceEnable = mode_lib->vba.Interlace[k]; + myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k]; + myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]; + myPipe.HTotal = mode_lib->vba.HTotal[k]; + myPipe.HActive = mode_lib->vba.HActive[k]; + myPipe.DCCEnable = mode_lib->vba.DCCEnable[k]; + myPipe.ODMMode = mode_lib->vba.ODMCombineEnabled[k]; + myPipe.SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k]; + myPipe.BytePerPixelY = v->BytePerPixelY[k]; + myPipe.BytePerPixelC = v->BytePerPixelC[k]; + myPipe.ProgressiveToInterlaceUnitInOPP = mode_lib->vba.ProgressiveToInterlaceUnitInOPP; + v->ErrorResult[k] = dml32_CalculatePrefetchSchedule(v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor, + &myPipe, v->DSCDelay[k], + mode_lib->vba.DPPCLKDelaySubtotal + mode_lib->vba.DPPCLKDelayCNVCFormater, + mode_lib->vba.DPPCLKDelaySCL, + mode_lib->vba.DPPCLKDelaySCLLBOnly, + mode_lib->vba.DPPCLKDelayCNVCCursor, + mode_lib->vba.DISPCLKDelaySubtotal, + (unsigned int) (v->SwathWidthY[k] / mode_lib->vba.HRatio[k]), + mode_lib->vba.OutputFormat[k], + mode_lib->vba.MaxInterDCNTileRepeaters, + dml_min(v->VStartupLines, v->MaxVStartupLines[k]), + v->MaxVStartupLines[k], + mode_lib->vba.GPUVMMaxPageTableLevels, + mode_lib->vba.GPUVMEnable, + mode_lib->vba.HostVMEnable, + mode_lib->vba.HostVMMaxNonCachedPageTableLevels, + mode_lib->vba.HostVMMinPageSize, + mode_lib->vba.DynamicMetadataEnable[k], + mode_lib->vba.DynamicMetadataVMEnabled, + mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k], + mode_lib->vba.DynamicMetadataTransmittedBytes[k], + v->UrgentLatency, + v->UrgentExtraLatency, + mode_lib->vba.TCalc, + v->PDEAndMetaPTEBytesFrame[k], + v->MetaRowByte[k], + v->PixelPTEBytesPerRow[k], + v->PrefetchSourceLinesY[k], + v->SwathWidthY[k], + v->VInitPreFillY[k], + v->MaxNumSwathY[k], + v->PrefetchSourceLinesC[k], + v->SwathWidthC[k], + v->VInitPreFillC[k], + v->MaxNumSwathC[k], + v->swath_width_luma_ub[k], + v->swath_width_chroma_ub[k], + mode_lib->vba.SwathHeightY[k], + mode_lib->vba.SwathHeightC[k], + TWait, + /* Output */ + &v->DSTXAfterScaler[k], + &v->DSTYAfterScaler[k], + &v->DestinationLinesForPrefetch[k], + &v->PrefetchBandwidth[k], + &v->DestinationLinesToRequestVMInVBlank[k], + &v->DestinationLinesToRequestRowInVBlank[k], + &v->VRatioPrefetchY[k], + &v->VRatioPrefetchC[k], + &v->RequiredPrefetchPixDataBWLuma[k], + &v->RequiredPrefetchPixDataBWChroma[k], + &v->NotEnoughTimeForDynamicMetadata[k], + &v->Tno_bw[k], &v->prefetch_vmrow_bw[k], + &v->Tdmdl_vm[k], + &v->Tdmdl[k], + &v->TSetup[k], + &v->VUpdateOffsetPix[k], + &v->VUpdateWidthPix[k], + &v->VReadyOffsetPix[k]); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d Prefetch calculation errResult=%0d\n", + __func__, k, mode_lib->vba.ErrorResult[k]); +#endif + v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]); + } + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + dml32_CalculateUrgentBurstFactor(mode_lib->vba.UsesMALLForPStateChange[k], + v->swath_width_luma_ub[k], + v->swath_width_chroma_ub[k], + mode_lib->vba.SwathHeightY[k], + mode_lib->vba.SwathHeightC[k], + mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], + v->UrgentLatency, + mode_lib->vba.CursorBufferSize, + mode_lib->vba.CursorWidth[k][0], + mode_lib->vba.CursorBPP[k][0], + v->VRatioPrefetchY[k], + v->VRatioPrefetchC[k], + v->BytePerPixelDETY[k], + v->BytePerPixelDETC[k], + mode_lib->vba.DETBufferSizeY[k], + mode_lib->vba.DETBufferSizeC[k], + /* Output */ + &v->UrgBurstFactorCursorPre[k], + &v->UrgBurstFactorLumaPre[k], + &v->UrgBurstFactorChromaPre[k], + &v->NoUrgentLatencyHidingPre[k]); + + v->cursor_bw_pre[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0] / + 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * v->VRatioPrefetchY[k]; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d DPPPerSurface=%d\n", __func__, k, mode_lib->vba.DPPPerPlane[k]); + dml_print("DML::%s: k=%0d UrgBurstFactorLuma=%f\n", __func__, k, v->UrgBurstFactorLuma[k]); + dml_print("DML::%s: k=%0d UrgBurstFactorChroma=%f\n", __func__, k, v->UrgBurstFactorChroma[k]); + dml_print("DML::%s: k=%0d UrgBurstFactorLumaPre=%f\n", __func__, k, + v->UrgBurstFactorLumaPre[k]); + dml_print("DML::%s: k=%0d UrgBurstFactorChromaPre=%f\n", __func__, k, + v->UrgBurstFactorChromaPre[k]); + + dml_print("DML::%s: k=%0d VRatioPrefetchY=%f\n", __func__, k, v->VRatioPrefetchY[k]); + dml_print("DML::%s: k=%0d VRatioY=%f\n", __func__, k, mode_lib->vba.VRatio[k]); + + dml_print("DML::%s: k=%0d prefetch_vmrow_bw=%f\n", __func__, k, v->prefetch_vmrow_bw[k]); + dml_print("DML::%s: k=%0d ReadBandwidthSurfaceLuma=%f\n", __func__, k, + v->ReadBandwidthSurfaceLuma[k]); + dml_print("DML::%s: k=%0d ReadBandwidthSurfaceChroma=%f\n", __func__, k, + v->ReadBandwidthSurfaceChroma[k]); + dml_print("DML::%s: k=%0d cursor_bw=%f\n", __func__, k, v->cursor_bw[k]); + dml_print("DML::%s: k=%0d meta_row_bw=%f\n", __func__, k, v->meta_row_bw[k]); + dml_print("DML::%s: k=%0d dpte_row_bw=%f\n", __func__, k, v->dpte_row_bw[k]); + dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWLuma=%f\n", __func__, k, + v->RequiredPrefetchPixDataBWLuma[k]); + dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWChroma=%f\n", __func__, k, + v->RequiredPrefetchPixDataBWChroma[k]); + dml_print("DML::%s: k=%0d cursor_bw_pre=%f\n", __func__, k, v->cursor_bw_pre[k]); + dml_print("DML::%s: k=%0d MaxTotalRDBandwidthNoUrgentBurst=%f\n", __func__, k, + MaxTotalRDBandwidthNoUrgentBurst); +#endif + if (v->DestinationLinesForPrefetch[k] < 2) + DestinationLineTimesForPrefetchLessThan2 = true; + + if (v->VRatioPrefetchY[k] > __DML_MAX_VRATIO_PRE__ + || v->VRatioPrefetchC[k] > __DML_MAX_VRATIO_PRE__) + VRatioPrefetchMoreThanMax = true; + + //bool DestinationLinesToRequestVMInVBlankEqualOrMoreThan32 = false; + //bool DestinationLinesToRequestRowInVBlankEqualOrMoreThan16 = false; + //if (v->DestinationLinesToRequestVMInVBlank[k] >= 32) { + // DestinationLinesToRequestVMInVBlankEqualOrMoreThan32 = true; + //} + + //if (v->DestinationLinesToRequestRowInVBlank[k] >= 16) { + // DestinationLinesToRequestRowInVBlankEqualOrMoreThan16 = true; + //} + } + + v->FractionOfUrgentBandwidth = MaxTotalRDBandwidthNoUrgentBurst / mode_lib->vba.ReturnBW; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: MaxTotalRDBandwidthNoUrgentBurst=%f\n", + __func__, MaxTotalRDBandwidthNoUrgentBurst); + dml_print("DML::%s: ReturnBW=%f\n", __func__, mode_lib->vba.ReturnBW); + dml_print("DML::%s: FractionOfUrgentBandwidth=%f\n", + __func__, mode_lib->vba.FractionOfUrgentBandwidth); +#endif + + { + double dummy_single[1]; + + dml32_CalculatePrefetchBandwithSupport( + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.ReturnBW, + v->NoUrgentLatencyHidingPre, + v->ReadBandwidthSurfaceLuma, + v->ReadBandwidthSurfaceChroma, + v->RequiredPrefetchPixDataBWLuma, + v->RequiredPrefetchPixDataBWChroma, + v->cursor_bw, + v->meta_row_bw, + v->dpte_row_bw, + v->cursor_bw_pre, + v->prefetch_vmrow_bw, + mode_lib->vba.DPPPerPlane, + v->UrgBurstFactorLuma, + v->UrgBurstFactorChroma, + v->UrgBurstFactorCursor, + v->UrgBurstFactorLumaPre, + v->UrgBurstFactorChromaPre, + v->UrgBurstFactorCursorPre, + + /* output */ + &MaxTotalRDBandwidth, + &dummy_single[0], + &v->PrefetchModeSupported); + } + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) + dummy_unit_vector[k] = 1.0; + + { + double dummy_single[1]; + bool dummy_boolean[1]; + dml32_CalculatePrefetchBandwithSupport(mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.ReturnBW, + v->NoUrgentLatencyHidingPre, + v->ReadBandwidthSurfaceLuma, + v->ReadBandwidthSurfaceChroma, + v->RequiredPrefetchPixDataBWLuma, + v->RequiredPrefetchPixDataBWChroma, + v->cursor_bw, + v->meta_row_bw, + v->dpte_row_bw, + v->cursor_bw_pre, + v->prefetch_vmrow_bw, + mode_lib->vba.DPPPerPlane, + dummy_unit_vector, + dummy_unit_vector, + dummy_unit_vector, + dummy_unit_vector, + dummy_unit_vector, + dummy_unit_vector, + + /* output */ + &dummy_single[0], + &v->FractionOfUrgentBandwidth, + &dummy_boolean[0]); + } + + if (VRatioPrefetchMoreThanMax != false || DestinationLineTimesForPrefetchLessThan2 != false) { + v->PrefetchModeSupported = false; + } + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (v->ErrorResult[k] == true || v->NotEnoughTimeForDynamicMetadata[k]) { + v->PrefetchModeSupported = false; + } + } + + if (v->PrefetchModeSupported == true && mode_lib->vba.ImmediateFlipSupport == true) { + mode_lib->vba.BandwidthAvailableForImmediateFlip = dml32_CalculateBandwidthAvailableForImmediateFlip( + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.ReturnBW, + v->ReadBandwidthSurfaceLuma, + v->ReadBandwidthSurfaceChroma, + v->RequiredPrefetchPixDataBWLuma, + v->RequiredPrefetchPixDataBWChroma, + v->cursor_bw, + v->cursor_bw_pre, + mode_lib->vba.DPPPerPlane, + v->UrgBurstFactorLuma, + v->UrgBurstFactorChroma, + v->UrgBurstFactorCursor, + v->UrgBurstFactorLumaPre, + v->UrgBurstFactorChromaPre, + v->UrgBurstFactorCursorPre); + + mode_lib->vba.TotImmediateFlipBytes = 0; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required) { + mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes + + mode_lib->vba.DPPPerPlane[k] + * (v->PDEAndMetaPTEBytesFrame[k] + + v->MetaRowByte[k]); + if (v->use_one_row_for_frame_flip[k]) { + mode_lib->vba.TotImmediateFlipBytes = + mode_lib->vba.TotImmediateFlipBytes + + 2 * v->PixelPTEBytesPerRow[k]; + } else { + mode_lib->vba.TotImmediateFlipBytes = + mode_lib->vba.TotImmediateFlipBytes + + v->PixelPTEBytesPerRow[k]; + } + } + } + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + dml32_CalculateFlipSchedule(v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor, + v->UrgentExtraLatency, + v->UrgentLatency, + mode_lib->vba.GPUVMMaxPageTableLevels, + mode_lib->vba.HostVMEnable, + mode_lib->vba.HostVMMaxNonCachedPageTableLevels, + mode_lib->vba.GPUVMEnable, + mode_lib->vba.HostVMMinPageSize, + v->PDEAndMetaPTEBytesFrame[k], + v->MetaRowByte[k], + v->PixelPTEBytesPerRow[k], + mode_lib->vba.BandwidthAvailableForImmediateFlip, + mode_lib->vba.TotImmediateFlipBytes, + mode_lib->vba.SourcePixelFormat[k], + mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], + mode_lib->vba.VRatio[k], + mode_lib->vba.VRatioChroma[k], + v->Tno_bw[k], + mode_lib->vba.DCCEnable[k], + v->dpte_row_height[k], + v->meta_row_height[k], + v->dpte_row_height_chroma[k], + v->meta_row_height_chroma[k], + v->Use_One_Row_For_Frame_Flip[k], + + /* Output */ + &v->DestinationLinesToRequestVMInImmediateFlip[k], + &v->DestinationLinesToRequestRowInImmediateFlip[k], + &v->final_flip_bw[k], + &v->ImmediateFlipSupportedForPipe[k]); + } + + { + double dummy_single[2]; + bool dummy_boolean[1]; + dml32_CalculateImmediateFlipBandwithSupport(mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.ReturnBW, + mode_lib->vba.ImmediateFlipRequirement, + v->final_flip_bw, + v->ReadBandwidthSurfaceLuma, + v->ReadBandwidthSurfaceChroma, + v->RequiredPrefetchPixDataBWLuma, + v->RequiredPrefetchPixDataBWChroma, + v->cursor_bw, + v->meta_row_bw, + v->dpte_row_bw, + v->cursor_bw_pre, + v->prefetch_vmrow_bw, + mode_lib->vba.DPPPerPlane, + v->UrgBurstFactorLuma, + v->UrgBurstFactorChroma, + v->UrgBurstFactorCursor, + v->UrgBurstFactorLumaPre, + v->UrgBurstFactorChromaPre, + v->UrgBurstFactorCursorPre, + + /* output */ + &v->total_dcn_read_bw_with_flip, // Single *TotalBandwidth + &dummy_single[0], // Single *FractionOfUrgentBandwidth + &v->ImmediateFlipSupported); // Boolean *ImmediateFlipBandwidthSupport + + dml32_CalculateImmediateFlipBandwithSupport(mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.ReturnBW, + mode_lib->vba.ImmediateFlipRequirement, + v->final_flip_bw, + v->ReadBandwidthSurfaceLuma, + v->ReadBandwidthSurfaceChroma, + v->RequiredPrefetchPixDataBWLuma, + v->RequiredPrefetchPixDataBWChroma, + v->cursor_bw, + v->meta_row_bw, + v->dpte_row_bw, + v->cursor_bw_pre, + v->prefetch_vmrow_bw, + mode_lib->vba.DPPPerPlane, + dummy_unit_vector, + dummy_unit_vector, + dummy_unit_vector, + dummy_unit_vector, + dummy_unit_vector, + dummy_unit_vector, + + /* output */ + &dummy_single[1], // Single *TotalBandwidth + &v->FractionOfUrgentBandwidthImmediateFlip, // Single *FractionOfUrgentBandwidth + &dummy_boolean[0]); // Boolean *ImmediateFlipBandwidthSupport + } + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required && v->ImmediateFlipSupportedForPipe[k] == false) { + v->ImmediateFlipSupported = false; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: Pipe %0d not supporing iflip\n", __func__, k); +#endif + } + } + } else { + v->ImmediateFlipSupported = false; + } + + /* consider flip support is okay if the flip bw is ok or (when user does't require a iflip and there is no host vm) */ + v->PrefetchAndImmediateFlipSupported = (v->PrefetchModeSupported == true && + ((!mode_lib->vba.ImmediateFlipSupport && !mode_lib->vba.HostVMEnable && !ImmediateFlipRequirementFinal) || + v->ImmediateFlipSupported)) ? true : false; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: PrefetchModeSupported = %d\n", __func__, locals->PrefetchModeSupported); + for (uint k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) + dml_print("DML::%s: ImmediateFlipRequirement[%d] = %d\n", __func__, k, mode_lib->vba.ImmediateFlipRequirement[k] == dm_immediate_flip_required); + dml_print("DML::%s: ImmediateFlipSupported = %d\n", __func__, locals->ImmediateFlipSupported); + dml_print("DML::%s: ImmediateFlipSupport = %d\n", __func__, mode_lib->vba.ImmediateFlipSupport); + dml_print("DML::%s: HostVMEnable = %d\n", __func__, mode_lib->vba.HostVMEnable); + dml_print("DML::%s: PrefetchAndImmediateFlipSupported = %d\n", __func__, locals->PrefetchAndImmediateFlipSupported); + dml_print("DML::%s: Done loop: Vstartup=%d, Max Vstartup=%d\n", __func__, locals->VStartupLines, locals->MaximumMaxVStartupLines); +#endif + + v->VStartupLines = v->VStartupLines + 1; + + if (v->VStartupLines > v->MaximumMaxVStartupLines) { +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: Vstartup exceeds max vstartup, exiting loop\n", __func__); +#endif + break; // VBA_DELTA: Implementation divergence! Gabe is *still* iterating across prefetch modes which we don't care to do + } + iteration++; + if (iteration > 2500) { +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: too many errors, exit now\n", __func__); + assert(0); +#endif + } + } while (!(v->PrefetchAndImmediateFlipSupported || NextPrefetchMode > mode_lib->vba.MaxPrefetchMode)); + + + if (v->VStartupLines <= v->MaximumMaxVStartupLines) { +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: Good, Prefetch and flip scheduling found solution at VStartupLines=%d\n", __func__, locals->VStartupLines-1); +#endif + } + + + //Watermarks and NB P-State/DRAM Clock Change Support + { + SOCParametersList mmSOCParameters; + enum clock_change_support dummy_dramchange_support; + enum dm_fclock_change_support dummy_fclkchange_support; + bool dummy_USRRetrainingSupport; + + mmSOCParameters.UrgentLatency = v->UrgentLatency; + mmSOCParameters.ExtraLatency = v->UrgentExtraLatency; + mmSOCParameters.WritebackLatency = mode_lib->vba.WritebackLatency; + mmSOCParameters.DRAMClockChangeLatency = mode_lib->vba.DRAMClockChangeLatency; + mmSOCParameters.FCLKChangeLatency = mode_lib->vba.FCLKChangeLatency; + mmSOCParameters.SRExitTime = mode_lib->vba.SRExitTime; + mmSOCParameters.SREnterPlusExitTime = mode_lib->vba.SREnterPlusExitTime; + mmSOCParameters.SRExitZ8Time = mode_lib->vba.SRExitZ8Time; + mmSOCParameters.SREnterPlusExitZ8Time = mode_lib->vba.SREnterPlusExitZ8Time; + mmSOCParameters.USRRetrainingLatency = mode_lib->vba.USRRetrainingLatency; + mmSOCParameters.SMNLatency = mode_lib->vba.SMNLatency; + + dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( + mode_lib->vba.USRRetrainingRequiredFinal, + mode_lib->vba.UsesMALLForPStateChange, + mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.MaxLineBufferLines, + mode_lib->vba.LineBufferSizeFinal, + mode_lib->vba.WritebackInterfaceBufferSize, + mode_lib->vba.DCFCLK, + mode_lib->vba.ReturnBW, + mode_lib->vba.SynchronizeTimingsFinal, + mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal, + mode_lib->vba.DRRDisplay, + v->dpte_group_bytes, + v->meta_row_height, + v->meta_row_height_chroma, + mmSOCParameters, + mode_lib->vba.WritebackChunkSize, + mode_lib->vba.SOCCLK, + v->DCFCLKDeepSleep, + mode_lib->vba.DETBufferSizeY, + mode_lib->vba.DETBufferSizeC, + mode_lib->vba.SwathHeightY, + mode_lib->vba.SwathHeightC, + mode_lib->vba.LBBitPerPixel, + v->SwathWidthY, + v->SwathWidthC, + mode_lib->vba.HRatio, + mode_lib->vba.HRatioChroma, + mode_lib->vba.vtaps, + mode_lib->vba.VTAPsChroma, + mode_lib->vba.VRatio, + mode_lib->vba.VRatioChroma, + mode_lib->vba.HTotal, + mode_lib->vba.VTotal, + mode_lib->vba.VActive, + mode_lib->vba.PixelClock, + mode_lib->vba.BlendingAndTiming, + mode_lib->vba.DPPPerPlane, + v->BytePerPixelDETY, + v->BytePerPixelDETC, + v->DSTXAfterScaler, + v->DSTYAfterScaler, + mode_lib->vba.WritebackEnable, + mode_lib->vba.WritebackPixelFormat, + mode_lib->vba.WritebackDestinationWidth, + mode_lib->vba.WritebackDestinationHeight, + mode_lib->vba.WritebackSourceHeight, + v->UnboundedRequestEnabled, + v->CompressedBufferSizeInkByte, + + /* Output */ + &v->Watermark, + &dummy_dramchange_support, + v->MaxActiveDRAMClockChangeLatencySupported, + v->SubViewportLinesNeededInMALL, + &dummy_fclkchange_support, + &v->MinActiveFCLKChangeLatencySupported, + &dummy_USRRetrainingSupport, + mode_lib->vba.ActiveDRAMClockChangeLatencyMargin); + + /* DCN32 has a new struct Watermarks (typedef) which is used to store + * calculated WM values. Copy over values from struct to vba varaibles + * to ensure that the DCN32 getters return the correct value. + */ + v->UrgentWatermark = v->Watermark.UrgentWatermark; + v->WritebackUrgentWatermark = v->Watermark.WritebackUrgentWatermark; + v->DRAMClockChangeWatermark = v->Watermark.DRAMClockChangeWatermark; + v->WritebackDRAMClockChangeWatermark = v->Watermark.WritebackDRAMClockChangeWatermark; + v->StutterExitWatermark = v->Watermark.StutterExitWatermark; + v->StutterEnterPlusExitWatermark = v->Watermark.StutterEnterPlusExitWatermark; + v->Z8StutterExitWatermark = v->Watermark.Z8StutterExitWatermark; + v->Z8StutterEnterPlusExitWatermark = v->Watermark.Z8StutterEnterPlusExitWatermark; + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.WritebackEnable[k] == true) { + v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(0, + v->VStartup[k] * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k] + - v->Watermark.WritebackDRAMClockChangeWatermark); + v->WritebackAllowFCLKChangeEndPosition[k] = dml_max(0, + v->VStartup[k] * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k] + - v->Watermark.WritebackFCLKChangeWatermark); + } else { + v->WritebackAllowDRAMClockChangeEndPosition[k] = 0; + v->WritebackAllowFCLKChangeEndPosition[k] = 0; + } + } + } + + //Display Pipeline Delivery Time in Prefetch, Groups + dml32_CalculatePixelDeliveryTimes( + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.VRatio, + mode_lib->vba.VRatioChroma, + v->VRatioPrefetchY, + v->VRatioPrefetchC, + v->swath_width_luma_ub, + v->swath_width_chroma_ub, + mode_lib->vba.DPPPerPlane, + mode_lib->vba.HRatio, + mode_lib->vba.HRatioChroma, + mode_lib->vba.PixelClock, + v->PSCL_THROUGHPUT_LUMA, + v->PSCL_THROUGHPUT_CHROMA, + mode_lib->vba.DPPCLK, + v->BytePerPixelC, + mode_lib->vba.SourceRotation, + mode_lib->vba.NumberOfCursors, + mode_lib->vba.CursorWidth, + mode_lib->vba.CursorBPP, + v->BlockWidth256BytesY, + v->BlockHeight256BytesY, + v->BlockWidth256BytesC, + v->BlockHeight256BytesC, + + /* Output */ + v->DisplayPipeLineDeliveryTimeLuma, + v->DisplayPipeLineDeliveryTimeChroma, + v->DisplayPipeLineDeliveryTimeLumaPrefetch, + v->DisplayPipeLineDeliveryTimeChromaPrefetch, + v->DisplayPipeRequestDeliveryTimeLuma, + v->DisplayPipeRequestDeliveryTimeChroma, + v->DisplayPipeRequestDeliveryTimeLumaPrefetch, + v->DisplayPipeRequestDeliveryTimeChromaPrefetch, + v->CursorRequestDeliveryTime, + v->CursorRequestDeliveryTimePrefetch); + + dml32_CalculateMetaAndPTETimes(v->Use_One_Row_For_Frame, + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.GPUVMEnable, + mode_lib->vba.MetaChunkSize, + mode_lib->vba.MinMetaChunkSizeBytes, + mode_lib->vba.HTotal, + mode_lib->vba.VRatio, + mode_lib->vba.VRatioChroma, + v->DestinationLinesToRequestRowInVBlank, + v->DestinationLinesToRequestRowInImmediateFlip, + mode_lib->vba.DCCEnable, + mode_lib->vba.PixelClock, + v->BytePerPixelY, + v->BytePerPixelC, + mode_lib->vba.SourceRotation, + v->dpte_row_height, + v->dpte_row_height_chroma, + v->meta_row_width, + v->meta_row_width_chroma, + v->meta_row_height, + v->meta_row_height_chroma, + v->meta_req_width, + v->meta_req_width_chroma, + v->meta_req_height, + v->meta_req_height_chroma, + v->dpte_group_bytes, + v->PTERequestSizeY, + v->PTERequestSizeC, + v->PixelPTEReqWidthY, + v->PixelPTEReqHeightY, + v->PixelPTEReqWidthC, + v->PixelPTEReqHeightC, + v->dpte_row_width_luma_ub, + v->dpte_row_width_chroma_ub, + + /* Output */ + v->DST_Y_PER_PTE_ROW_NOM_L, + v->DST_Y_PER_PTE_ROW_NOM_C, + v->DST_Y_PER_META_ROW_NOM_L, + v->DST_Y_PER_META_ROW_NOM_C, + v->TimePerMetaChunkNominal, + v->TimePerChromaMetaChunkNominal, + v->TimePerMetaChunkVBlank, + v->TimePerChromaMetaChunkVBlank, + v->TimePerMetaChunkFlip, + v->TimePerChromaMetaChunkFlip, + v->time_per_pte_group_nom_luma, + v->time_per_pte_group_vblank_luma, + v->time_per_pte_group_flip_luma, + v->time_per_pte_group_nom_chroma, + v->time_per_pte_group_vblank_chroma, + v->time_per_pte_group_flip_chroma); + + dml32_CalculateVMGroupAndRequestTimes( + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.GPUVMEnable, + mode_lib->vba.GPUVMMaxPageTableLevels, + mode_lib->vba.HTotal, + v->BytePerPixelC, + v->DestinationLinesToRequestVMInVBlank, + v->DestinationLinesToRequestVMInImmediateFlip, + mode_lib->vba.DCCEnable, + mode_lib->vba.PixelClock, + v->dpte_row_width_luma_ub, + v->dpte_row_width_chroma_ub, + v->vm_group_bytes, + v->dpde0_bytes_per_frame_ub_l, + v->dpde0_bytes_per_frame_ub_c, + v->meta_pte_bytes_per_frame_ub_l, + v->meta_pte_bytes_per_frame_ub_c, + + /* Output */ + v->TimePerVMGroupVBlank, + v->TimePerVMGroupFlip, + v->TimePerVMRequestVBlank, + v->TimePerVMRequestFlip); + + // Min TTUVBlank + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) { + v->MinTTUVBlank[k] = dml_max4(v->Watermark.DRAMClockChangeWatermark, + v->Watermark.FCLKChangeWatermark, v->Watermark.StutterEnterPlusExitWatermark, + v->Watermark.UrgentWatermark); + } else if (mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] + == 1) { + v->MinTTUVBlank[k] = dml_max3(v->Watermark.FCLKChangeWatermark, + v->Watermark.StutterEnterPlusExitWatermark, v->Watermark.UrgentWatermark); + } else if (mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] + == 2) { + v->MinTTUVBlank[k] = dml_max(v->Watermark.StutterEnterPlusExitWatermark, + v->Watermark.UrgentWatermark); + } else { + v->MinTTUVBlank[k] = v->Watermark.UrgentWatermark; + } + if (!mode_lib->vba.DynamicMetadataEnable[k]) + v->MinTTUVBlank[k] = mode_lib->vba.TCalc + v->MinTTUVBlank[k]; + } + + // DCC Configuration + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: Calculate DCC configuration for surface k=%d\n", __func__, k); +#endif + dml32_CalculateDCCConfiguration( + mode_lib->vba.DCCEnable[k], + mode_lib->vba.DCCProgrammingAssumesScanDirectionUnknownFinal, + mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceWidthY[k], + mode_lib->vba.SurfaceWidthC[k], + mode_lib->vba.SurfaceHeightY[k], + mode_lib->vba.SurfaceHeightC[k], + mode_lib->vba.nomDETInKByte, + v->BlockHeight256BytesY[k], + v->BlockHeight256BytesC[k], + mode_lib->vba.SurfaceTiling[k], + v->BytePerPixelY[k], + v->BytePerPixelC[k], + v->BytePerPixelDETY[k], + v->BytePerPixelDETC[k], + mode_lib->vba.SourceScan[k], + /* Output */ + &v->DCCYMaxUncompressedBlock[k], + &v->DCCCMaxUncompressedBlock[k], + &v->DCCYMaxCompressedBlock[k], + &v->DCCCMaxCompressedBlock[k], + &v->DCCYIndependentBlock[k], + &v->DCCCIndependentBlock[k]); + } + + // VStartup Adjustment + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + bool isInterlaceTiming; + double Tvstartup_margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * mode_lib->vba.HTotal[k] + / mode_lib->vba.PixelClock[k]; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d, MinTTUVBlank = %f (before vstartup margin)\n", __func__, k, + v->MinTTUVBlank[k]); +#endif + + v->MinTTUVBlank[k] = v->MinTTUVBlank[k] + Tvstartup_margin; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d, Tvstartup_margin = %f\n", __func__, k, Tvstartup_margin); + dml_print("DML::%s: k=%d, MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]); + dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]); + dml_print("DML::%s: k=%d, MinTTUVBlank = %f\n", __func__, k, v->MinTTUVBlank[k]); +#endif + + v->Tdmdl[k] = v->Tdmdl[k] + Tvstartup_margin; + if (mode_lib->vba.DynamicMetadataEnable[k] && mode_lib->vba.DynamicMetadataVMEnabled) + v->Tdmdl_vm[k] = v->Tdmdl_vm[k] + Tvstartup_margin; + + isInterlaceTiming = (mode_lib->vba.Interlace[k] && + !mode_lib->vba.ProgressiveToInterlaceUnitInOPP); + + v->MIN_DST_Y_NEXT_START[k] = ((isInterlaceTiming ? dml_floor((mode_lib->vba.VTotal[k] - + mode_lib->vba.VFrontPorch[k]) / 2.0, 1.0) : + mode_lib->vba.VTotal[k]) - mode_lib->vba.VFrontPorch[k]) + + dml_max(1.0, + dml_ceil(v->WritebackDelay[mode_lib->vba.VoltageLevel][k] + / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0)) + + dml_floor(4.0 * v->TSetup[k] / (mode_lib->vba.HTotal[k] + / mode_lib->vba.PixelClock[k]), 1.0) / 4.0; + + v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]); + + if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k]) + / mode_lib->vba.HTotal[k]) <= (isInterlaceTiming ? dml_floor((mode_lib->vba.VTotal[k] + - mode_lib->vba.VActive[k] - mode_lib->vba.VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) : + (int) (mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] + - mode_lib->vba.VFrontPorch[k] - v->VStartup[k]))) { + v->VREADY_AT_OR_AFTER_VSYNC[k] = true; + } else { + v->VREADY_AT_OR_AFTER_VSYNC[k] = false; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d, VStartup = %d (max)\n", __func__, k, v->VStartup[k]); + dml_print("DML::%s: k=%d, VUpdateOffsetPix = %d\n", __func__, k, v->VUpdateOffsetPix[k]); + dml_print("DML::%s: k=%d, VUpdateWidthPix = %d\n", __func__, k, v->VUpdateWidthPix[k]); + dml_print("DML::%s: k=%d, VReadyOffsetPix = %d\n", __func__, k, v->VReadyOffsetPix[k]); + dml_print("DML::%s: k=%d, HTotal = %d\n", __func__, k, mode_lib->vba.HTotal[k]); + dml_print("DML::%s: k=%d, VTotal = %d\n", __func__, k, mode_lib->vba.VTotal[k]); + dml_print("DML::%s: k=%d, VActive = %d\n", __func__, k, mode_lib->vba.VActive[k]); + dml_print("DML::%s: k=%d, VFrontPorch = %d\n", __func__, k, mode_lib->vba.VFrontPorch[k]); + dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]); + dml_print("DML::%s: k=%d, TSetup = %f\n", __func__, k, v->TSetup[k]); + dml_print("DML::%s: k=%d, MIN_DST_Y_NEXT_START = %f\n", __func__, k, v->MIN_DST_Y_NEXT_START[k]); + dml_print("DML::%s: k=%d, VREADY_AT_OR_AFTER_VSYNC = %d\n", __func__, k, + v->VREADY_AT_OR_AFTER_VSYNC[k]); +#endif + } + + { + //Maximum Bandwidth Used + double TotalWRBandwidth = 0; + double WRBandwidth = 0; + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.WritebackEnable[k] == true + && mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) { + WRBandwidth = mode_lib->vba.WritebackDestinationWidth[k] + * mode_lib->vba.WritebackDestinationHeight[k] + / (mode_lib->vba.HTotal[k] * mode_lib->vba.WritebackSourceHeight[k] + / mode_lib->vba.PixelClock[k]) * 4; + } else if (mode_lib->vba.WritebackEnable[k] == true) { + WRBandwidth = mode_lib->vba.WritebackDestinationWidth[k] + * mode_lib->vba.WritebackDestinationHeight[k] + / (mode_lib->vba.HTotal[k] * mode_lib->vba.WritebackSourceHeight[k] + / mode_lib->vba.PixelClock[k]) * 8; + } + TotalWRBandwidth = TotalWRBandwidth + WRBandwidth; + } + + v->TotalDataReadBandwidth = 0; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + v->TotalDataReadBandwidth = v->TotalDataReadBandwidth + v->ReadBandwidthSurfaceLuma[k] + + v->ReadBandwidthSurfaceChroma[k]; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d, TotalDataReadBandwidth = %f\n", + __func__, k, v->TotalDataReadBandwidth); + dml_print("DML::%s: k=%d, ReadBandwidthSurfaceLuma = %f\n", + __func__, k, v->ReadBandwidthSurfaceLuma[k]); + dml_print("DML::%s: k=%d, ReadBandwidthSurfaceChroma = %f\n", + __func__, k, v->ReadBandwidthSurfaceChroma[k]); +#endif + } + } + + // Stutter Efficiency + dml32_CalculateStutterEfficiency(v->CompressedBufferSizeInkByte, + mode_lib->vba.UsesMALLForPStateChange, + v->UnboundedRequestEnabled, + mode_lib->vba.MetaFIFOSizeInKEntries, + mode_lib->vba.ZeroSizeBufferEntries, + mode_lib->vba.PixelChunkSizeInKByte, + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.ROBBufferSizeInKByte, + v->TotalDataReadBandwidth, + mode_lib->vba.DCFCLK, + mode_lib->vba.ReturnBW, + mode_lib->vba.CompbufReservedSpace64B, + mode_lib->vba.CompbufReservedSpaceZs, + mode_lib->vba.SRExitTime, + mode_lib->vba.SRExitZ8Time, + mode_lib->vba.SynchronizeTimingsFinal, + mode_lib->vba.BlendingAndTiming, + v->Watermark.StutterEnterPlusExitWatermark, + v->Watermark.Z8StutterEnterPlusExitWatermark, + mode_lib->vba.ProgressiveToInterlaceUnitInOPP, + mode_lib->vba.Interlace, + v->MinTTUVBlank, mode_lib->vba.DPPPerPlane, + mode_lib->vba.DETBufferSizeY, + v->BytePerPixelY, + v->BytePerPixelDETY, + v->SwathWidthY, + mode_lib->vba.SwathHeightY, + mode_lib->vba.SwathHeightC, + mode_lib->vba.DCCRateLuma, + mode_lib->vba.DCCRateChroma, + mode_lib->vba.DCCFractionOfZeroSizeRequestsLuma, + mode_lib->vba.DCCFractionOfZeroSizeRequestsChroma, + mode_lib->vba.HTotal, mode_lib->vba.VTotal, + mode_lib->vba.PixelClock, + mode_lib->vba.VRatio, + mode_lib->vba.SourceRotation, + v->BlockHeight256BytesY, + v->BlockWidth256BytesY, + v->BlockHeight256BytesC, + v->BlockWidth256BytesC, + v->DCCYMaxUncompressedBlock, + v->DCCCMaxUncompressedBlock, + mode_lib->vba.VActive, + mode_lib->vba.DCCEnable, + mode_lib->vba.WritebackEnable, + v->ReadBandwidthSurfaceLuma, + v->ReadBandwidthSurfaceChroma, + v->meta_row_bw, + v->dpte_row_bw, + /* Output */ + &v->StutterEfficiencyNotIncludingVBlank, + &v->StutterEfficiency, + &v->NumberOfStutterBurstsPerFrame, + &v->Z8StutterEfficiencyNotIncludingVBlank, + &v->Z8StutterEfficiency, + &v->Z8NumberOfStutterBurstsPerFrame, + &v->StutterPeriod, + &v->DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE); + +#ifdef __DML_VBA_ALLOW_DELTA__ + { + double dummy_single[2]; + unsigned int dummy_integer[1]; + bool dummy_boolean[1]; + + // Calculate z8 stutter eff assuming 0 reserved space + dml32_CalculateStutterEfficiency(v->CompressedBufferSizeInkByte, + mode_lib->vba.UsesMALLForPStateChange, + v->UnboundedRequestEnabled, + mode_lib->vba.MetaFIFOSizeInKEntries, + mode_lib->vba.ZeroSizeBufferEntries, + mode_lib->vba.PixelChunkSizeInKByte, + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.ROBBufferSizeInKByte, + v->TotalDataReadBandwidth, + mode_lib->vba.DCFCLK, + mode_lib->vba.ReturnBW, + 0, //mode_lib->vba.CompbufReservedSpace64B, + 0, //mode_lib->vba.CompbufReservedSpaceZs, + mode_lib->vba.SRExitTime, + mode_lib->vba.SRExitZ8Time, + mode_lib->vba.SynchronizeTimingsFinal, + mode_lib->vba.BlendingAndTiming, + v->Watermark.StutterEnterPlusExitWatermark, + v->Watermark.Z8StutterEnterPlusExitWatermark, + mode_lib->vba.ProgressiveToInterlaceUnitInOPP, + mode_lib->vba.Interlace, + v->MinTTUVBlank, + mode_lib->vba.DPPPerPlane, + mode_lib->vba.DETBufferSizeY, + v->BytePerPixelY, v->BytePerPixelDETY, + v->SwathWidthY, mode_lib->vba.SwathHeightY, + mode_lib->vba.SwathHeightC, + mode_lib->vba.DCCRateLuma, + mode_lib->vba.DCCRateChroma, + mode_lib->vba.DCCFractionOfZeroSizeRequestsLuma, + mode_lib->vba.DCCFractionOfZeroSizeRequestsChroma, + mode_lib->vba.HTotal, + mode_lib->vba.VTotal, + mode_lib->vba.PixelClock, + mode_lib->vba.VRatio, + mode_lib->vba.SourceRotation, + v->BlockHeight256BytesY, + v->BlockWidth256BytesY, + v->BlockHeight256BytesC, + v->BlockWidth256BytesC, + v->DCCYMaxUncompressedBlock, + v->DCCCMaxUncompressedBlock, + mode_lib->vba.VActive, + mode_lib->vba.DCCEnable, + mode_lib->vba.WritebackEnable, + v->ReadBandwidthSurfaceLuma, + v->ReadBandwidthSurfaceChroma, + v->meta_row_bw, v->dpte_row_bw, + + /* Output */ + &dummy_single[0], + &dummy_single[1], + &dummy_integer[0], + &v->Z8StutterEfficiencyNotIncludingVBlankBestCase, + &v->Z8StutterEfficiencyBestCase, + &v->Z8NumberOfStutterBurstsPerFrameBestCase, + &v->StutterPeriodBestCase, + &dummy_boolean[0]); + } +#else + v->Z8StutterEfficiencyNotIncludingVBlankBestCase = v->Z8StutterEfficiencyNotIncludingVBlank; + v->Z8StutterEfficiencyBestCase = v->Z8StutterEfficiency; + v->Z8NumberOfStutterBurstsPerFrameBestCase = v->Z8NumberOfStutterBurstsPerFrame; + v->StutterPeriodBestCase = v->StutterPeriod; +#endif + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: --- END ---\n", __func__); +#endif +} + +void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) +{ + bool dummy_boolean[2]; + unsigned int dummy_integer[1]; + bool MPCCombineMethodAsNeededForPStateChangeAndVoltage; + bool MPCCombineMethodAsPossible; + enum odm_combine_mode dummy_odm_mode[DC__NUM_DPP__MAX]; + unsigned int TotalNumberOfActiveOTG; + unsigned int TotalNumberOfActiveHDMIFRL; + unsigned int TotalNumberOfActiveDP2p0; + unsigned int TotalNumberOfActiveDP2p0Outputs; + unsigned int TotalDSCUnitsRequired; + unsigned int m; + unsigned int ReorderingBytes; + bool FullFrameMALLPStateMethod; + bool SubViewportMALLPStateMethod; + bool PhantomPipeMALLPStateMethod; + double MaxTotalVActiveRDBandwidth; + double DSTYAfterScaler[DC__NUM_DPP__MAX]; + double DSTXAfterScaler[DC__NUM_DPP__MAX]; + unsigned int MaximumMPCCombine; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: called\n", __func__); +#endif + struct vba_vars_st *v = &mode_lib->vba; + + int i, j; + unsigned int k; + + /*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/ + + /*Scale Ratio, taps Support Check*/ + + mode_lib->vba.ScaleRatioAndTapsSupport = true; + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + if (mode_lib->vba.ScalerEnabled[k] == false + && ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64 + && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 + && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 + && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 + && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8 + && mode_lib->vba.SourcePixelFormat[k] != dm_rgbe + && mode_lib->vba.SourcePixelFormat[k] != dm_rgbe_alpha) + || mode_lib->vba.HRatio[k] != 1.0 || mode_lib->vba.htaps[k] != 1.0 + || mode_lib->vba.VRatio[k] != 1.0 || mode_lib->vba.vtaps[k] != 1.0)) { + mode_lib->vba.ScaleRatioAndTapsSupport = false; + } else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0 || mode_lib->vba.htaps[k] < 1.0 + || mode_lib->vba.htaps[k] > 8.0 + || (mode_lib->vba.htaps[k] > 1.0 && (mode_lib->vba.htaps[k] % 2) == 1) + || mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio + || mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio + || mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k] + || mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k] + || (mode_lib->vba.SourcePixelFormat[k] != dm_444_64 + && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 + && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 + && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 + && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8 + && mode_lib->vba.SourcePixelFormat[k] != dm_rgbe + && (mode_lib->vba.VTAPsChroma[k] < 1 + || mode_lib->vba.VTAPsChroma[k] > 8 + || mode_lib->vba.HTAPsChroma[k] < 1 + || mode_lib->vba.HTAPsChroma[k] > 8 + || (mode_lib->vba.HTAPsChroma[k] > 1 + && mode_lib->vba.HTAPsChroma[k] % 2 + == 1) + || mode_lib->vba.HRatioChroma[k] + > mode_lib->vba.MaxHSCLRatio + || mode_lib->vba.VRatioChroma[k] + > mode_lib->vba.MaxVSCLRatio + || mode_lib->vba.HRatioChroma[k] + > mode_lib->vba.HTAPsChroma[k] + || mode_lib->vba.VRatioChroma[k] + > mode_lib->vba.VTAPsChroma[k]))) { + mode_lib->vba.ScaleRatioAndTapsSupport = false; + } + } + + /*Source Format, Pixel Format and Scan Support Check*/ + mode_lib->vba.SourceFormatPixelAndScanSupport = true; + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear + && (!(!IsVertical(mode_lib->vba.SourceScan[k])) || mode_lib->vba.DCCEnable[k] == true)) { + mode_lib->vba.SourceFormatPixelAndScanSupport = false; + } + } + + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + dml32_CalculateBytePerPixelAndBlockSizes( + mode_lib->vba.SourcePixelFormat[k], + mode_lib->vba.SurfaceTiling[k], + + /* Output */ + &mode_lib->vba.BytePerPixelY[k], + &mode_lib->vba.BytePerPixelC[k], + &mode_lib->vba.BytePerPixelInDETY[k], + &mode_lib->vba.BytePerPixelInDETC[k], + &mode_lib->vba.Read256BlockHeightY[k], + &mode_lib->vba.Read256BlockHeightC[k], + &mode_lib->vba.Read256BlockWidthY[k], + &mode_lib->vba.Read256BlockWidthC[k], + &mode_lib->vba.MicroTileHeightY[k], + &mode_lib->vba.MicroTileHeightC[k], + &mode_lib->vba.MicroTileWidthY[k], + &mode_lib->vba.MicroTileWidthC[k]); + } + + /*Bandwidth Support Check*/ + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + if (!IsVertical(mode_lib->vba.SourceRotation[k])) { + v->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k]; + v->SwathWidthCSingleDPP[k] = mode_lib->vba.ViewportWidthChroma[k]; + } else { + v->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k]; + v->SwathWidthCSingleDPP[k] = mode_lib->vba.ViewportHeightChroma[k]; + } + } + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0) + / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; + v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0) + / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] + / 2.0; + } + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + if (mode_lib->vba.WritebackEnable[k] == true && mode_lib->vba.WritebackPixelFormat[k] == dm_444_64) { + v->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] + * mode_lib->vba.WritebackDestinationHeight[k] + / (mode_lib->vba.WritebackSourceHeight[k] * mode_lib->vba.HTotal[k] + / mode_lib->vba.PixelClock[k]) * 8.0; + } else if (mode_lib->vba.WritebackEnable[k] == true) { + v->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] + * mode_lib->vba.WritebackDestinationHeight[k] + / (mode_lib->vba.WritebackSourceHeight[k] * mode_lib->vba.HTotal[k] + / mode_lib->vba.PixelClock[k]) * 4.0; + } else { + v->WriteBandwidth[k] = 0.0; + } + } + + /*Writeback Latency support check*/ + + mode_lib->vba.WritebackLatencySupport = true; + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + if (mode_lib->vba.WritebackEnable[k] == true + && (v->WriteBandwidth[k] + > mode_lib->vba.WritebackInterfaceBufferSize * 1024 + / mode_lib->vba.WritebackLatency)) { + mode_lib->vba.WritebackLatencySupport = false; + } + } + + /*Writeback Mode Support Check*/ + mode_lib->vba.EnoughWritebackUnits = true; + mode_lib->vba.TotalNumberOfActiveWriteback = 0; + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + if (mode_lib->vba.WritebackEnable[k] == true) + mode_lib->vba.TotalNumberOfActiveWriteback = mode_lib->vba.TotalNumberOfActiveWriteback + 1; + } + + if (mode_lib->vba.TotalNumberOfActiveWriteback > mode_lib->vba.MaxNumWriteback) + mode_lib->vba.EnoughWritebackUnits = false; + + /*Writeback Scale Ratio and Taps Support Check*/ + mode_lib->vba.WritebackScaleRatioAndTapsSupport = true; + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + if (mode_lib->vba.WritebackEnable[k] == true) { + if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio + || mode_lib->vba.WritebackVRatio[k] > mode_lib->vba.WritebackMaxVSCLRatio + || mode_lib->vba.WritebackHRatio[k] < mode_lib->vba.WritebackMinHSCLRatio + || mode_lib->vba.WritebackVRatio[k] < mode_lib->vba.WritebackMinVSCLRatio + || mode_lib->vba.WritebackHTaps[k] > mode_lib->vba.WritebackMaxHSCLTaps + || mode_lib->vba.WritebackVTaps[k] > mode_lib->vba.WritebackMaxVSCLTaps + || mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackHTaps[k] + || mode_lib->vba.WritebackVRatio[k] > mode_lib->vba.WritebackVTaps[k] + || (mode_lib->vba.WritebackHTaps[k] > 2.0 + && ((mode_lib->vba.WritebackHTaps[k] % 2) == 1))) { + mode_lib->vba.WritebackScaleRatioAndTapsSupport = false; + } + if (2.0 * mode_lib->vba.WritebackDestinationWidth[k] * (mode_lib->vba.WritebackVTaps[k] - 1) + * 57 > mode_lib->vba.WritebackLineBufferSize) { + mode_lib->vba.WritebackScaleRatioAndTapsSupport = false; + } + } + } + + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(mode_lib->vba.HRatio[k], mode_lib->vba.HRatioChroma[k], + mode_lib->vba.VRatio[k], mode_lib->vba.VRatioChroma[k], + mode_lib->vba.MaxDCHUBToPSCLThroughput, mode_lib->vba.MaxPSCLToLBThroughput, + mode_lib->vba.PixelClock[k], mode_lib->vba.SourcePixelFormat[k], + mode_lib->vba.htaps[k], mode_lib->vba.HTAPsChroma[k], mode_lib->vba.vtaps[k], + mode_lib->vba.VTAPsChroma[k], + /* Output */ + &mode_lib->vba.PSCL_FACTOR[k], &mode_lib->vba.PSCL_FACTOR_CHROMA[k], + &mode_lib->vba.MinDPPCLKUsingSingleDPP[k]); + } + + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + + if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 8192; + } else if (!IsVertical(mode_lib->vba.SourceRotation[k]) && v->BytePerPixelC[k] > 0 + && mode_lib->vba.SourcePixelFormat[k] != dm_rgbe_alpha) { + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 7680; + } else if (IsVertical(mode_lib->vba.SourceRotation[k]) && v->BytePerPixelC[k] > 0 + && mode_lib->vba.SourcePixelFormat[k] != dm_rgbe_alpha) { + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 4320; + } else if (mode_lib->vba.SourcePixelFormat[k] == dm_rgbe_alpha) { + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 3840; + } else if (IsVertical(mode_lib->vba.SourceRotation[k]) && v->BytePerPixelY[k] == 8 && + mode_lib->vba.DCCEnable[k] == true) { + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 3072; + } else { + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 6144; + } + + if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8 || mode_lib->vba.SourcePixelFormat[k] == dm_420_10 + || mode_lib->vba.SourcePixelFormat[k] == dm_420_12) { + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma / 2.0; + } else { + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma; + } + v->MaximumSwathWidthInLineBufferLuma = mode_lib->vba.LineBufferSizeFinal + * dml_max(mode_lib->vba.HRatio[k], 1.0) / mode_lib->vba.LBBitPerPixel[k] + / (mode_lib->vba.vtaps[k] + dml_max(dml_ceil(mode_lib->vba.VRatio[k], 1.0) - 2, 0.0)); + if (v->BytePerPixelC[k] == 0.0) { + v->MaximumSwathWidthInLineBufferChroma = 0; + } else { + v->MaximumSwathWidthInLineBufferChroma = mode_lib->vba.LineBufferSizeFinal + * dml_max(mode_lib->vba.HRatioChroma[k], 1.0) / mode_lib->vba.LBBitPerPixel[k] + / (mode_lib->vba.VTAPsChroma[k] + + dml_max(dml_ceil(mode_lib->vba.VRatioChroma[k], 1.0) - 2, + 0.0)); + } + v->MaximumSwathWidthLuma[k] = dml_min(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma, + v->MaximumSwathWidthInLineBufferLuma); + v->MaximumSwathWidthChroma[k] = dml_min(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma, + v->MaximumSwathWidthInLineBufferChroma); + } + + /*Number Of DSC Slices*/ + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.BlendingAndTiming[k] == k) { + if (mode_lib->vba.PixelClockBackEnd[k] > 4800) { + mode_lib->vba.NumberOfDSCSlices[k] = dml_ceil(mode_lib->vba.PixelClockBackEnd[k] / 600, + 4); + } else if (mode_lib->vba.PixelClockBackEnd[k] > 2400) { + mode_lib->vba.NumberOfDSCSlices[k] = 8; + } else if (mode_lib->vba.PixelClockBackEnd[k] > 1200) { + mode_lib->vba.NumberOfDSCSlices[k] = 4; + } else if (mode_lib->vba.PixelClockBackEnd[k] > 340) { + mode_lib->vba.NumberOfDSCSlices[k] = 2; + } else { + mode_lib->vba.NumberOfDSCSlices[k] = 1; + } + } else { + mode_lib->vba.NumberOfDSCSlices[k] = 0; + } + } + + dml32_CalculateSwathAndDETConfiguration( + mode_lib->vba.DETSizeOverride, + mode_lib->vba.UsesMALLForPStateChange, + mode_lib->vba.ConfigReturnBufferSizeInKByte, + mode_lib->vba.MaxTotalDETInKByte, + mode_lib->vba.MinCompressedBufferSizeInKByte, + 1, /* ForceSingleDPP */ + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.nomDETInKByte, + mode_lib->vba.UseUnboundedRequesting, + mode_lib->vba.CompressedBufferSegmentSizeInkByteFinal, + mode_lib->vba.Output, + mode_lib->vba.ReadBandwidthLuma, + mode_lib->vba.ReadBandwidthChroma, + mode_lib->vba.MaximumSwathWidthLuma, + mode_lib->vba.MaximumSwathWidthChroma, + mode_lib->vba.SourceRotation, + mode_lib->vba.ViewportStationary, + mode_lib->vba.SourcePixelFormat, + mode_lib->vba.SurfaceTiling, + mode_lib->vba.ViewportWidth, + mode_lib->vba.ViewportHeight, + mode_lib->vba.ViewportXStartY, + mode_lib->vba.ViewportYStartY, + mode_lib->vba.ViewportXStartC, + mode_lib->vba.ViewportYStartC, + mode_lib->vba.SurfaceWidthY, + mode_lib->vba.SurfaceWidthC, + mode_lib->vba.SurfaceHeightY, + mode_lib->vba.SurfaceHeightC, + mode_lib->vba.Read256BlockHeightY, + mode_lib->vba.Read256BlockHeightC, + mode_lib->vba.Read256BlockWidthY, + mode_lib->vba.Read256BlockWidthC, + dummy_odm_mode, + mode_lib->vba.BlendingAndTiming, + mode_lib->vba.BytePerPixelY, + mode_lib->vba.BytePerPixelC, + mode_lib->vba.BytePerPixelInDETY, + mode_lib->vba.BytePerPixelInDETC, + mode_lib->vba.HActive, + mode_lib->vba.HRatio, + mode_lib->vba.HRatioChroma, + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[0], /* Integer DPPPerSurface[] */ + + /* Output */ + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[1], /* Long swath_width_luma_ub[] */ + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[2], /* Long swath_width_chroma_ub[] */ + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_double_array[0], /* Long SwathWidth[] */ + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_double_array[1], /* Long SwathWidthChroma[] */ + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[3], /* Integer SwathHeightY[] */ + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[4], /* Integer SwathHeightC[] */ + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[5], /* Long DETBufferSizeInKByte[] */ + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[6], /* Long DETBufferSizeY[] */ + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[7], /* Long DETBufferSizeC[] */ + &dummy_boolean[0], /* bool *UnboundedRequestEnabled */ + &dummy_integer[0], /* Long *CompressedBufferSizeInkByte */ + mode_lib->vba.SingleDPPViewportSizeSupportPerSurface,/* bool ViewportSizeSupportPerSurface[] */ + &dummy_boolean[1]); /* bool *ViewportSizeSupport */ + + MPCCombineMethodAsNeededForPStateChangeAndVoltage = false; + MPCCombineMethodAsPossible = false; + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.MPCCombineUse[k] == dm_mpc_reduce_voltage_and_clocks) + MPCCombineMethodAsNeededForPStateChangeAndVoltage = true; + if (mode_lib->vba.MPCCombineUse[k] == dm_mpc_always_when_possible) + MPCCombineMethodAsPossible = true; + } + mode_lib->vba.MPCCombineMethodIncompatible = MPCCombineMethodAsNeededForPStateChangeAndVoltage + && MPCCombineMethodAsPossible; + + for (i = 0; i < v->soc.num_states; i++) { + for (j = 0; j < 2; j++) { + bool NoChroma; + mode_lib->vba.TotalNumberOfActiveDPP[i][j] = 0; + mode_lib->vba.TotalAvailablePipesSupport[i][j] = true; + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + + bool TotalAvailablePipesSupportNoDSC; + unsigned int NumberOfDPPNoDSC; + enum odm_combine_mode ODMModeNoDSC = dm_odm_combine_mode_disabled; + double RequiredDISPCLKPerSurfaceNoDSC; + bool TotalAvailablePipesSupportDSC; + unsigned int NumberOfDPPDSC; + enum odm_combine_mode ODMModeDSC = dm_odm_combine_mode_disabled; + double RequiredDISPCLKPerSurfaceDSC; + + dml32_CalculateODMMode( + mode_lib->vba.MaximumPixelsPerLinePerDSCUnit, + mode_lib->vba.HActive[k], + mode_lib->vba.Output[k], + mode_lib->vba.ODMUse[k], + mode_lib->vba.MaxDispclk[i], + mode_lib->vba.MaxDispclk[v->soc.num_states - 1], + false, + mode_lib->vba.TotalNumberOfActiveDPP[i][j], + mode_lib->vba.MaxNumDPP, + mode_lib->vba.PixelClock[k], + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading, + mode_lib->vba.DISPCLKRampingMargin, + mode_lib->vba.DISPCLKDPPCLKVCOSpeed, + + /* Output */ + &TotalAvailablePipesSupportNoDSC, + &NumberOfDPPNoDSC, + &ODMModeNoDSC, + &RequiredDISPCLKPerSurfaceNoDSC); + + dml32_CalculateODMMode( + mode_lib->vba.MaximumPixelsPerLinePerDSCUnit, + mode_lib->vba.HActive[k], + mode_lib->vba.Output[k], + mode_lib->vba.ODMUse[k], + mode_lib->vba.MaxDispclk[i], + mode_lib->vba.MaxDispclk[v->soc.num_states - 1], + true, + mode_lib->vba.TotalNumberOfActiveDPP[i][j], + mode_lib->vba.MaxNumDPP, + mode_lib->vba.PixelClock[k], + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading, + mode_lib->vba.DISPCLKRampingMargin, + mode_lib->vba.DISPCLKDPPCLKVCOSpeed, + + /* Output */ + &TotalAvailablePipesSupportDSC, + &NumberOfDPPDSC, + &ODMModeDSC, + &RequiredDISPCLKPerSurfaceDSC); + + dml32_CalculateOutputLink( + mode_lib->vba.PHYCLKPerState[i], + mode_lib->vba.PHYCLKD18PerState[i], + mode_lib->vba.PHYCLKD32PerState[i], + mode_lib->vba.Downspreading, + (mode_lib->vba.BlendingAndTiming[k] == k), + mode_lib->vba.Output[k], + mode_lib->vba.OutputFormat[k], + mode_lib->vba.HTotal[k], + mode_lib->vba.HActive[k], + mode_lib->vba.PixelClockBackEnd[k], + mode_lib->vba.ForcedOutputLinkBPP[k], + mode_lib->vba.DSCInputBitPerComponent[k], + mode_lib->vba.NumberOfDSCSlices[k], + mode_lib->vba.AudioSampleRate[k], + mode_lib->vba.AudioSampleLayout[k], + ODMModeNoDSC, + ODMModeDSC, + mode_lib->vba.DSCEnable[k], + mode_lib->vba.OutputLinkDPLanes[k], + mode_lib->vba.OutputLinkDPRate[k], + + /* Output */ + &mode_lib->vba.RequiresDSC[i][k], + &mode_lib->vba.RequiresFEC[i][k], + &mode_lib->vba.OutputBppPerState[i][k], + &mode_lib->vba.OutputTypePerState[i][k], + &mode_lib->vba.OutputRatePerState[i][k], + &mode_lib->vba.RequiredSlots[i][k]); + + if (mode_lib->vba.RequiresDSC[i][k] == false) { + mode_lib->vba.ODMCombineEnablePerState[i][k] = ODMModeNoDSC; + mode_lib->vba.RequiredDISPCLKPerSurface[i][j][k] = + RequiredDISPCLKPerSurfaceNoDSC; + if (!TotalAvailablePipesSupportNoDSC) + mode_lib->vba.TotalAvailablePipesSupport[i][j] = false; + mode_lib->vba.TotalNumberOfActiveDPP[i][j] = + mode_lib->vba.TotalNumberOfActiveDPP[i][j] + NumberOfDPPNoDSC; + } else { + mode_lib->vba.ODMCombineEnablePerState[i][k] = ODMModeDSC; + mode_lib->vba.RequiredDISPCLKPerSurface[i][j][k] = + RequiredDISPCLKPerSurfaceDSC; + if (!TotalAvailablePipesSupportDSC) + mode_lib->vba.TotalAvailablePipesSupport[i][j] = false; + mode_lib->vba.TotalNumberOfActiveDPP[i][j] = + mode_lib->vba.TotalNumberOfActiveDPP[i][j] + NumberOfDPPDSC; + } + } + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) { + mode_lib->vba.MPCCombine[i][j][k] = false; + mode_lib->vba.NoOfDPP[i][j][k] = 4; + } else if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) { + mode_lib->vba.MPCCombine[i][j][k] = false; + mode_lib->vba.NoOfDPP[i][j][k] = 2; + } else if (mode_lib->vba.MPCCombineUse[k] == dm_mpc_never) { + mode_lib->vba.MPCCombine[i][j][k] = false; + mode_lib->vba.NoOfDPP[i][j][k] = 1; + } else if (dml32_RoundToDFSGranularity( + mode_lib->vba.MinDPPCLKUsingSingleDPP[k] + * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading + / 100), 1, + mode_lib->vba.DISPCLKDPPCLKVCOSpeed) <= mode_lib->vba.MaxDppclk[i] && + mode_lib->vba.SingleDPPViewportSizeSupportPerSurface[k] == true) { + mode_lib->vba.MPCCombine[i][j][k] = false; + mode_lib->vba.NoOfDPP[i][j][k] = 1; + } else if (mode_lib->vba.TotalNumberOfActiveDPP[i][j] < mode_lib->vba.MaxNumDPP) { + mode_lib->vba.MPCCombine[i][j][k] = true; + mode_lib->vba.NoOfDPP[i][j][k] = 2; + mode_lib->vba.TotalNumberOfActiveDPP[i][j] = + mode_lib->vba.TotalNumberOfActiveDPP[i][j] + 1; + } else { + mode_lib->vba.MPCCombine[i][j][k] = false; + mode_lib->vba.NoOfDPP[i][j][k] = 1; + mode_lib->vba.TotalAvailablePipesSupport[i][j] = false; + } + } + + mode_lib->vba.TotalNumberOfSingleDPPSurfaces[i][j] = 0; + NoChroma = true; + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.NoOfDPP[i][j][k] == 1) + mode_lib->vba.TotalNumberOfSingleDPPSurfaces[i][j] = + mode_lib->vba.TotalNumberOfSingleDPPSurfaces[i][j] + 1; + if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8 + || mode_lib->vba.SourcePixelFormat[k] == dm_420_10 + || mode_lib->vba.SourcePixelFormat[k] == dm_420_12 + || mode_lib->vba.SourcePixelFormat[k] == dm_rgbe_alpha) { + NoChroma = false; + } + } + + if (j == 1 && !dml32_UnboundedRequest(mode_lib->vba.UseUnboundedRequesting, + mode_lib->vba.TotalNumberOfActiveDPP[i][j], NoChroma, + mode_lib->vba.Output[0])) { + while (!(mode_lib->vba.TotalNumberOfActiveDPP[i][j] >= mode_lib->vba.MaxNumDPP + || mode_lib->vba.TotalNumberOfSingleDPPSurfaces[i][j] == 0)) { + double BWOfNonCombinedSurfaceOfMaximumBandwidth = 0; + unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth = 0; + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.MPCCombineUse[k] + != dm_mpc_never && + mode_lib->vba.MPCCombineUse[k] != dm_mpc_reduce_voltage && + mode_lib->vba.ReadBandwidthLuma[k] + + mode_lib->vba.ReadBandwidthChroma[k] > + BWOfNonCombinedSurfaceOfMaximumBandwidth && + (mode_lib->vba.ODMCombineEnablePerState[i][k] != + dm_odm_combine_mode_2to1 && + mode_lib->vba.ODMCombineEnablePerState[i][k] != + dm_odm_combine_mode_4to1) && + mode_lib->vba.MPCCombine[i][j][k] == false) { + BWOfNonCombinedSurfaceOfMaximumBandwidth = + mode_lib->vba.ReadBandwidthLuma[k] + + mode_lib->vba.ReadBandwidthChroma[k]; + NumberOfNonCombinedSurfaceOfMaximumBandwidth = k; + } + } + mode_lib->vba.MPCCombine[i][j][NumberOfNonCombinedSurfaceOfMaximumBandwidth] = + true; + mode_lib->vba.NoOfDPP[i][j][NumberOfNonCombinedSurfaceOfMaximumBandwidth] = 2; + mode_lib->vba.TotalNumberOfActiveDPP[i][j] = + mode_lib->vba.TotalNumberOfActiveDPP[i][j] + 1; + mode_lib->vba.TotalNumberOfSingleDPPSurfaces[i][j] = + mode_lib->vba.TotalNumberOfSingleDPPSurfaces[i][j] - 1; + } + } + + //DISPCLK/DPPCLK + mode_lib->vba.WritebackRequiredDISPCLK = 0; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.WritebackEnable[k]) { + mode_lib->vba.WritebackRequiredDISPCLK = dml_max( + mode_lib->vba.WritebackRequiredDISPCLK, + dml32_CalculateWriteBackDISPCLK( + mode_lib->vba.WritebackPixelFormat[k], + mode_lib->vba.PixelClock[k], + mode_lib->vba.WritebackHRatio[k], + mode_lib->vba.WritebackVRatio[k], + mode_lib->vba.WritebackHTaps[k], + mode_lib->vba.WritebackVTaps[k], + mode_lib->vba.WritebackSourceWidth[k], + mode_lib->vba.WritebackDestinationWidth[k], + mode_lib->vba.HTotal[k], + mode_lib->vba.WritebackLineBufferSize, + mode_lib->vba.DISPCLKDPPCLKVCOSpeed)); + } + } + + mode_lib->vba.RequiredDISPCLK[i][j] = mode_lib->vba.WritebackRequiredDISPCLK; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + mode_lib->vba.RequiredDISPCLK[i][j] = dml_max(mode_lib->vba.RequiredDISPCLK[i][j], + mode_lib->vba.RequiredDISPCLKPerSurface[i][j][k]); + } + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) + mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k]; + + dml32_CalculateDPPCLK(mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading, + mode_lib->vba.DISPCLKDPPCLKVCOSpeed, mode_lib->vba.MinDPPCLKUsingSingleDPP, + mode_lib->vba.NoOfDPPThisState, + /* Output */ + &mode_lib->vba.GlobalDPPCLK, mode_lib->vba.RequiredDPPCLKThisState); + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) + mode_lib->vba.RequiredDPPCLK[i][j][k] = mode_lib->vba.RequiredDPPCLKThisState[k]; + + mode_lib->vba.DISPCLK_DPPCLK_Support[i][j] = !((mode_lib->vba.RequiredDISPCLK[i][j] + > mode_lib->vba.MaxDispclk[i]) + || (mode_lib->vba.GlobalDPPCLK > mode_lib->vba.MaxDppclk[i])); + + if (mode_lib->vba.TotalNumberOfActiveDPP[i][j] > mode_lib->vba.MaxNumDPP) + mode_lib->vba.TotalAvailablePipesSupport[i][j] = false; + } // j + } // i (VOLTAGE_STATE) + + /* Total Available OTG, HDMIFRL, DP Support Check */ + TotalNumberOfActiveOTG = 0; + TotalNumberOfActiveHDMIFRL = 0; + TotalNumberOfActiveDP2p0 = 0; + TotalNumberOfActiveDP2p0Outputs = 0; + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.BlendingAndTiming[k] == k) { + TotalNumberOfActiveOTG = TotalNumberOfActiveOTG + 1; + if (mode_lib->vba.Output[k] == dm_dp2p0) { + TotalNumberOfActiveDP2p0 = TotalNumberOfActiveDP2p0 + 1; + if (mode_lib->vba.OutputMultistreamId[k] + == k || mode_lib->vba.OutputMultistreamEn[k] == false) { + TotalNumberOfActiveDP2p0Outputs = TotalNumberOfActiveDP2p0Outputs + 1; + } + } + } + } + + mode_lib->vba.NumberOfOTGSupport = (TotalNumberOfActiveOTG <= mode_lib->vba.MaxNumOTG); + mode_lib->vba.NumberOfHDMIFRLSupport = (TotalNumberOfActiveHDMIFRL <= mode_lib->vba.MaxNumHDMIFRLOutputs); + mode_lib->vba.NumberOfDP2p0Support = (TotalNumberOfActiveDP2p0 <= mode_lib->vba.MaxNumDP2p0Streams + && TotalNumberOfActiveDP2p0Outputs <= mode_lib->vba.MaxNumDP2p0Outputs); + + /* Display IO and DSC Support Check */ + mode_lib->vba.NonsupportedDSCInputBPC = false; + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0 + || mode_lib->vba.DSCInputBitPerComponent[k] == 10.0 + || mode_lib->vba.DSCInputBitPerComponent[k] == 8.0 + || mode_lib->vba.DSCInputBitPerComponent[k] > + mode_lib->vba.MaximumDSCBitsPerComponent)) { + mode_lib->vba.NonsupportedDSCInputBPC = true; + } + } + + for (i = 0; i < v->soc.num_states; ++i) { + unsigned int TotalSlots; + + mode_lib->vba.ExceededMultistreamSlots[i] = false; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == k) { + TotalSlots = mode_lib->vba.RequiredSlots[i][k]; + for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; ++j) { + if (mode_lib->vba.OutputMultistreamId[j] == k) + TotalSlots = TotalSlots + mode_lib->vba.RequiredSlots[i][j]; + } + if (mode_lib->vba.Output[k] == dm_dp && TotalSlots > 63) + mode_lib->vba.ExceededMultistreamSlots[i] = true; + if (mode_lib->vba.Output[k] == dm_dp2p0 && TotalSlots > 64) + mode_lib->vba.ExceededMultistreamSlots[i] = true; + } + } + mode_lib->vba.LinkCapacitySupport[i] = true; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.BlendingAndTiming[k] == k + && (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_dp2p0 + || mode_lib->vba.Output[k] == dm_edp + || mode_lib->vba.Output[k] == dm_hdmi) + && mode_lib->vba.OutputBppPerState[i][k] == 0) { + mode_lib->vba.LinkCapacitySupport[i] = false; + } + } + } + + mode_lib->vba.P2IWith420 = false; + mode_lib->vba.DSCOnlyIfNecessaryWithBPP = false; + mode_lib->vba.DSC422NativeNotSupported = false; + mode_lib->vba.LinkRateDoesNotMatchDPVersion = false; + mode_lib->vba.LinkRateForMultistreamNotIndicated = false; + mode_lib->vba.BPPForMultistreamNotIndicated = false; + mode_lib->vba.MultistreamWithHDMIOreDP = false; + mode_lib->vba.MSOOrODMSplitWithNonDPLink = false; + mode_lib->vba.NotEnoughLanesForMSO = false; + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.BlendingAndTiming[k] == k + && (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_dp2p0 + || mode_lib->vba.Output[k] == dm_edp + || mode_lib->vba.Output[k] == dm_hdmi)) { + if (mode_lib->vba.OutputFormat[k] + == dm_420 && mode_lib->vba.Interlace[k] == 1 && + mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true) + mode_lib->vba.P2IWith420 = true; + + if (mode_lib->vba.DSCEnable[k] && mode_lib->vba.ForcedOutputLinkBPP[k] != 0) + mode_lib->vba.DSCOnlyIfNecessaryWithBPP = true; + if ((mode_lib->vba.DSCEnable[k] || mode_lib->vba.DSCEnable[k]) + && mode_lib->vba.OutputFormat[k] == dm_n422 + && !mode_lib->vba.DSC422NativeSupport) + mode_lib->vba.DSC422NativeNotSupported = true; + + if (((mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_hbr + || mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_hbr2 + || mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_hbr3) + && mode_lib->vba.Output[k] != dm_dp && mode_lib->vba.Output[k] != dm_edp) + || ((mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_uhbr10 + || mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_uhbr13p5 + || mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_uhbr20) + && mode_lib->vba.Output[k] != dm_dp2p0)) + mode_lib->vba.LinkRateDoesNotMatchDPVersion = true; + + if (mode_lib->vba.OutputMultistreamEn[k] == true) { + if (mode_lib->vba.OutputMultistreamId[k] == k + && mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_na) + mode_lib->vba.LinkRateForMultistreamNotIndicated = true; + if (mode_lib->vba.OutputMultistreamId[k] == k && mode_lib->vba.ForcedOutputLinkBPP[k] == 0) + mode_lib->vba.BPPForMultistreamNotIndicated = true; + for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; ++j) { + if (mode_lib->vba.OutputMultistreamId[k] == j && mode_lib->vba.OutputMultistreamEn[k] + && mode_lib->vba.ForcedOutputLinkBPP[k] == 0) + mode_lib->vba.BPPForMultistreamNotIndicated = true; + } + } + + if ((mode_lib->vba.Output[k] == dm_edp || mode_lib->vba.Output[k] == dm_hdmi)) { + if (mode_lib->vba.OutputMultistreamId[k] == k && mode_lib->vba.OutputMultistreamEn[k]) + mode_lib->vba.MultistreamWithHDMIOreDP = true; + + for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; ++j) { + if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == j) + mode_lib->vba.MultistreamWithHDMIOreDP = true; + } + } + + if (mode_lib->vba.Output[k] != dm_dp + && (mode_lib->vba.ODMUse[k] == dm_odm_split_policy_1to2 + || mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to2 + || mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to4)) + mode_lib->vba.MSOOrODMSplitWithNonDPLink = true; + + if ((mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to2 + && mode_lib->vba.OutputLinkDPLanes[k] < 2) + || (mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to4 + && mode_lib->vba.OutputLinkDPLanes[k] < 4)) + mode_lib->vba.NotEnoughLanesForMSO = true; + } + } + + for (i = 0; i < v->soc.num_states; ++i) { + mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] = false; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.BlendingAndTiming[k] == k + && dml32_RequiredDTBCLK(mode_lib->vba.RequiresDSC[i][k], + mode_lib->vba.PixelClockBackEnd[k], + mode_lib->vba.OutputFormat[k], + mode_lib->vba.OutputBppPerState[i][k], + mode_lib->vba.NumberOfDSCSlices[k], mode_lib->vba.HTotal[k], + mode_lib->vba.HActive[k], mode_lib->vba.AudioSampleRate[k], + mode_lib->vba.AudioSampleLayout[k]) + > mode_lib->vba.DTBCLKPerState[i]) { + mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] = true; + } + } + } + + for (i = 0; i < v->soc.num_states; ++i) { + mode_lib->vba.ODMCombine2To1SupportCheckOK[i] = true; + mode_lib->vba.ODMCombine4To1SupportCheckOK[i] = true; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.BlendingAndTiming[k] == k + && mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1 + && mode_lib->vba.Output[k] == dm_hdmi) { + mode_lib->vba.ODMCombine2To1SupportCheckOK[i] = false; + } + if (mode_lib->vba.BlendingAndTiming[k] == k + && mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1 + && (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_edp + || mode_lib->vba.Output[k] == dm_hdmi)) { + mode_lib->vba.ODMCombine4To1SupportCheckOK[i] = false; + } + } + } + + for (i = 0; i < v->soc.num_states; i++) { + mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = false; + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + if (mode_lib->vba.BlendingAndTiming[k] == k) { + if (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_dp2p0 + || mode_lib->vba.Output[k] == dm_edp) { + if (mode_lib->vba.OutputFormat[k] == dm_420) { + mode_lib->vba.DSCFormatFactor = 2; + } else if (mode_lib->vba.OutputFormat[k] == dm_444) { + mode_lib->vba.DSCFormatFactor = 1; + } else if (mode_lib->vba.OutputFormat[k] == dm_n422) { + mode_lib->vba.DSCFormatFactor = 2; + } else { + mode_lib->vba.DSCFormatFactor = 1; + } + if (mode_lib->vba.RequiresDSC[i][k] == true) { + if (mode_lib->vba.ODMCombineEnablePerState[i][k] + == dm_odm_combine_mode_4to1) { + if (mode_lib->vba.PixelClockBackEnd[k] / 12.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i]) + mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = true; + } else if (mode_lib->vba.ODMCombineEnablePerState[i][k] + == dm_odm_combine_mode_2to1) { + if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i]) + mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = true; + } else { + if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i]) + mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = true; + } + } + } + } + } + } + + /* Check DSC Unit and Slices Support */ + TotalDSCUnitsRequired = 0; + + for (i = 0; i < v->soc.num_states; ++i) { + mode_lib->vba.NotEnoughDSCUnits[i] = false; + mode_lib->vba.NotEnoughDSCSlices[i] = false; + TotalDSCUnitsRequired = 0; + mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i] = true; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.RequiresDSC[i][k] == true) { + if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) { + if (mode_lib->vba.HActive[k] + > 4 * mode_lib->vba.MaximumPixelsPerLinePerDSCUnit) + mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i] = false; + TotalDSCUnitsRequired = TotalDSCUnitsRequired + 4; + if (mode_lib->vba.NumberOfDSCSlices[k] > 16) + mode_lib->vba.NotEnoughDSCSlices[i] = true; + } else if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) { + if (mode_lib->vba.HActive[k] + > 2 * mode_lib->vba.MaximumPixelsPerLinePerDSCUnit) + mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i] = false; + TotalDSCUnitsRequired = TotalDSCUnitsRequired + 2; + if (mode_lib->vba.NumberOfDSCSlices[k] > 8) + mode_lib->vba.NotEnoughDSCSlices[i] = true; + } else { + if (mode_lib->vba.HActive[k] > mode_lib->vba.MaximumPixelsPerLinePerDSCUnit) + mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i] = false; + TotalDSCUnitsRequired = TotalDSCUnitsRequired + 1; + if (mode_lib->vba.NumberOfDSCSlices[k] > 4) + mode_lib->vba.NotEnoughDSCSlices[i] = true; + } + } + } + if (TotalDSCUnitsRequired > mode_lib->vba.NumberOfDSC) + mode_lib->vba.NotEnoughDSCUnits[i] = true; + } + + /*DSC Delay per state*/ + for (i = 0; i < v->soc.num_states; ++i) { + unsigned int m; + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + mode_lib->vba.DSCDelayPerState[i][k] = dml32_DSCDelayRequirement( + mode_lib->vba.RequiresDSC[i][k], mode_lib->vba.ODMCombineEnablePerState[i][k], + mode_lib->vba.DSCInputBitPerComponent[k], + mode_lib->vba.OutputBppPerState[i][k], mode_lib->vba.HActive[k], + mode_lib->vba.HTotal[k], mode_lib->vba.NumberOfDSCSlices[k], + mode_lib->vba.OutputFormat[k], mode_lib->vba.Output[k], + mode_lib->vba.PixelClock[k], mode_lib->vba.PixelClockBackEnd[k]); + } + + m = 0; + + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + for (m = 0; m <= mode_lib->vba.NumberOfActiveSurfaces - 1; m++) { + for (j = 0; j <= mode_lib->vba.NumberOfActiveSurfaces - 1; j++) { + if (mode_lib->vba.BlendingAndTiming[k] == m && + mode_lib->vba.RequiresDSC[i][m] == true) { + mode_lib->vba.DSCDelayPerState[i][k] = + mode_lib->vba.DSCDelayPerState[i][m]; + } + } + } + } + } + + //Calculate Swath, DET Configuration, DCFCLKDeepSleep + // + for (i = 0; i < (int) v->soc.num_states; ++i) { + for (j = 0; j <= 1; ++j) { + bool dummy_boolean_array[1][DC__NUM_DPP__MAX]; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + mode_lib->vba.RequiredDPPCLKThisState[k] = mode_lib->vba.RequiredDPPCLK[i][j][k]; + mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k]; + mode_lib->vba.ODMCombineEnableThisState[k] = + mode_lib->vba.ODMCombineEnablePerState[i][k]; + } + + dml32_CalculateSwathAndDETConfiguration( + mode_lib->vba.DETSizeOverride, + mode_lib->vba.UsesMALLForPStateChange, + mode_lib->vba.ConfigReturnBufferSizeInKByte, + mode_lib->vba.MaxTotalDETInKByte, + mode_lib->vba.MinCompressedBufferSizeInKByte, + false, /* ForceSingleDPP */ + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.nomDETInKByte, + mode_lib->vba.UseUnboundedRequesting, + mode_lib->vba.CompressedBufferSegmentSizeInkByteFinal, + mode_lib->vba.Output, + mode_lib->vba.ReadBandwidthLuma, + mode_lib->vba.ReadBandwidthChroma, + mode_lib->vba.MaximumSwathWidthLuma, + mode_lib->vba.MaximumSwathWidthChroma, + mode_lib->vba.SourceRotation, + mode_lib->vba.ViewportStationary, + mode_lib->vba.SourcePixelFormat, + mode_lib->vba.SurfaceTiling, + mode_lib->vba.ViewportWidth, + mode_lib->vba.ViewportHeight, + mode_lib->vba.ViewportXStartY, + mode_lib->vba.ViewportYStartY, + mode_lib->vba.ViewportXStartC, + mode_lib->vba.ViewportYStartC, + mode_lib->vba.SurfaceWidthY, + mode_lib->vba.SurfaceWidthC, + mode_lib->vba.SurfaceHeightY, + mode_lib->vba.SurfaceHeightC, + mode_lib->vba.Read256BlockHeightY, + mode_lib->vba.Read256BlockHeightC, + mode_lib->vba.Read256BlockWidthY, + mode_lib->vba.Read256BlockWidthC, + mode_lib->vba.ODMCombineEnableThisState, + mode_lib->vba.BlendingAndTiming, + mode_lib->vba.BytePerPixelY, + mode_lib->vba.BytePerPixelC, + mode_lib->vba.BytePerPixelInDETY, + mode_lib->vba.BytePerPixelInDETC, + mode_lib->vba.HActive, + mode_lib->vba.HRatio, + mode_lib->vba.HRatioChroma, + mode_lib->vba.NoOfDPPThisState, + /* Output */ + mode_lib->vba.swath_width_luma_ub_this_state, + mode_lib->vba.swath_width_chroma_ub_this_state, + mode_lib->vba.SwathWidthYThisState, + mode_lib->vba.SwathWidthCThisState, + mode_lib->vba.SwathHeightYThisState, + mode_lib->vba.SwathHeightCThisState, + mode_lib->vba.DETBufferSizeInKByteThisState, + mode_lib->vba.DETBufferSizeYThisState, + mode_lib->vba.DETBufferSizeCThisState, + &mode_lib->vba.UnboundedRequestEnabledThisState, + &mode_lib->vba.CompressedBufferSizeInkByteThisState, + dummy_boolean_array[0], + &mode_lib->vba.ViewportSizeSupport[i][j]); + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + mode_lib->vba.swath_width_luma_ub_all_states[i][j][k] = + mode_lib->vba.swath_width_luma_ub_this_state[k]; + mode_lib->vba.swath_width_chroma_ub_all_states[i][j][k] = + mode_lib->vba.swath_width_chroma_ub_this_state[k]; + mode_lib->vba.SwathWidthYAllStates[i][j][k] = mode_lib->vba.SwathWidthYThisState[k]; + mode_lib->vba.SwathWidthCAllStates[i][j][k] = mode_lib->vba.SwathWidthCThisState[k]; + mode_lib->vba.SwathHeightYAllStates[i][j][k] = mode_lib->vba.SwathHeightYThisState[k]; + mode_lib->vba.SwathHeightCAllStates[i][j][k] = mode_lib->vba.SwathHeightCThisState[k]; + mode_lib->vba.UnboundedRequestEnabledAllStates[i][j] = + mode_lib->vba.UnboundedRequestEnabledThisState; + mode_lib->vba.CompressedBufferSizeInkByteAllStates[i][j] = + mode_lib->vba.CompressedBufferSizeInkByteThisState; + mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k] = + mode_lib->vba.DETBufferSizeInKByteThisState[k]; + mode_lib->vba.DETBufferSizeYAllStates[i][j][k] = + mode_lib->vba.DETBufferSizeYThisState[k]; + mode_lib->vba.DETBufferSizeCAllStates[i][j][k] = + mode_lib->vba.DETBufferSizeCThisState[k]; + } + } + } + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + mode_lib->vba.cursor_bw[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] + * mode_lib->vba.CursorBPP[k][0] / 8.0 + / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; + } + + dml32_CalculateSurfaceSizeInMall( + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.MALLAllocatedForDCNFinal, + mode_lib->vba.UseMALLForStaticScreen, + mode_lib->vba.DCCEnable, + mode_lib->vba.ViewportStationary, + mode_lib->vba.ViewportXStartY, + mode_lib->vba.ViewportYStartY, + mode_lib->vba.ViewportXStartC, + mode_lib->vba.ViewportYStartC, + mode_lib->vba.ViewportWidth, + mode_lib->vba.ViewportHeight, + mode_lib->vba.BytePerPixelY, + mode_lib->vba.ViewportWidthChroma, + mode_lib->vba.ViewportHeightChroma, + mode_lib->vba.BytePerPixelC, + mode_lib->vba.SurfaceWidthY, + mode_lib->vba.SurfaceWidthC, + mode_lib->vba.SurfaceHeightY, + mode_lib->vba.SurfaceHeightC, + mode_lib->vba.Read256BlockWidthY, + mode_lib->vba.Read256BlockWidthC, + mode_lib->vba.Read256BlockHeightY, + mode_lib->vba.Read256BlockHeightC, + mode_lib->vba.MicroTileWidthY, + mode_lib->vba.MicroTileWidthC, + mode_lib->vba.MicroTileHeightY, + mode_lib->vba.MicroTileHeightC, + + /* Output */ + mode_lib->vba.SurfaceSizeInMALL, + &mode_lib->vba.ExceededMALLSize); + + for (i = 0; i < v->soc.num_states; i++) { + for (j = 0; j < 2; j++) { + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + mode_lib->vba.swath_width_luma_ub_this_state[k] = + mode_lib->vba.swath_width_luma_ub_all_states[i][j][k]; + mode_lib->vba.swath_width_chroma_ub_this_state[k] = + mode_lib->vba.swath_width_chroma_ub_all_states[i][j][k]; + mode_lib->vba.SwathWidthYThisState[k] = mode_lib->vba.SwathWidthYAllStates[i][j][k]; + mode_lib->vba.SwathWidthCThisState[k] = mode_lib->vba.SwathWidthCAllStates[i][j][k]; + mode_lib->vba.SwathHeightYThisState[k] = mode_lib->vba.SwathHeightYAllStates[i][j][k]; + mode_lib->vba.SwathHeightCThisState[k] = mode_lib->vba.SwathHeightCAllStates[i][j][k]; + mode_lib->vba.DETBufferSizeInKByteThisState[k] = + mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k]; + mode_lib->vba.DETBufferSizeYThisState[k] = + mode_lib->vba.DETBufferSizeYAllStates[i][j][k]; + mode_lib->vba.DETBufferSizeCThisState[k] = + mode_lib->vba.DETBufferSizeCAllStates[i][j][k]; + mode_lib->vba.RequiredDPPCLKThisState[k] = mode_lib->vba.RequiredDPPCLK[i][j][k]; + mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k]; + } + + mode_lib->vba.TotalNumberOfDCCActiveDPP[i][j] = 0; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.DCCEnable[k] == true) { + mode_lib->vba.TotalNumberOfDCCActiveDPP[i][j] = + mode_lib->vba.TotalNumberOfDCCActiveDPP[i][j] + + mode_lib->vba.NoOfDPP[i][j][k]; + } + } + + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].PixelClock = mode_lib->vba.PixelClock[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DPPPerSurface = mode_lib->vba.NoOfDPP[i][j][k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SourceRotation = mode_lib->vba.SourceRotation[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportHeight = mode_lib->vba.ViewportHeight[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportHeightChroma = mode_lib->vba.ViewportHeightChroma[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidth256BytesY = mode_lib->vba.Read256BlockWidthY[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeight256BytesY = mode_lib->vba.Read256BlockHeightY[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidth256BytesC = mode_lib->vba.Read256BlockWidthC[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeight256BytesC = mode_lib->vba.Read256BlockHeightC[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthY = mode_lib->vba.MicroTileWidthY[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightY = mode_lib->vba.MicroTileHeightY[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthC = mode_lib->vba.MicroTileWidthC[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightC = mode_lib->vba.MicroTileHeightC[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].HTotal = mode_lib->vba.HTotal[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCEnable = mode_lib->vba.DCCEnable[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SurfaceTiling = mode_lib->vba.SurfaceTiling[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BytePerPixelY = mode_lib->vba.BytePerPixelY[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BytePerPixelC = mode_lib->vba.BytePerPixelC[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ProgressiveToInterlaceUnitInOPP = + mode_lib->vba.ProgressiveToInterlaceUnitInOPP; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VRatio = mode_lib->vba.VRatio[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VRatioChroma = mode_lib->vba.VRatioChroma[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VTaps = mode_lib->vba.vtaps[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VTapsChroma = mode_lib->vba.VTAPsChroma[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].PitchY = mode_lib->vba.PitchY[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCMetaPitchY = mode_lib->vba.DCCMetaPitchY[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].PitchC = mode_lib->vba.PitchC[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCMetaPitchC = mode_lib->vba.DCCMetaPitchC[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportStationary = mode_lib->vba.ViewportStationary[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportXStart = mode_lib->vba.ViewportXStartY[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportYStart = mode_lib->vba.ViewportYStartY[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportXStartC = mode_lib->vba.ViewportXStartC[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportYStartC = mode_lib->vba.ViewportYStartC[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->vba.ForceOneRowForFrame[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SwathHeightY = mode_lib->vba.SwathHeightYThisState[k]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SwathHeightC = mode_lib->vba.SwathHeightCThisState[k]; + } + + { + bool dummy_boolean_array[2][DC__NUM_DPP__MAX]; + unsigned int dummy_integer_array[22][DC__NUM_DPP__MAX]; + + dml32_CalculateVMRowAndSwath( + mode_lib->vba.NumberOfActiveSurfaces, + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters, + mode_lib->vba.SurfaceSizeInMALL, + mode_lib->vba.PTEBufferSizeInRequestsLuma, + mode_lib->vba.PTEBufferSizeInRequestsChroma, + mode_lib->vba.DCCMetaBufferSizeBytes, + mode_lib->vba.UseMALLForStaticScreen, + mode_lib->vba.UsesMALLForPStateChange, + mode_lib->vba.MALLAllocatedForDCNFinal, + mode_lib->vba.SwathWidthYThisState, + mode_lib->vba.SwathWidthCThisState, + mode_lib->vba.GPUVMEnable, + mode_lib->vba.HostVMEnable, + mode_lib->vba.HostVMMaxNonCachedPageTableLevels, + mode_lib->vba.GPUVMMaxPageTableLevels, + mode_lib->vba.GPUVMMinPageSizeKBytes, + mode_lib->vba.HostVMMinPageSize, + + /* Output */ + mode_lib->vba.PTEBufferSizeNotExceededPerState, + mode_lib->vba.DCCMetaBufferSizeNotExceededPerState, + dummy_integer_array[0], + dummy_integer_array[1], + mode_lib->vba.dpte_row_height, + mode_lib->vba.dpte_row_height_chroma, + dummy_integer_array[2], + dummy_integer_array[3], + dummy_integer_array[4], + dummy_integer_array[5], + dummy_integer_array[6], + dummy_integer_array[7], + dummy_integer_array[8], + dummy_integer_array[9], + mode_lib->vba.meta_row_height, + mode_lib->vba.meta_row_height_chroma, + dummy_integer_array[10], + mode_lib->vba.dpte_group_bytes, + dummy_integer_array[11], + dummy_integer_array[12], + dummy_integer_array[13], + dummy_integer_array[14], + dummy_integer_array[15], + dummy_integer_array[16], + dummy_integer_array[17], + dummy_integer_array[18], + dummy_integer_array[19], + dummy_integer_array[20], + mode_lib->vba.PrefetchLinesYThisState, + mode_lib->vba.PrefetchLinesCThisState, + mode_lib->vba.PrefillY, + mode_lib->vba.PrefillC, + mode_lib->vba.MaxNumSwY, + mode_lib->vba.MaxNumSwC, + mode_lib->vba.meta_row_bandwidth_this_state, + mode_lib->vba.dpte_row_bandwidth_this_state, + mode_lib->vba.DPTEBytesPerRowThisState, + mode_lib->vba.PDEAndMetaPTEBytesPerFrameThisState, + mode_lib->vba.MetaRowBytesThisState, + mode_lib->vba.use_one_row_for_frame_this_state, + mode_lib->vba.use_one_row_for_frame_flip_this_state, + dummy_boolean_array[0], // Boolean UsesMALLForStaticScreen[] + dummy_boolean_array[1], // Boolean PTE_BUFFER_MODE[] + dummy_integer_array[21]); // Long BIGK_FRAGMENT_SIZE[] + } + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + mode_lib->vba.PrefetchLinesY[i][j][k] = mode_lib->vba.PrefetchLinesYThisState[k]; + mode_lib->vba.PrefetchLinesC[i][j][k] = mode_lib->vba.PrefetchLinesCThisState[k]; + mode_lib->vba.meta_row_bandwidth[i][j][k] = + mode_lib->vba.meta_row_bandwidth_this_state[k]; + mode_lib->vba.dpte_row_bandwidth[i][j][k] = + mode_lib->vba.dpte_row_bandwidth_this_state[k]; + mode_lib->vba.DPTEBytesPerRow[i][j][k] = mode_lib->vba.DPTEBytesPerRowThisState[k]; + mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k] = + mode_lib->vba.PDEAndMetaPTEBytesPerFrameThisState[k]; + mode_lib->vba.MetaRowBytes[i][j][k] = mode_lib->vba.MetaRowBytesThisState[k]; + mode_lib->vba.use_one_row_for_frame[i][j][k] = + mode_lib->vba.use_one_row_for_frame_this_state[k]; + mode_lib->vba.use_one_row_for_frame_flip[i][j][k] = + mode_lib->vba.use_one_row_for_frame_flip_this_state[k]; + } + + mode_lib->vba.PTEBufferSizeNotExceeded[i][j] = true; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.PTEBufferSizeNotExceededPerState[k] == false) + mode_lib->vba.PTEBufferSizeNotExceeded[i][j] = false; + } + + mode_lib->vba.DCCMetaBufferSizeNotExceeded[i][j] = true; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.DCCMetaBufferSizeNotExceededPerState[k] == false) + mode_lib->vba.DCCMetaBufferSizeNotExceeded[i][j] = false; + } + + mode_lib->vba.UrgLatency[i] = dml32_CalculateUrgentLatency( + mode_lib->vba.UrgentLatencyPixelDataOnly, + mode_lib->vba.UrgentLatencyPixelMixedWithVMData, + mode_lib->vba.UrgentLatencyVMDataOnly, mode_lib->vba.DoUrgentLatencyAdjustment, + mode_lib->vba.UrgentLatencyAdjustmentFabricClockComponent, + mode_lib->vba.UrgentLatencyAdjustmentFabricClockReference, + mode_lib->vba.FabricClockPerState[i]); + + //bool NotUrgentLatencyHiding[DC__NUM_DPP__MAX]; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + dml32_CalculateUrgentBurstFactor( + mode_lib->vba.UsesMALLForPStateChange[k], + mode_lib->vba.swath_width_luma_ub_this_state[k], + mode_lib->vba.swath_width_chroma_ub_this_state[k], + mode_lib->vba.SwathHeightYThisState[k], + mode_lib->vba.SwathHeightCThisState[k], + (double) mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], + mode_lib->vba.UrgLatency[i], + mode_lib->vba.CursorBufferSize, + mode_lib->vba.CursorWidth[k][0], + mode_lib->vba.CursorBPP[k][0], + mode_lib->vba.VRatio[k], + mode_lib->vba.VRatioChroma[k], + mode_lib->vba.BytePerPixelInDETY[k], + mode_lib->vba.BytePerPixelInDETC[k], + mode_lib->vba.DETBufferSizeYThisState[k], + mode_lib->vba.DETBufferSizeCThisState[k], + /* Output */ + &mode_lib->vba.UrgentBurstFactorCursor[k], + &mode_lib->vba.UrgentBurstFactorLuma[k], + &mode_lib->vba.UrgentBurstFactorChroma[k], + &mode_lib->vba.NoUrgentLatencyHiding[k]); + } + + dml32_CalculateDCFCLKDeepSleep( + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.BytePerPixelY, + mode_lib->vba.BytePerPixelC, + mode_lib->vba.VRatio, + mode_lib->vba.VRatioChroma, + mode_lib->vba.SwathWidthYThisState, + mode_lib->vba.SwathWidthCThisState, + mode_lib->vba.NoOfDPPThisState, + mode_lib->vba.HRatio, + mode_lib->vba.HRatioChroma, + mode_lib->vba.PixelClock, + mode_lib->vba.PSCL_FACTOR, + mode_lib->vba.PSCL_FACTOR_CHROMA, + mode_lib->vba.RequiredDPPCLKThisState, + mode_lib->vba.ReadBandwidthLuma, + mode_lib->vba.ReadBandwidthChroma, + mode_lib->vba.ReturnBusWidth, + + /* Output */ + &mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j]); + } + } + + m = 0; + + //Calculate Return BW + for (i = 0; i < (int) v->soc.num_states; ++i) { + for (j = 0; j <= 1; ++j) { + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + if (mode_lib->vba.BlendingAndTiming[k] == k) { + if (mode_lib->vba.WritebackEnable[k] == true) { + mode_lib->vba.WritebackDelayTime[k] = + mode_lib->vba.WritebackLatency + + dml32_CalculateWriteBackDelay( + mode_lib->vba.WritebackPixelFormat[k], + mode_lib->vba.WritebackHRatio[k], + mode_lib->vba.WritebackVRatio[k], + mode_lib->vba.WritebackVTaps[k], + mode_lib->vba.WritebackDestinationWidth[k], + mode_lib->vba.WritebackDestinationHeight[k], + mode_lib->vba.WritebackSourceHeight[k], + mode_lib->vba.HTotal[k]) + / mode_lib->vba.RequiredDISPCLK[i][j]; + } else { + mode_lib->vba.WritebackDelayTime[k] = 0.0; + } + for (m = 0; m <= mode_lib->vba.NumberOfActiveSurfaces - 1; m++) { + if (mode_lib->vba.BlendingAndTiming[m] + == k && mode_lib->vba.WritebackEnable[m] == true) { + mode_lib->vba.WritebackDelayTime[k] = + dml_max(mode_lib->vba.WritebackDelayTime[k], + mode_lib->vba.WritebackLatency + + dml32_CalculateWriteBackDelay( + mode_lib->vba.WritebackPixelFormat[m], + mode_lib->vba.WritebackHRatio[m], + mode_lib->vba.WritebackVRatio[m], + mode_lib->vba.WritebackVTaps[m], + mode_lib->vba.WritebackDestinationWidth[m], + mode_lib->vba.WritebackDestinationHeight[m], + mode_lib->vba.WritebackSourceHeight[m], + mode_lib->vba.HTotal[m]) / + mode_lib->vba.RequiredDISPCLK[i][j]); + } + } + } + } + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + for (m = 0; m <= mode_lib->vba.NumberOfActiveSurfaces - 1; m++) { + if (mode_lib->vba.BlendingAndTiming[k] == m) { + mode_lib->vba.WritebackDelayTime[k] = + mode_lib->vba.WritebackDelayTime[m]; + } + } + } + mode_lib->vba.MaxMaxVStartup[i][j] = 0; + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + mode_lib->vba.MaximumVStartup[i][j][k] = ((mode_lib->vba.Interlace[k] && + !mode_lib->vba.ProgressiveToInterlaceUnitInOPP) ? + dml_floor((mode_lib->vba.VTotal[k] - + mode_lib->vba.VActive[k]) / 2.0, 1.0) : + mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]) + - dml_max(1.0, dml_ceil(1.0 * + mode_lib->vba.WritebackDelayTime[k] / + (mode_lib->vba.HTotal[k] / + mode_lib->vba.PixelClock[k]), 1.0)); + + // Clamp to max OTG vstartup register limit + if (mode_lib->vba.MaximumVStartup[i][j][k] > 1023) + mode_lib->vba.MaximumVStartup[i][j][k] = 1023; + + mode_lib->vba.MaxMaxVStartup[i][j] = dml_max(mode_lib->vba.MaxMaxVStartup[i][j], + mode_lib->vba.MaximumVStartup[i][j][k]); + } + } + } + + ReorderingBytes = mode_lib->vba.NumberOfChannels + * dml_max3(mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly, + mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, + mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly); + + dml32_CalculateMinAndMaxPrefetchMode(mode_lib->vba.AllowForPStateChangeOrStutterInVBlankFinal, + &mode_lib->vba.MinPrefetchMode, + &mode_lib->vba.MaxPrefetchMode); + + for (i = 0; i < (int) v->soc.num_states; ++i) { + for (j = 0; j <= 1; ++j) + mode_lib->vba.DCFCLKState[i][j] = mode_lib->vba.DCFCLKPerState[i]; + } + + /* Immediate Flip and MALL parameters */ + mode_lib->vba.ImmediateFlipRequiredFinal = false; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + mode_lib->vba.ImmediateFlipRequiredFinal = mode_lib->vba.ImmediateFlipRequiredFinal + || (mode_lib->vba.ImmediateFlipRequirement[k] == dm_immediate_flip_required); + } + + mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified = false; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified = + mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified + || ((mode_lib->vba.ImmediateFlipRequirement[k] + != dm_immediate_flip_required) + && (mode_lib->vba.ImmediateFlipRequirement[k] + != dm_immediate_flip_not_required)); + } + mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified = + mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified + && mode_lib->vba.ImmediateFlipRequiredFinal; + + mode_lib->vba.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = false; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + mode_lib->vba.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = + mode_lib->vba.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe || + ((mode_lib->vba.HostVMEnable == true || mode_lib->vba.ImmediateFlipRequirement[k] != + dm_immediate_flip_not_required) && + (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame || + mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe)); + } + + mode_lib->vba.InvalidCombinationOfMALLUseForPStateAndStaticScreen = false; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + mode_lib->vba.InvalidCombinationOfMALLUseForPStateAndStaticScreen = + mode_lib->vba.InvalidCombinationOfMALLUseForPStateAndStaticScreen + || ((mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_enable + || mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_optimize) + && (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe)) + || ((mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_disable + || mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_optimize) + && (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame)); + } + + FullFrameMALLPStateMethod = false; + SubViewportMALLPStateMethod = false; + PhantomPipeMALLPStateMethod = false; + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame) + FullFrameMALLPStateMethod = true; + if (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport) + SubViewportMALLPStateMethod = true; + if (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) + PhantomPipeMALLPStateMethod = true; + } + mode_lib->vba.InvalidCombinationOfMALLUseForPState = (SubViewportMALLPStateMethod + != PhantomPipeMALLPStateMethod) || (SubViewportMALLPStateMethod && FullFrameMALLPStateMethod); + + if (mode_lib->vba.UseMinimumRequiredDCFCLK == true) { + dml32_UseMinimumDCFCLK( + mode_lib->vba.UsesMALLForPStateChange, + mode_lib->vba.DRRDisplay, + mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal, + mode_lib->vba.MaxInterDCNTileRepeaters, + mode_lib->vba.MaxPrefetchMode, + mode_lib->vba.DRAMClockChangeLatency, + mode_lib->vba.FCLKChangeLatency, + mode_lib->vba.SREnterPlusExitTime, + mode_lib->vba.ReturnBusWidth, + mode_lib->vba.RoundTripPingLatencyCycles, + ReorderingBytes, + mode_lib->vba.PixelChunkSizeInKByte, + mode_lib->vba.MetaChunkSize, + mode_lib->vba.GPUVMEnable, + mode_lib->vba.GPUVMMaxPageTableLevels, + mode_lib->vba.HostVMEnable, + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.HostVMMinPageSize, + mode_lib->vba.HostVMMaxNonCachedPageTableLevels, + mode_lib->vba.DynamicMetadataVMEnabled, + mode_lib->vba.ImmediateFlipRequiredFinal, + mode_lib->vba.ProgressiveToInterlaceUnitInOPP, + mode_lib->vba.MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation, + mode_lib->vba.PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency, + mode_lib->vba.VTotal, + mode_lib->vba.VActive, + mode_lib->vba.DynamicMetadataTransmittedBytes, + mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired, + mode_lib->vba.Interlace, + mode_lib->vba.RequiredDPPCLK, + mode_lib->vba.RequiredDISPCLK, + mode_lib->vba.UrgLatency, + mode_lib->vba.NoOfDPP, + mode_lib->vba.ProjectedDCFCLKDeepSleep, + mode_lib->vba.MaximumVStartup, + mode_lib->vba.TotalNumberOfActiveDPP, + mode_lib->vba.TotalNumberOfDCCActiveDPP, + mode_lib->vba.dpte_group_bytes, + mode_lib->vba.PrefetchLinesY, + mode_lib->vba.PrefetchLinesC, + mode_lib->vba.swath_width_luma_ub_all_states, + mode_lib->vba.swath_width_chroma_ub_all_states, + mode_lib->vba.BytePerPixelY, + mode_lib->vba.BytePerPixelC, + mode_lib->vba.HTotal, + mode_lib->vba.PixelClock, + mode_lib->vba.PDEAndMetaPTEBytesPerFrame, + mode_lib->vba.DPTEBytesPerRow, + mode_lib->vba.MetaRowBytes, + mode_lib->vba.DynamicMetadataEnable, + mode_lib->vba.ReadBandwidthLuma, + mode_lib->vba.ReadBandwidthChroma, + mode_lib->vba.DCFCLKPerState, + + /* Output */ + mode_lib->vba.DCFCLKState); + } // UseMinimumRequiredDCFCLK == true + + for (i = 0; i < (int) v->soc.num_states; ++i) { + for (j = 0; j <= 1; ++j) { + mode_lib->vba.ReturnBWPerState[i][j] = dml32_get_return_bw_mbps(&mode_lib->vba.soc, i, + mode_lib->vba.HostVMEnable, mode_lib->vba.DCFCLKState[i][j], + mode_lib->vba.FabricClockPerState[i], mode_lib->vba.DRAMSpeedPerState[i]); + } + } + + //Re-ordering Buffer Support Check + for (i = 0; i < (int) v->soc.num_states; ++i) { + for (j = 0; j <= 1; ++j) { + if ((mode_lib->vba.ROBBufferSizeInKByte - mode_lib->vba.PixelChunkSizeInKByte) * 1024 + / mode_lib->vba.ReturnBWPerState[i][j] + > (mode_lib->vba.RoundTripPingLatencyCycles + 32) + / mode_lib->vba.DCFCLKState[i][j] + + ReorderingBytes / mode_lib->vba.ReturnBWPerState[i][j]) { + mode_lib->vba.ROBSupport[i][j] = true; + } else { + mode_lib->vba.ROBSupport[i][j] = false; + } + } + } + + //Vertical Active BW support check + MaxTotalVActiveRDBandwidth = 0; + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + mode_lib->vba.ReadBandwidthLuma[k] + + mode_lib->vba.ReadBandwidthChroma[k]; + } + + for (i = 0; i < (int) v->soc.num_states; ++i) { + for (j = 0; j <= 1; ++j) { + mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i][j] = + dml_min3(mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLKState[i][j] + * mode_lib->vba.MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation / 100, + mode_lib->vba.FabricClockPerState[i] + * mode_lib->vba.FabricDatapathToDCNDataReturn + * mode_lib->vba.MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation / 100, + mode_lib->vba.DRAMSpeedPerState[i] + * mode_lib->vba.NumberOfChannels + * mode_lib->vba.DRAMChannelWidth + * (i < 2 ? mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE : mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation) / 100); + + if (MaxTotalVActiveRDBandwidth + <= mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i][j]) { + mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][j] = true; + } else { + mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][j] = false; + } + } + } + + /* Prefetch Check */ + + for (i = 0; i < (int) v->soc.num_states; ++i) { + for (j = 0; j <= 1; ++j) { + double VMDataOnlyReturnBWPerState; + double HostVMInefficiencyFactor; + unsigned int NextPrefetchModeState; + + mode_lib->vba.TimeCalc = 24 / mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j]; + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k]; + mode_lib->vba.swath_width_luma_ub_this_state[k] = + mode_lib->vba.swath_width_luma_ub_all_states[i][j][k]; + mode_lib->vba.swath_width_chroma_ub_this_state[k] = + mode_lib->vba.swath_width_chroma_ub_all_states[i][j][k]; + mode_lib->vba.SwathWidthYThisState[k] = mode_lib->vba.SwathWidthYAllStates[i][j][k]; + mode_lib->vba.SwathWidthCThisState[k] = mode_lib->vba.SwathWidthCAllStates[i][j][k]; + mode_lib->vba.SwathHeightYThisState[k] = mode_lib->vba.SwathHeightYAllStates[i][j][k]; + mode_lib->vba.SwathHeightCThisState[k] = mode_lib->vba.SwathHeightCAllStates[i][j][k]; + mode_lib->vba.UnboundedRequestEnabledThisState = + mode_lib->vba.UnboundedRequestEnabledAllStates[i][j]; + mode_lib->vba.CompressedBufferSizeInkByteThisState = + mode_lib->vba.CompressedBufferSizeInkByteAllStates[i][j]; + mode_lib->vba.DETBufferSizeInKByteThisState[k] = + mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k]; + mode_lib->vba.DETBufferSizeYThisState[k] = + mode_lib->vba.DETBufferSizeYAllStates[i][j][k]; + mode_lib->vba.DETBufferSizeCThisState[k] = + mode_lib->vba.DETBufferSizeCAllStates[i][j][k]; + } + + mode_lib->vba.VActiveBandwithSupport[i][j] = dml32_CalculateVActiveBandwithSupport( + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.ReturnBWPerState[i][j], + mode_lib->vba.NoUrgentLatencyHiding, + mode_lib->vba.ReadBandwidthLuma, + mode_lib->vba.ReadBandwidthChroma, + mode_lib->vba.cursor_bw, + mode_lib->vba.meta_row_bandwidth_this_state, + mode_lib->vba.dpte_row_bandwidth_this_state, + mode_lib->vba.NoOfDPPThisState, + mode_lib->vba.UrgentBurstFactorLuma, + mode_lib->vba.UrgentBurstFactorChroma, + mode_lib->vba.UrgentBurstFactorCursor); + + VMDataOnlyReturnBWPerState = dml32_get_return_bw_mbps_vm_only(&mode_lib->vba.soc, i, + mode_lib->vba.DCFCLKState[i][j], mode_lib->vba.FabricClockPerState[i], + mode_lib->vba.DRAMSpeedPerState[i]); + HostVMInefficiencyFactor = 1; + + if (mode_lib->vba.GPUVMEnable && mode_lib->vba.HostVMEnable) + HostVMInefficiencyFactor = mode_lib->vba.ReturnBWPerState[i][j] + / VMDataOnlyReturnBWPerState; + + mode_lib->vba.ExtraLatency = dml32_CalculateExtraLatency( + mode_lib->vba.RoundTripPingLatencyCycles, ReorderingBytes, + mode_lib->vba.DCFCLKState[i][j], mode_lib->vba.TotalNumberOfActiveDPP[i][j], + mode_lib->vba.PixelChunkSizeInKByte, + mode_lib->vba.TotalNumberOfDCCActiveDPP[i][j], mode_lib->vba.MetaChunkSize, + mode_lib->vba.ReturnBWPerState[i][j], mode_lib->vba.GPUVMEnable, + mode_lib->vba.HostVMEnable, mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.NoOfDPPThisState, mode_lib->vba.dpte_group_bytes, + HostVMInefficiencyFactor, mode_lib->vba.HostVMMinPageSize, + mode_lib->vba.HostVMMaxNonCachedPageTableLevels); + + NextPrefetchModeState = mode_lib->vba.MinPrefetchMode; + + mode_lib->vba.NextMaxVStartup = mode_lib->vba.MaxMaxVStartup[i][j]; + + do { + mode_lib->vba.PrefetchModePerState[i][j] = NextPrefetchModeState; + mode_lib->vba.MaxVStartup = mode_lib->vba.NextMaxVStartup; + + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + DmlPipe myPipe; + unsigned int dummy_integer; + + mode_lib->vba.TWait = dml32_CalculateTWait( + mode_lib->vba.PrefetchModePerState[i][j], + mode_lib->vba.UsesMALLForPStateChange[k], + mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal, + mode_lib->vba.DRRDisplay[k], + mode_lib->vba.DRAMClockChangeLatency, + mode_lib->vba.FCLKChangeLatency, mode_lib->vba.UrgLatency[i], + mode_lib->vba.SREnterPlusExitTime); + + myPipe.Dppclk = mode_lib->vba.RequiredDPPCLK[i][j][k]; + myPipe.Dispclk = mode_lib->vba.RequiredDISPCLK[i][j]; + myPipe.PixelClock = mode_lib->vba.PixelClock[k]; + myPipe.DCFClkDeepSleep = mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j]; + myPipe.DPPPerSurface = mode_lib->vba.NoOfDPP[i][j][k]; + myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k]; + myPipe.SourceRotation = mode_lib->vba.SourceRotation[k]; + myPipe.BlockWidth256BytesY = mode_lib->vba.Read256BlockWidthY[k]; + myPipe.BlockHeight256BytesY = mode_lib->vba.Read256BlockHeightY[k]; + myPipe.BlockWidth256BytesC = mode_lib->vba.Read256BlockWidthC[k]; + myPipe.BlockHeight256BytesC = mode_lib->vba.Read256BlockHeightC[k]; + myPipe.InterlaceEnable = mode_lib->vba.Interlace[k]; + myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k]; + myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]; + myPipe.HTotal = mode_lib->vba.HTotal[k]; + myPipe.HActive = mode_lib->vba.HActive[k]; + myPipe.DCCEnable = mode_lib->vba.DCCEnable[k]; + myPipe.ODMMode = mode_lib->vba.ODMCombineEnablePerState[i][k]; + myPipe.SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k]; + myPipe.BytePerPixelY = mode_lib->vba.BytePerPixelY[k]; + myPipe.BytePerPixelC = mode_lib->vba.BytePerPixelC[k]; + myPipe.ProgressiveToInterlaceUnitInOPP = + mode_lib->vba.ProgressiveToInterlaceUnitInOPP; + + mode_lib->vba.NoTimeForPrefetch[i][j][k] = + dml32_CalculatePrefetchSchedule( + HostVMInefficiencyFactor, + &myPipe, + mode_lib->vba.DSCDelayPerState[i][k], + mode_lib->vba.DPPCLKDelaySubtotal + + mode_lib->vba.DPPCLKDelayCNVCFormater, + mode_lib->vba.DPPCLKDelaySCL, + mode_lib->vba.DPPCLKDelaySCLLBOnly, + mode_lib->vba.DPPCLKDelayCNVCCursor, + mode_lib->vba.DISPCLKDelaySubtotal, + mode_lib->vba.SwathWidthYThisState[k] / + mode_lib->vba.HRatio[k], + mode_lib->vba.OutputFormat[k], + mode_lib->vba.MaxInterDCNTileRepeaters, + dml_min(mode_lib->vba.MaxVStartup, + mode_lib->vba.MaximumVStartup[i][j][k]), + mode_lib->vba.MaximumVStartup[i][j][k], + mode_lib->vba.GPUVMMaxPageTableLevels, + mode_lib->vba.GPUVMEnable, mode_lib->vba.HostVMEnable, + mode_lib->vba.HostVMMaxNonCachedPageTableLevels, + mode_lib->vba.HostVMMinPageSize, + mode_lib->vba.DynamicMetadataEnable[k], + mode_lib->vba.DynamicMetadataVMEnabled, + mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k], + mode_lib->vba.DynamicMetadataTransmittedBytes[k], + mode_lib->vba.UrgLatency[i], + mode_lib->vba.ExtraLatency, + mode_lib->vba.TimeCalc, + mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k], + mode_lib->vba.MetaRowBytes[i][j][k], + mode_lib->vba.DPTEBytesPerRow[i][j][k], + mode_lib->vba.PrefetchLinesY[i][j][k], + mode_lib->vba.SwathWidthYThisState[k], + mode_lib->vba.PrefillY[k], + mode_lib->vba.MaxNumSwY[k], + mode_lib->vba.PrefetchLinesC[i][j][k], + mode_lib->vba.SwathWidthCThisState[k], + mode_lib->vba.PrefillC[k], + mode_lib->vba.MaxNumSwC[k], + mode_lib->vba.swath_width_luma_ub_this_state[k], + mode_lib->vba.swath_width_chroma_ub_this_state[k], + mode_lib->vba.SwathHeightYThisState[k], + mode_lib->vba.SwathHeightCThisState[k], mode_lib->vba.TWait, + + /* Output */ + &DSTXAfterScaler[k], + &DSTYAfterScaler[k], + &mode_lib->vba.LineTimesForPrefetch[k], + &mode_lib->vba.PrefetchBW[k], + &mode_lib->vba.LinesForMetaPTE[k], + &mode_lib->vba.LinesForMetaAndDPTERow[k], + &mode_lib->vba.VRatioPreY[i][j][k], + &mode_lib->vba.VRatioPreC[i][j][k], + &mode_lib->vba.RequiredPrefetchPixelDataBWLuma[0][0][k], + &mode_lib->vba.RequiredPrefetchPixelDataBWChroma[0][0][k], + &mode_lib->vba.NoTimeForDynamicMetadata[i][j][k], + &mode_lib->vba.Tno_bw[k], + &mode_lib->vba.prefetch_vmrow_bw[k], + &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[0], // double *Tdmdl_vm + &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[1], // double *Tdmdl + &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[2], // double *TSetup + &dummy_integer, // unsigned int *VUpdateOffsetPix + &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[3], // unsigned int *VUpdateWidthPix + &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[4]); // unsigned int *VReadyOffsetPix + } + + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + dml32_CalculateUrgentBurstFactor( + mode_lib->vba.UsesMALLForPStateChange[k], + mode_lib->vba.swath_width_luma_ub_this_state[k], + mode_lib->vba.swath_width_chroma_ub_this_state[k], + mode_lib->vba.SwathHeightYThisState[k], + mode_lib->vba.SwathHeightCThisState[k], + mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], + mode_lib->vba.UrgLatency[i], mode_lib->vba.CursorBufferSize, + mode_lib->vba.CursorWidth[k][0], mode_lib->vba.CursorBPP[k][0], + mode_lib->vba.VRatioPreY[i][j][k], + mode_lib->vba.VRatioPreC[i][j][k], + mode_lib->vba.BytePerPixelInDETY[k], + mode_lib->vba.BytePerPixelInDETC[k], + mode_lib->vba.DETBufferSizeYThisState[k], + mode_lib->vba.DETBufferSizeCThisState[k], + /* Output */ + &mode_lib->vba.UrgentBurstFactorCursorPre[k], + &mode_lib->vba.UrgentBurstFactorLumaPre[k], + &mode_lib->vba.UrgentBurstFactorChroma[k], + &mode_lib->vba.NotUrgentLatencyHidingPre[k]); + } + + { + double dummy_single[2]; + dml32_CalculatePrefetchBandwithSupport( + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.ReturnBWPerState[i][j], + mode_lib->vba.NotUrgentLatencyHidingPre, + mode_lib->vba.ReadBandwidthLuma, + mode_lib->vba.ReadBandwidthChroma, + mode_lib->vba.RequiredPrefetchPixelDataBWLuma[0][0], + mode_lib->vba.RequiredPrefetchPixelDataBWChroma[0][0], + mode_lib->vba.cursor_bw, + mode_lib->vba.meta_row_bandwidth_this_state, + mode_lib->vba.dpte_row_bandwidth_this_state, + mode_lib->vba.cursor_bw_pre, + mode_lib->vba.prefetch_vmrow_bw, + mode_lib->vba.NoOfDPPThisState, + mode_lib->vba.UrgentBurstFactorLuma, + mode_lib->vba.UrgentBurstFactorChroma, + mode_lib->vba.UrgentBurstFactorCursor, + mode_lib->vba.UrgentBurstFactorLumaPre, + mode_lib->vba.UrgentBurstFactorChromaPre, + mode_lib->vba.UrgentBurstFactorCursorPre, + + /* output */ + &dummy_single[0], // Single *PrefetchBandwidth + &dummy_single[1], // Single *FractionOfUrgentBandwidth + &mode_lib->vba.PrefetchSupported[i][j]); + } + + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + if (mode_lib->vba.LineTimesForPrefetch[k] + < 2.0 || mode_lib->vba.LinesForMetaPTE[k] >= 32.0 + || mode_lib->vba.LinesForMetaAndDPTERow[k] >= 16.0 + || mode_lib->vba.NoTimeForPrefetch[i][j][k] == true) { + mode_lib->vba.PrefetchSupported[i][j] = false; + } + } + + mode_lib->vba.DynamicMetadataSupported[i][j] = true; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.NoTimeForDynamicMetadata[i][j][k] == true) + mode_lib->vba.DynamicMetadataSupported[i][j] = false; + } + + mode_lib->vba.VRatioInPrefetchSupported[i][j] = true; + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + if (mode_lib->vba.VRatioPreY[i][j][k] > __DML_MAX_VRATIO_PRE__ + || mode_lib->vba.VRatioPreC[i][j][k] > __DML_MAX_VRATIO_PRE__ + || mode_lib->vba.NoTimeForPrefetch[i][j][k] == true) { + mode_lib->vba.VRatioInPrefetchSupported[i][j] = false; + } + } + mode_lib->vba.AnyLinesForVMOrRowTooLarge = false; + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + if (mode_lib->vba.LinesForMetaAndDPTERow[k] >= 16 + || mode_lib->vba.LinesForMetaPTE[k] >= 32) { + mode_lib->vba.AnyLinesForVMOrRowTooLarge = true; + } + } + + if (mode_lib->vba.PrefetchSupported[i][j] == true + && mode_lib->vba.VRatioInPrefetchSupported[i][j] == true) { + mode_lib->vba.BandwidthAvailableForImmediateFlip = + dml32_CalculateBandwidthAvailableForImmediateFlip( + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.ReturnBWPerState[i][j], + mode_lib->vba.ReadBandwidthLuma, + mode_lib->vba.ReadBandwidthChroma, + mode_lib->vba.RequiredPrefetchPixelDataBWLuma[0][0], + mode_lib->vba.RequiredPrefetchPixelDataBWChroma[0][0], + mode_lib->vba.cursor_bw, + mode_lib->vba.cursor_bw_pre, + mode_lib->vba.NoOfDPPThisState, + mode_lib->vba.UrgentBurstFactorLuma, + mode_lib->vba.UrgentBurstFactorChroma, + mode_lib->vba.UrgentBurstFactorCursor, + mode_lib->vba.UrgentBurstFactorLumaPre, + mode_lib->vba.UrgentBurstFactorChromaPre, + mode_lib->vba.UrgentBurstFactorCursorPre); + + mode_lib->vba.TotImmediateFlipBytes = 0.0; + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + if (!(mode_lib->vba.ImmediateFlipRequirement[k] == + dm_immediate_flip_not_required)) { + mode_lib->vba.TotImmediateFlipBytes = + mode_lib->vba.TotImmediateFlipBytes + + mode_lib->vba.NoOfDPP[i][j][k] + * mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k] + + mode_lib->vba.MetaRowBytes[i][j][k]; + if (mode_lib->vba.use_one_row_for_frame_flip[i][j][k]) { + mode_lib->vba.TotImmediateFlipBytes = + mode_lib->vba.TotImmediateFlipBytes + 2 + * mode_lib->vba.DPTEBytesPerRow[i][j][k]; + } else { + mode_lib->vba.TotImmediateFlipBytes = + mode_lib->vba.TotImmediateFlipBytes + + mode_lib->vba.DPTEBytesPerRow[i][j][k]; + } + } + } + + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + dml32_CalculateFlipSchedule(HostVMInefficiencyFactor, + mode_lib->vba.ExtraLatency, + mode_lib->vba.UrgLatency[i], + mode_lib->vba.GPUVMMaxPageTableLevels, + mode_lib->vba.HostVMEnable, + mode_lib->vba.HostVMMaxNonCachedPageTableLevels, + mode_lib->vba.GPUVMEnable, + mode_lib->vba.HostVMMinPageSize, + mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k], + mode_lib->vba.MetaRowBytes[i][j][k], + mode_lib->vba.DPTEBytesPerRow[i][j][k], + mode_lib->vba.BandwidthAvailableForImmediateFlip, + mode_lib->vba.TotImmediateFlipBytes, + mode_lib->vba.SourcePixelFormat[k], + (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), + mode_lib->vba.VRatio[k], + mode_lib->vba.VRatioChroma[k], + mode_lib->vba.Tno_bw[k], + mode_lib->vba.DCCEnable[k], + mode_lib->vba.dpte_row_height[k], + mode_lib->vba.meta_row_height[k], + mode_lib->vba.dpte_row_height_chroma[k], + mode_lib->vba.meta_row_height_chroma[k], + mode_lib->vba.use_one_row_for_frame_flip[i][j][k], // 24 + + /* Output */ + &mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k], + &mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k], + &mode_lib->vba.final_flip_bw[k], + &mode_lib->vba.ImmediateFlipSupportedForPipe[k]); + } + + { + double dummy_single[2]; + dml32_CalculateImmediateFlipBandwithSupport(mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.ReturnBWPerState[i][j], + mode_lib->vba.ImmediateFlipRequirement, + mode_lib->vba.final_flip_bw, + mode_lib->vba.ReadBandwidthLuma, + mode_lib->vba.ReadBandwidthChroma, + mode_lib->vba.RequiredPrefetchPixelDataBWLuma[0][0], + mode_lib->vba.RequiredPrefetchPixelDataBWChroma[0][0], + mode_lib->vba.cursor_bw, + mode_lib->vba.meta_row_bandwidth_this_state, + mode_lib->vba.dpte_row_bandwidth_this_state, + mode_lib->vba.cursor_bw_pre, + mode_lib->vba.prefetch_vmrow_bw, + mode_lib->vba.DPPPerPlane, + mode_lib->vba.UrgentBurstFactorLuma, + mode_lib->vba.UrgentBurstFactorChroma, + mode_lib->vba.UrgentBurstFactorCursor, + mode_lib->vba.UrgentBurstFactorLumaPre, + mode_lib->vba.UrgentBurstFactorChromaPre, + mode_lib->vba.UrgentBurstFactorCursorPre, + + /* output */ + &dummy_single[0], // Single *TotalBandwidth + &dummy_single[1], // Single *FractionOfUrgentBandwidth + &mode_lib->vba.ImmediateFlipSupportedForState[i][j]); // Boolean *ImmediateFlipBandwidthSupport + } + + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + if (!(mode_lib->vba.ImmediateFlipRequirement[k] + == dm_immediate_flip_not_required) + && (mode_lib->vba.ImmediateFlipSupportedForPipe[k] + == false)) + mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false; + } + } else { // if prefetch not support, assume iflip not supported + mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false; + } + + if (mode_lib->vba.MaxVStartup <= __DML_VBA_MIN_VSTARTUP__ + || mode_lib->vba.AnyLinesForVMOrRowTooLarge == false) { + mode_lib->vba.NextMaxVStartup = mode_lib->vba.MaxMaxVStartup[i][j]; + NextPrefetchModeState = NextPrefetchModeState + 1; + } else { + mode_lib->vba.NextMaxVStartup = mode_lib->vba.NextMaxVStartup - 1; + } + } while (!((mode_lib->vba.PrefetchSupported[i][j] == true + && mode_lib->vba.DynamicMetadataSupported[i][j] == true + && mode_lib->vba.VRatioInPrefetchSupported[i][j] == true && + // consider flip support is okay if when there is no hostvm and the + // user does't require a iflip OR the flip bw is ok + // If there is hostvm, DCN needs to support iflip for invalidation + ((mode_lib->vba.HostVMEnable == false + && !mode_lib->vba.ImmediateFlipRequiredFinal) + || mode_lib->vba.ImmediateFlipSupportedForState[i][j] == true)) + || (mode_lib->vba.NextMaxVStartup == mode_lib->vba.MaxMaxVStartup[i][j] + && NextPrefetchModeState > mode_lib->vba.MaxPrefetchMode))); + + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { + mode_lib->vba.use_one_row_for_frame_this_state[k] = + mode_lib->vba.use_one_row_for_frame[i][j][k]; + } + + + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.UrgentLatency = mode_lib->vba.UrgLatency[i]; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.ExtraLatency = mode_lib->vba.ExtraLatency; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.WritebackLatency = mode_lib->vba.WritebackLatency; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.DRAMClockChangeLatency = mode_lib->vba.DRAMClockChangeLatency; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.FCLKChangeLatency = mode_lib->vba.FCLKChangeLatency; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SRExitTime = mode_lib->vba.SRExitTime; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SREnterPlusExitTime = mode_lib->vba.SREnterPlusExitTime; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SRExitZ8Time = mode_lib->vba.SRExitZ8Time; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SREnterPlusExitZ8Time = mode_lib->vba.SREnterPlusExitZ8Time; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.USRRetrainingLatency = mode_lib->vba.USRRetrainingLatency; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SMNLatency = mode_lib->vba.SMNLatency; + + { + unsigned int dummy_integer[4]; + dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( + mode_lib->vba.USRRetrainingRequiredFinal, + mode_lib->vba.UsesMALLForPStateChange, + mode_lib->vba.PrefetchModePerState[i][j], + mode_lib->vba.NumberOfActiveSurfaces, + mode_lib->vba.MaxLineBufferLines, + mode_lib->vba.LineBufferSizeFinal, + mode_lib->vba.WritebackInterfaceBufferSize, + mode_lib->vba.DCFCLKState[i][j], + mode_lib->vba.ReturnBWPerState[i][j], + mode_lib->vba.SynchronizeTimingsFinal, + mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal, + mode_lib->vba.DRRDisplay, + mode_lib->vba.dpte_group_bytes, + mode_lib->vba.meta_row_height, + mode_lib->vba.meta_row_height_chroma, + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters, + mode_lib->vba.WritebackChunkSize, + mode_lib->vba.SOCCLKPerState[i], + mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j], + mode_lib->vba.DETBufferSizeYThisState, + mode_lib->vba.DETBufferSizeCThisState, + mode_lib->vba.SwathHeightYThisState, + mode_lib->vba.SwathHeightCThisState, + mode_lib->vba.LBBitPerPixel, + mode_lib->vba.SwathWidthYThisState, // 24 + mode_lib->vba.SwathWidthCThisState, + mode_lib->vba.HRatio, + mode_lib->vba.HRatioChroma, + mode_lib->vba.vtaps, + mode_lib->vba.VTAPsChroma, + mode_lib->vba.VRatio, + mode_lib->vba.VRatioChroma, + mode_lib->vba.HTotal, + mode_lib->vba.VTotal, + mode_lib->vba.VActive, + mode_lib->vba.PixelClock, + mode_lib->vba.BlendingAndTiming, + mode_lib->vba.NoOfDPPThisState, + mode_lib->vba.BytePerPixelInDETY, + mode_lib->vba.BytePerPixelInDETC, + DSTXAfterScaler, + DSTYAfterScaler, + mode_lib->vba.WritebackEnable, + mode_lib->vba.WritebackPixelFormat, + mode_lib->vba.WritebackDestinationWidth, + mode_lib->vba.WritebackDestinationHeight, + mode_lib->vba.WritebackSourceHeight, + mode_lib->vba.UnboundedRequestEnabledThisState, + mode_lib->vba.CompressedBufferSizeInkByteThisState, + + /* Output */ + &mode_lib->vba.Watermark, // Store the values in vba + &mode_lib->vba.DRAMClockChangeSupport[i][j], + &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single2[0], // double *MaxActiveDRAMClockChangeLatencySupported + &dummy_integer[0], // Long SubViewportLinesNeededInMALL[] + &mode_lib->vba.FCLKChangeSupport[i][j], + &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single2[1], // double *MinActiveFCLKChangeLatencySupported + &mode_lib->vba.USRRetrainingSupport[i][j], + mode_lib->vba.ActiveDRAMClockChangeLatencyMargin); + } + } + } // End of Prefetch Check + + /*Cursor Support Check*/ + mode_lib->vba.CursorSupport = true; + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + if (mode_lib->vba.CursorWidth[k][0] > 0.0) { + if (mode_lib->vba.CursorBPP[k][0] == 64 && mode_lib->vba.Cursor64BppSupport == false) + mode_lib->vba.CursorSupport = false; + } + } + + /*Valid Pitch Check*/ + mode_lib->vba.PitchSupport = true; + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + mode_lib->vba.AlignedYPitch[k] = dml_ceil( + dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.SurfaceWidthY[k]), + mode_lib->vba.MacroTileWidthY[k]); + if (mode_lib->vba.DCCEnable[k] == true) { + mode_lib->vba.AlignedDCCMetaPitchY[k] = dml_ceil( + dml_max(mode_lib->vba.DCCMetaPitchY[k], mode_lib->vba.SurfaceWidthY[k]), + 64.0 * mode_lib->vba.Read256BlockWidthY[k]); + } else { + mode_lib->vba.AlignedDCCMetaPitchY[k] = mode_lib->vba.DCCMetaPitchY[k]; + } + if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64 && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 + && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 + && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 + && mode_lib->vba.SourcePixelFormat[k] != dm_rgbe + && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) { + mode_lib->vba.AlignedCPitch[k] = dml_ceil( + dml_max(mode_lib->vba.PitchC[k], mode_lib->vba.SurfaceWidthC[k]), + mode_lib->vba.MacroTileWidthC[k]); + if (mode_lib->vba.DCCEnable[k] == true) { + mode_lib->vba.AlignedDCCMetaPitchC[k] = dml_ceil( + dml_max(mode_lib->vba.DCCMetaPitchC[k], + mode_lib->vba.SurfaceWidthC[k]), + 64.0 * mode_lib->vba.Read256BlockWidthC[k]); + } else { + mode_lib->vba.AlignedDCCMetaPitchC[k] = mode_lib->vba.DCCMetaPitchC[k]; + } + } else { + mode_lib->vba.AlignedCPitch[k] = mode_lib->vba.PitchC[k]; + mode_lib->vba.AlignedDCCMetaPitchC[k] = mode_lib->vba.DCCMetaPitchC[k]; + } + if (mode_lib->vba.AlignedYPitch[k] > mode_lib->vba.PitchY[k] + || mode_lib->vba.AlignedCPitch[k] > mode_lib->vba.PitchC[k] + || mode_lib->vba.AlignedDCCMetaPitchY[k] > mode_lib->vba.DCCMetaPitchY[k] + || mode_lib->vba.AlignedDCCMetaPitchC[k] > mode_lib->vba.DCCMetaPitchC[k]) { + mode_lib->vba.PitchSupport = false; + } + } + + mode_lib->vba.ViewportExceedsSurface = false; + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + if (mode_lib->vba.ViewportWidth[k] > mode_lib->vba.SurfaceWidthY[k] + || mode_lib->vba.ViewportHeight[k] > mode_lib->vba.SurfaceHeightY[k]) { + mode_lib->vba.ViewportExceedsSurface = true; + if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64 + && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 + && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 + && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 + && mode_lib->vba.SourcePixelFormat[k] != dm_444_8 + && mode_lib->vba.SourcePixelFormat[k] != dm_rgbe) { + if (mode_lib->vba.ViewportWidthChroma[k] > mode_lib->vba.SurfaceWidthC[k] + || mode_lib->vba.ViewportHeightChroma[k] + > mode_lib->vba.SurfaceHeightC[k]) { + mode_lib->vba.ViewportExceedsSurface = true; + } + } + } + } + + /*Mode Support, Voltage State and SOC Configuration*/ + for (i = v->soc.num_states - 1; i >= 0; i--) { + for (j = 0; j < 2; j++) { + if (mode_lib->vba.ScaleRatioAndTapsSupport == true + && mode_lib->vba.SourceFormatPixelAndScanSupport == true + && mode_lib->vba.ViewportSizeSupport[i][j] == true + && !mode_lib->vba.LinkRateDoesNotMatchDPVersion + && !mode_lib->vba.LinkRateForMultistreamNotIndicated + && !mode_lib->vba.BPPForMultistreamNotIndicated + && !mode_lib->vba.MultistreamWithHDMIOreDP + && !mode_lib->vba.ExceededMultistreamSlots[i] + && !mode_lib->vba.MSOOrODMSplitWithNonDPLink + && !mode_lib->vba.NotEnoughLanesForMSO + && mode_lib->vba.LinkCapacitySupport[i] == true && !mode_lib->vba.P2IWith420 + && !mode_lib->vba.DSCOnlyIfNecessaryWithBPP + && !mode_lib->vba.DSC422NativeNotSupported + && !mode_lib->vba.MPCCombineMethodIncompatible + && mode_lib->vba.ODMCombine2To1SupportCheckOK[i] == true + && mode_lib->vba.ODMCombine4To1SupportCheckOK[i] == true + && mode_lib->vba.NotEnoughDSCUnits[i] == false + && !mode_lib->vba.NotEnoughDSCSlices[i] + && !mode_lib->vba.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe + && !mode_lib->vba.InvalidCombinationOfMALLUseForPStateAndStaticScreen + && mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] == false + && mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i] + && mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] == false + && !mode_lib->vba.InvalidCombinationOfMALLUseForPState + && !mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified + && mode_lib->vba.ROBSupport[i][j] == true + && mode_lib->vba.DISPCLK_DPPCLK_Support[i][j] == true + && mode_lib->vba.TotalAvailablePipesSupport[i][j] == true + && mode_lib->vba.NumberOfOTGSupport == true + && mode_lib->vba.NumberOfHDMIFRLSupport == true + && mode_lib->vba.EnoughWritebackUnits == true + && mode_lib->vba.WritebackLatencySupport == true + && mode_lib->vba.WritebackScaleRatioAndTapsSupport == true + && mode_lib->vba.CursorSupport == true && mode_lib->vba.PitchSupport == true + && mode_lib->vba.ViewportExceedsSurface == false + && mode_lib->vba.PrefetchSupported[i][j] == true + && mode_lib->vba.VActiveBandwithSupport[i][j] == true + && mode_lib->vba.DynamicMetadataSupported[i][j] == true + && mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][j] == true + && mode_lib->vba.VRatioInPrefetchSupported[i][j] == true + && mode_lib->vba.PTEBufferSizeNotExceeded[i][j] == true + && mode_lib->vba.DCCMetaBufferSizeNotExceeded[i][j] == true + && mode_lib->vba.NonsupportedDSCInputBPC == false + && !mode_lib->vba.ExceededMALLSize + && ((mode_lib->vba.HostVMEnable == false + && !mode_lib->vba.ImmediateFlipRequiredFinal) + || mode_lib->vba.ImmediateFlipSupportedForState[i][j]) + && (!mode_lib->vba.DRAMClockChangeRequirementFinal + || i == v->soc.num_states - 1 + || mode_lib->vba.DRAMClockChangeSupport[i][j] != dm_dram_clock_change_unsupported) + && (!mode_lib->vba.FCLKChangeRequirementFinal || i == v->soc.num_states - 1 + || mode_lib->vba.FCLKChangeSupport[i][j] != dm_fclock_change_unsupported) + && (!mode_lib->vba.USRRetrainingRequiredFinal + || &mode_lib->vba.USRRetrainingSupport[i][j])) { + mode_lib->vba.ModeSupport[i][j] = true; + } else { + mode_lib->vba.ModeSupport[i][j] = false; + } + } + } + + MaximumMPCCombine = 0; + + for (i = v->soc.num_states; i >= 0; i--) { + if (i == v->soc.num_states || mode_lib->vba.ModeSupport[i][0] == true || + mode_lib->vba.ModeSupport[i][1] == true) { + mode_lib->vba.VoltageLevel = i; + mode_lib->vba.ModeIsSupported = mode_lib->vba.ModeSupport[i][0] == true + || mode_lib->vba.ModeSupport[i][1] == true; + + if ((mode_lib->vba.ModeSupport[i][0] == false && mode_lib->vba.ModeSupport[i][1] == true) + || MPCCombineMethodAsPossible + || (MPCCombineMethodAsNeededForPStateChangeAndVoltage + && mode_lib->vba.DRAMClockChangeRequirementFinal + && (((mode_lib->vba.DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vactive + || mode_lib->vba.DRAMClockChangeSupport[i][1] == + dm_dram_clock_change_vactive_w_mall_full_frame + || mode_lib->vba.DRAMClockChangeSupport[i][1] == + dm_dram_clock_change_vactive_w_mall_sub_vp) + && !(mode_lib->vba.DRAMClockChangeSupport[i][0] == dm_dram_clock_change_vactive + || mode_lib->vba.DRAMClockChangeSupport[i][0] == + dm_dram_clock_change_vactive_w_mall_full_frame + || mode_lib->vba.DRAMClockChangeSupport[i][0] == + dm_dram_clock_change_vactive_w_mall_sub_vp)) + || ((mode_lib->vba.DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vblank + || mode_lib->vba.DRAMClockChangeSupport[i][1] == + dm_dram_clock_change_vblank_w_mall_full_frame + || mode_lib->vba.DRAMClockChangeSupport[i][1] == + dm_dram_clock_change_vblank_w_mall_sub_vp) + && mode_lib->vba.DRAMClockChangeSupport[i][0] == dm_dram_clock_change_unsupported))) + || (MPCCombineMethodAsNeededForPStateChangeAndVoltage && + mode_lib->vba.FCLKChangeRequirementFinal + && ((mode_lib->vba.FCLKChangeSupport[i][1] == dm_fclock_change_vactive + && mode_lib->vba.FCLKChangeSupport[i][0] != dm_fclock_change_vactive) + || (mode_lib->vba.FCLKChangeSupport[i][1] == dm_fclock_change_vblank + && mode_lib->vba.FCLKChangeSupport[i][0] == dm_fclock_change_unsupported)))) { + MaximumMPCCombine = 1; + } else { + MaximumMPCCombine = 0; + } + } + } + + mode_lib->vba.ImmediateFlipSupport = + mode_lib->vba.ImmediateFlipSupportedForState[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; + mode_lib->vba.UnboundedRequestEnabled = + mode_lib->vba.UnboundedRequestEnabledAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; + mode_lib->vba.CompressedBufferSizeInkByte = + mode_lib->vba.CompressedBufferSizeInkByteAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; // Not used, informational + + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + mode_lib->vba.MPCCombineEnable[k] = + mode_lib->vba.MPCCombine[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; + mode_lib->vba.DPPPerPlane[k] = mode_lib->vba.NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; + mode_lib->vba.SwathHeightY[k] = + mode_lib->vba.SwathHeightYAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; + mode_lib->vba.SwathHeightC[k] = + mode_lib->vba.SwathHeightCAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; + mode_lib->vba.DETBufferSizeInKByte[k] = + mode_lib->vba.DETBufferSizeInKByteAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; + mode_lib->vba.DETBufferSizeY[k] = + mode_lib->vba.DETBufferSizeYAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; + mode_lib->vba.DETBufferSizeC[k] = + mode_lib->vba.DETBufferSizeCAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; + mode_lib->vba.OutputType[k] = mode_lib->vba.OutputTypePerState[mode_lib->vba.VoltageLevel][k]; + mode_lib->vba.OutputRate[k] = mode_lib->vba.OutputRatePerState[mode_lib->vba.VoltageLevel][k]; + } + + mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKState[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; + mode_lib->vba.DRAMSpeed = mode_lib->vba.DRAMSpeedPerState[mode_lib->vba.VoltageLevel]; + mode_lib->vba.FabricClock = mode_lib->vba.FabricClockPerState[mode_lib->vba.VoltageLevel]; + mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel]; + mode_lib->vba.ReturnBW = mode_lib->vba.ReturnBWPerState[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; + mode_lib->vba.DISPCLK = mode_lib->vba.RequiredDISPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; + mode_lib->vba.maxMpcComb = MaximumMPCCombine; + + for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { + if (mode_lib->vba.BlendingAndTiming[k] == k) { + mode_lib->vba.ODMCombineEnabled[k] = + mode_lib->vba.ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k]; + } else { + mode_lib->vba.ODMCombineEnabled[k] = dm_odm_combine_mode_disabled; + } + + mode_lib->vba.DSCEnabled[k] = mode_lib->vba.RequiresDSC[mode_lib->vba.VoltageLevel][k]; + mode_lib->vba.FECEnable[k] = mode_lib->vba.RequiresFEC[mode_lib->vba.VoltageLevel][k]; + mode_lib->vba.OutputBpp[k] = mode_lib->vba.OutputBppPerState[mode_lib->vba.VoltageLevel][k]; + } + + mode_lib->vba.UrgentWatermark = mode_lib->vba.Watermark.UrgentWatermark; + mode_lib->vba.StutterEnterPlusExitWatermark = mode_lib->vba.Watermark.StutterEnterPlusExitWatermark; + mode_lib->vba.StutterExitWatermark = mode_lib->vba.Watermark.StutterExitWatermark; + mode_lib->vba.WritebackDRAMClockChangeWatermark = mode_lib->vba.Watermark.WritebackDRAMClockChangeWatermark; + mode_lib->vba.DRAMClockChangeWatermark = mode_lib->vba.Watermark.DRAMClockChangeWatermark; + mode_lib->vba.UrgentLatency = mode_lib->vba.UrgLatency[mode_lib->vba.VoltageLevel]; + mode_lib->vba.DCFCLKDeepSleep = mode_lib->vba.ProjectedDCFCLKDeepSleep[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; + + /* VBA has Error type to Error Msg output here, but not necessary for DML-C */ +} // ModeSupportAndSystemConfigurationFull diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h new file mode 100644 index 000000000000..c62e0991358b --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h @@ -0,0 +1,57 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DML32_DISPLAY_MODE_VBA_H__ +#define __DML32_DISPLAY_MODE_VBA_H__ + +#include "../display_mode_enums.h" + +// To enable a lot of debug msg +//#define __DML_VBA_DEBUG__ +// For DML-C changes that hasn't been propagated to VBA yet +//#define __DML_VBA_ALLOW_DELTA__ + +// Move these to ip parameters/constant +// At which vstartup the DML start to try if the mode can be supported +#define __DML_VBA_MIN_VSTARTUP__ 9 + +// Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET) +#define __DML_ARB_TO_RET_DELAY__ 7 + 95 + +// fudge factor for min dcfclk calclation +#define __DML_MIN_DCFCLK_FACTOR__ 1.15 + +// Prefetch schedule max vratio +#define __DML_MAX_VRATIO_PRE__ 4.0 + +#define BPP_INVALID 0 +#define BPP_BLENDED_PIPE 0xffffffff + +struct display_mode_lib; + +void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib); +void dml32_recalculate(struct display_mode_lib *mode_lib); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c new file mode 100644 index 000000000000..6509a84eeb64 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c @@ -0,0 +1,6254 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "display_mode_vba_util_32.h" +#include "../dml_inline_defs.h" +#include "display_mode_vba_32.h" +#include "../display_mode_lib.h" + +unsigned int dml32_dscceComputeDelay( + unsigned int bpc, + double BPP, + unsigned int sliceWidth, + unsigned int numSlices, + enum output_format_class pixelFormat, + enum output_encoder_class Output) +{ + // valid bpc = source bits per component in the set of {8, 10, 12} + // valid bpp = increments of 1/16 of a bit + // min = 6/7/8 in N420/N422/444, respectively + // max = such that compression is 1:1 + //valid sliceWidth = number of pixels per slice line, + // must be less than or equal to 5184/numSlices (or 4096/numSlices in 420 mode) + //valid numSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4} + //valid pixelFormat = pixel/color format in the set of {:N444_RGB, :S422, :N422, :N420} + + // fixed value + unsigned int rcModelSize = 8192; + + // N422/N420 operate at 2 pixels per clock + unsigned int pixelsPerClock, lstall, D, initalXmitDelay, w, s, ix, wx, p, l0, a, ax, L, + Delay, pixels; + + if (pixelFormat == dm_420) + pixelsPerClock = 2; + else if (pixelFormat == dm_n422) + pixelsPerClock = 2; + // #all other modes operate at 1 pixel per clock + else + pixelsPerClock = 1; + + //initial transmit delay as per PPS + initalXmitDelay = dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock); + + //compute ssm delay + if (bpc == 8) + D = 81; + else if (bpc == 10) + D = 89; + else + D = 113; + + //divide by pixel per cycle to compute slice width as seen by DSC + w = sliceWidth / pixelsPerClock; + + //422 mode has an additional cycle of delay + if (pixelFormat == dm_420 || pixelFormat == dm_444 || pixelFormat == dm_n422) + s = 0; + else + s = 1; + + //main calculation for the dscce + ix = initalXmitDelay + 45; + wx = (w + 2) / 3; + p = 3 * wx - w; + l0 = ix / w; + a = ix + p * l0; + ax = (a + 2) / 3 + D + 6 + 1; + L = (ax + wx - 1) / wx; + if ((ix % w) == 0 && p != 0) + lstall = 1; + else + lstall = 0; + Delay = L * wx * (numSlices - 1) + ax + s + lstall + 22; + + //dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels + pixels = Delay * 3 * pixelsPerClock; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: bpc: %d\n", __func__, bpc); + dml_print("DML::%s: BPP: %f\n", __func__, BPP); + dml_print("DML::%s: sliceWidth: %d\n", __func__, sliceWidth); + dml_print("DML::%s: numSlices: %d\n", __func__, numSlices); + dml_print("DML::%s: pixelFormat: %d\n", __func__, pixelFormat); + dml_print("DML::%s: Output: %d\n", __func__, Output); + dml_print("DML::%s: pixels: %d\n", __func__, pixels); +#endif + + return pixels; +} + +unsigned int dml32_dscComputeDelay(enum output_format_class pixelFormat, enum output_encoder_class Output) +{ + unsigned int Delay = 0; + + if (pixelFormat == dm_420) { + // sfr + Delay = Delay + 2; + // dsccif + Delay = Delay + 0; + // dscc - input deserializer + Delay = Delay + 3; + // dscc gets pixels every other cycle + Delay = Delay + 2; + // dscc - input cdc fifo + Delay = Delay + 12; + // dscc gets pixels every other cycle + Delay = Delay + 13; + // dscc - cdc uncertainty + Delay = Delay + 2; + // dscc - output cdc fifo + Delay = Delay + 7; + // dscc gets pixels every other cycle + Delay = Delay + 3; + // dscc - cdc uncertainty + Delay = Delay + 2; + // dscc - output serializer + Delay = Delay + 1; + // sft + Delay = Delay + 1; + } else if (pixelFormat == dm_n422 || (pixelFormat != dm_444)) { + // sfr + Delay = Delay + 2; + // dsccif + Delay = Delay + 1; + // dscc - input deserializer + Delay = Delay + 5; + // dscc - input cdc fifo + Delay = Delay + 25; + // dscc - cdc uncertainty + Delay = Delay + 2; + // dscc - output cdc fifo + Delay = Delay + 10; + // dscc - cdc uncertainty + Delay = Delay + 2; + // dscc - output serializer + Delay = Delay + 1; + // sft + Delay = Delay + 1; + } else { + // sfr + Delay = Delay + 2; + // dsccif + Delay = Delay + 0; + // dscc - input deserializer + Delay = Delay + 3; + // dscc - input cdc fifo + Delay = Delay + 12; + // dscc - cdc uncertainty + Delay = Delay + 2; + // dscc - output cdc fifo + Delay = Delay + 7; + // dscc - output serializer + Delay = Delay + 1; + // dscc - cdc uncertainty + Delay = Delay + 2; + // sft + Delay = Delay + 1; + } + + return Delay; +} + + +bool IsVertical(enum dm_rotation_angle Scan) +{ + bool is_vert = false; + + if (Scan == dm_rotation_90 || Scan == dm_rotation_90m || Scan == dm_rotation_270 || Scan == dm_rotation_270m) + is_vert = true; + else + is_vert = false; + return is_vert; +} + +void dml32_CalculateSinglePipeDPPCLKAndSCLThroughput( + double HRatio, + double HRatioChroma, + double VRatio, + double VRatioChroma, + double MaxDCHUBToPSCLThroughput, + double MaxPSCLToLBThroughput, + double PixelClock, + enum source_format_class SourcePixelFormat, + unsigned int HTaps, + unsigned int HTapsChroma, + unsigned int VTaps, + unsigned int VTapsChroma, + + /* output */ + double *PSCL_THROUGHPUT, + double *PSCL_THROUGHPUT_CHROMA, + double *DPPCLKUsingSingleDPP) +{ + double DPPCLKUsingSingleDPPLuma; + double DPPCLKUsingSingleDPPChroma; + + if (HRatio > 1) { + *PSCL_THROUGHPUT = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput * HRatio / + dml_ceil((double) HTaps / 6.0, 1.0)); + } else { + *PSCL_THROUGHPUT = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput); + } + + DPPCLKUsingSingleDPPLuma = PixelClock * dml_max3(VTaps / 6 * dml_min(1, HRatio), HRatio * VRatio / + *PSCL_THROUGHPUT, 1); + + if ((HTaps > 6 || VTaps > 6) && DPPCLKUsingSingleDPPLuma < 2 * PixelClock) + DPPCLKUsingSingleDPPLuma = 2 * PixelClock; + + if ((SourcePixelFormat != dm_420_8 && SourcePixelFormat != dm_420_10 && SourcePixelFormat != dm_420_12 && + SourcePixelFormat != dm_rgbe_alpha)) { + *PSCL_THROUGHPUT_CHROMA = 0; + *DPPCLKUsingSingleDPP = DPPCLKUsingSingleDPPLuma; + } else { + if (HRatioChroma > 1) { + *PSCL_THROUGHPUT_CHROMA = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput * + HRatioChroma / dml_ceil((double) HTapsChroma / 6.0, 1.0)); + } else { + *PSCL_THROUGHPUT_CHROMA = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput); + } + DPPCLKUsingSingleDPPChroma = PixelClock * dml_max3(VTapsChroma / 6 * dml_min(1, HRatioChroma), + HRatioChroma * VRatioChroma / *PSCL_THROUGHPUT_CHROMA, 1); + if ((HTapsChroma > 6 || VTapsChroma > 6) && DPPCLKUsingSingleDPPChroma < 2 * PixelClock) + DPPCLKUsingSingleDPPChroma = 2 * PixelClock; + *DPPCLKUsingSingleDPP = dml_max(DPPCLKUsingSingleDPPLuma, DPPCLKUsingSingleDPPChroma); + } +} + +void dml32_CalculateBytePerPixelAndBlockSizes( + enum source_format_class SourcePixelFormat, + enum dm_swizzle_mode SurfaceTiling, + + /* Output */ + unsigned int *BytePerPixelY, + unsigned int *BytePerPixelC, + double *BytePerPixelDETY, + double *BytePerPixelDETC, + unsigned int *BlockHeight256BytesY, + unsigned int *BlockHeight256BytesC, + unsigned int *BlockWidth256BytesY, + unsigned int *BlockWidth256BytesC, + unsigned int *MacroTileHeightY, + unsigned int *MacroTileHeightC, + unsigned int *MacroTileWidthY, + unsigned int *MacroTileWidthC) +{ + if (SourcePixelFormat == dm_444_64) { + *BytePerPixelDETY = 8; + *BytePerPixelDETC = 0; + *BytePerPixelY = 8; + *BytePerPixelC = 0; + } else if (SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_rgbe) { + *BytePerPixelDETY = 4; + *BytePerPixelDETC = 0; + *BytePerPixelY = 4; + *BytePerPixelC = 0; + } else if (SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_16) { + *BytePerPixelDETY = 2; + *BytePerPixelDETC = 0; + *BytePerPixelY = 2; + *BytePerPixelC = 0; + } else if (SourcePixelFormat == dm_444_8) { + *BytePerPixelDETY = 1; + *BytePerPixelDETC = 0; + *BytePerPixelY = 1; + *BytePerPixelC = 0; + } else if (SourcePixelFormat == dm_rgbe_alpha) { + *BytePerPixelDETY = 4; + *BytePerPixelDETC = 1; + *BytePerPixelY = 4; + *BytePerPixelC = 1; + } else if (SourcePixelFormat == dm_420_8) { + *BytePerPixelDETY = 1; + *BytePerPixelDETC = 2; + *BytePerPixelY = 1; + *BytePerPixelC = 2; + } else if (SourcePixelFormat == dm_420_12) { + *BytePerPixelDETY = 2; + *BytePerPixelDETC = 4; + *BytePerPixelY = 2; + *BytePerPixelC = 4; + } else { + *BytePerPixelDETY = 4.0 / 3; + *BytePerPixelDETC = 8.0 / 3; + *BytePerPixelY = 2; + *BytePerPixelC = 4; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: SourcePixelFormat = %d\n", __func__, SourcePixelFormat); + dml_print("DML::%s: BytePerPixelDETY = %f\n", __func__, *BytePerPixelDETY); + dml_print("DML::%s: BytePerPixelDETC = %f\n", __func__, *BytePerPixelDETC); + dml_print("DML::%s: BytePerPixelY = %d\n", __func__, *BytePerPixelY); + dml_print("DML::%s: BytePerPixelC = %d\n", __func__, *BytePerPixelC); +#endif + if ((SourcePixelFormat == dm_444_64 || SourcePixelFormat == dm_444_32 + || SourcePixelFormat == dm_444_16 + || SourcePixelFormat == dm_444_8 + || SourcePixelFormat == dm_mono_16 + || SourcePixelFormat == dm_mono_8 + || SourcePixelFormat == dm_rgbe)) { + if (SurfaceTiling == dm_sw_linear) + *BlockHeight256BytesY = 1; + else if (SourcePixelFormat == dm_444_64) + *BlockHeight256BytesY = 4; + else if (SourcePixelFormat == dm_444_8) + *BlockHeight256BytesY = 16; + else + *BlockHeight256BytesY = 8; + + *BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY; + *BlockHeight256BytesC = 0; + *BlockWidth256BytesC = 0; + } else { + if (SurfaceTiling == dm_sw_linear) { + *BlockHeight256BytesY = 1; + *BlockHeight256BytesC = 1; + } else if (SourcePixelFormat == dm_rgbe_alpha) { + *BlockHeight256BytesY = 8; + *BlockHeight256BytesC = 16; + } else if (SourcePixelFormat == dm_420_8) { + *BlockHeight256BytesY = 16; + *BlockHeight256BytesC = 8; + } else { + *BlockHeight256BytesY = 8; + *BlockHeight256BytesC = 8; + } + *BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY; + *BlockWidth256BytesC = 256U / *BytePerPixelC / *BlockHeight256BytesC; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: BlockWidth256BytesY = %d\n", __func__, *BlockWidth256BytesY); + dml_print("DML::%s: BlockHeight256BytesY = %d\n", __func__, *BlockHeight256BytesY); + dml_print("DML::%s: BlockWidth256BytesC = %d\n", __func__, *BlockWidth256BytesC); + dml_print("DML::%s: BlockHeight256BytesC = %d\n", __func__, *BlockHeight256BytesC); +#endif + + if (SurfaceTiling == dm_sw_linear) { + *MacroTileHeightY = *BlockHeight256BytesY; + *MacroTileWidthY = 256 / *BytePerPixelY / *MacroTileHeightY; + *MacroTileHeightC = *BlockHeight256BytesC; + if (*MacroTileHeightC == 0) + *MacroTileWidthC = 0; + else + *MacroTileWidthC = 256 / *BytePerPixelC / *MacroTileHeightC; + } else if (SurfaceTiling == dm_sw_64kb_d || SurfaceTiling == dm_sw_64kb_d_t || + SurfaceTiling == dm_sw_64kb_d_x || SurfaceTiling == dm_sw_64kb_r_x) { + *MacroTileHeightY = 16 * *BlockHeight256BytesY; + *MacroTileWidthY = 65536 / *BytePerPixelY / *MacroTileHeightY; + *MacroTileHeightC = 16 * *BlockHeight256BytesC; + if (*MacroTileHeightC == 0) + *MacroTileWidthC = 0; + else + *MacroTileWidthC = 65536 / *BytePerPixelC / *MacroTileHeightC; + } else { + *MacroTileHeightY = 32 * *BlockHeight256BytesY; + *MacroTileWidthY = 65536 * 4 / *BytePerPixelY / *MacroTileHeightY; + *MacroTileHeightC = 32 * *BlockHeight256BytesC; + if (*MacroTileHeightC == 0) + *MacroTileWidthC = 0; + else + *MacroTileWidthC = 65536 * 4 / *BytePerPixelC / *MacroTileHeightC; + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: MacroTileWidthY = %d\n", __func__, *MacroTileWidthY); + dml_print("DML::%s: MacroTileHeightY = %d\n", __func__, *MacroTileHeightY); + dml_print("DML::%s: MacroTileWidthC = %d\n", __func__, *MacroTileWidthC); + dml_print("DML::%s: MacroTileHeightC = %d\n", __func__, *MacroTileHeightC); +#endif +} // CalculateBytePerPixelAndBlockSizes + +void dml32_CalculatedoublePipeDPPCLKAndSCLThroughput( + double HRatio, + double HRatioChroma, + double VRatio, + double VRatioChroma, + double MaxDCHUBToPSCLThroughput, + double MaxPSCLToLBThroughput, + double PixelClock, + enum source_format_class SourcePixelFormat, + unsigned int HTaps, + unsigned int HTapsChroma, + unsigned int VTaps, + unsigned int VTapsChroma, + + /* output */ + double *PSCL_THROUGHPUT, + double *PSCL_THROUGHPUT_CHROMA, + double *DPPCLKUsingdoubleDPP) +{ + double DPPCLKUsingdoubleDPPLuma; + double DPPCLKUsingdoubleDPPChroma; + + if (HRatio > 1) { + *PSCL_THROUGHPUT = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput * HRatio / + dml_ceil((double) HTaps / 6.0, 1.0)); + } else { + *PSCL_THROUGHPUT = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput); + } + + DPPCLKUsingdoubleDPPLuma = PixelClock * dml_max3(VTaps / 6 * dml_min(1, HRatio), HRatio * VRatio / + *PSCL_THROUGHPUT, 1); + + if ((HTaps > 6 || VTaps > 6) && DPPCLKUsingdoubleDPPLuma < 2 * PixelClock) + DPPCLKUsingdoubleDPPLuma = 2 * PixelClock; + + if ((SourcePixelFormat != dm_420_8 && SourcePixelFormat != dm_420_10 && SourcePixelFormat != dm_420_12 && + SourcePixelFormat != dm_rgbe_alpha)) { + *PSCL_THROUGHPUT_CHROMA = 0; + *DPPCLKUsingdoubleDPP = DPPCLKUsingdoubleDPPLuma; + } else { + if (HRatioChroma > 1) { + *PSCL_THROUGHPUT_CHROMA = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput * + HRatioChroma / dml_ceil((double) HTapsChroma / 6.0, 1.0)); + } else { + *PSCL_THROUGHPUT_CHROMA = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput); + } + DPPCLKUsingdoubleDPPChroma = PixelClock * dml_max3(VTapsChroma / 6 * dml_min(1, HRatioChroma), + HRatioChroma * VRatioChroma / *PSCL_THROUGHPUT_CHROMA, 1); + if ((HTapsChroma > 6 || VTapsChroma > 6) && DPPCLKUsingdoubleDPPChroma < 2 * PixelClock) + DPPCLKUsingdoubleDPPChroma = 2 * PixelClock; + *DPPCLKUsingdoubleDPP = dml_max(DPPCLKUsingdoubleDPPLuma, DPPCLKUsingdoubleDPPChroma); + } +} + +void dml32_CalculateSwathAndDETConfiguration( + unsigned int DETSizeOverride[], + enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[], + unsigned int ConfigReturnBufferSizeInKByte, + unsigned int MaxTotalDETInKByte, + unsigned int MinCompressedBufferSizeInKByte, + double ForceSingleDPP, + unsigned int NumberOfActiveSurfaces, + unsigned int nomDETInKByte, + enum unbounded_requesting_policy UseUnboundedRequestingFinal, + unsigned int CompressedBufferSegmentSizeInkByteFinal, + enum output_encoder_class Output[], + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + double MaximumSwathWidthLuma[], + double MaximumSwathWidthChroma[], + enum dm_rotation_angle SourceRotation[], + bool ViewportStationary[], + enum source_format_class SourcePixelFormat[], + enum dm_swizzle_mode SurfaceTiling[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int ViewportXStart[], + unsigned int ViewportYStart[], + unsigned int ViewportXStartC[], + unsigned int ViewportYStartC[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], + enum odm_combine_mode ODMMode[], + unsigned int BlendingAndTiming[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], + double BytePerPixDETY[], + double BytePerPixDETC[], + unsigned int HActive[], + double HRatio[], + double HRatioChroma[], + unsigned int DPPPerSurface[], + + /* Output */ + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[], + double SwathWidth[], + double SwathWidthChroma[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], + unsigned int DETBufferSizeInKByte[], + unsigned int DETBufferSizeY[], + unsigned int DETBufferSizeC[], + bool *UnboundedRequestEnabled, + unsigned int *CompressedBufferSizeInkByte, + bool ViewportSizeSupportPerSurface[], + bool *ViewportSizeSupport) +{ + unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX]; + unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX]; + unsigned int RoundedUpMaxSwathSizeBytesY[DC__NUM_DPP__MAX]; + unsigned int RoundedUpMaxSwathSizeBytesC[DC__NUM_DPP__MAX]; + unsigned int RoundedUpSwathSizeBytesY; + unsigned int RoundedUpSwathSizeBytesC; + double SwathWidthdoubleDPP[DC__NUM_DPP__MAX]; + double SwathWidthdoubleDPPChroma[DC__NUM_DPP__MAX]; + unsigned int k; + unsigned int TotalActiveDPP = 0; + bool NoChromaSurfaces = true; + unsigned int DETBufferSizeInKByteForSwathCalculation; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: ForceSingleDPP = %d\n", __func__, ForceSingleDPP); +#endif + dml32_CalculateSwathWidth(ForceSingleDPP, + NumberOfActiveSurfaces, + SourcePixelFormat, + SourceRotation, + ViewportStationary, + ViewportWidth, + ViewportHeight, + ViewportXStart, + ViewportYStart, + ViewportXStartC, + ViewportYStartC, + SurfaceWidthY, + SurfaceWidthC, + SurfaceHeightY, + SurfaceHeightC, + ODMMode, + BytePerPixY, + BytePerPixC, + Read256BytesBlockHeightY, + Read256BytesBlockHeightC, + Read256BytesBlockWidthY, + Read256BytesBlockWidthC, + BlendingAndTiming, + HActive, + HRatio, + DPPPerSurface, + + /* Output */ + SwathWidthdoubleDPP, + SwathWidthdoubleDPPChroma, + SwathWidth, + SwathWidthChroma, + MaximumSwathHeightY, + MaximumSwathHeightC, + swath_width_luma_ub, + swath_width_chroma_ub); + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + RoundedUpMaxSwathSizeBytesY[k] = swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k]; + RoundedUpMaxSwathSizeBytesC[k] = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k]; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d DPPPerSurface = %d\n", __func__, k, DPPPerSurface[k]); + dml_print("DML::%s: k=%0d swath_width_luma_ub = %d\n", __func__, k, swath_width_luma_ub[k]); + dml_print("DML::%s: k=%0d BytePerPixDETY = %f\n", __func__, k, BytePerPixDETY[k]); + dml_print("DML::%s: k=%0d MaximumSwathHeightY = %d\n", __func__, k, MaximumSwathHeightY[k]); + dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesY = %d\n", __func__, k, + RoundedUpMaxSwathSizeBytesY[k]); + dml_print("DML::%s: k=%0d swath_width_chroma_ub = %d\n", __func__, k, swath_width_chroma_ub[k]); + dml_print("DML::%s: k=%0d BytePerPixDETC = %f\n", __func__, k, BytePerPixDETC[k]); + dml_print("DML::%s: k=%0d MaximumSwathHeightC = %d\n", __func__, k, MaximumSwathHeightC[k]); + dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesC = %d\n", __func__, k, + RoundedUpMaxSwathSizeBytesC[k]); +#endif + + if (SourcePixelFormat[k] == dm_420_10) { + RoundedUpMaxSwathSizeBytesY[k] = dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesY[k], 256); + RoundedUpMaxSwathSizeBytesC[k] = dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesC[k], 256); + } + } + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + TotalActiveDPP = TotalActiveDPP + (ForceSingleDPP ? 1 : DPPPerSurface[k]); + if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 || + SourcePixelFormat[k] == dm_420_12 || SourcePixelFormat[k] == dm_rgbe_alpha) { + NoChromaSurfaces = false; + } + } + + *UnboundedRequestEnabled = dml32_UnboundedRequest(UseUnboundedRequestingFinal, TotalActiveDPP, + NoChromaSurfaces, Output[0]); + + dml32_CalculateDETBufferSize(DETSizeOverride, + UseMALLForPStateChange, + ForceSingleDPP, + NumberOfActiveSurfaces, + *UnboundedRequestEnabled, + nomDETInKByte, + MaxTotalDETInKByte, + ConfigReturnBufferSizeInKByte, + MinCompressedBufferSizeInKByte, + CompressedBufferSegmentSizeInkByteFinal, + SourcePixelFormat, + ReadBandwidthLuma, + ReadBandwidthChroma, + RoundedUpMaxSwathSizeBytesY, + RoundedUpMaxSwathSizeBytesC, + DPPPerSurface, + + /* Output */ + DETBufferSizeInKByte, // per hubp pipe + CompressedBufferSizeInkByte); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: TotalActiveDPP = %d\n", __func__, TotalActiveDPP); + dml_print("DML::%s: nomDETInKByte = %d\n", __func__, nomDETInKByte); + dml_print("DML::%s: ConfigReturnBufferSizeInKByte = %d\n", __func__, ConfigReturnBufferSizeInKByte); + dml_print("DML::%s: UseUnboundedRequestingFinal = %d\n", __func__, UseUnboundedRequestingFinal); + dml_print("DML::%s: UnboundedRequestEnabled = %d\n", __func__, *UnboundedRequestEnabled); + dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, *CompressedBufferSizeInkByte); +#endif + + *ViewportSizeSupport = true; + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + + DETBufferSizeInKByteForSwathCalculation = (UseMALLForPStateChange[k] == + dm_use_mall_pstate_change_phantom_pipe ? 1024 : DETBufferSizeInKByte[k]); +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d DETBufferSizeInKByteForSwathCalculation = %d\n", __func__, k, + DETBufferSizeInKByteForSwathCalculation); +#endif + + if (RoundedUpMaxSwathSizeBytesY[k] + RoundedUpMaxSwathSizeBytesC[k] <= + DETBufferSizeInKByteForSwathCalculation * 1024 / 2) { + SwathHeightY[k] = MaximumSwathHeightY[k]; + SwathHeightC[k] = MaximumSwathHeightC[k]; + RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k]; + RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k]; + } else if (RoundedUpMaxSwathSizeBytesY[k] >= 1.5 * RoundedUpMaxSwathSizeBytesC[k] && + RoundedUpMaxSwathSizeBytesY[k] / 2 + RoundedUpMaxSwathSizeBytesC[k] <= + DETBufferSizeInKByteForSwathCalculation * 1024 / 2) { + SwathHeightY[k] = MaximumSwathHeightY[k] / 2; + SwathHeightC[k] = MaximumSwathHeightC[k]; + RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k] / 2; + RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k]; + } else if (RoundedUpMaxSwathSizeBytesY[k] < 1.5 * RoundedUpMaxSwathSizeBytesC[k] && + RoundedUpMaxSwathSizeBytesY[k] + RoundedUpMaxSwathSizeBytesC[k] / 2 <= + DETBufferSizeInKByteForSwathCalculation * 1024 / 2) { + SwathHeightY[k] = MaximumSwathHeightY[k]; + SwathHeightC[k] = MaximumSwathHeightC[k] / 2; + RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k]; + RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k] / 2; + } else { + SwathHeightY[k] = MaximumSwathHeightY[k] / 2; + SwathHeightC[k] = MaximumSwathHeightC[k] / 2; + RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k] / 2; + RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k] / 2; + } + + if ((RoundedUpMaxSwathSizeBytesY[k] / 2 + RoundedUpMaxSwathSizeBytesC[k] / 2 > + DETBufferSizeInKByteForSwathCalculation * 1024 / 2) + || SwathWidth[k] > MaximumSwathWidthLuma[k] || (SwathHeightC[k] > 0 && + SwathWidthChroma[k] > MaximumSwathWidthChroma[k])) { + *ViewportSizeSupport = false; + ViewportSizeSupportPerSurface[k] = false; + } else { + ViewportSizeSupportPerSurface[k] = true; + } + + if (SwathHeightC[k] == 0) { +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d All DET for plane0\n", __func__, k); +#endif + DETBufferSizeY[k] = DETBufferSizeInKByte[k] * 1024; + DETBufferSizeC[k] = 0; + } else if (RoundedUpSwathSizeBytesY <= 1.5 * RoundedUpSwathSizeBytesC) { +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d Half DET for plane0, half for plane1\n", __func__, k); +#endif + DETBufferSizeY[k] = DETBufferSizeInKByte[k] * 1024 / 2; + DETBufferSizeC[k] = DETBufferSizeInKByte[k] * 1024 / 2; + } else { +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d 2/3 DET for plane0, 1/3 for plane1\n", __func__, k); +#endif + DETBufferSizeY[k] = dml_floor(DETBufferSizeInKByte[k] * 1024 * 2 / 3, 1024); + DETBufferSizeC[k] = DETBufferSizeInKByte[k] * 1024 - DETBufferSizeY[k]; + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d SwathHeightY = %d\n", __func__, k, SwathHeightY[k]); + dml_print("DML::%s: k=%0d SwathHeightC = %d\n", __func__, k, SwathHeightC[k]); + dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesY = %d\n", __func__, + k, RoundedUpMaxSwathSizeBytesY[k]); + dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesC = %d\n", __func__, + k, RoundedUpMaxSwathSizeBytesC[k]); + dml_print("DML::%s: k=%0d RoundedUpSwathSizeBytesY = %d\n", __func__, k, RoundedUpSwathSizeBytesY); + dml_print("DML::%s: k=%0d RoundedUpSwathSizeBytesC = %d\n", __func__, k, RoundedUpSwathSizeBytesC); + dml_print("DML::%s: k=%0d DETBufferSizeInKByte = %d\n", __func__, k, DETBufferSizeInKByte[k]); + dml_print("DML::%s: k=%0d DETBufferSizeY = %d\n", __func__, k, DETBufferSizeY[k]); + dml_print("DML::%s: k=%0d DETBufferSizeC = %d\n", __func__, k, DETBufferSizeC[k]); + dml_print("DML::%s: k=%0d ViewportSizeSupportPerSurface = %d\n", __func__, k, + ViewportSizeSupportPerSurface[k]); +#endif + + } +} // CalculateSwathAndDETConfiguration + +void dml32_CalculateSwathWidth( + bool ForceSingleDPP, + unsigned int NumberOfActiveSurfaces, + enum source_format_class SourcePixelFormat[], + enum dm_rotation_angle SourceRotation[], + bool ViewportStationary[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int ViewportXStart[], + unsigned int ViewportYStart[], + unsigned int ViewportXStartC[], + unsigned int ViewportYStartC[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], + enum odm_combine_mode ODMMode[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], + unsigned int BlendingAndTiming[], + unsigned int HActive[], + double HRatio[], + unsigned int DPPPerSurface[], + + /* Output */ + double SwathWidthdoubleDPPY[], + double SwathWidthdoubleDPPC[], + double SwathWidthY[], // per-pipe + double SwathWidthC[], // per-pipe + unsigned int MaximumSwathHeightY[], + unsigned int MaximumSwathHeightC[], + unsigned int swath_width_luma_ub[], // per-pipe + unsigned int swath_width_chroma_ub[]) // per-pipe +{ + unsigned int k, j; + enum odm_combine_mode MainSurfaceODMMode; + + unsigned int surface_width_ub_l; + unsigned int surface_height_ub_l; + unsigned int surface_width_ub_c; + unsigned int surface_height_ub_c; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: ForceSingleDPP = %d\n", __func__, ForceSingleDPP); + dml_print("DML::%s: NumberOfActiveSurfaces = %d\n", __func__, NumberOfActiveSurfaces); +#endif + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (!IsVertical(SourceRotation[k])) + SwathWidthdoubleDPPY[k] = ViewportWidth[k]; + else + SwathWidthdoubleDPPY[k] = ViewportHeight[k]; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d ViewportWidth=%d\n", __func__, k, ViewportWidth[k]); + dml_print("DML::%s: k=%d ViewportHeight=%d\n", __func__, k, ViewportHeight[k]); +#endif + + MainSurfaceODMMode = ODMMode[k]; + for (j = 0; j < NumberOfActiveSurfaces; ++j) { + if (BlendingAndTiming[k] == j) + MainSurfaceODMMode = ODMMode[j]; + } + + if (ForceSingleDPP) { + SwathWidthY[k] = SwathWidthdoubleDPPY[k]; + } else { + if (MainSurfaceODMMode == dm_odm_combine_mode_4to1) { + SwathWidthY[k] = dml_min(SwathWidthdoubleDPPY[k], + dml_round(HActive[k] / 4.0 * HRatio[k])); + } else if (MainSurfaceODMMode == dm_odm_combine_mode_2to1) { + SwathWidthY[k] = dml_min(SwathWidthdoubleDPPY[k], + dml_round(HActive[k] / 2.0 * HRatio[k])); + } else if (DPPPerSurface[k] == 2) { + SwathWidthY[k] = SwathWidthdoubleDPPY[k] / 2; + } else { + SwathWidthY[k] = SwathWidthdoubleDPPY[k]; + } + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d HActive=%d\n", __func__, k, HActive[k]); + dml_print("DML::%s: k=%d HRatio=%f\n", __func__, k, HRatio[k]); + dml_print("DML::%s: k=%d MainSurfaceODMMode=%d\n", __func__, k, MainSurfaceODMMode); + dml_print("DML::%s: k=%d SwathWidthdoubleDPPY=%d\n", __func__, k, SwathWidthdoubleDPPY[k]); + dml_print("DML::%s: k=%d SwathWidthY=%d\n", __func__, k, SwathWidthY[k]); +#endif + + if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 || + SourcePixelFormat[k] == dm_420_12) { + SwathWidthC[k] = SwathWidthY[k] / 2; + SwathWidthdoubleDPPC[k] = SwathWidthdoubleDPPY[k] / 2; + } else { + SwathWidthC[k] = SwathWidthY[k]; + SwathWidthdoubleDPPC[k] = SwathWidthdoubleDPPY[k]; + } + + if (ForceSingleDPP == true) { + SwathWidthY[k] = SwathWidthdoubleDPPY[k]; + SwathWidthC[k] = SwathWidthdoubleDPPC[k]; + } + + surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); + surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); + surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); + surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d surface_width_ub_l=%0d\n", __func__, k, surface_width_ub_l); + dml_print("DML::%s: k=%d surface_height_ub_l=%0d\n", __func__, k, surface_height_ub_l); + dml_print("DML::%s: k=%d surface_width_ub_c=%0d\n", __func__, k, surface_width_ub_c); + dml_print("DML::%s: k=%d surface_height_ub_c=%0d\n", __func__, k, surface_height_ub_c); + dml_print("DML::%s: k=%d Read256BytesBlockWidthY=%0d\n", __func__, k, Read256BytesBlockWidthY[k]); + dml_print("DML::%s: k=%d Read256BytesBlockHeightY=%0d\n", __func__, k, Read256BytesBlockHeightY[k]); + dml_print("DML::%s: k=%d Read256BytesBlockWidthC=%0d\n", __func__, k, Read256BytesBlockWidthC[k]); + dml_print("DML::%s: k=%d Read256BytesBlockHeightC=%0d\n", __func__, k, Read256BytesBlockHeightC[k]); + dml_print("DML::%s: k=%d ViewportStationary=%0d\n", __func__, k, ViewportStationary[k]); + dml_print("DML::%s: k=%d DPPPerSurface=%0d\n", __func__, k, DPPPerSurface[k]); +#endif + + if (!IsVertical(SourceRotation[k])) { + MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k]; + MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k]; + if (ViewportStationary[k] && DPPPerSurface[k] == 1) { + swath_width_luma_ub[k] = dml_min(surface_width_ub_l, + dml_floor(ViewportXStart[k] + + SwathWidthY[k] + + Read256BytesBlockWidthY[k] - 1, + Read256BytesBlockWidthY[k]) - + dml_floor(ViewportXStart[k], + Read256BytesBlockWidthY[k])); + } else { + swath_width_luma_ub[k] = dml_min(surface_width_ub_l, + dml_ceil(SwathWidthY[k] - 1, + Read256BytesBlockWidthY[k]) + + Read256BytesBlockWidthY[k]); + } + if (BytePerPixC[k] > 0) { + if (ViewportStationary[k] && DPPPerSurface[k] == 1) { + swath_width_chroma_ub[k] = dml_min(surface_width_ub_c, + dml_floor(ViewportXStartC[k] + SwathWidthC[k] + + Read256BytesBlockWidthC[k] - 1, + Read256BytesBlockWidthC[k]) - + dml_floor(ViewportXStartC[k], + Read256BytesBlockWidthC[k])); + } else { + swath_width_chroma_ub[k] = dml_min(surface_width_ub_c, + dml_ceil(SwathWidthC[k] - 1, + Read256BytesBlockWidthC[k]) + + Read256BytesBlockWidthC[k]); + } + } else { + swath_width_chroma_ub[k] = 0; + } + } else { + MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k]; + MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k]; + + if (ViewportStationary[k] && DPPPerSurface[k] == 1) { + swath_width_luma_ub[k] = dml_min(surface_height_ub_l, dml_floor(ViewportYStart[k] + + SwathWidthY[k] + Read256BytesBlockHeightY[k] - 1, + Read256BytesBlockHeightY[k]) - + dml_floor(ViewportYStart[k], Read256BytesBlockHeightY[k])); + } else { + swath_width_luma_ub[k] = dml_min(surface_height_ub_l, dml_ceil(SwathWidthY[k] - 1, + Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]); + } + if (BytePerPixC[k] > 0) { + if (ViewportStationary[k] && DPPPerSurface[k] == 1) { + swath_width_chroma_ub[k] = dml_min(surface_height_ub_c, + dml_floor(ViewportYStartC[k] + SwathWidthC[k] + + Read256BytesBlockHeightC[k] - 1, + Read256BytesBlockHeightC[k]) - + dml_floor(ViewportYStartC[k], + Read256BytesBlockHeightC[k])); + } else { + swath_width_chroma_ub[k] = dml_min(surface_height_ub_c, + dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + + Read256BytesBlockHeightC[k]); + } + } else { + swath_width_chroma_ub[k] = 0; + } + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d swath_width_luma_ub=%0d\n", __func__, k, swath_width_luma_ub[k]); + dml_print("DML::%s: k=%d swath_width_chroma_ub=%0d\n", __func__, k, swath_width_chroma_ub[k]); + dml_print("DML::%s: k=%d MaximumSwathHeightY=%0d\n", __func__, k, MaximumSwathHeightY[k]); + dml_print("DML::%s: k=%d MaximumSwathHeightC=%0d\n", __func__, k, MaximumSwathHeightC[k]); +#endif + + } +} // CalculateSwathWidth + +bool dml32_UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, + unsigned int TotalNumberOfActiveDPP, + bool NoChroma, + enum output_encoder_class Output) +{ + bool ret_val = false; + + ret_val = (UseUnboundedRequestingFinal != dm_unbounded_requesting_disable && + TotalNumberOfActiveDPP == 1 && NoChroma); + if (UseUnboundedRequestingFinal == dm_unbounded_requesting_edp_only && Output != dm_edp) + ret_val = false; + return ret_val; +} + +void dml32_CalculateDETBufferSize( + unsigned int DETSizeOverride[], + enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[], + bool ForceSingleDPP, + unsigned int NumberOfActiveSurfaces, + bool UnboundedRequestEnabled, + unsigned int nomDETInKByte, + unsigned int MaxTotalDETInKByte, + unsigned int ConfigReturnBufferSizeInKByte, + unsigned int MinCompressedBufferSizeInKByte, + unsigned int CompressedBufferSegmentSizeInkByteFinal, + enum source_format_class SourcePixelFormat[], + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + unsigned int RoundedUpMaxSwathSizeBytesY[], + unsigned int RoundedUpMaxSwathSizeBytesC[], + unsigned int DPPPerSurface[], + /* Output */ + unsigned int DETBufferSizeInKByte[], + unsigned int *CompressedBufferSizeInkByte) +{ + unsigned int DETBufferSizePoolInKByte; + unsigned int NextDETBufferPieceInKByte; + bool DETPieceAssignedToThisSurfaceAlready[DC__NUM_DPP__MAX]; + bool NextPotentialSurfaceToAssignDETPieceFound; + unsigned int NextSurfaceToAssignDETPiece; + double TotalBandwidth; + double BandwidthOfSurfacesNotAssignedDETPiece; + unsigned int max_minDET; + unsigned int minDET; + unsigned int minDET_pipe; + unsigned int j, k; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: ForceSingleDPP = %d\n", __func__, ForceSingleDPP); + dml_print("DML::%s: nomDETInKByte = %d\n", __func__, nomDETInKByte); + dml_print("DML::%s: NumberOfActiveSurfaces = %d\n", __func__, NumberOfActiveSurfaces); + dml_print("DML::%s: UnboundedRequestEnabled = %d\n", __func__, UnboundedRequestEnabled); + dml_print("DML::%s: MaxTotalDETInKByte = %d\n", __func__, MaxTotalDETInKByte); + dml_print("DML::%s: ConfigReturnBufferSizeInKByte = %d\n", __func__, ConfigReturnBufferSizeInKByte); + dml_print("DML::%s: MinCompressedBufferSizeInKByte = %d\n", __func__, MinCompressedBufferSizeInKByte); + dml_print("DML::%s: CompressedBufferSegmentSizeInkByteFinal = %d\n", __func__, + CompressedBufferSegmentSizeInkByteFinal); +#endif + + // Note: Will use default det size if that fits 2 swaths + if (UnboundedRequestEnabled) { + if (DETSizeOverride[0] > 0) { + DETBufferSizeInKByte[0] = DETSizeOverride[0]; + } else { + DETBufferSizeInKByte[0] = dml_max(nomDETInKByte, dml_ceil(2.0 * + ((double) RoundedUpMaxSwathSizeBytesY[0] + + (double) RoundedUpMaxSwathSizeBytesC[0]) / 1024.0, 64.0)); + } + *CompressedBufferSizeInkByte = ConfigReturnBufferSizeInKByte - DETBufferSizeInKByte[0]; + } else { + DETBufferSizePoolInKByte = MaxTotalDETInKByte; + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + DETBufferSizeInKByte[k] = nomDETInKByte; + if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 || + SourcePixelFormat[k] == dm_420_12) { + max_minDET = nomDETInKByte - 64; + } else { + max_minDET = nomDETInKByte; + } + minDET = 128; + minDET_pipe = 0; + + // add DET resource until can hold 2 full swaths + while (minDET <= max_minDET && minDET_pipe == 0) { + if (2.0 * ((double) RoundedUpMaxSwathSizeBytesY[k] + + (double) RoundedUpMaxSwathSizeBytesC[k]) / 1024.0 <= minDET) + minDET_pipe = minDET; + minDET = minDET + 64; + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d minDET = %d\n", __func__, k, minDET); + dml_print("DML::%s: k=%0d max_minDET = %d\n", __func__, k, max_minDET); + dml_print("DML::%s: k=%0d minDET_pipe = %d\n", __func__, k, minDET_pipe); + dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesY = %d\n", __func__, k, + RoundedUpMaxSwathSizeBytesY[k]); + dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesC = %d\n", __func__, k, + RoundedUpMaxSwathSizeBytesC[k]); +#endif + + if (minDET_pipe == 0) { + minDET_pipe = dml_max(128, dml_ceil(((double)RoundedUpMaxSwathSizeBytesY[k] + + (double)RoundedUpMaxSwathSizeBytesC[k]) / 1024.0, 64)); +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d minDET_pipe = %d (assume each plane take half DET)\n", + __func__, k, minDET_pipe); +#endif + } + + if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) { + DETBufferSizeInKByte[k] = 0; + } else if (DETSizeOverride[k] > 0) { + DETBufferSizeInKByte[k] = DETSizeOverride[k]; + DETBufferSizePoolInKByte = DETBufferSizePoolInKByte - + (ForceSingleDPP ? 1 : DPPPerSurface[k]) * DETSizeOverride[k]; + } else if ((ForceSingleDPP ? 1 : DPPPerSurface[k]) * minDET_pipe <= DETBufferSizePoolInKByte) { + DETBufferSizeInKByte[k] = minDET_pipe; + DETBufferSizePoolInKByte = DETBufferSizePoolInKByte - + (ForceSingleDPP ? 1 : DPPPerSurface[k]) * minDET_pipe; + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d DPPPerSurface = %d\n", __func__, k, DPPPerSurface[k]); + dml_print("DML::%s: k=%d DETSizeOverride = %d\n", __func__, k, DETSizeOverride[k]); + dml_print("DML::%s: k=%d DETBufferSizeInKByte = %d\n", __func__, k, DETBufferSizeInKByte[k]); + dml_print("DML::%s: DETBufferSizePoolInKByte = %d\n", __func__, DETBufferSizePoolInKByte); +#endif + } + + TotalBandwidth = 0; + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) + TotalBandwidth = TotalBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k]; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: --- Before bandwidth adjustment ---\n", __func__); + for (uint k = 0; k < NumberOfActiveSurfaces; ++k) + dml_print("DML::%s: k=%d DETBufferSizeInKByte = %d\n", __func__, k, DETBufferSizeInKByte[k]); + dml_print("DML::%s: --- DET allocation with bandwidth ---\n", __func__); + dml_print("DML::%s: TotalBandwidth = %f\n", __func__, TotalBandwidth); +#endif + BandwidthOfSurfacesNotAssignedDETPiece = TotalBandwidth; + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + + if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) { + DETPieceAssignedToThisSurfaceAlready[k] = true; + } else if (DETSizeOverride[k] > 0 || (((double) (ForceSingleDPP ? 1 : DPPPerSurface[k]) * + (double) DETBufferSizeInKByte[k] / (double) MaxTotalDETInKByte) >= + ((ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) / TotalBandwidth))) { + DETPieceAssignedToThisSurfaceAlready[k] = true; + BandwidthOfSurfacesNotAssignedDETPiece = BandwidthOfSurfacesNotAssignedDETPiece - + ReadBandwidthLuma[k] - ReadBandwidthChroma[k]; + } else { + DETPieceAssignedToThisSurfaceAlready[k] = false; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d DETPieceAssignedToThisSurfaceAlready = %d\n", __func__, k, + DETPieceAssignedToThisSurfaceAlready[k]); + dml_print("DML::%s: k=%d BandwidthOfSurfacesNotAssignedDETPiece = %f\n", __func__, k, + BandwidthOfSurfacesNotAssignedDETPiece); +#endif + } + + for (j = 0; j < NumberOfActiveSurfaces; ++j) { + NextPotentialSurfaceToAssignDETPieceFound = false; + NextSurfaceToAssignDETPiece = 0; + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: j=%d k=%d, ReadBandwidthLuma[k] = %f\n", __func__, j, k, + ReadBandwidthLuma[k]); + dml_print("DML::%s: j=%d k=%d, ReadBandwidthChroma[k] = %f\n", __func__, j, k, + ReadBandwidthChroma[k]); + dml_print("DML::%s: j=%d k=%d, ReadBandwidthLuma[Next] = %f\n", __func__, j, k, + ReadBandwidthLuma[NextSurfaceToAssignDETPiece]); + dml_print("DML::%s: j=%d k=%d, ReadBandwidthChroma[Next] = %f\n", __func__, j, k, + ReadBandwidthChroma[NextSurfaceToAssignDETPiece]); + dml_print("DML::%s: j=%d k=%d, NextSurfaceToAssignDETPiece = %d\n", __func__, j, k, + NextSurfaceToAssignDETPiece); +#endif + if (!DETPieceAssignedToThisSurfaceAlready[k] && + (!NextPotentialSurfaceToAssignDETPieceFound || + ReadBandwidthLuma[k] + ReadBandwidthChroma[k] < + ReadBandwidthLuma[NextSurfaceToAssignDETPiece] + + ReadBandwidthChroma[NextSurfaceToAssignDETPiece])) { + NextSurfaceToAssignDETPiece = k; + NextPotentialSurfaceToAssignDETPieceFound = true; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: j=%d k=%d, DETPieceAssignedToThisSurfaceAlready = %d\n", + __func__, j, k, DETPieceAssignedToThisSurfaceAlready[k]); + dml_print("DML::%s: j=%d k=%d, NextPotentialSurfaceToAssignDETPieceFound = %d\n", + __func__, j, k, NextPotentialSurfaceToAssignDETPieceFound); +#endif + } + + if (NextPotentialSurfaceToAssignDETPieceFound) { + // Note: To show the banker's rounding behavior in VBA and also the fact + // that the DET buffer size varies due to precision issue + // + //double tmp1 = ((double) DETBufferSizePoolInKByte * + // (ReadBandwidthLuma[NextSurfaceToAssignDETPiece] + + // ReadBandwidthChroma[NextSurfaceToAssignDETPiece]) / + // BandwidthOfSurfacesNotAssignedDETPiece / + // ((ForceSingleDPP ? 1 : DPPPerSurface[NextSurfaceToAssignDETPiece]) * 64.0)); + //double tmp2 = dml_round((double) DETBufferSizePoolInKByte * + // (ReadBandwidthLuma[NextSurfaceToAssignDETPiece] + + // ReadBandwidthChroma[NextSurfaceToAssignDETPiece]) / + //BandwidthOfSurfacesNotAssignedDETPiece / + // ((ForceSingleDPP ? 1 : DPPPerSurface[NextSurfaceToAssignDETPiece]) * 64.0)); + // + //dml_print("DML::%s: j=%d, tmp1 = %f\n", __func__, j, tmp1); + //dml_print("DML::%s: j=%d, tmp2 = %f\n", __func__, j, tmp2); + + NextDETBufferPieceInKByte = dml_min( + dml_round((double) DETBufferSizePoolInKByte * + (ReadBandwidthLuma[NextSurfaceToAssignDETPiece] + + ReadBandwidthChroma[NextSurfaceToAssignDETPiece]) / + BandwidthOfSurfacesNotAssignedDETPiece / + ((ForceSingleDPP ? 1 : + DPPPerSurface[NextSurfaceToAssignDETPiece]) * 64.0)) * + (ForceSingleDPP ? 1 : + DPPPerSurface[NextSurfaceToAssignDETPiece]) * 64.0, + dml_floor((double) DETBufferSizePoolInKByte, + (ForceSingleDPP ? 1 : + DPPPerSurface[NextSurfaceToAssignDETPiece]) * 64.0)); + + // Above calculation can assign the entire DET buffer allocation to a single pipe. + // We should limit the per-pipe DET size to the nominal / max per pipe. + if (NextDETBufferPieceInKByte > nomDETInKByte * (ForceSingleDPP ? 1 : DPPPerSurface[k])) { + if (DETBufferSizeInKByte[NextSurfaceToAssignDETPiece] < + nomDETInKByte * (ForceSingleDPP ? 1 : DPPPerSurface[k])) { + NextDETBufferPieceInKByte = nomDETInKByte * (ForceSingleDPP ? 1 : DPPPerSurface[k]) - + DETBufferSizeInKByte[NextSurfaceToAssignDETPiece]; + } else { + // Case where DETBufferSizeInKByte[NextSurfaceToAssignDETPiece] + // already has the max per-pipe value + NextDETBufferPieceInKByte = 0; + } + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: j=%0d, DETBufferSizePoolInKByte = %d\n", __func__, j, + DETBufferSizePoolInKByte); + dml_print("DML::%s: j=%0d, NextSurfaceToAssignDETPiece = %d\n", __func__, j, + NextSurfaceToAssignDETPiece); + dml_print("DML::%s: j=%0d, ReadBandwidthLuma[%0d] = %f\n", __func__, j, + NextSurfaceToAssignDETPiece, ReadBandwidthLuma[NextSurfaceToAssignDETPiece]); + dml_print("DML::%s: j=%0d, ReadBandwidthChroma[%0d] = %f\n", __func__, j, + NextSurfaceToAssignDETPiece, ReadBandwidthChroma[NextSurfaceToAssignDETPiece]); + dml_print("DML::%s: j=%0d, BandwidthOfSurfacesNotAssignedDETPiece = %f\n", + __func__, j, BandwidthOfSurfacesNotAssignedDETPiece); + dml_print("DML::%s: j=%0d, NextDETBufferPieceInKByte = %d\n", __func__, j, + NextDETBufferPieceInKByte); + dml_print("DML::%s: j=%0d, DETBufferSizeInKByte[%0d] increases from %0d ", + __func__, j, NextSurfaceToAssignDETPiece, + DETBufferSizeInKByte[NextSurfaceToAssignDETPiece]); +#endif + + DETBufferSizeInKByte[NextSurfaceToAssignDETPiece] = + DETBufferSizeInKByte[NextSurfaceToAssignDETPiece] + + NextDETBufferPieceInKByte + / (ForceSingleDPP ? 1 : DPPPerSurface[NextSurfaceToAssignDETPiece]); +#ifdef __DML_VBA_DEBUG__ + dml_print("to %0d\n", DETBufferSizeInKByte[NextSurfaceToAssignDETPiece]); +#endif + + DETBufferSizePoolInKByte = DETBufferSizePoolInKByte - NextDETBufferPieceInKByte; + DETPieceAssignedToThisSurfaceAlready[NextSurfaceToAssignDETPiece] = true; + BandwidthOfSurfacesNotAssignedDETPiece = BandwidthOfSurfacesNotAssignedDETPiece - + (ReadBandwidthLuma[NextSurfaceToAssignDETPiece] + + ReadBandwidthChroma[NextSurfaceToAssignDETPiece]); + } + } + *CompressedBufferSizeInkByte = MinCompressedBufferSizeInKByte; + } + *CompressedBufferSizeInkByte = *CompressedBufferSizeInkByte * CompressedBufferSegmentSizeInkByteFinal / 64; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: --- After bandwidth adjustment ---\n", __func__); + dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, *CompressedBufferSizeInkByte); + for (uint k = 0; k < NumberOfActiveSurfaces; ++k) { + dml_print("DML::%s: k=%d DETBufferSizeInKByte = %d (TotalReadBandWidth=%f)\n", + __func__, k, DETBufferSizeInKByte[k], ReadBandwidthLuma[k] + ReadBandwidthChroma[k]); + } +#endif +} // CalculateDETBufferSize + +void dml32_CalculateODMMode( + unsigned int MaximumPixelsPerLinePerDSCUnit, + unsigned int HActive, + enum output_encoder_class Output, + enum odm_combine_policy ODMUse, + double StateDispclk, + double MaxDispclk, + bool DSCEnable, + unsigned int TotalNumberOfActiveDPP, + unsigned int MaxNumDPP, + double PixelClock, + double DISPCLKDPPCLKDSCCLKDownSpreading, + double DISPCLKRampingMargin, + double DISPCLKDPPCLKVCOSpeed, + + /* Output */ + bool *TotalAvailablePipesSupport, + unsigned int *NumberOfDPP, + enum odm_combine_mode *ODMMode, + double *RequiredDISPCLKPerSurface) +{ + + double SurfaceRequiredDISPCLKWithoutODMCombine; + double SurfaceRequiredDISPCLKWithODMCombineTwoToOne; + double SurfaceRequiredDISPCLKWithODMCombineFourToOne; + + SurfaceRequiredDISPCLKWithoutODMCombine = dml32_CalculateRequiredDispclk(dm_odm_combine_mode_disabled, + PixelClock, DISPCLKDPPCLKDSCCLKDownSpreading, DISPCLKRampingMargin, DISPCLKDPPCLKVCOSpeed, + MaxDispclk); + SurfaceRequiredDISPCLKWithODMCombineTwoToOne = dml32_CalculateRequiredDispclk(dm_odm_combine_mode_2to1, + PixelClock, DISPCLKDPPCLKDSCCLKDownSpreading, DISPCLKRampingMargin, DISPCLKDPPCLKVCOSpeed, + MaxDispclk); + SurfaceRequiredDISPCLKWithODMCombineFourToOne = dml32_CalculateRequiredDispclk(dm_odm_combine_mode_4to1, + PixelClock, DISPCLKDPPCLKDSCCLKDownSpreading, DISPCLKRampingMargin, DISPCLKDPPCLKVCOSpeed, + MaxDispclk); + *TotalAvailablePipesSupport = true; + *ODMMode = dm_odm_combine_mode_disabled; // initialize as disable + + if (ODMUse == dm_odm_combine_policy_none) + *ODMMode = dm_odm_combine_mode_disabled; + + *RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithoutODMCombine; + *NumberOfDPP = 0; + + // FIXME check ODMUse == "" condition does it mean bypass or Gabriel means something like don't care?? + // (ODMUse == "" || ODMUse == "CombineAsNeeded") + + if (!(Output == dm_hdmi || Output == dm_dp || Output == dm_edp) && (ODMUse == dm_odm_combine_policy_4to1 || + ((SurfaceRequiredDISPCLKWithODMCombineTwoToOne > StateDispclk || + (DSCEnable && (HActive > 2 * MaximumPixelsPerLinePerDSCUnit)))))) { + if (TotalNumberOfActiveDPP + 4 <= MaxNumDPP) { + *ODMMode = dm_odm_combine_mode_4to1; + *RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithODMCombineFourToOne; + *NumberOfDPP = 4; + } else { + *TotalAvailablePipesSupport = false; + } + } else if (Output != dm_hdmi && (ODMUse == dm_odm_combine_policy_2to1 || + (((SurfaceRequiredDISPCLKWithoutODMCombine > StateDispclk && + SurfaceRequiredDISPCLKWithODMCombineTwoToOne <= StateDispclk) || + (DSCEnable && (HActive > MaximumPixelsPerLinePerDSCUnit)))))) { + if (TotalNumberOfActiveDPP + 2 <= MaxNumDPP) { + *ODMMode = dm_odm_combine_mode_2to1; + *RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithODMCombineTwoToOne; + *NumberOfDPP = 2; + } else { + *TotalAvailablePipesSupport = false; + } + } else { + if (TotalNumberOfActiveDPP + 1 <= MaxNumDPP) + *NumberOfDPP = 1; + else + *TotalAvailablePipesSupport = false; + } +} + +double dml32_CalculateRequiredDispclk( + enum odm_combine_mode ODMMode, + double PixelClock, + double DISPCLKDPPCLKDSCCLKDownSpreading, + double DISPCLKRampingMargin, + double DISPCLKDPPCLKVCOSpeed, + double MaxDispclk) +{ + double RequiredDispclk = 0.; + double PixelClockAfterODM; + double DISPCLKWithRampingRoundedToDFSGranularity; + double DISPCLKWithoutRampingRoundedToDFSGranularity; + double MaxDispclkRoundedDownToDFSGranularity; + + if (ODMMode == dm_odm_combine_mode_4to1) + PixelClockAfterODM = PixelClock / 4; + else if (ODMMode == dm_odm_combine_mode_2to1) + PixelClockAfterODM = PixelClock / 2; + else + PixelClockAfterODM = PixelClock; + + + DISPCLKWithRampingRoundedToDFSGranularity = dml32_RoundToDFSGranularity( + PixelClockAfterODM * (1 + DISPCLKDPPCLKDSCCLKDownSpreading / 100) + * (1 + DISPCLKRampingMargin / 100), 1, DISPCLKDPPCLKVCOSpeed); + + DISPCLKWithoutRampingRoundedToDFSGranularity = dml32_RoundToDFSGranularity( + PixelClockAfterODM * (1 + DISPCLKDPPCLKDSCCLKDownSpreading / 100), 1, DISPCLKDPPCLKVCOSpeed); + + MaxDispclkRoundedDownToDFSGranularity = dml32_RoundToDFSGranularity(MaxDispclk, 0, DISPCLKDPPCLKVCOSpeed); + + if (DISPCLKWithoutRampingRoundedToDFSGranularity > MaxDispclkRoundedDownToDFSGranularity) + RequiredDispclk = DISPCLKWithoutRampingRoundedToDFSGranularity; + else if (DISPCLKWithRampingRoundedToDFSGranularity > MaxDispclkRoundedDownToDFSGranularity) + RequiredDispclk = MaxDispclkRoundedDownToDFSGranularity; + else + RequiredDispclk = DISPCLKWithRampingRoundedToDFSGranularity; + + return RequiredDispclk; +} + +double dml32_RoundToDFSGranularity(double Clock, bool round_up, double VCOSpeed) +{ + if (Clock <= 0.0) + return 0.0; + + if (round_up) + return VCOSpeed * 4.0 / dml_floor(VCOSpeed * 4.0 / Clock, 1.0); + else + return VCOSpeed * 4.0 / dml_ceil(VCOSpeed * 4.0 / Clock, 1.0); +} + +void dml32_CalculateOutputLink( + double PHYCLKPerState, + double PHYCLKD18PerState, + double PHYCLKD32PerState, + double Downspreading, + bool IsMainSurfaceUsingTheIndicatedTiming, + enum output_encoder_class Output, + enum output_format_class OutputFormat, + unsigned int HTotal, + unsigned int HActive, + double PixelClockBackEnd, + double ForcedOutputLinkBPP, + unsigned int DSCInputBitPerComponent, + unsigned int NumberOfDSCSlices, + double AudioSampleRate, + unsigned int AudioSampleLayout, + enum odm_combine_mode ODMModeNoDSC, + enum odm_combine_mode ODMModeDSC, + bool DSCEnable, + unsigned int OutputLinkDPLanes, + enum dm_output_link_dp_rate OutputLinkDPRate, + + /* Output */ + bool *RequiresDSC, + double *RequiresFEC, + double *OutBpp, + enum dm_output_type *OutputType, + enum dm_output_rate *OutputRate, + unsigned int *RequiredSlots) +{ + bool LinkDSCEnable; + unsigned int dummy; + *RequiresDSC = false; + *RequiresFEC = false; + *OutBpp = 0; + *OutputType = dm_output_type_unknown; + *OutputRate = dm_output_rate_unknown; + + if (IsMainSurfaceUsingTheIndicatedTiming) { + if (Output == dm_hdmi) { + *RequiresDSC = false; + *RequiresFEC = false; + *OutBpp = dml32_TruncToValidBPP(dml_min(600, PHYCLKPerState) * 10, 3, HTotal, HActive, + PixelClockBackEnd, ForcedOutputLinkBPP, false, Output, OutputFormat, + DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + ODMModeNoDSC, ODMModeDSC, &dummy); + //OutputTypeAndRate = "HDMI"; + *OutputType = dm_output_type_hdmi; + + } else if (Output == dm_dp || Output == dm_dp2p0 || Output == dm_edp) { + if (DSCEnable == true) { + *RequiresDSC = true; + LinkDSCEnable = true; + if (Output == dm_dp || Output == dm_dp2p0) + *RequiresFEC = true; + else + *RequiresFEC = false; + } else { + *RequiresDSC = false; + LinkDSCEnable = false; + if (Output == dm_dp2p0) + *RequiresFEC = true; + else + *RequiresFEC = false; + } + if (Output == dm_dp2p0) { + *OutBpp = 0; + if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_uhbr10) && + PHYCLKD32PerState >= 10000 / 32) { + *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 10000, + OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, + ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, + DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, + AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); + if (*OutBpp == 0 && PHYCLKD32PerState < 13500 / 32 && DSCEnable == true && + ForcedOutputLinkBPP == 0) { + *RequiresDSC = true; + LinkDSCEnable = true; + *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 10000, + OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, + ForcedOutputLinkBPP, LinkDSCEnable, Output, + OutputFormat, DSCInputBitPerComponent, + NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + ODMModeNoDSC, ODMModeDSC, RequiredSlots); + } + //OutputTypeAndRate = Output & " UHBR10"; + *OutputType = dm_output_type_dp2p0; + *OutputRate = dm_output_rate_dp_rate_uhbr10; + } + if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_uhbr13p5) && + *OutBpp == 0 && PHYCLKD32PerState >= 13500 / 32) { + *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 13500, + OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, + ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, + DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, + AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); + + if (*OutBpp == 0 && PHYCLKD32PerState < 20000 / 32 && DSCEnable == true && + ForcedOutputLinkBPP == 0) { + *RequiresDSC = true; + LinkDSCEnable = true; + *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 13500, + OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, + ForcedOutputLinkBPP, LinkDSCEnable, Output, + OutputFormat, DSCInputBitPerComponent, + NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + ODMModeNoDSC, ODMModeDSC, RequiredSlots); + } + //OutputTypeAndRate = Output & " UHBR13p5"; + *OutputType = dm_output_type_dp2p0; + *OutputRate = dm_output_rate_dp_rate_uhbr13p5; + } + if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_uhbr20) && + *OutBpp == 0 && PHYCLKD32PerState >= 20000 / 32) { + *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 20000, + OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, + ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, + DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, + AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); + if (*OutBpp == 0 && DSCEnable == true && ForcedOutputLinkBPP == 0) { + *RequiresDSC = true; + LinkDSCEnable = true; + *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 20000, + OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, + ForcedOutputLinkBPP, LinkDSCEnable, Output, + OutputFormat, DSCInputBitPerComponent, + NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + ODMModeNoDSC, ODMModeDSC, RequiredSlots); + } + //OutputTypeAndRate = Output & " UHBR20"; + *OutputType = dm_output_type_dp2p0; + *OutputRate = dm_output_rate_dp_rate_uhbr20; + } + } else { + *OutBpp = 0; + if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_hbr) && + PHYCLKPerState >= 270) { + *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 2700, + OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, + ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, + DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, + AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); + if (*OutBpp == 0 && PHYCLKPerState < 540 && DSCEnable == true && + ForcedOutputLinkBPP == 0) { + *RequiresDSC = true; + LinkDSCEnable = true; + if (Output == dm_dp) + *RequiresFEC = true; + *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 2700, + OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, + ForcedOutputLinkBPP, LinkDSCEnable, Output, + OutputFormat, DSCInputBitPerComponent, + NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + ODMModeNoDSC, ODMModeDSC, RequiredSlots); + } + //OutputTypeAndRate = Output & " HBR"; + *OutputType = (Output == dm_dp) ? dm_output_type_dp : dm_output_type_edp; + *OutputRate = dm_output_rate_dp_rate_hbr; + } + if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_hbr2) && + *OutBpp == 0 && PHYCLKPerState >= 540) { + *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 5400, + OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, + ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, + DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, + AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); + + if (*OutBpp == 0 && PHYCLKPerState < 810 && DSCEnable == true && + ForcedOutputLinkBPP == 0) { + *RequiresDSC = true; + LinkDSCEnable = true; + if (Output == dm_dp) + *RequiresFEC = true; + + *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 5400, + OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, + ForcedOutputLinkBPP, LinkDSCEnable, Output, + OutputFormat, DSCInputBitPerComponent, + NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + ODMModeNoDSC, ODMModeDSC, RequiredSlots); + } + //OutputTypeAndRate = Output & " HBR2"; + *OutputType = (Output == dm_dp) ? dm_output_type_dp : dm_output_type_edp; + *OutputRate = dm_output_rate_dp_rate_hbr2; + } + if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_hbr3) && *OutBpp == 0 && PHYCLKPerState >= 810) { + *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 8100, + OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, + ForcedOutputLinkBPP, LinkDSCEnable, Output, + OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, + AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, + RequiredSlots); + + if (*OutBpp == 0 && DSCEnable == true && ForcedOutputLinkBPP == 0) { + *RequiresDSC = true; + LinkDSCEnable = true; + if (Output == dm_dp) + *RequiresFEC = true; + + *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 8100, + OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, + ForcedOutputLinkBPP, LinkDSCEnable, Output, + OutputFormat, DSCInputBitPerComponent, + NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + ODMModeNoDSC, ODMModeDSC, RequiredSlots); + } + //OutputTypeAndRate = Output & " HBR3"; + *OutputType = (Output == dm_dp) ? dm_output_type_dp : dm_output_type_edp; + *OutputRate = dm_output_rate_dp_rate_hbr3; + } + } + } + } +} + +void dml32_CalculateDPPCLK( + unsigned int NumberOfActiveSurfaces, + double DISPCLKDPPCLKDSCCLKDownSpreading, + double DISPCLKDPPCLKVCOSpeed, + double DPPCLKUsingSingleDPP[], + unsigned int DPPPerSurface[], + + /* output */ + double *GlobalDPPCLK, + double Dppclk[]) +{ + unsigned int k; + *GlobalDPPCLK = 0; + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + Dppclk[k] = DPPCLKUsingSingleDPP[k] / DPPPerSurface[k] * (1 + DISPCLKDPPCLKDSCCLKDownSpreading / 100); + *GlobalDPPCLK = dml_max(*GlobalDPPCLK, Dppclk[k]); + } + *GlobalDPPCLK = dml32_RoundToDFSGranularity(*GlobalDPPCLK, 1, DISPCLKDPPCLKVCOSpeed); + for (k = 0; k < NumberOfActiveSurfaces; ++k) + Dppclk[k] = *GlobalDPPCLK / 255 * dml_ceil(Dppclk[k] * 255.0 / *GlobalDPPCLK, 1.0); +} + +double dml32_TruncToValidBPP( + double LinkBitRate, + unsigned int Lanes, + unsigned int HTotal, + unsigned int HActive, + double PixelClock, + double DesiredBPP, + bool DSCEnable, + enum output_encoder_class Output, + enum output_format_class Format, + unsigned int DSCInputBitPerComponent, + unsigned int DSCSlices, + unsigned int AudioRate, + unsigned int AudioLayout, + enum odm_combine_mode ODMModeNoDSC, + enum odm_combine_mode ODMModeDSC, + /* Output */ + unsigned int *RequiredSlots) +{ + double MaxLinkBPP; + unsigned int MinDSCBPP; + double MaxDSCBPP; + unsigned int NonDSCBPP0; + unsigned int NonDSCBPP1; + unsigned int NonDSCBPP2; + unsigned int NonDSCBPP3; + + if (Format == dm_420) { + NonDSCBPP0 = 12; + NonDSCBPP1 = 15; + NonDSCBPP2 = 18; + MinDSCBPP = 6; + MaxDSCBPP = 1.5 * DSCInputBitPerComponent - 1 / 16; + } else if (Format == dm_444) { + NonDSCBPP0 = 18; + NonDSCBPP1 = 24; + NonDSCBPP2 = 30; + NonDSCBPP3 = 36; + MinDSCBPP = 8; + MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16; + } else { + if (Output == dm_hdmi) { + NonDSCBPP0 = 24; + NonDSCBPP1 = 24; + NonDSCBPP2 = 24; + } else { + NonDSCBPP0 = 16; + NonDSCBPP1 = 20; + NonDSCBPP2 = 24; + } + if (Format == dm_n422) { + MinDSCBPP = 7; + MaxDSCBPP = 2 * DSCInputBitPerComponent - 1.0 / 16.0; + } else { + MinDSCBPP = 8; + MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16.0; + } + } + if (Output == dm_dp2p0) { + MaxLinkBPP = LinkBitRate * Lanes / PixelClock * 128 / 132 * 383 / 384 * 65536 / 65540; + } else if (DSCEnable && Output == dm_dp) { + MaxLinkBPP = LinkBitRate / 10 * 8 * Lanes / PixelClock * (1 - 2.4 / 100); + } else { + MaxLinkBPP = LinkBitRate / 10 * 8 * Lanes / PixelClock; + } + + if (DSCEnable) { + if (ODMModeDSC == dm_odm_combine_mode_4to1) + MaxLinkBPP = dml_min(MaxLinkBPP, 16); + else if (ODMModeDSC == dm_odm_combine_mode_2to1) + MaxLinkBPP = dml_min(MaxLinkBPP, 32); + else if (ODMModeDSC == dm_odm_split_mode_1to2) + MaxLinkBPP = 2 * MaxLinkBPP; + } else { + if (ODMModeNoDSC == dm_odm_combine_mode_4to1) + MaxLinkBPP = dml_min(MaxLinkBPP, 16); + else if (ODMModeNoDSC == dm_odm_combine_mode_2to1) + MaxLinkBPP = dml_min(MaxLinkBPP, 32); + else if (ODMModeNoDSC == dm_odm_split_mode_1to2) + MaxLinkBPP = 2 * MaxLinkBPP; + } + + if (DesiredBPP == 0) { + if (DSCEnable) { + if (MaxLinkBPP < MinDSCBPP) + return BPP_INVALID; + else if (MaxLinkBPP >= MaxDSCBPP) + return MaxDSCBPP; + else + return dml_floor(16.0 * MaxLinkBPP, 1.0) / 16.0; + } else { + if (MaxLinkBPP >= NonDSCBPP3) + return NonDSCBPP3; + else if (MaxLinkBPP >= NonDSCBPP2) + return NonDSCBPP2; + else if (MaxLinkBPP >= NonDSCBPP1) + return NonDSCBPP1; + else if (MaxLinkBPP >= NonDSCBPP0) + return 16.0; + else + return BPP_INVALID; + } + } else { + if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || + DesiredBPP == NonDSCBPP0 || DesiredBPP == NonDSCBPP3)) || + (DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP))) + return BPP_INVALID; + else + return DesiredBPP; + } + + *RequiredSlots = dml_ceil(DesiredBPP / MaxLinkBPP * 64, 1); + + return BPP_INVALID; +} // TruncToValidBPP + +double dml32_RequiredDTBCLK( + bool DSCEnable, + double PixelClock, + enum output_format_class OutputFormat, + double OutputBpp, + unsigned int DSCSlices, + unsigned int HTotal, + unsigned int HActive, + unsigned int AudioRate, + unsigned int AudioLayout) +{ + double PixelWordRate = PixelClock / (OutputFormat == dm_444 ? 1 : 2); + double HCActive = dml_ceil(DSCSlices * dml_ceil(OutputBpp * + dml_ceil(HActive / DSCSlices, 1) / 8.0, 1) / 3.0, 1); + double HCBlank = 64 + 32 * + dml_ceil(AudioRate * (AudioLayout == 1 ? 1 : 0.25) * HTotal / (PixelClock * 1000), 1); + double AverageTribyteRate = PixelWordRate * (HCActive + HCBlank) / HTotal; + double HActiveTribyteRate = PixelWordRate * HCActive / HActive; + + if (DSCEnable != true) + return dml_max(PixelClock / 4.0 * OutputBpp / 24.0, 25.0); + + return dml_max4(PixelWordRate / 4.0, AverageTribyteRate / 4.0, HActiveTribyteRate / 4.0, 25.0) * 1.002; +} + +unsigned int dml32_DSCDelayRequirement(bool DSCEnabled, + enum odm_combine_mode ODMMode, + unsigned int DSCInputBitPerComponent, + double OutputBpp, + unsigned int HActive, + unsigned int HTotal, + unsigned int NumberOfDSCSlices, + enum output_format_class OutputFormat, + enum output_encoder_class Output, + double PixelClock, + double PixelClockBackEnd) +{ + unsigned int DSCDelayRequirement_val; + + if (DSCEnabled == true && OutputBpp != 0) { + if (ODMMode == dm_odm_combine_mode_4to1) { + DSCDelayRequirement_val = 4 * (dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, + dml_ceil(HActive / NumberOfDSCSlices, 1), NumberOfDSCSlices / 4, + OutputFormat, Output) + dml32_dscComputeDelay(OutputFormat, Output)); + } else if (ODMMode == dm_odm_combine_mode_2to1) { + DSCDelayRequirement_val = 2 * (dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, + dml_ceil(HActive / NumberOfDSCSlices, 1), NumberOfDSCSlices / 2, + OutputFormat, Output) + dml32_dscComputeDelay(OutputFormat, Output)); + } else { + DSCDelayRequirement_val = dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, + dml_ceil(HActive / NumberOfDSCSlices, 1), NumberOfDSCSlices, + OutputFormat, Output) + dml32_dscComputeDelay(OutputFormat, Output); + } + + DSCDelayRequirement_val = DSCDelayRequirement_val + (HTotal - HActive) * + dml_ceil(DSCDelayRequirement_val / HActive, 1); + + DSCDelayRequirement_val = DSCDelayRequirement_val * PixelClock / PixelClockBackEnd; + + } else { + DSCDelayRequirement_val = 0; + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: DSCEnabled = %d\n", __func__, DSCEnabled); + dml_print("DML::%s: OutputBpp = %f\n", __func__, OutputBpp); + dml_print("DML::%s: HActive = %d\n", __func__, HActive); + dml_print("DML::%s: OutputFormat = %d\n", __func__, OutputFormat); + dml_print("DML::%s: DSCInputBitPerComponent = %d\n", __func__, DSCInputBitPerComponent); + dml_print("DML::%s: NumberOfDSCSlices = %d\n", __func__, NumberOfDSCSlices); + dml_print("DML::%s: DSCDelayRequirement_val = %d\n", __func__, DSCDelayRequirement_val); +#endif + + return DSCDelayRequirement_val; +} + +void dml32_CalculateSurfaceSizeInMall( + unsigned int NumberOfActiveSurfaces, + unsigned int MALLAllocatedForDCN, + enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[], + bool DCCEnable[], + bool ViewportStationary[], + unsigned int ViewportXStartY[], + unsigned int ViewportYStartY[], + unsigned int ViewportXStartC[], + unsigned int ViewportYStartC[], + unsigned int ViewportWidthY[], + unsigned int ViewportHeightY[], + unsigned int BytesPerPixelY[], + unsigned int ViewportWidthC[], + unsigned int ViewportHeightC[], + unsigned int BytesPerPixelC[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int ReadBlockWidthY[], + unsigned int ReadBlockWidthC[], + unsigned int ReadBlockHeightY[], + unsigned int ReadBlockHeightC[], + + /* Output */ + unsigned int SurfaceSizeInMALL[], + bool *ExceededMALLSize) +{ + unsigned int TotalSurfaceSizeInMALL = 0; + unsigned int k; + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (ViewportStationary[k]) { + SurfaceSizeInMALL[k] = dml_min(dml_ceil(SurfaceWidthY[k], ReadBlockWidthY[k]), + dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + ReadBlockWidthY[k] - 1, + ReadBlockWidthY[k]) - dml_floor(ViewportXStartY[k], + ReadBlockWidthY[k])) * dml_min(dml_ceil(SurfaceHeightY[k], + ReadBlockHeightY[k]), dml_floor(ViewportYStartY[k] + + ViewportHeightY[k] + ReadBlockHeightY[k] - 1, ReadBlockHeightY[k]) - + dml_floor(ViewportYStartY[k], ReadBlockHeightY[k])) * BytesPerPixelY[k]; + + if (ReadBlockWidthC[k] > 0) { + SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] + + dml_min(dml_ceil(SurfaceWidthC[k], ReadBlockWidthC[k]), + dml_floor(ViewportXStartC[k] + ViewportWidthC[k] + + ReadBlockWidthC[k] - 1, ReadBlockWidthC[k]) - + dml_floor(ViewportXStartC[k], ReadBlockWidthC[k])) * + dml_min(dml_ceil(SurfaceHeightC[k], ReadBlockHeightC[k]), + dml_floor(ViewportYStartC[k] + ViewportHeightC[k] + + ReadBlockHeightC[k] - 1, ReadBlockHeightC[k]) - + dml_floor(ViewportYStartC[k], ReadBlockHeightC[k])) * + BytesPerPixelC[k]; + } + if (DCCEnable[k] == true) { + SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] + + dml_min(dml_ceil(SurfaceWidthY[k], 8 * Read256BytesBlockWidthY[k]), + dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + 8 * + Read256BytesBlockWidthY[k] - 1, 8 * Read256BytesBlockWidthY[k]) + - dml_floor(ViewportXStartY[k], 8 * Read256BytesBlockWidthY[k])) + * dml_min(dml_ceil(SurfaceHeightY[k], 8 * + Read256BytesBlockHeightY[k]), dml_floor(ViewportYStartY[k] + + ViewportHeightY[k] + 8 * Read256BytesBlockHeightY[k] - 1, 8 * + Read256BytesBlockHeightY[k]) - dml_floor(ViewportYStartY[k], 8 + * Read256BytesBlockHeightY[k])) * BytesPerPixelY[k] / 256; + if (Read256BytesBlockWidthC[k] > 0) { + SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] + + dml_min(dml_ceil(SurfaceWidthC[k], 8 * + Read256BytesBlockWidthC[k]), + dml_floor(ViewportXStartC[k] + ViewportWidthC[k] + 8 + * Read256BytesBlockWidthC[k] - 1, 8 * + Read256BytesBlockWidthC[k]) - + dml_floor(ViewportXStartC[k], 8 * + Read256BytesBlockWidthC[k])) * + dml_min(dml_ceil(SurfaceHeightC[k], 8 * + Read256BytesBlockHeightC[k]), + dml_floor(ViewportYStartC[k] + ViewportHeightC[k] + + 8 * Read256BytesBlockHeightC[k] - 1, 8 * + Read256BytesBlockHeightC[k]) - + dml_floor(ViewportYStartC[k], 8 * + Read256BytesBlockHeightC[k])) * + BytesPerPixelC[k] / 256; + } + } + } else { + SurfaceSizeInMALL[k] = dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] + + ReadBlockWidthY[k] - 1), ReadBlockWidthY[k]) * + dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] + + ReadBlockHeightY[k] - 1), ReadBlockHeightY[k]) * + BytesPerPixelY[k]; + if (ReadBlockWidthC[k] > 0) { + SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] + + dml_ceil(dml_min(SurfaceWidthC[k], ViewportWidthC[k] + + ReadBlockWidthC[k] - 1), ReadBlockWidthC[k]) * + dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] + + ReadBlockHeightC[k] - 1), ReadBlockHeightC[k]) * + BytesPerPixelC[k]; + } + if (DCCEnable[k] == true) { + SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] + + dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] + 8 * + Read256BytesBlockWidthY[k] - 1), 8 * + Read256BytesBlockWidthY[k]) * + dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] + 8 * + Read256BytesBlockHeightY[k] - 1), 8 * + Read256BytesBlockHeightY[k]) * BytesPerPixelY[k] / 256; + + if (Read256BytesBlockWidthC[k] > 0) { + SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] + + dml_ceil(dml_min(SurfaceWidthC[k], ViewportWidthC[k] + 8 * + Read256BytesBlockWidthC[k] - 1), 8 * + Read256BytesBlockWidthC[k]) * + dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] + 8 * + Read256BytesBlockHeightC[k] - 1), 8 * + Read256BytesBlockHeightC[k]) * + BytesPerPixelC[k] / 256; + } + } + } + } + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (UseMALLForStaticScreen[k] == dm_use_mall_static_screen_enable) + TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k]; + } + *ExceededMALLSize = (TotalSurfaceSizeInMALL <= MALLAllocatedForDCN * 1024 * 1024 ? false : true); +} // CalculateSurfaceSizeInMall + +void dml32_CalculateVMRowAndSwath( + unsigned int NumberOfActiveSurfaces, + DmlPipe myPipe[], + unsigned int SurfaceSizeInMALL[], + unsigned int PTEBufferSizeInRequestsLuma, + unsigned int PTEBufferSizeInRequestsChroma, + unsigned int DCCMetaBufferSizeBytes, + enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[], + enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[], + unsigned int MALLAllocatedForDCN, + double SwathWidthY[], + double SwathWidthC[], + bool GPUVMEnable, + bool HostVMEnable, + unsigned int HostVMMaxNonCachedPageTableLevels, + unsigned int GPUVMMaxPageTableLevels, + unsigned int GPUVMMinPageSizeKBytes[], + unsigned int HostVMMinPageSize, + + /* Output */ + bool PTEBufferSizeNotExceeded[], + bool DCCMetaBufferSizeNotExceeded[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], + unsigned int dpte_row_height_luma[], + unsigned int dpte_row_height_chroma[], + unsigned int dpte_row_height_linear_luma[], // VBA_DELTA + unsigned int dpte_row_height_linear_chroma[], // VBA_DELTA + unsigned int meta_req_width[], + unsigned int meta_req_width_chroma[], + unsigned int meta_req_height[], + unsigned int meta_req_height_chroma[], + unsigned int meta_row_width[], + unsigned int meta_row_width_chroma[], + unsigned int meta_row_height[], + unsigned int meta_row_height_chroma[], + unsigned int vm_group_bytes[], + unsigned int dpte_group_bytes[], + unsigned int PixelPTEReqWidthY[], + unsigned int PixelPTEReqHeightY[], + unsigned int PTERequestSizeY[], + unsigned int PixelPTEReqWidthC[], + unsigned int PixelPTEReqHeightC[], + unsigned int PTERequestSizeC[], + unsigned int dpde0_bytes_per_frame_ub_l[], + unsigned int meta_pte_bytes_per_frame_ub_l[], + unsigned int dpde0_bytes_per_frame_ub_c[], + unsigned int meta_pte_bytes_per_frame_ub_c[], + double PrefetchSourceLinesY[], + double PrefetchSourceLinesC[], + double VInitPreFillY[], + double VInitPreFillC[], + unsigned int MaxNumSwathY[], + unsigned int MaxNumSwathC[], + double meta_row_bw[], + double dpte_row_bw[], + double PixelPTEBytesPerRow[], + double PDEAndMetaPTEBytesFrame[], + double MetaRowByte[], + bool use_one_row_for_frame[], + bool use_one_row_for_frame_flip[], + bool UsesMALLForStaticScreen[], + bool PTE_BUFFER_MODE[], + unsigned int BIGK_FRAGMENT_SIZE[]) +{ + unsigned int k; + unsigned int PTEBufferSizeInRequestsForLuma[DC__NUM_DPP__MAX]; + unsigned int PTEBufferSizeInRequestsForChroma[DC__NUM_DPP__MAX]; + unsigned int PDEAndMetaPTEBytesFrameY; + unsigned int PDEAndMetaPTEBytesFrameC; + unsigned int MetaRowByteY[DC__NUM_DPP__MAX]; + unsigned int MetaRowByteC[DC__NUM_DPP__MAX]; + unsigned int PixelPTEBytesPerRowY[DC__NUM_DPP__MAX]; + unsigned int PixelPTEBytesPerRowC[DC__NUM_DPP__MAX]; + unsigned int PixelPTEBytesPerRowY_one_row_per_frame[DC__NUM_DPP__MAX]; + unsigned int PixelPTEBytesPerRowC_one_row_per_frame[DC__NUM_DPP__MAX]; + unsigned int dpte_row_width_luma_ub_one_row_per_frame[DC__NUM_DPP__MAX]; + unsigned int dpte_row_height_luma_one_row_per_frame[DC__NUM_DPP__MAX]; + unsigned int dpte_row_width_chroma_ub_one_row_per_frame[DC__NUM_DPP__MAX]; + unsigned int dpte_row_height_chroma_one_row_per_frame[DC__NUM_DPP__MAX]; + bool one_row_per_frame_fits_in_buffer[DC__NUM_DPP__MAX]; + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (HostVMEnable == true) { + vm_group_bytes[k] = 512; + dpte_group_bytes[k] = 512; + } else if (GPUVMEnable == true) { + vm_group_bytes[k] = 2048; + if (GPUVMMinPageSizeKBytes[k] >= 64 && IsVertical(myPipe[k].SourceRotation)) + dpte_group_bytes[k] = 512; + else + dpte_group_bytes[k] = 2048; + } else { + vm_group_bytes[k] = 0; + dpte_group_bytes[k] = 0; + } + + if (myPipe[k].SourcePixelFormat == dm_420_8 || myPipe[k].SourcePixelFormat == dm_420_10 || + myPipe[k].SourcePixelFormat == dm_420_12 || + myPipe[k].SourcePixelFormat == dm_rgbe_alpha) { + if ((myPipe[k].SourcePixelFormat == dm_420_10 || myPipe[k].SourcePixelFormat == dm_420_12) && + !IsVertical(myPipe[k].SourceRotation)) { + PTEBufferSizeInRequestsForLuma[k] = + (PTEBufferSizeInRequestsLuma + PTEBufferSizeInRequestsChroma) / 2; + PTEBufferSizeInRequestsForChroma[k] = PTEBufferSizeInRequestsForLuma[k]; + } else { + PTEBufferSizeInRequestsForLuma[k] = PTEBufferSizeInRequestsLuma; + PTEBufferSizeInRequestsForChroma[k] = PTEBufferSizeInRequestsChroma; + } + + PDEAndMetaPTEBytesFrameC = dml32_CalculateVMAndRowBytes( + myPipe[k].ViewportStationary, + myPipe[k].DCCEnable, + myPipe[k].DPPPerSurface, + myPipe[k].BlockHeight256BytesC, + myPipe[k].BlockWidth256BytesC, + myPipe[k].SourcePixelFormat, + myPipe[k].SurfaceTiling, + myPipe[k].BytePerPixelC, + myPipe[k].SourceRotation, + SwathWidthC[k], + myPipe[k].ViewportHeightChroma, + myPipe[k].ViewportXStartC, + myPipe[k].ViewportYStartC, + GPUVMEnable, + HostVMEnable, + HostVMMaxNonCachedPageTableLevels, + GPUVMMaxPageTableLevels, + GPUVMMinPageSizeKBytes[k], + HostVMMinPageSize, + PTEBufferSizeInRequestsForChroma[k], + myPipe[k].PitchC, + myPipe[k].DCCMetaPitchC, + myPipe[k].BlockWidthC, + myPipe[k].BlockHeightC, + + /* Output */ + &MetaRowByteC[k], + &PixelPTEBytesPerRowC[k], + &dpte_row_width_chroma_ub[k], + &dpte_row_height_chroma[k], + &dpte_row_height_linear_chroma[k], + &PixelPTEBytesPerRowC_one_row_per_frame[k], + &dpte_row_width_chroma_ub_one_row_per_frame[k], + &dpte_row_height_chroma_one_row_per_frame[k], + &meta_req_width_chroma[k], + &meta_req_height_chroma[k], + &meta_row_width_chroma[k], + &meta_row_height_chroma[k], + &PixelPTEReqWidthC[k], + &PixelPTEReqHeightC[k], + &PTERequestSizeC[k], + &dpde0_bytes_per_frame_ub_c[k], + &meta_pte_bytes_per_frame_ub_c[k]); + + PrefetchSourceLinesC[k] = dml32_CalculatePrefetchSourceLines( + myPipe[k].VRatioChroma, + myPipe[k].VTapsChroma, + myPipe[k].InterlaceEnable, + myPipe[k].ProgressiveToInterlaceUnitInOPP, + myPipe[k].SwathHeightC, + myPipe[k].SourceRotation, + myPipe[k].ViewportStationary, + SwathWidthC[k], + myPipe[k].ViewportHeightChroma, + myPipe[k].ViewportXStartC, + myPipe[k].ViewportYStartC, + + /* Output */ + &VInitPreFillC[k], + &MaxNumSwathC[k]); + } else { + PTEBufferSizeInRequestsForLuma[k] = PTEBufferSizeInRequestsLuma + PTEBufferSizeInRequestsChroma; + PTEBufferSizeInRequestsForChroma[k] = 0; + PixelPTEBytesPerRowC[k] = 0; + PDEAndMetaPTEBytesFrameC = 0; + MetaRowByteC[k] = 0; + MaxNumSwathC[k] = 0; + PrefetchSourceLinesC[k] = 0; + dpte_row_height_chroma_one_row_per_frame[k] = 0; + dpte_row_width_chroma_ub_one_row_per_frame[k] = 0; + PixelPTEBytesPerRowC_one_row_per_frame[k] = 0; + } + + PDEAndMetaPTEBytesFrameY = dml32_CalculateVMAndRowBytes( + myPipe[k].ViewportStationary, + myPipe[k].DCCEnable, + myPipe[k].DPPPerSurface, + myPipe[k].BlockHeight256BytesY, + myPipe[k].BlockWidth256BytesY, + myPipe[k].SourcePixelFormat, + myPipe[k].SurfaceTiling, + myPipe[k].BytePerPixelY, + myPipe[k].SourceRotation, + SwathWidthY[k], + myPipe[k].ViewportHeight, + myPipe[k].ViewportXStart, + myPipe[k].ViewportYStart, + GPUVMEnable, + HostVMEnable, + HostVMMaxNonCachedPageTableLevels, + GPUVMMaxPageTableLevels, + GPUVMMinPageSizeKBytes[k], + HostVMMinPageSize, + PTEBufferSizeInRequestsForLuma[k], + myPipe[k].PitchY, + myPipe[k].DCCMetaPitchY, + myPipe[k].BlockWidthY, + myPipe[k].BlockHeightY, + + /* Output */ + &MetaRowByteY[k], + &PixelPTEBytesPerRowY[k], + &dpte_row_width_luma_ub[k], + &dpte_row_height_luma[k], + &dpte_row_height_linear_luma[k], + &PixelPTEBytesPerRowY_one_row_per_frame[k], + &dpte_row_width_luma_ub_one_row_per_frame[k], + &dpte_row_height_luma_one_row_per_frame[k], + &meta_req_width[k], + &meta_req_height[k], + &meta_row_width[k], + &meta_row_height[k], + &PixelPTEReqWidthY[k], + &PixelPTEReqHeightY[k], + &PTERequestSizeY[k], + &dpde0_bytes_per_frame_ub_l[k], + &meta_pte_bytes_per_frame_ub_l[k]); + + PrefetchSourceLinesY[k] = dml32_CalculatePrefetchSourceLines( + myPipe[k].VRatio, + myPipe[k].VTaps, + myPipe[k].InterlaceEnable, + myPipe[k].ProgressiveToInterlaceUnitInOPP, + myPipe[k].SwathHeightY, + myPipe[k].SourceRotation, + myPipe[k].ViewportStationary, + SwathWidthY[k], + myPipe[k].ViewportHeight, + myPipe[k].ViewportXStart, + myPipe[k].ViewportYStart, + + /* Output */ + &VInitPreFillY[k], + &MaxNumSwathY[k]); + + PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY + PDEAndMetaPTEBytesFrameC; + MetaRowByte[k] = MetaRowByteY[k] + MetaRowByteC[k]; + + if (PixelPTEBytesPerRowY[k] <= 64 * PTEBufferSizeInRequestsForLuma[k] && + PixelPTEBytesPerRowC[k] <= 64 * PTEBufferSizeInRequestsForChroma[k]) { + PTEBufferSizeNotExceeded[k] = true; + } else { + PTEBufferSizeNotExceeded[k] = false; + } + + one_row_per_frame_fits_in_buffer[k] = (PixelPTEBytesPerRowY_one_row_per_frame[k] <= 64 * 2 * + PTEBufferSizeInRequestsForLuma[k] && + PixelPTEBytesPerRowC_one_row_per_frame[k] <= 64 * 2 * PTEBufferSizeInRequestsForChroma[k]); + } + + dml32_CalculateMALLUseForStaticScreen( + NumberOfActiveSurfaces, + MALLAllocatedForDCN, + UseMALLForStaticScreen, // mode + SurfaceSizeInMALL, + one_row_per_frame_fits_in_buffer, + /* Output */ + UsesMALLForStaticScreen); // boolen + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + PTE_BUFFER_MODE[k] = myPipe[k].FORCE_ONE_ROW_FOR_FRAME || UsesMALLForStaticScreen[k] || + (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport) || + (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) || + (GPUVMMinPageSizeKBytes[k] > 64); + BIGK_FRAGMENT_SIZE[k] = dml_log2(GPUVMMinPageSizeKBytes[k] * 1024) - 12; + } + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d, SurfaceSizeInMALL = %d\n", __func__, k, SurfaceSizeInMALL[k]); + dml_print("DML::%s: k=%d, UsesMALLForStaticScreen = %d\n", __func__, k, UsesMALLForStaticScreen[k]); +#endif + use_one_row_for_frame[k] = myPipe[k].FORCE_ONE_ROW_FOR_FRAME || UsesMALLForStaticScreen[k] || + (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport) || + (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) || + (GPUVMMinPageSizeKBytes[k] > 64 && IsVertical(myPipe[k].SourceRotation)); + + use_one_row_for_frame_flip[k] = use_one_row_for_frame[k] && + !(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame); + + if (use_one_row_for_frame[k]) { + dpte_row_height_luma[k] = dpte_row_height_luma_one_row_per_frame[k]; + dpte_row_width_luma_ub[k] = dpte_row_width_luma_ub_one_row_per_frame[k]; + PixelPTEBytesPerRowY[k] = PixelPTEBytesPerRowY_one_row_per_frame[k]; + dpte_row_height_chroma[k] = dpte_row_height_chroma_one_row_per_frame[k]; + dpte_row_width_chroma_ub[k] = dpte_row_width_chroma_ub_one_row_per_frame[k]; + PixelPTEBytesPerRowC[k] = PixelPTEBytesPerRowC_one_row_per_frame[k]; + PTEBufferSizeNotExceeded[k] = one_row_per_frame_fits_in_buffer[k]; + } + + if (MetaRowByte[k] <= DCCMetaBufferSizeBytes) + DCCMetaBufferSizeNotExceeded[k] = true; + else + DCCMetaBufferSizeNotExceeded[k] = false; + + PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY[k] + PixelPTEBytesPerRowC[k]; + if (use_one_row_for_frame[k]) + PixelPTEBytesPerRow[k] = PixelPTEBytesPerRow[k] / 2; + + dml32_CalculateRowBandwidth( + GPUVMEnable, + myPipe[k].SourcePixelFormat, + myPipe[k].VRatio, + myPipe[k].VRatioChroma, + myPipe[k].DCCEnable, + myPipe[k].HTotal / myPipe[k].PixelClock, + MetaRowByteY[k], MetaRowByteC[k], + meta_row_height[k], + meta_row_height_chroma[k], + PixelPTEBytesPerRowY[k], + PixelPTEBytesPerRowC[k], + dpte_row_height_luma[k], + dpte_row_height_chroma[k], + + /* Output */ + &meta_row_bw[k], + &dpte_row_bw[k]); +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d, use_one_row_for_frame = %d\n", __func__, k, use_one_row_for_frame[k]); + dml_print("DML::%s: k=%d, use_one_row_for_frame_flip = %d\n", + __func__, k, use_one_row_for_frame_flip[k]); + dml_print("DML::%s: k=%d, UseMALLForPStateChange = %d\n", + __func__, k, UseMALLForPStateChange[k]); + dml_print("DML::%s: k=%d, dpte_row_height_luma = %d\n", __func__, k, dpte_row_height_luma[k]); + dml_print("DML::%s: k=%d, dpte_row_width_luma_ub = %d\n", + __func__, k, dpte_row_width_luma_ub[k]); + dml_print("DML::%s: k=%d, PixelPTEBytesPerRowY = %d\n", __func__, k, PixelPTEBytesPerRowY[k]); + dml_print("DML::%s: k=%d, dpte_row_height_chroma = %d\n", + __func__, k, dpte_row_height_chroma[k]); + dml_print("DML::%s: k=%d, dpte_row_width_chroma_ub = %d\n", + __func__, k, dpte_row_width_chroma_ub[k]); + dml_print("DML::%s: k=%d, PixelPTEBytesPerRowC = %d\n", __func__, k, PixelPTEBytesPerRowC[k]); + dml_print("DML::%s: k=%d, PixelPTEBytesPerRow = %d\n", __func__, k, PixelPTEBytesPerRow[k]); + dml_print("DML::%s: k=%d, PTEBufferSizeNotExceeded = %d\n", + __func__, k, PTEBufferSizeNotExceeded[k]); + dml_print("DML::%s: k=%d, PTE_BUFFER_MODE = %d\n", __func__, k, PTE_BUFFER_MODE[k]); + dml_print("DML::%s: k=%d, BIGK_FRAGMENT_SIZE = %d\n", __func__, k, BIGK_FRAGMENT_SIZE[k]); +#endif + } +} // CalculateVMRowAndSwath + +unsigned int dml32_CalculateVMAndRowBytes( + bool ViewportStationary, + bool DCCEnable, + unsigned int NumberOfDPPs, + unsigned int BlockHeight256Bytes, + unsigned int BlockWidth256Bytes, + enum source_format_class SourcePixelFormat, + unsigned int SurfaceTiling, + unsigned int BytePerPixel, + enum dm_rotation_angle SourceRotation, + double SwathWidth, + unsigned int ViewportHeight, + unsigned int ViewportXStart, + unsigned int ViewportYStart, + bool GPUVMEnable, + bool HostVMEnable, + unsigned int HostVMMaxNonCachedPageTableLevels, + unsigned int GPUVMMaxPageTableLevels, + unsigned int GPUVMMinPageSizeKBytes, + unsigned int HostVMMinPageSize, + unsigned int PTEBufferSizeInRequests, + unsigned int Pitch, + unsigned int DCCMetaPitch, + unsigned int MacroTileWidth, + unsigned int MacroTileHeight, + + /* Output */ + unsigned int *MetaRowByte, + unsigned int *PixelPTEBytesPerRow, + unsigned int *dpte_row_width_ub, + unsigned int *dpte_row_height, + unsigned int *dpte_row_height_linear, + unsigned int *PixelPTEBytesPerRow_one_row_per_frame, + unsigned int *dpte_row_width_ub_one_row_per_frame, + unsigned int *dpte_row_height_one_row_per_frame, + unsigned int *MetaRequestWidth, + unsigned int *MetaRequestHeight, + unsigned int *meta_row_width, + unsigned int *meta_row_height, + unsigned int *PixelPTEReqWidth, + unsigned int *PixelPTEReqHeight, + unsigned int *PTERequestSize, + unsigned int *DPDE0BytesFrame, + unsigned int *MetaPTEBytesFrame) +{ + unsigned int MPDEBytesFrame; + unsigned int DCCMetaSurfaceBytes; + unsigned int ExtraDPDEBytesFrame; + unsigned int PDEAndMetaPTEBytesFrame; + unsigned int HostVMDynamicLevels = 0; + unsigned int MacroTileSizeBytes; + unsigned int vp_height_meta_ub; + unsigned int vp_height_dpte_ub; + unsigned int PixelPTEReqWidth_linear = 0; // VBA_DELTA. VBA doesn't calculate this + + if (GPUVMEnable == true && HostVMEnable == true) { + if (HostVMMinPageSize < 2048) + HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; + else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) + HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + else + HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + } + + *MetaRequestHeight = 8 * BlockHeight256Bytes; + *MetaRequestWidth = 8 * BlockWidth256Bytes; + if (SurfaceTiling == dm_sw_linear) { + *meta_row_height = 32; + *meta_row_width = dml_floor(ViewportXStart + SwathWidth + *MetaRequestWidth - 1, *MetaRequestWidth) + - dml_floor(ViewportXStart, *MetaRequestWidth); + } else if (!IsVertical(SourceRotation)) { + *meta_row_height = *MetaRequestHeight; + if (ViewportStationary && NumberOfDPPs == 1) { + *meta_row_width = dml_floor(ViewportXStart + SwathWidth + *MetaRequestWidth - 1, + *MetaRequestWidth) - dml_floor(ViewportXStart, *MetaRequestWidth); + } else { + *meta_row_width = dml_ceil(SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth; + } + *MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0; + } else { + *meta_row_height = *MetaRequestWidth; + if (ViewportStationary && NumberOfDPPs == 1) { + *meta_row_width = dml_floor(ViewportYStart + ViewportHeight + *MetaRequestHeight - 1, + *MetaRequestHeight) - dml_floor(ViewportYStart, *MetaRequestHeight); + } else { + *meta_row_width = dml_ceil(SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight; + } + *MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0; + } + + if (ViewportStationary && (NumberOfDPPs == 1 || !IsVertical(SourceRotation))) { + vp_height_meta_ub = dml_floor(ViewportYStart + ViewportHeight + 64 * BlockHeight256Bytes - 1, + 64 * BlockHeight256Bytes) - dml_floor(ViewportYStart, 64 * BlockHeight256Bytes); + } else if (!IsVertical(SourceRotation)) { + vp_height_meta_ub = dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes; + } else { + vp_height_meta_ub = dml_ceil(SwathWidth - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes; + } + + DCCMetaSurfaceBytes = DCCMetaPitch * vp_height_meta_ub * BytePerPixel / 256.0; + + if (GPUVMEnable == true) { + *MetaPTEBytesFrame = (dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / + (8 * 4.0 * 1024), 1) + 1) * 64; + MPDEBytesFrame = 128 * (GPUVMMaxPageTableLevels - 1); + } else { + *MetaPTEBytesFrame = 0; + MPDEBytesFrame = 0; + } + + if (DCCEnable != true) { + *MetaPTEBytesFrame = 0; + MPDEBytesFrame = 0; + *MetaRowByte = 0; + } + + MacroTileSizeBytes = MacroTileWidth * BytePerPixel * MacroTileHeight; + + if (GPUVMEnable == true && GPUVMMaxPageTableLevels > 1) { + if (ViewportStationary && (NumberOfDPPs == 1 || !IsVertical(SourceRotation))) { + vp_height_dpte_ub = dml_floor(ViewportYStart + ViewportHeight + + MacroTileHeight - 1, MacroTileHeight) - + dml_floor(ViewportYStart, MacroTileHeight); + } else if (!IsVertical(SourceRotation)) { + vp_height_dpte_ub = dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight; + } else { + vp_height_dpte_ub = dml_ceil(SwathWidth - 1, MacroTileHeight) + MacroTileHeight; + } + *DPDE0BytesFrame = 64 * (dml_ceil((Pitch * vp_height_dpte_ub * BytePerPixel - MacroTileSizeBytes) / + (8 * 2097152), 1) + 1); + ExtraDPDEBytesFrame = 128 * (GPUVMMaxPageTableLevels - 2); + } else { + *DPDE0BytesFrame = 0; + ExtraDPDEBytesFrame = 0; + vp_height_dpte_ub = 0; + } + + PDEAndMetaPTEBytesFrame = *MetaPTEBytesFrame + MPDEBytesFrame + *DPDE0BytesFrame + ExtraDPDEBytesFrame; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: DCCEnable = %d\n", __func__, DCCEnable); + dml_print("DML::%s: GPUVMEnable = %d\n", __func__, GPUVMEnable); + dml_print("DML::%s: SwModeLinear = %d\n", __func__, SurfaceTiling == dm_sw_linear); + dml_print("DML::%s: BytePerPixel = %d\n", __func__, BytePerPixel); + dml_print("DML::%s: GPUVMMaxPageTableLevels = %d\n", __func__, GPUVMMaxPageTableLevels); + dml_print("DML::%s: BlockHeight256Bytes = %d\n", __func__, BlockHeight256Bytes); + dml_print("DML::%s: BlockWidth256Bytes = %d\n", __func__, BlockWidth256Bytes); + dml_print("DML::%s: MacroTileHeight = %d\n", __func__, MacroTileHeight); + dml_print("DML::%s: MacroTileWidth = %d\n", __func__, MacroTileWidth); + dml_print("DML::%s: MetaPTEBytesFrame = %d\n", __func__, *MetaPTEBytesFrame); + dml_print("DML::%s: MPDEBytesFrame = %d\n", __func__, MPDEBytesFrame); + dml_print("DML::%s: DPDE0BytesFrame = %d\n", __func__, *DPDE0BytesFrame); + dml_print("DML::%s: ExtraDPDEBytesFrame= %d\n", __func__, ExtraDPDEBytesFrame); + dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, PDEAndMetaPTEBytesFrame); + dml_print("DML::%s: ViewportHeight = %d\n", __func__, ViewportHeight); + dml_print("DML::%s: SwathWidth = %d\n", __func__, SwathWidth); + dml_print("DML::%s: vp_height_dpte_ub = %d\n", __func__, vp_height_dpte_ub); +#endif + + if (HostVMEnable == true) + PDEAndMetaPTEBytesFrame = PDEAndMetaPTEBytesFrame * (1 + 8 * HostVMDynamicLevels); + + if (SurfaceTiling == dm_sw_linear) { + *PixelPTEReqHeight = 1; + *PixelPTEReqWidth = GPUVMMinPageSizeKBytes * 1024 * 8 / BytePerPixel; + PixelPTEReqWidth_linear = GPUVMMinPageSizeKBytes * 1024 * 8 / BytePerPixel; + *PTERequestSize = 64; + } else if (GPUVMMinPageSizeKBytes == 4) { + *PixelPTEReqHeight = 16 * BlockHeight256Bytes; + *PixelPTEReqWidth = 16 * BlockWidth256Bytes; + *PTERequestSize = 128; + } else { + *PixelPTEReqHeight = MacroTileHeight; + *PixelPTEReqWidth = 8 * 1024 * GPUVMMinPageSizeKBytes / (MacroTileHeight * BytePerPixel); + *PTERequestSize = 64; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: GPUVMMinPageSizeKBytes = %d\n", __func__, GPUVMMinPageSizeKBytes); + dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d (after HostVM factor)\n", __func__, PDEAndMetaPTEBytesFrame); + dml_print("DML::%s: PixelPTEReqHeight = %d\n", __func__, *PixelPTEReqHeight); + dml_print("DML::%s: PixelPTEReqWidth = %d\n", __func__, *PixelPTEReqWidth); + dml_print("DML::%s: PixelPTEReqWidth_linear = %d\n", __func__, PixelPTEReqWidth_linear); + dml_print("DML::%s: PTERequestSize = %d\n", __func__, *PTERequestSize); + dml_print("DML::%s: Pitch = %d\n", __func__, Pitch); +#endif + + *dpte_row_height_one_row_per_frame = vp_height_dpte_ub; + *dpte_row_width_ub_one_row_per_frame = (dml_ceil(((double)Pitch * (double)*dpte_row_height_one_row_per_frame / + (double) *PixelPTEReqHeight - 1) / (double) *PixelPTEReqWidth, 1) + 1) * + (double) *PixelPTEReqWidth; + *PixelPTEBytesPerRow_one_row_per_frame = *dpte_row_width_ub_one_row_per_frame / *PixelPTEReqWidth * + *PTERequestSize; + + if (SurfaceTiling == dm_sw_linear) { + *dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * + *PixelPTEReqWidth / Pitch), 1)); +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: dpte_row_height = %d (1)\n", __func__, + PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch); + dml_print("DML::%s: dpte_row_height = %f (2)\n", __func__, + dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch)); + dml_print("DML::%s: dpte_row_height = %f (3)\n", __func__, + dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); + dml_print("DML::%s: dpte_row_height = %d (4)\n", __func__, + 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * + *PixelPTEReqWidth / Pitch), 1)); + dml_print("DML::%s: dpte_row_height = %d\n", __func__, *dpte_row_height); +#endif + *dpte_row_width_ub = dml_ceil(((double) Pitch * (double) *dpte_row_height - 1), + (double) *PixelPTEReqWidth) + *PixelPTEReqWidth; + *PixelPTEBytesPerRow = *dpte_row_width_ub / (double)*PixelPTEReqWidth * (double)*PTERequestSize; + + // VBA_DELTA, VBA doesn't have programming value for pte row height linear. + *dpte_row_height_linear = 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * + PixelPTEReqWidth_linear / Pitch), 1); + if (*dpte_row_height_linear > 128) + *dpte_row_height_linear = 128; + + } else if (!IsVertical(SourceRotation)) { + *dpte_row_height = *PixelPTEReqHeight; + + if (GPUVMMinPageSizeKBytes > 64) { + *dpte_row_width_ub = (dml_ceil((Pitch * *dpte_row_height / *PixelPTEReqHeight - 1) / + *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + } else if (ViewportStationary && (NumberOfDPPs == 1)) { + *dpte_row_width_ub = dml_floor(ViewportXStart + SwathWidth + + *PixelPTEReqWidth - 1, *PixelPTEReqWidth) - + dml_floor(ViewportXStart, *PixelPTEReqWidth); + } else { + *dpte_row_width_ub = (dml_ceil((SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * + *PixelPTEReqWidth; + } + + *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; + } else { + *dpte_row_height = dml_min(*PixelPTEReqWidth, MacroTileWidth); + + if (ViewportStationary && (NumberOfDPPs == 1)) { + *dpte_row_width_ub = dml_floor(ViewportYStart + ViewportHeight + *PixelPTEReqHeight - 1, + *PixelPTEReqHeight) - dml_floor(ViewportYStart, *PixelPTEReqHeight); + } else { + *dpte_row_width_ub = (dml_ceil((SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) + * *PixelPTEReqHeight; + } + + *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize; + } + + if (GPUVMEnable != true) + *PixelPTEBytesPerRow = 0; + if (HostVMEnable == true) + *PixelPTEBytesPerRow = *PixelPTEBytesPerRow * (1 + 8 * HostVMDynamicLevels); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: GPUVMMinPageSizeKBytes = %d\n", __func__, GPUVMMinPageSizeKBytes); + dml_print("DML::%s: dpte_row_height = %d\n", __func__, *dpte_row_height); + dml_print("DML::%s: dpte_row_height_linear = %d\n", __func__, *dpte_row_height_linear); + dml_print("DML::%s: dpte_row_width_ub = %d\n", __func__, *dpte_row_width_ub); + dml_print("DML::%s: PixelPTEBytesPerRow = %d\n", __func__, *PixelPTEBytesPerRow); + dml_print("DML::%s: PTEBufferSizeInRequests = %d\n", __func__, PTEBufferSizeInRequests); + dml_print("DML::%s: dpte_row_height_one_row_per_frame = %d\n", __func__, *dpte_row_height_one_row_per_frame); + dml_print("DML::%s: dpte_row_width_ub_one_row_per_frame = %d\n", + __func__, *dpte_row_width_ub_one_row_per_frame); + dml_print("DML::%s: PixelPTEBytesPerRow_one_row_per_frame = %d\n", + __func__, *PixelPTEBytesPerRow_one_row_per_frame); + dml_print("DML: vm_bytes = meta_pte_bytes_per_frame (per_pipe) = MetaPTEBytesFrame = : %i\n", + *MetaPTEBytesFrame); +#endif + + return PDEAndMetaPTEBytesFrame; +} // CalculateVMAndRowBytes + +double dml32_CalculatePrefetchSourceLines( + double VRatio, + unsigned int VTaps, + bool Interlace, + bool ProgressiveToInterlaceUnitInOPP, + unsigned int SwathHeight, + enum dm_rotation_angle SourceRotation, + bool ViewportStationary, + double SwathWidth, + unsigned int ViewportHeight, + unsigned int ViewportXStart, + unsigned int ViewportYStart, + + /* Output */ + double *VInitPreFill, + unsigned int *MaxNumSwath) +{ + + unsigned int vp_start_rot; + unsigned int sw0_tmp; + unsigned int MaxPartialSwath; + double numLines; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: VRatio = %f\n", __func__, VRatio); + dml_print("DML::%s: VTaps = %d\n", __func__, VTaps); + dml_print("DML::%s: ViewportXStart = %d\n", __func__, ViewportXStart); + dml_print("DML::%s: ViewportYStart = %d\n", __func__, ViewportYStart); + dml_print("DML::%s: ViewportStationary = %d\n", __func__, ViewportStationary); + dml_print("DML::%s: SwathHeight = %d\n", __func__, SwathHeight); +#endif + if (ProgressiveToInterlaceUnitInOPP) + *VInitPreFill = dml_floor((VRatio + (double) VTaps + 1) / 2.0, 1); + else + *VInitPreFill = dml_floor((VRatio + (double) VTaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); + + if (ViewportStationary) { + if (SourceRotation == dm_rotation_180 || SourceRotation == dm_rotation_180m) { + vp_start_rot = SwathHeight - + (((unsigned int) (ViewportYStart + ViewportHeight - 1) % SwathHeight) + 1); + } else if (SourceRotation == dm_rotation_270 || SourceRotation == dm_rotation_90m) { + vp_start_rot = ViewportXStart; + } else if (SourceRotation == dm_rotation_90 || SourceRotation == dm_rotation_270m) { + vp_start_rot = SwathHeight - + (((unsigned int)(ViewportYStart + SwathWidth - 1) % SwathHeight) + 1); + } else { + vp_start_rot = ViewportYStart; + } + sw0_tmp = SwathHeight - (vp_start_rot % SwathHeight); + if (sw0_tmp < *VInitPreFill) + *MaxNumSwath = dml_ceil((*VInitPreFill - sw0_tmp) / SwathHeight, 1) + 1; + else + *MaxNumSwath = 1; + MaxPartialSwath = dml_max(1, (unsigned int) (vp_start_rot + *VInitPreFill - 1) % SwathHeight); + } else { + *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1; + if (*VInitPreFill > 1) + MaxPartialSwath = dml_max(1, (unsigned int) (*VInitPreFill - 2) % SwathHeight); + else + MaxPartialSwath = dml_max(1, (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight); + } + numLines = *MaxNumSwath * SwathHeight + MaxPartialSwath; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: vp_start_rot = %d\n", __func__, vp_start_rot); + dml_print("DML::%s: VInitPreFill = %d\n", __func__, *VInitPreFill); + dml_print("DML::%s: MaxPartialSwath = %d\n", __func__, MaxPartialSwath); + dml_print("DML::%s: MaxNumSwath = %d\n", __func__, *MaxNumSwath); + dml_print("DML::%s: Prefetch source lines = %3.2f\n", __func__, numLines); +#endif + return numLines; + +} // CalculatePrefetchSourceLines + +void dml32_CalculateMALLUseForStaticScreen( + unsigned int NumberOfActiveSurfaces, + unsigned int MALLAllocatedForDCNFinal, + enum dm_use_mall_for_static_screen_mode *UseMALLForStaticScreen, + unsigned int SurfaceSizeInMALL[], + bool one_row_per_frame_fits_in_buffer[], + + /* output */ + bool UsesMALLForStaticScreen[]) +{ + unsigned int k; + unsigned int SurfaceToAddToMALL; + bool CanAddAnotherSurfaceToMALL; + unsigned int TotalSurfaceSizeInMALL; + + TotalSurfaceSizeInMALL = 0; + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + UsesMALLForStaticScreen[k] = (UseMALLForStaticScreen[k] == dm_use_mall_static_screen_enable); + if (UsesMALLForStaticScreen[k]) + TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k]; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d, UsesMALLForStaticScreen = %d\n", __func__, k, UsesMALLForStaticScreen[k]); + dml_print("DML::%s: k=%d, TotalSurfaceSizeInMALL = %d\n", __func__, k, TotalSurfaceSizeInMALL); +#endif + } + + SurfaceToAddToMALL = 0; + CanAddAnotherSurfaceToMALL = true; + while (CanAddAnotherSurfaceToMALL) { + CanAddAnotherSurfaceToMALL = false; + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k] <= MALLAllocatedForDCNFinal * 1024 * 1024 && + !UsesMALLForStaticScreen[k] && + UseMALLForStaticScreen[k] != dm_use_mall_static_screen_disable && + one_row_per_frame_fits_in_buffer[k] && + (!CanAddAnotherSurfaceToMALL || + SurfaceSizeInMALL[k] < SurfaceSizeInMALL[SurfaceToAddToMALL])) { + CanAddAnotherSurfaceToMALL = true; + SurfaceToAddToMALL = k; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d, UseMALLForStaticScreen = %d (dis, en, optimize)\n", + __func__, k, UseMALLForStaticScreen[k]); +#endif + } + } + if (CanAddAnotherSurfaceToMALL) { + UsesMALLForStaticScreen[SurfaceToAddToMALL] = true; + TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[SurfaceToAddToMALL]; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: SurfaceToAddToMALL = %d\n", __func__, SurfaceToAddToMALL); + dml_print("DML::%s: TotalSurfaceSizeInMALL = %d\n", __func__, TotalSurfaceSizeInMALL); +#endif + + } + } +} + +void dml32_CalculateRowBandwidth( + bool GPUVMEnable, + enum source_format_class SourcePixelFormat, + double VRatio, + double VRatioChroma, + bool DCCEnable, + double LineTime, + unsigned int MetaRowByteLuma, + unsigned int MetaRowByteChroma, + unsigned int meta_row_height_luma, + unsigned int meta_row_height_chroma, + unsigned int PixelPTEBytesPerRowLuma, + unsigned int PixelPTEBytesPerRowChroma, + unsigned int dpte_row_height_luma, + unsigned int dpte_row_height_chroma, + /* Output */ + double *meta_row_bw, + double *dpte_row_bw) +{ + if (DCCEnable != true) { + *meta_row_bw = 0; + } else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_420_12 || + SourcePixelFormat == dm_rgbe_alpha) { + *meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime) + VRatioChroma * + MetaRowByteChroma / (meta_row_height_chroma * LineTime); + } else { + *meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime); + } + + if (GPUVMEnable != true) { + *dpte_row_bw = 0; + } else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_420_12 || + SourcePixelFormat == dm_rgbe_alpha) { + *dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime) + + VRatioChroma * PixelPTEBytesPerRowChroma / (dpte_row_height_chroma * LineTime); + } else { + *dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime); + } +} + +double dml32_CalculateUrgentLatency( + double UrgentLatencyPixelDataOnly, + double UrgentLatencyPixelMixedWithVMData, + double UrgentLatencyVMDataOnly, + bool DoUrgentLatencyAdjustment, + double UrgentLatencyAdjustmentFabricClockComponent, + double UrgentLatencyAdjustmentFabricClockReference, + double FabricClock) +{ + double ret; + + ret = dml_max3(UrgentLatencyPixelDataOnly, UrgentLatencyPixelMixedWithVMData, UrgentLatencyVMDataOnly); + if (DoUrgentLatencyAdjustment == true) { + ret = ret + UrgentLatencyAdjustmentFabricClockComponent * + (UrgentLatencyAdjustmentFabricClockReference / FabricClock - 1); + } + return ret; +} + +void dml32_CalculateUrgentBurstFactor( + enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange, + unsigned int swath_width_luma_ub, + unsigned int swath_width_chroma_ub, + unsigned int SwathHeightY, + unsigned int SwathHeightC, + double LineTime, + double UrgentLatency, + double CursorBufferSize, + unsigned int CursorWidth, + unsigned int CursorBPP, + double VRatio, + double VRatioC, + double BytePerPixelInDETY, + double BytePerPixelInDETC, + unsigned int DETBufferSizeY, + unsigned int DETBufferSizeC, + /* Output */ + double *UrgentBurstFactorCursor, + double *UrgentBurstFactorLuma, + double *UrgentBurstFactorChroma, + bool *NotEnoughUrgentLatencyHiding) +{ + double LinesInDETLuma; + double LinesInDETChroma; + unsigned int LinesInCursorBuffer; + double CursorBufferSizeInTime; + double DETBufferSizeInTimeLuma; + double DETBufferSizeInTimeChroma; + + *NotEnoughUrgentLatencyHiding = 0; + + if (CursorWidth > 0) { + LinesInCursorBuffer = 1 << (unsigned int) dml_floor(dml_log2(CursorBufferSize * 1024.0 / + (CursorWidth * CursorBPP / 8.0)), 1.0); + if (VRatio > 0) { + CursorBufferSizeInTime = LinesInCursorBuffer * LineTime / VRatio; + if (CursorBufferSizeInTime - UrgentLatency <= 0) { + *NotEnoughUrgentLatencyHiding = 1; + *UrgentBurstFactorCursor = 0; + } else { + *UrgentBurstFactorCursor = CursorBufferSizeInTime / + (CursorBufferSizeInTime - UrgentLatency); + } + } else { + *UrgentBurstFactorCursor = 1; + } + } + + LinesInDETLuma = (UseMALLForPStateChange == dm_use_mall_pstate_change_phantom_pipe ? 1024*1024 : + DETBufferSizeY) / BytePerPixelInDETY / swath_width_luma_ub; + + if (VRatio > 0) { + DETBufferSizeInTimeLuma = dml_floor(LinesInDETLuma, SwathHeightY) * LineTime / VRatio; + if (DETBufferSizeInTimeLuma - UrgentLatency <= 0) { + *NotEnoughUrgentLatencyHiding = 1; + *UrgentBurstFactorLuma = 0; + } else { + *UrgentBurstFactorLuma = DETBufferSizeInTimeLuma / (DETBufferSizeInTimeLuma - UrgentLatency); + } + } else { + *UrgentBurstFactorLuma = 1; + } + + if (BytePerPixelInDETC > 0) { + LinesInDETChroma = (UseMALLForPStateChange == dm_use_mall_pstate_change_phantom_pipe ? + 1024 * 1024 : DETBufferSizeC) / BytePerPixelInDETC + / swath_width_chroma_ub; + + if (VRatio > 0) { + DETBufferSizeInTimeChroma = dml_floor(LinesInDETChroma, SwathHeightC) * LineTime / VRatio; + if (DETBufferSizeInTimeChroma - UrgentLatency <= 0) { + *NotEnoughUrgentLatencyHiding = 1; + *UrgentBurstFactorChroma = 0; + } else { + *UrgentBurstFactorChroma = DETBufferSizeInTimeChroma + / (DETBufferSizeInTimeChroma - UrgentLatency); + } + } else { + *UrgentBurstFactorChroma = 1; + } + } +} // CalculateUrgentBurstFactor + +void dml32_CalculateDCFCLKDeepSleep( + unsigned int NumberOfActiveSurfaces, + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], + double VRatio[], + double VRatioChroma[], + double SwathWidthY[], + double SwathWidthC[], + unsigned int DPPPerSurface[], + double HRatio[], + double HRatioChroma[], + double PixelClock[], + double PSCL_THROUGHPUT[], + double PSCL_THROUGHPUT_CHROMA[], + double Dppclk[], + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + unsigned int ReturnBusWidth, + + /* Output */ + double *DCFClkDeepSleep) +{ + unsigned int k; + double DisplayPipeLineDeliveryTimeLuma; + double DisplayPipeLineDeliveryTimeChroma; + double DCFClkDeepSleepPerSurface[DC__NUM_DPP__MAX]; + double ReadBandwidth = 0.0; + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + + if (VRatio[k] <= 1) { + DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerSurface[k] / HRatio[k] + / PixelClock[k]; + } else { + DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / Dppclk[k]; + } + if (BytePerPixelC[k] == 0) { + DisplayPipeLineDeliveryTimeChroma = 0; + } else { + if (VRatioChroma[k] <= 1) { + DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] * + DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k]; + } else { + DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k] + / Dppclk[k]; + } + } + + if (BytePerPixelC[k] > 0) { + DCFClkDeepSleepPerSurface[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * + BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma, + __DML_MIN_DCFCLK_FACTOR__ * SwathWidthC[k] * BytePerPixelC[k] / + 32.0 / DisplayPipeLineDeliveryTimeChroma); + } else { + DCFClkDeepSleepPerSurface[k] = __DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / + 64.0 / DisplayPipeLineDeliveryTimeLuma; + } + DCFClkDeepSleepPerSurface[k] = dml_max(DCFClkDeepSleepPerSurface[k], PixelClock[k] / 16); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d, PixelClock = %f\n", __func__, k, PixelClock[k]); + dml_print("DML::%s: k=%d, DCFClkDeepSleepPerSurface = %f\n", __func__, k, DCFClkDeepSleepPerSurface[k]); +#endif + } + + for (k = 0; k < NumberOfActiveSurfaces; ++k) + ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k]; + + *DCFClkDeepSleep = dml_max(8.0, __DML_MIN_DCFCLK_FACTOR__ * ReadBandwidth / (double) ReturnBusWidth); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: __DML_MIN_DCFCLK_FACTOR__ = %f\n", __func__, __DML_MIN_DCFCLK_FACTOR__); + dml_print("DML::%s: ReadBandwidth = %f\n", __func__, ReadBandwidth); + dml_print("DML::%s: ReturnBusWidth = %d\n", __func__, ReturnBusWidth); + dml_print("DML::%s: DCFClkDeepSleep = %f\n", __func__, *DCFClkDeepSleep); +#endif + + for (k = 0; k < NumberOfActiveSurfaces; ++k) + *DCFClkDeepSleep = dml_max(*DCFClkDeepSleep, DCFClkDeepSleepPerSurface[k]); +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: DCFClkDeepSleep = %f (final)\n", __func__, *DCFClkDeepSleep); +#endif +} // CalculateDCFCLKDeepSleep + +double dml32_CalculateWriteBackDelay( + enum source_format_class WritebackPixelFormat, + double WritebackHRatio, + double WritebackVRatio, + unsigned int WritebackVTaps, + unsigned int WritebackDestinationWidth, + unsigned int WritebackDestinationHeight, + unsigned int WritebackSourceHeight, + unsigned int HTotal) +{ + double CalculateWriteBackDelay; + double Line_length; + double Output_lines_last_notclamped; + double WritebackVInit; + + WritebackVInit = (WritebackVRatio + WritebackVTaps + 1) / 2; + Line_length = dml_max((double) WritebackDestinationWidth, + dml_ceil((double)WritebackDestinationWidth / 6.0, 1.0) * WritebackVTaps); + Output_lines_last_notclamped = WritebackDestinationHeight - 1 - + dml_ceil(((double)WritebackSourceHeight - + (double) WritebackVInit) / (double)WritebackVRatio, 1.0); + if (Output_lines_last_notclamped < 0) { + CalculateWriteBackDelay = 0; + } else { + CalculateWriteBackDelay = Output_lines_last_notclamped * Line_length + + (HTotal - WritebackDestinationWidth) + 80; + } + return CalculateWriteBackDelay; +} + +void dml32_UseMinimumDCFCLK( + enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[], + bool DRRDisplay[], + bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal, + unsigned int MaxInterDCNTileRepeaters, + unsigned int MaxPrefetchMode, + double DRAMClockChangeLatencyFinal, + double FCLKChangeLatency, + double SREnterPlusExitTime, + unsigned int ReturnBusWidth, + unsigned int RoundTripPingLatencyCycles, + unsigned int ReorderingBytes, + unsigned int PixelChunkSizeInKByte, + unsigned int MetaChunkSize, + bool GPUVMEnable, + unsigned int GPUVMMaxPageTableLevels, + bool HostVMEnable, + unsigned int NumberOfActiveSurfaces, + double HostVMMinPageSize, + unsigned int HostVMMaxNonCachedPageTableLevels, + bool DynamicMetadataVMEnabled, + bool ImmediateFlipRequirement, + bool ProgressiveToInterlaceUnitInOPP, + double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation, + double PercentOfIdealSDPPortBWReceivedAfterUrgLatency, + unsigned int VTotal[], + unsigned int VActive[], + unsigned int DynamicMetadataTransmittedBytes[], + unsigned int DynamicMetadataLinesBeforeActiveRequired[], + bool Interlace[], + double RequiredDPPCLKPerSurface[][2][DC__NUM_DPP__MAX], + double RequiredDISPCLK[][2], + double UrgLatency[], + unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX], + double ProjectedDCFClkDeepSleep[][2], + double MaximumVStartup[][2][DC__NUM_DPP__MAX], + unsigned int TotalNumberOfActiveDPP[][2], + unsigned int TotalNumberOfDCCActiveDPP[][2], + unsigned int dpte_group_bytes[], + double PrefetchLinesY[][2][DC__NUM_DPP__MAX], + double PrefetchLinesC[][2][DC__NUM_DPP__MAX], + unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX], + unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], + unsigned int HTotal[], + double PixelClock[], + double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX], + double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX], + double MetaRowBytes[][2][DC__NUM_DPP__MAX], + bool DynamicMetadataEnable[], + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + double DCFCLKPerState[], + /* Output */ + double DCFCLKState[][2]) +{ + unsigned int i, j, k; + unsigned int dummy1; + double dummy2, dummy3; + double NormalEfficiency; + double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2]; + + NormalEfficiency = PercentOfIdealSDPPortBWReceivedAfterUrgLatency / 100.0; + for (i = 0; i < DC__VOLTAGE_STATES; ++i) { + for (j = 0; j <= 1; ++j) { + double PixelDCFCLKCyclesRequiredInPrefetch[DC__NUM_DPP__MAX]; + double PrefetchPixelLinesTime[DC__NUM_DPP__MAX]; + double DCFCLKRequiredForPeakBandwidthPerSurface[DC__NUM_DPP__MAX]; + double DynamicMetadataVMExtraLatency[DC__NUM_DPP__MAX]; + double MinimumTWait = 0.0; + double DPTEBandwidth; + double DCFCLKRequiredForAverageBandwidth; + unsigned int ExtraLatencyBytes; + double ExtraLatencyCycles; + double DCFCLKRequiredForPeakBandwidth; + unsigned int NoOfDPPState[DC__NUM_DPP__MAX]; + double MinimumTvmPlus2Tr0; + + TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0; + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = TotalMaxPrefetchFlipDPTERowBandwidth[i][j] + + NoOfDPP[i][j][k] * DPTEBytesPerRow[i][j][k] + / (15.75 * HTotal[k] / PixelClock[k]); + } + + for (k = 0; k <= NumberOfActiveSurfaces - 1; ++k) + NoOfDPPState[k] = NoOfDPP[i][j][k]; + + DPTEBandwidth = TotalMaxPrefetchFlipDPTERowBandwidth[i][j]; + DCFCLKRequiredForAverageBandwidth = dml_max(ProjectedDCFClkDeepSleep[i][j], DPTEBandwidth / NormalEfficiency / ReturnBusWidth); + + ExtraLatencyBytes = dml32_CalculateExtraLatencyBytes(ReorderingBytes, + TotalNumberOfActiveDPP[i][j], PixelChunkSizeInKByte, + TotalNumberOfDCCActiveDPP[i][j], MetaChunkSize, GPUVMEnable, HostVMEnable, + NumberOfActiveSurfaces, NoOfDPPState, dpte_group_bytes, 1, HostVMMinPageSize, + HostVMMaxNonCachedPageTableLevels); + ExtraLatencyCycles = RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__ + + ExtraLatencyBytes / NormalEfficiency / ReturnBusWidth; + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + double DCFCLKCyclesRequiredInPrefetch; + double PrefetchTime; + + PixelDCFCLKCyclesRequiredInPrefetch[k] = (PrefetchLinesY[i][j][k] + * swath_width_luma_ub_all_states[i][j][k] * BytePerPixelY[k] + + PrefetchLinesC[i][j][k] * swath_width_chroma_ub_all_states[i][j][k] + * BytePerPixelC[k]) / NormalEfficiency + / ReturnBusWidth; + DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k] + + PDEAndMetaPTEBytesPerFrame[i][j][k] / NormalEfficiency + / NormalEfficiency / ReturnBusWidth + * (GPUVMMaxPageTableLevels > 2 ? 1 : 0) + + 2 * DPTEBytesPerRow[i][j][k] / NormalEfficiency / NormalEfficiency + / ReturnBusWidth + + 2 * MetaRowBytes[i][j][k] / NormalEfficiency / ReturnBusWidth + + PixelDCFCLKCyclesRequiredInPrefetch[k]; + PrefetchPixelLinesTime[k] = dml_max(PrefetchLinesY[i][j][k], PrefetchLinesC[i][j][k]) + * HTotal[k] / PixelClock[k]; + DynamicMetadataVMExtraLatency[k] = (GPUVMEnable == true && + DynamicMetadataEnable[k] == true && DynamicMetadataVMEnabled == true) ? + UrgLatency[i] * GPUVMMaxPageTableLevels * + (HostVMEnable == true ? HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0; + + MinimumTWait = dml32_CalculateTWait(MaxPrefetchMode, + UseMALLForPStateChange[k], + SynchronizeDRRDisplaysForUCLKPStateChangeFinal, + DRRDisplay[k], + DRAMClockChangeLatencyFinal, + FCLKChangeLatency, + UrgLatency[i], + SREnterPlusExitTime); + + PrefetchTime = (MaximumVStartup[i][j][k] - 1) * HTotal[k] / PixelClock[k] - + MinimumTWait - UrgLatency[i] * + ((GPUVMMaxPageTableLevels <= 2 ? GPUVMMaxPageTableLevels : + GPUVMMaxPageTableLevels - 2) * (HostVMEnable == true ? + HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1) - + DynamicMetadataVMExtraLatency[k]; + + if (PrefetchTime > 0) { + double ExpectedVRatioPrefetch; + + ExpectedVRatioPrefetch = PrefetchPixelLinesTime[k] / (PrefetchTime * + PixelDCFCLKCyclesRequiredInPrefetch[k] / + DCFCLKCyclesRequiredInPrefetch); + DCFCLKRequiredForPeakBandwidthPerSurface[k] = NoOfDPPState[k] * + PixelDCFCLKCyclesRequiredInPrefetch[k] / + PrefetchPixelLinesTime[k] * + dml_max(1.0, ExpectedVRatioPrefetch) * + dml_max(1.0, ExpectedVRatioPrefetch / 4); + if (HostVMEnable == true || ImmediateFlipRequirement == true) { + DCFCLKRequiredForPeakBandwidthPerSurface[k] = + DCFCLKRequiredForPeakBandwidthPerSurface[k] + + NoOfDPPState[k] * DPTEBandwidth / NormalEfficiency / + NormalEfficiency / ReturnBusWidth; + } + } else { + DCFCLKRequiredForPeakBandwidthPerSurface[k] = DCFCLKPerState[i]; + } + if (DynamicMetadataEnable[k] == true) { + double TSetupPipe; + double TdmbfPipe; + double TdmsksPipe; + double TdmecPipe; + double AllowedTimeForUrgentExtraLatency; + + dml32_CalculateVUpdateAndDynamicMetadataParameters( + MaxInterDCNTileRepeaters, + RequiredDPPCLKPerSurface[i][j][k], + RequiredDISPCLK[i][j], + ProjectedDCFClkDeepSleep[i][j], + PixelClock[k], + HTotal[k], + VTotal[k] - VActive[k], + DynamicMetadataTransmittedBytes[k], + DynamicMetadataLinesBeforeActiveRequired[k], + Interlace[k], + ProgressiveToInterlaceUnitInOPP, + + /* output */ + &TSetupPipe, + &TdmbfPipe, + &TdmecPipe, + &TdmsksPipe, + &dummy1, + &dummy2, + &dummy3); + AllowedTimeForUrgentExtraLatency = MaximumVStartup[i][j][k] * HTotal[k] / + PixelClock[k] - MinimumTWait - TSetupPipe - TdmbfPipe - + TdmecPipe - TdmsksPipe - DynamicMetadataVMExtraLatency[k]; + if (AllowedTimeForUrgentExtraLatency > 0) + DCFCLKRequiredForPeakBandwidthPerSurface[k] = + dml_max(DCFCLKRequiredForPeakBandwidthPerSurface[k], + ExtraLatencyCycles / AllowedTimeForUrgentExtraLatency); + else + DCFCLKRequiredForPeakBandwidthPerSurface[k] = DCFCLKPerState[i]; + } + } + DCFCLKRequiredForPeakBandwidth = 0; + for (k = 0; k <= NumberOfActiveSurfaces - 1; ++k) { + DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + + DCFCLKRequiredForPeakBandwidthPerSurface[k]; + } + MinimumTvmPlus2Tr0 = UrgLatency[i] * (GPUVMEnable == true ? + (HostVMEnable == true ? (GPUVMMaxPageTableLevels + 2) * + (HostVMMaxNonCachedPageTableLevels + 1) - 1 : GPUVMMaxPageTableLevels + 1) : 0); + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + double MaximumTvmPlus2Tr0PlusTsw; + + MaximumTvmPlus2Tr0PlusTsw = (MaximumVStartup[i][j][k] - 2) * HTotal[k] / + PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k]; + if (MaximumTvmPlus2Tr0PlusTsw <= MinimumTvmPlus2Tr0 + PrefetchPixelLinesTime[k] / 4) { + DCFCLKRequiredForPeakBandwidth = DCFCLKPerState[i]; + } else { + DCFCLKRequiredForPeakBandwidth = dml_max3(DCFCLKRequiredForPeakBandwidth, + 2 * ExtraLatencyCycles / (MaximumTvmPlus2Tr0PlusTsw - + MinimumTvmPlus2Tr0 - + PrefetchPixelLinesTime[k] / 4), + (2 * ExtraLatencyCycles + + PixelDCFCLKCyclesRequiredInPrefetch[k]) / + (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0)); + } + } + DCFCLKState[i][j] = dml_min(DCFCLKPerState[i], 1.05 * + dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth)); + } + } +} + +unsigned int dml32_CalculateExtraLatencyBytes(unsigned int ReorderingBytes, + unsigned int TotalNumberOfActiveDPP, + unsigned int PixelChunkSizeInKByte, + unsigned int TotalNumberOfDCCActiveDPP, + unsigned int MetaChunkSize, + bool GPUVMEnable, + bool HostVMEnable, + unsigned int NumberOfActiveSurfaces, + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], + double HostVMInefficiencyFactor, + double HostVMMinPageSize, + unsigned int HostVMMaxNonCachedPageTableLevels) +{ + unsigned int k; + double ret; + unsigned int HostVMDynamicLevels; + + if (GPUVMEnable == true && HostVMEnable == true) { + if (HostVMMinPageSize < 2048) + HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; + else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) + HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + else + HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + } else { + HostVMDynamicLevels = 0; + } + + ret = ReorderingBytes + (TotalNumberOfActiveDPP * PixelChunkSizeInKByte + + TotalNumberOfDCCActiveDPP * MetaChunkSize) * 1024.0; + + if (GPUVMEnable == true) { + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + ret = ret + NumberOfDPP[k] * dpte_group_bytes[k] * + (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor; + } + } + return ret; +} + +void dml32_CalculateVUpdateAndDynamicMetadataParameters( + unsigned int MaxInterDCNTileRepeaters, + double Dppclk, + double Dispclk, + double DCFClkDeepSleep, + double PixelClock, + unsigned int HTotal, + unsigned int VBlank, + unsigned int DynamicMetadataTransmittedBytes, + unsigned int DynamicMetadataLinesBeforeActiveRequired, + unsigned int InterlaceEnable, + bool ProgressiveToInterlaceUnitInOPP, + + /* output */ + double *TSetup, + double *Tdmbf, + double *Tdmec, + double *Tdmsks, + unsigned int *VUpdateOffsetPix, + double *VUpdateWidthPix, + double *VReadyOffsetPix) +{ + double TotalRepeaterDelayTime; + + TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2 / Dppclk + 3 / Dispclk); + *VUpdateWidthPix = + dml_ceil((14.0 / DCFClkDeepSleep + 12.0 / Dppclk + TotalRepeaterDelayTime) * PixelClock, 1.0); + *VReadyOffsetPix = dml_ceil(dml_max(150.0 / Dppclk, + TotalRepeaterDelayTime + 20.0 / DCFClkDeepSleep + 10.0 / Dppclk) * PixelClock, 1.0); + *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1.0); + *TSetup = (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / PixelClock; + *Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / Dispclk; + *Tdmec = HTotal / PixelClock; + + if (DynamicMetadataLinesBeforeActiveRequired == 0) + *Tdmsks = VBlank * HTotal / PixelClock / 2.0; + else + *Tdmsks = DynamicMetadataLinesBeforeActiveRequired * HTotal / PixelClock; + + if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) + *Tdmsks = *Tdmsks / 2; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: VUpdateWidthPix = %d\n", __func__, *VUpdateWidthPix); + dml_print("DML::%s: VReadyOffsetPix = %d\n", __func__, *VReadyOffsetPix); + dml_print("DML::%s: VUpdateOffsetPix = %d\n", __func__, *VUpdateOffsetPix); + + dml_print("DML::%s: DynamicMetadataLinesBeforeActiveRequired = %d\n", + __func__, DynamicMetadataLinesBeforeActiveRequired); + dml_print("DML::%s: VBlank = %d\n", __func__, VBlank); + dml_print("DML::%s: HTotal = %d\n", __func__, HTotal); + dml_print("DML::%s: PixelClock = %f\n", __func__, PixelClock); + dml_print("DML::%s: Tdmsks = %f\n", __func__, *Tdmsks); +#endif +} + +double dml32_CalculateTWait( + unsigned int PrefetchMode, + enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange, + bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal, + bool DRRDisplay, + double DRAMClockChangeLatency, + double FCLKChangeLatency, + double UrgentLatency, + double SREnterPlusExitTime) +{ + double TWait = 0.0; + + if (PrefetchMode == 0 && + !(UseMALLForPStateChange == dm_use_mall_pstate_change_full_frame) && + !(UseMALLForPStateChange == dm_use_mall_pstate_change_sub_viewport) && + !(UseMALLForPStateChange == dm_use_mall_pstate_change_phantom_pipe) && + !(SynchronizeDRRDisplaysForUCLKPStateChangeFinal && DRRDisplay)) { + TWait = dml_max3(DRAMClockChangeLatency + UrgentLatency, SREnterPlusExitTime, UrgentLatency); + } else if (PrefetchMode <= 1 && !(UseMALLForPStateChange == dm_use_mall_pstate_change_phantom_pipe)) { + TWait = dml_max3(FCLKChangeLatency + UrgentLatency, SREnterPlusExitTime, UrgentLatency); + } else if (PrefetchMode <= 2 && !(UseMALLForPStateChange == dm_use_mall_pstate_change_phantom_pipe)) { + TWait = dml_max(SREnterPlusExitTime, UrgentLatency); + } else { + TWait = UrgentLatency; + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: PrefetchMode = %d\n", __func__, PrefetchMode); + dml_print("DML::%s: TWait = %f\n", __func__, TWait); +#endif + return TWait; +} // CalculateTWait + +// Function: get_return_bw_mbps +// Megabyte per second +double dml32_get_return_bw_mbps(const soc_bounding_box_st *soc, + const int VoltageLevel, + const bool HostVMEnable, + const double DCFCLK, + const double FabricClock, + const double DRAMSpeed) +{ + double ReturnBW = 0.; + double IdealSDPPortBandwidth = soc->return_bus_width_bytes /*mode_lib->vba.ReturnBusWidth*/ * DCFCLK; + double IdealFabricBandwidth = FabricClock * soc->fabric_datapath_to_dcn_data_return_bytes; + double IdealDRAMBandwidth = DRAMSpeed * soc->num_chans * soc->dram_channel_width_bytes; + double PixelDataOnlyReturnBW = dml_min3(IdealSDPPortBandwidth * soc->pct_ideal_sdp_bw_after_urgent / 100, + IdealFabricBandwidth * soc->pct_ideal_fabric_bw_after_urgent / 100, + IdealDRAMBandwidth * (VoltageLevel < 2 ? soc->pct_ideal_dram_bw_after_urgent_strobe : + soc->pct_ideal_dram_sdp_bw_after_urgent_pixel_only) / 100); + double PixelMixedWithVMDataReturnBW = dml_min3(IdealSDPPortBandwidth * soc->pct_ideal_sdp_bw_after_urgent / 100, + IdealFabricBandwidth * soc->pct_ideal_fabric_bw_after_urgent / 100, + IdealDRAMBandwidth * (VoltageLevel < 2 ? soc->pct_ideal_dram_bw_after_urgent_strobe : + soc->pct_ideal_dram_sdp_bw_after_urgent_pixel_only) / 100); + + if (HostVMEnable != true) + ReturnBW = PixelDataOnlyReturnBW; + else + ReturnBW = PixelMixedWithVMDataReturnBW; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: VoltageLevel = %d\n", __func__, VoltageLevel); + dml_print("DML::%s: HostVMEnable = %d\n", __func__, HostVMEnable); + dml_print("DML::%s: DCFCLK = %f\n", __func__, DCFCLK); + dml_print("DML::%s: FabricClock = %f\n", __func__, FabricClock); + dml_print("DML::%s: DRAMSpeed = %f\n", __func__, DRAMSpeed); + dml_print("DML::%s: IdealSDPPortBandwidth = %f\n", __func__, IdealSDPPortBandwidth); + dml_print("DML::%s: IdealFabricBandwidth = %f\n", __func__, IdealFabricBandwidth); + dml_print("DML::%s: IdealDRAMBandwidth = %f\n", __func__, IdealDRAMBandwidth); + dml_print("DML::%s: PixelDataOnlyReturnBW = %f\n", __func__, PixelDataOnlyReturnBW); + dml_print("DML::%s: PixelMixedWithVMDataReturnBW = %f\n", __func__, PixelMixedWithVMDataReturnBW); + dml_print("DML::%s: ReturnBW = %f MBps\n", __func__, ReturnBW); +#endif + return ReturnBW; +} + +// Function: get_return_bw_mbps_vm_only +// Megabyte per second +double dml32_get_return_bw_mbps_vm_only(const soc_bounding_box_st *soc, + const int VoltageLevel, + const double DCFCLK, + const double FabricClock, + const double DRAMSpeed) +{ + double VMDataOnlyReturnBW = dml_min3( + soc->return_bus_width_bytes * DCFCLK * soc->pct_ideal_sdp_bw_after_urgent / 100.0, + FabricClock * soc->fabric_datapath_to_dcn_data_return_bytes + * soc->pct_ideal_sdp_bw_after_urgent / 100.0, + DRAMSpeed * soc->num_chans * soc->dram_channel_width_bytes + * (VoltageLevel < 2 ? + soc->pct_ideal_dram_bw_after_urgent_strobe : + soc->pct_ideal_dram_sdp_bw_after_urgent_vm_only) / 100.0); +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: VoltageLevel = %d\n", __func__, VoltageLevel); + dml_print("DML::%s: DCFCLK = %f\n", __func__, DCFCLK); + dml_print("DML::%s: FabricClock = %f\n", __func__, FabricClock); + dml_print("DML::%s: DRAMSpeed = %f\n", __func__, DRAMSpeed); + dml_print("DML::%s: VMDataOnlyReturnBW = %f\n", __func__, VMDataOnlyReturnBW); +#endif + return VMDataOnlyReturnBW; +} + +double dml32_CalculateExtraLatency( + unsigned int RoundTripPingLatencyCycles, + unsigned int ReorderingBytes, + double DCFCLK, + unsigned int TotalNumberOfActiveDPP, + unsigned int PixelChunkSizeInKByte, + unsigned int TotalNumberOfDCCActiveDPP, + unsigned int MetaChunkSize, + double ReturnBW, + bool GPUVMEnable, + bool HostVMEnable, + unsigned int NumberOfActiveSurfaces, + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], + double HostVMInefficiencyFactor, + double HostVMMinPageSize, + unsigned int HostVMMaxNonCachedPageTableLevels) +{ + double ExtraLatencyBytes; + double ExtraLatency; + + ExtraLatencyBytes = dml32_CalculateExtraLatencyBytes( + ReorderingBytes, + TotalNumberOfActiveDPP, + PixelChunkSizeInKByte, + TotalNumberOfDCCActiveDPP, + MetaChunkSize, + GPUVMEnable, + HostVMEnable, + NumberOfActiveSurfaces, + NumberOfDPP, + dpte_group_bytes, + HostVMInefficiencyFactor, + HostVMMinPageSize, + HostVMMaxNonCachedPageTableLevels); + + ExtraLatency = (RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / DCFCLK + ExtraLatencyBytes / ReturnBW; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: RoundTripPingLatencyCycles=%d\n", __func__, RoundTripPingLatencyCycles); + dml_print("DML::%s: DCFCLK=%f\n", __func__, DCFCLK); + dml_print("DML::%s: ExtraLatencyBytes=%f\n", __func__, ExtraLatencyBytes); + dml_print("DML::%s: ReturnBW=%f\n", __func__, ReturnBW); + dml_print("DML::%s: ExtraLatency=%f\n", __func__, ExtraLatency); +#endif + + return ExtraLatency; +} // CalculateExtraLatency + +bool dml32_CalculatePrefetchSchedule( + double HostVMInefficiencyFactor, + DmlPipe *myPipe, + unsigned int DSCDelay, + double DPPCLKDelaySubtotalPlusCNVCFormater, + double DPPCLKDelaySCL, + double DPPCLKDelaySCLLBOnly, + double DPPCLKDelayCNVCCursor, + double DISPCLKDelaySubtotal, + unsigned int DPP_RECOUT_WIDTH, + enum output_format_class OutputFormat, + unsigned int MaxInterDCNTileRepeaters, + unsigned int VStartup, + unsigned int MaxVStartup, + unsigned int GPUVMPageTableLevels, + bool GPUVMEnable, + bool HostVMEnable, + unsigned int HostVMMaxNonCachedPageTableLevels, + double HostVMMinPageSize, + bool DynamicMetadataEnable, + bool DynamicMetadataVMEnabled, + int DynamicMetadataLinesBeforeActiveRequired, + unsigned int DynamicMetadataTransmittedBytes, + double UrgentLatency, + double UrgentExtraLatency, + double TCalc, + unsigned int PDEAndMetaPTEBytesFrame, + unsigned int MetaRowByte, + unsigned int PixelPTEBytesPerRow, + double PrefetchSourceLinesY, + unsigned int SwathWidthY, + unsigned int VInitPreFillY, + unsigned int MaxNumSwathY, + double PrefetchSourceLinesC, + unsigned int SwathWidthC, + unsigned int VInitPreFillC, + unsigned int MaxNumSwathC, + unsigned int swath_width_luma_ub, + unsigned int swath_width_chroma_ub, + unsigned int SwathHeightY, + unsigned int SwathHeightC, + double TWait, + /* Output */ + double *DSTXAfterScaler, + double *DSTYAfterScaler, + double *DestinationLinesForPrefetch, + double *PrefetchBandwidth, + double *DestinationLinesToRequestVMInVBlank, + double *DestinationLinesToRequestRowInVBlank, + double *VRatioPrefetchY, + double *VRatioPrefetchC, + double *RequiredPrefetchPixDataBWLuma, + double *RequiredPrefetchPixDataBWChroma, + bool *NotEnoughTimeForDynamicMetadata, + double *Tno_bw, + double *prefetch_vmrow_bw, + double *Tdmdl_vm, + double *Tdmdl, + double *TSetup, + unsigned int *VUpdateOffsetPix, + double *VUpdateWidthPix, + double *VReadyOffsetPix) +{ + bool MyError = false; + unsigned int DPPCycles, DISPCLKCycles; + double DSTTotalPixelsAfterScaler; + double LineTime; + double dst_y_prefetch_equ; + double prefetch_bw_oto; + double Tvm_oto; + double Tr0_oto; + double Tvm_oto_lines; + double Tr0_oto_lines; + double dst_y_prefetch_oto; + double TimeForFetchingMetaPTE = 0; + double TimeForFetchingRowInVBlank = 0; + double LinesToRequestPrefetchPixelData = 0; + unsigned int HostVMDynamicLevelsTrips; + double trip_to_mem; + double Tvm_trips; + double Tr0_trips; + double Tvm_trips_rounded; + double Tr0_trips_rounded; + double Lsw_oto; + double Tpre_rounded; + double prefetch_bw_equ; + double Tvm_equ; + double Tr0_equ; + double Tdmbf; + double Tdmec; + double Tdmsks; + double prefetch_sw_bytes; + double bytes_pp; + double dep_bytes; + unsigned int max_vratio_pre = __DML_MAX_VRATIO_PRE__; + double min_Lsw; + double Tsw_est1 = 0; + double Tsw_est3 = 0; + + if (GPUVMEnable == true && HostVMEnable == true) + HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels; + else + HostVMDynamicLevelsTrips = 0; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: GPUVMEnable = %d\n", __func__, GPUVMEnable); + dml_print("DML::%s: GPUVMPageTableLevels = %d\n", __func__, GPUVMPageTableLevels); + dml_print("DML::%s: DCCEnable = %d\n", __func__, myPipe->DCCEnable); + dml_print("DML::%s: HostVMEnable=%d HostVMInefficiencyFactor=%f\n", + __func__, HostVMEnable, HostVMInefficiencyFactor); +#endif + dml32_CalculateVUpdateAndDynamicMetadataParameters( + MaxInterDCNTileRepeaters, + myPipe->Dppclk, + myPipe->Dispclk, + myPipe->DCFClkDeepSleep, + myPipe->PixelClock, + myPipe->HTotal, + myPipe->VBlank, + DynamicMetadataTransmittedBytes, + DynamicMetadataLinesBeforeActiveRequired, + myPipe->InterlaceEnable, + myPipe->ProgressiveToInterlaceUnitInOPP, + TSetup, + + /* output */ + &Tdmbf, + &Tdmec, + &Tdmsks, + VUpdateOffsetPix, + VUpdateWidthPix, + VReadyOffsetPix); + + LineTime = myPipe->HTotal / myPipe->PixelClock; + trip_to_mem = UrgentLatency; + Tvm_trips = UrgentExtraLatency + trip_to_mem * (GPUVMPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1); + + if (DynamicMetadataVMEnabled == true) + *Tdmdl = TWait + Tvm_trips + trip_to_mem; + else + *Tdmdl = TWait + UrgentExtraLatency; + +#ifdef __DML_VBA_ALLOW_DELTA__ + if (DynamicMetadataEnable == false) + *Tdmdl = 0.0; +#endif + + if (DynamicMetadataEnable == true) { + if (VStartup * LineTime < *TSetup + *Tdmdl + Tdmbf + Tdmec + Tdmsks) { + *NotEnoughTimeForDynamicMetadata = true; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: Not Enough Time for Dynamic Meta!\n", __func__); + dml_print("DML::%s: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", + __func__, Tdmbf); + dml_print("DML::%s: Tdmec: %fus - time dio takes to transfer dmd\n", __func__, Tdmec); + dml_print("DML::%s: Tdmsks: %fus - time before active dmd must complete transmission at dio\n", + __func__, Tdmsks); + dml_print("DML::%s: Tdmdl: %fus - time for fabric to become ready and fetch dmd\n", + __func__, *Tdmdl); +#endif + } else { + *NotEnoughTimeForDynamicMetadata = false; + } + } else { + *NotEnoughTimeForDynamicMetadata = false; + } + + *Tdmdl_vm = (DynamicMetadataEnable == true && DynamicMetadataVMEnabled == true && + GPUVMEnable == true ? TWait + Tvm_trips : 0); + + if (myPipe->ScalerEnabled) + DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCL; + else + DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCLLBOnly; + + DPPCycles = DPPCycles + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor; + + DISPCLKCycles = DISPCLKDelaySubtotal; + + if (myPipe->Dppclk == 0.0 || myPipe->Dispclk == 0.0) + return true; + + *DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->Dppclk + DISPCLKCycles * + myPipe->PixelClock / myPipe->Dispclk + DSCDelay; + + *DSTXAfterScaler = *DSTXAfterScaler + (myPipe->ODMMode != dm_odm_combine_mode_disabled ? 18 : 0) + + (myPipe->DPPPerSurface - 1) * DPP_RECOUT_WIDTH + + ((myPipe->ODMMode == dm_odm_split_mode_1to2 || myPipe->ODMMode == dm_odm_mode_mso_1to2) ? + myPipe->HActive / 2 : 0) + + ((myPipe->ODMMode == dm_odm_mode_mso_1to4) ? myPipe->HActive * 3 / 4 : 0); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: DPPCycles: %d\n", __func__, DPPCycles); + dml_print("DML::%s: PixelClock: %f\n", __func__, myPipe->PixelClock); + dml_print("DML::%s: Dppclk: %f\n", __func__, myPipe->Dppclk); + dml_print("DML::%s: DISPCLKCycles: %d\n", __func__, DISPCLKCycles); + dml_print("DML::%s: DISPCLK: %f\n", __func__, myPipe->Dispclk); + dml_print("DML::%s: DSCDelay: %d\n", __func__, DSCDelay); + dml_print("DML::%s: ODMMode: %d\n", __func__, myPipe->ODMMode); + dml_print("DML::%s: DPP_RECOUT_WIDTH: %d\n", __func__, DPP_RECOUT_WIDTH); + dml_print("DML::%s: DSTXAfterScaler: %d\n", __func__, *DSTXAfterScaler); +#endif + + if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP)) + *DSTYAfterScaler = 1; + else + *DSTYAfterScaler = 0; + + DSTTotalPixelsAfterScaler = *DSTYAfterScaler * myPipe->HTotal + *DSTXAfterScaler; + *DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / myPipe->HTotal, 1); + *DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * myPipe->HTotal)); +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: DSTXAfterScaler: %d (final)\n", __func__, *DSTXAfterScaler); + dml_print("DML::%s: DSTYAfterScaler: %d (final)\n", __func__, *DSTYAfterScaler); +#endif + + MyError = false; + + Tr0_trips = trip_to_mem * (HostVMDynamicLevelsTrips + 1); + + if (GPUVMEnable == true) { + Tvm_trips_rounded = dml_ceil(4.0 * Tvm_trips / LineTime, 1.0) / 4.0 * LineTime; + Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1.0) / 4.0 * LineTime; + if (GPUVMPageTableLevels >= 3) { + *Tno_bw = UrgentExtraLatency + trip_to_mem * + (double) ((GPUVMPageTableLevels - 2) * (HostVMDynamicLevelsTrips + 1) - 1); + } else if (GPUVMPageTableLevels == 1 && myPipe->DCCEnable != true) { + Tr0_trips_rounded = dml_ceil(4.0 * UrgentExtraLatency / LineTime, 1.0) / + 4.0 * LineTime; // VBA_ERROR + *Tno_bw = UrgentExtraLatency; + } else { + *Tno_bw = 0; + } + } else if (myPipe->DCCEnable == true) { + Tvm_trips_rounded = LineTime / 4.0; + Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1.0) / 4.0 * LineTime; + *Tno_bw = 0; + } else { + Tvm_trips_rounded = LineTime / 4.0; + Tr0_trips_rounded = LineTime / 2.0; + *Tno_bw = 0; + } + Tvm_trips_rounded = dml_max(Tvm_trips_rounded, LineTime / 4.0); + Tr0_trips_rounded = dml_max(Tr0_trips_rounded, LineTime / 4.0); + + if (myPipe->SourcePixelFormat == dm_420_8 || myPipe->SourcePixelFormat == dm_420_10 + || myPipe->SourcePixelFormat == dm_420_12) { + bytes_pp = myPipe->BytePerPixelY + myPipe->BytePerPixelC / 4; + } else { + bytes_pp = myPipe->BytePerPixelY + myPipe->BytePerPixelC; + } + + prefetch_sw_bytes = PrefetchSourceLinesY * swath_width_luma_ub * myPipe->BytePerPixelY + + PrefetchSourceLinesC * swath_width_chroma_ub * myPipe->BytePerPixelC; + prefetch_bw_oto = dml_max(bytes_pp * myPipe->PixelClock / myPipe->DPPPerSurface, + prefetch_sw_bytes / (dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime)); + + min_Lsw = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) / max_vratio_pre; + min_Lsw = dml_max(min_Lsw, 1.0); + Lsw_oto = dml_ceil(4.0 * dml_max(prefetch_sw_bytes / prefetch_bw_oto / LineTime, min_Lsw), 1.0) / 4.0; + + if (GPUVMEnable == true) { + Tvm_oto = dml_max3( + Tvm_trips, + *Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto, + LineTime / 4.0); + } else + Tvm_oto = LineTime / 4.0; + + if ((GPUVMEnable == true || myPipe->DCCEnable == true)) { + Tr0_oto = dml_max4( + Tr0_trips, + (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto, + (LineTime - Tvm_oto)/2.0, + LineTime / 4.0); +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: Tr0_oto max0 = %f\n", __func__, + (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto); + dml_print("DML::%s: Tr0_oto max1 = %f\n", __func__, Tr0_trips); + dml_print("DML::%s: Tr0_oto max2 = %f\n", __func__, LineTime - Tvm_oto); + dml_print("DML::%s: Tr0_oto max3 = %f\n", __func__, LineTime / 4); +#endif + } else + Tr0_oto = (LineTime - Tvm_oto) / 2.0; + + Tvm_oto_lines = dml_ceil(4.0 * Tvm_oto / LineTime, 1) / 4.0; + Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0; + dst_y_prefetch_oto = Tvm_oto_lines + 2 * Tr0_oto_lines + Lsw_oto; + + dst_y_prefetch_equ = VStartup - (*TSetup + dml_max(TWait + TCalc, *Tdmdl)) / LineTime - + (*DSTYAfterScaler + (double) *DSTXAfterScaler / (double) myPipe->HTotal); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: HTotal = %d\n", __func__, myPipe->HTotal); + dml_print("DML::%s: min_Lsw = %f\n", __func__, min_Lsw); + dml_print("DML::%s: *Tno_bw = %f\n", __func__, *Tno_bw); + dml_print("DML::%s: UrgentExtraLatency = %f\n", __func__, UrgentExtraLatency); + dml_print("DML::%s: trip_to_mem = %f\n", __func__, trip_to_mem); + dml_print("DML::%s: BytePerPixelY = %d\n", __func__, myPipe->BytePerPixelY); + dml_print("DML::%s: PrefetchSourceLinesY = %f\n", __func__, PrefetchSourceLinesY); + dml_print("DML::%s: swath_width_luma_ub = %d\n", __func__, swath_width_luma_ub); + dml_print("DML::%s: BytePerPixelC = %d\n", __func__, myPipe->BytePerPixelC); + dml_print("DML::%s: PrefetchSourceLinesC = %f\n", __func__, PrefetchSourceLinesC); + dml_print("DML::%s: swath_width_chroma_ub = %d\n", __func__, swath_width_chroma_ub); + dml_print("DML::%s: prefetch_sw_bytes = %f\n", __func__, prefetch_sw_bytes); + dml_print("DML::%s: bytes_pp = %f\n", __func__, bytes_pp); + dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, PDEAndMetaPTEBytesFrame); + dml_print("DML::%s: MetaRowByte = %d\n", __func__, MetaRowByte); + dml_print("DML::%s: PixelPTEBytesPerRow = %d\n", __func__, PixelPTEBytesPerRow); + dml_print("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, HostVMInefficiencyFactor); + dml_print("DML::%s: Tvm_trips = %f\n", __func__, Tvm_trips); + dml_print("DML::%s: Tr0_trips = %f\n", __func__, Tr0_trips); + dml_print("DML::%s: prefetch_bw_oto = %f\n", __func__, prefetch_bw_oto); + dml_print("DML::%s: Tr0_oto = %f\n", __func__, Tr0_oto); + dml_print("DML::%s: Tvm_oto = %f\n", __func__, Tvm_oto); + dml_print("DML::%s: Tvm_oto_lines = %f\n", __func__, Tvm_oto_lines); + dml_print("DML::%s: Tr0_oto_lines = %f\n", __func__, Tr0_oto_lines); + dml_print("DML::%s: Lsw_oto = %f\n", __func__, Lsw_oto); + dml_print("DML::%s: dst_y_prefetch_oto = %f\n", __func__, dst_y_prefetch_oto); + dml_print("DML::%s: dst_y_prefetch_equ = %f\n", __func__, dst_y_prefetch_equ); +#endif + + dst_y_prefetch_equ = dml_floor(4.0 * (dst_y_prefetch_equ + 0.125), 1) / 4.0; + Tpre_rounded = dst_y_prefetch_equ * LineTime; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: dst_y_prefetch_equ: %f (after round)\n", __func__, dst_y_prefetch_equ); + dml_print("DML::%s: LineTime: %f\n", __func__, LineTime); + dml_print("DML::%s: VStartup: %d\n", __func__, VStartup); + dml_print("DML::%s: Tvstartup: %fus - time between vstartup and first pixel of active\n", + __func__, VStartup * LineTime); + dml_print("DML::%s: TSetup: %fus - time from vstartup to vready\n", __func__, *TSetup); + dml_print("DML::%s: TCalc: %fus - time for calculations in dchub starting at vready\n", __func__, TCalc); + dml_print("DML::%s: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", __func__, Tdmbf); + dml_print("DML::%s: Tdmec: %fus - time dio takes to transfer dmd\n", __func__, Tdmec); + dml_print("DML::%s: Tdmdl_vm: %fus - time for vm stages of dmd\n", __func__, *Tdmdl_vm); + dml_print("DML::%s: Tdmdl: %fus - time for fabric to become ready and fetch dmd\n", __func__, *Tdmdl); + dml_print("DML::%s: DSTYAfterScaler: %d lines - number of lines of pipeline and buffer delay after scaler\n", + __func__, *DSTYAfterScaler); +#endif + dep_bytes = dml_max(PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor, + MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor); + + if (prefetch_sw_bytes < dep_bytes) + prefetch_sw_bytes = 2 * dep_bytes; + + *PrefetchBandwidth = 0; + *DestinationLinesToRequestVMInVBlank = 0; + *DestinationLinesToRequestRowInVBlank = 0; + *VRatioPrefetchY = 0; + *VRatioPrefetchC = 0; + *RequiredPrefetchPixDataBWLuma = 0; + if (dst_y_prefetch_equ > 1) { + double PrefetchBandwidth1; + double PrefetchBandwidth2; + double PrefetchBandwidth3; + double PrefetchBandwidth4; + + if (Tpre_rounded - *Tno_bw > 0) { + PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte + + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor + + prefetch_sw_bytes) / (Tpre_rounded - *Tno_bw); + Tsw_est1 = prefetch_sw_bytes / PrefetchBandwidth1; + } else + PrefetchBandwidth1 = 0; + + if (VStartup == MaxVStartup && (Tsw_est1 / LineTime < min_Lsw) + && Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - *Tno_bw > 0) { + PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte + + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor) + / (Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - *Tno_bw); + } + + if (Tpre_rounded - *Tno_bw - 2 * Tr0_trips_rounded > 0) + PrefetchBandwidth2 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + prefetch_sw_bytes) / + (Tpre_rounded - *Tno_bw - 2 * Tr0_trips_rounded); + else + PrefetchBandwidth2 = 0; + + if (Tpre_rounded - Tvm_trips_rounded > 0) { + PrefetchBandwidth3 = (2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor + + prefetch_sw_bytes) / (Tpre_rounded - Tvm_trips_rounded); + Tsw_est3 = prefetch_sw_bytes / PrefetchBandwidth3; + } else + PrefetchBandwidth3 = 0; + + + if (VStartup == MaxVStartup && + (Tsw_est3 / LineTime < min_Lsw) && Tpre_rounded - min_Lsw * LineTime - 0.75 * + LineTime - Tvm_trips_rounded > 0) { + PrefetchBandwidth3 = (2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor) + / (Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - Tvm_trips_rounded); + } + + if (Tpre_rounded - Tvm_trips_rounded - 2 * Tr0_trips_rounded > 0) { + PrefetchBandwidth4 = prefetch_sw_bytes / + (Tpre_rounded - Tvm_trips_rounded - 2 * Tr0_trips_rounded); + } else { + PrefetchBandwidth4 = 0; + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: Tpre_rounded: %f\n", __func__, Tpre_rounded); + dml_print("DML::%s: Tno_bw: %f\n", __func__, *Tno_bw); + dml_print("DML::%s: Tvm_trips_rounded: %f\n", __func__, Tvm_trips_rounded); + dml_print("DML::%s: Tsw_est1: %f\n", __func__, Tsw_est1); + dml_print("DML::%s: Tsw_est3: %f\n", __func__, Tsw_est3); + dml_print("DML::%s: PrefetchBandwidth1: %f\n", __func__, PrefetchBandwidth1); + dml_print("DML::%s: PrefetchBandwidth2: %f\n", __func__, PrefetchBandwidth2); + dml_print("DML::%s: PrefetchBandwidth3: %f\n", __func__, PrefetchBandwidth3); + dml_print("DML::%s: PrefetchBandwidth4: %f\n", __func__, PrefetchBandwidth4); +#endif + { + bool Case1OK; + bool Case2OK; + bool Case3OK; + + if (PrefetchBandwidth1 > 0) { + if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth1 + >= Tvm_trips_rounded + && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) + / PrefetchBandwidth1 >= Tr0_trips_rounded) { + Case1OK = true; + } else { + Case1OK = false; + } + } else { + Case1OK = false; + } + + if (PrefetchBandwidth2 > 0) { + if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth2 + >= Tvm_trips_rounded + && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) + / PrefetchBandwidth2 < Tr0_trips_rounded) { + Case2OK = true; + } else { + Case2OK = false; + } + } else { + Case2OK = false; + } + + if (PrefetchBandwidth3 > 0) { + if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth3 < + Tvm_trips_rounded && (MetaRowByte + PixelPTEBytesPerRow * + HostVMInefficiencyFactor) / PrefetchBandwidth3 >= + Tr0_trips_rounded) { + Case3OK = true; + } else { + Case3OK = false; + } + } else { + Case3OK = false; + } + + if (Case1OK) + prefetch_bw_equ = PrefetchBandwidth1; + else if (Case2OK) + prefetch_bw_equ = PrefetchBandwidth2; + else if (Case3OK) + prefetch_bw_equ = PrefetchBandwidth3; + else + prefetch_bw_equ = PrefetchBandwidth4; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: Case1OK: %d\n", __func__, Case1OK); + dml_print("DML::%s: Case2OK: %d\n", __func__, Case2OK); + dml_print("DML::%s: Case3OK: %d\n", __func__, Case3OK); + dml_print("DML::%s: prefetch_bw_equ: %f\n", __func__, prefetch_bw_equ); +#endif + + if (prefetch_bw_equ > 0) { + if (GPUVMEnable == true) { + Tvm_equ = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame * + HostVMInefficiencyFactor / prefetch_bw_equ, + Tvm_trips, LineTime / 4); + } else { + Tvm_equ = LineTime / 4; + } + + if ((GPUVMEnable == true || myPipe->DCCEnable == true)) { + Tr0_equ = dml_max4((MetaRowByte + PixelPTEBytesPerRow * + HostVMInefficiencyFactor) / prefetch_bw_equ, Tr0_trips, + (LineTime - Tvm_equ) / 2, LineTime / 4); + } else { + Tr0_equ = (LineTime - Tvm_equ) / 2; + } + } else { + Tvm_equ = 0; + Tr0_equ = 0; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML: prefetch_bw_equ equals 0! %s:%d\n", __FILE__, __LINE__); +#endif + } + } + + if (dst_y_prefetch_oto < dst_y_prefetch_equ) { + *DestinationLinesForPrefetch = dst_y_prefetch_oto; + TimeForFetchingMetaPTE = Tvm_oto; + TimeForFetchingRowInVBlank = Tr0_oto; + *PrefetchBandwidth = prefetch_bw_oto; + } else { + *DestinationLinesForPrefetch = dst_y_prefetch_equ; + TimeForFetchingMetaPTE = Tvm_equ; + TimeForFetchingRowInVBlank = Tr0_equ; + *PrefetchBandwidth = prefetch_bw_equ; + } + + *DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0; + + *DestinationLinesToRequestRowInVBlank = + dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0) / 4.0; + + LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch - + *DestinationLinesToRequestVMInVBlank - 2 * *DestinationLinesToRequestRowInVBlank; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: DestinationLinesForPrefetch = %f\n", __func__, *DestinationLinesForPrefetch); + dml_print("DML::%s: DestinationLinesToRequestVMInVBlank = %f\n", + __func__, *DestinationLinesToRequestVMInVBlank); + dml_print("DML::%s: TimeForFetchingRowInVBlank = %f\n", __func__, TimeForFetchingRowInVBlank); + dml_print("DML::%s: LineTime = %f\n", __func__, LineTime); + dml_print("DML::%s: DestinationLinesToRequestRowInVBlank = %f\n", + __func__, *DestinationLinesToRequestRowInVBlank); + dml_print("DML::%s: PrefetchSourceLinesY = %f\n", __func__, PrefetchSourceLinesY); + dml_print("DML::%s: LinesToRequestPrefetchPixelData = %f\n", __func__, LinesToRequestPrefetchPixelData); +#endif + + if (LinesToRequestPrefetchPixelData >= 1 && prefetch_bw_equ > 0) { + *VRatioPrefetchY = (double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData; + *VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0); +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: VRatioPrefetchY = %f\n", __func__, *VRatioPrefetchY); + dml_print("DML::%s: SwathHeightY = %d\n", __func__, SwathHeightY); + dml_print("DML::%s: VInitPreFillY = %d\n", __func__, VInitPreFillY); +#endif + if ((SwathHeightY > 4) && (VInitPreFillY > 3)) { + if (LinesToRequestPrefetchPixelData > (VInitPreFillY - 3.0) / 2.0) { + *VRatioPrefetchY = + dml_max((double) PrefetchSourceLinesY / + LinesToRequestPrefetchPixelData, + (double) MaxNumSwathY * SwathHeightY / + (LinesToRequestPrefetchPixelData - + (VInitPreFillY - 3.0) / 2.0)); + *VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0); + } else { + MyError = true; + *VRatioPrefetchY = 0; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: VRatioPrefetchY = %f\n", __func__, *VRatioPrefetchY); + dml_print("DML::%s: PrefetchSourceLinesY = %f\n", __func__, PrefetchSourceLinesY); + dml_print("DML::%s: MaxNumSwathY = %d\n", __func__, MaxNumSwathY); +#endif + } + + *VRatioPrefetchC = (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData; + *VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: VRatioPrefetchC = %f\n", __func__, *VRatioPrefetchC); + dml_print("DML::%s: SwathHeightC = %d\n", __func__, SwathHeightC); + dml_print("DML::%s: VInitPreFillC = %d\n", __func__, VInitPreFillC); +#endif + if ((SwathHeightC > 4)) { + if (LinesToRequestPrefetchPixelData > (VInitPreFillC - 3.0) / 2.0) { + *VRatioPrefetchC = + dml_max(*VRatioPrefetchC, + (double) MaxNumSwathC * SwathHeightC / + (LinesToRequestPrefetchPixelData - + (VInitPreFillC - 3.0) / 2.0)); + *VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0); + } else { + MyError = true; + *VRatioPrefetchC = 0; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: VRatioPrefetchC = %f\n", __func__, *VRatioPrefetchC); + dml_print("DML::%s: PrefetchSourceLinesC = %f\n", __func__, PrefetchSourceLinesC); + dml_print("DML::%s: MaxNumSwathC = %d\n", __func__, MaxNumSwathC); +#endif + } + + *RequiredPrefetchPixDataBWLuma = (double) PrefetchSourceLinesY + / LinesToRequestPrefetchPixelData * myPipe->BytePerPixelY * swath_width_luma_ub + / LineTime; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: BytePerPixelY = %d\n", __func__, myPipe->BytePerPixelY); + dml_print("DML::%s: swath_width_luma_ub = %d\n", __func__, swath_width_luma_ub); + dml_print("DML::%s: LineTime = %f\n", __func__, LineTime); + dml_print("DML::%s: RequiredPrefetchPixDataBWLuma = %f\n", + __func__, *RequiredPrefetchPixDataBWLuma); +#endif + *RequiredPrefetchPixDataBWChroma = (double) PrefetchSourceLinesC / + LinesToRequestPrefetchPixelData + * myPipe->BytePerPixelC + * swath_width_chroma_ub / LineTime; + } else { + MyError = true; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML:%s: MyErr set. LinesToRequestPrefetchPixelData: %f, should be > 0\n", + __func__, LinesToRequestPrefetchPixelData); +#endif + *VRatioPrefetchY = 0; + *VRatioPrefetchC = 0; + *RequiredPrefetchPixDataBWLuma = 0; + *RequiredPrefetchPixDataBWChroma = 0; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML: Tpre: %fus - sum of time to request meta pte, 2 x data pte + meta data, swaths\n", + (double)LinesToRequestPrefetchPixelData * LineTime + + 2.0*TimeForFetchingRowInVBlank + TimeForFetchingMetaPTE); + dml_print("DML: Tvm: %fus - time to fetch page tables for meta surface\n", TimeForFetchingMetaPTE); + dml_print("DML: To: %fus - time for propagation from scaler to optc\n", + (*DSTYAfterScaler + ((double) (*DSTXAfterScaler) / (double) myPipe->HTotal)) * LineTime); + dml_print("DML: Tvstartup - TSetup - Tcalc - Twait - Tpre - To > 0\n"); + dml_print("DML: Tslack(pre): %fus - time left over in schedule\n", VStartup * LineTime - + TimeForFetchingMetaPTE - 2*TimeForFetchingRowInVBlank - (*DSTYAfterScaler + + ((double) (*DSTXAfterScaler) / (double) myPipe->HTotal)) * LineTime - TWait - TCalc - *TSetup); + dml_print("DML: row_bytes = dpte_row_bytes (per_pipe) = PixelPTEBytesPerRow = : %d\n", + PixelPTEBytesPerRow); +#endif + } else { + MyError = true; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: MyErr set, dst_y_prefetch_equ = %f (should be > 1)\n", + __func__, dst_y_prefetch_equ); +#endif + } + + { + double prefetch_vm_bw; + double prefetch_row_bw; + + if (PDEAndMetaPTEBytesFrame == 0) { + prefetch_vm_bw = 0; + } else if (*DestinationLinesToRequestVMInVBlank > 0) { +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, PDEAndMetaPTEBytesFrame); + dml_print("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, HostVMInefficiencyFactor); + dml_print("DML::%s: DestinationLinesToRequestVMInVBlank = %f\n", + __func__, *DestinationLinesToRequestVMInVBlank); + dml_print("DML::%s: LineTime = %f\n", __func__, LineTime); +#endif + prefetch_vm_bw = PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / + (*DestinationLinesToRequestVMInVBlank * LineTime); +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: prefetch_vm_bw = %f\n", __func__, prefetch_vm_bw); +#endif + } else { + prefetch_vm_bw = 0; + MyError = true; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: MyErr set. DestinationLinesToRequestVMInVBlank=%f (should be > 0)\n", + __func__, *DestinationLinesToRequestVMInVBlank); +#endif + } + + if (MetaRowByte + PixelPTEBytesPerRow == 0) { + prefetch_row_bw = 0; + } else if (*DestinationLinesToRequestRowInVBlank > 0) { + prefetch_row_bw = (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / + (*DestinationLinesToRequestRowInVBlank * LineTime); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: MetaRowByte = %d\n", __func__, MetaRowByte); + dml_print("DML::%s: PixelPTEBytesPerRow = %d\n", __func__, PixelPTEBytesPerRow); + dml_print("DML::%s: DestinationLinesToRequestRowInVBlank = %f\n", + __func__, *DestinationLinesToRequestRowInVBlank); + dml_print("DML::%s: prefetch_row_bw = %f\n", __func__, prefetch_row_bw); +#endif + } else { + prefetch_row_bw = 0; + MyError = true; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: MyErr set. DestinationLinesToRequestRowInVBlank=%f (should be > 0)\n", + __func__, *DestinationLinesToRequestRowInVBlank); +#endif + } + + *prefetch_vmrow_bw = dml_max(prefetch_vm_bw, prefetch_row_bw); + } + + if (MyError) { + *PrefetchBandwidth = 0; + TimeForFetchingMetaPTE = 0; + TimeForFetchingRowInVBlank = 0; + *DestinationLinesToRequestVMInVBlank = 0; + *DestinationLinesToRequestRowInVBlank = 0; + *DestinationLinesForPrefetch = 0; + LinesToRequestPrefetchPixelData = 0; + *VRatioPrefetchY = 0; + *VRatioPrefetchC = 0; + *RequiredPrefetchPixDataBWLuma = 0; + *RequiredPrefetchPixDataBWChroma = 0; + } + + return MyError; +} // CalculatePrefetchSchedule + +void dml32_CalculateFlipSchedule( + double HostVMInefficiencyFactor, + double UrgentExtraLatency, + double UrgentLatency, + unsigned int GPUVMMaxPageTableLevels, + bool HostVMEnable, + unsigned int HostVMMaxNonCachedPageTableLevels, + bool GPUVMEnable, + double HostVMMinPageSize, + double PDEAndMetaPTEBytesPerFrame, + double MetaRowBytes, + double DPTEBytesPerRow, + double BandwidthAvailableForImmediateFlip, + unsigned int TotImmediateFlipBytes, + enum source_format_class SourcePixelFormat, + double LineTime, + double VRatio, + double VRatioChroma, + double Tno_bw, + bool DCCEnable, + unsigned int dpte_row_height, + unsigned int meta_row_height, + unsigned int dpte_row_height_chroma, + unsigned int meta_row_height_chroma, + bool use_one_row_for_frame_flip, + + /* Output */ + double *DestinationLinesToRequestVMInImmediateFlip, + double *DestinationLinesToRequestRowInImmediateFlip, + double *final_flip_bw, + bool *ImmediateFlipSupportedForPipe) +{ + double min_row_time = 0.0; + unsigned int HostVMDynamicLevelsTrips; + double TimeForFetchingMetaPTEImmediateFlip; + double TimeForFetchingRowInVBlankImmediateFlip; + double ImmediateFlipBW; + + if (GPUVMEnable == true && HostVMEnable == true) + HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels; + else + HostVMDynamicLevelsTrips = 0; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: TotImmediateFlipBytes = %d\n", __func__, TotImmediateFlipBytes); + dml_print("DML::%s: BandwidthAvailableForImmediateFlip = %f\n", __func__, BandwidthAvailableForImmediateFlip); +#endif + + if (TotImmediateFlipBytes > 0) { + if (use_one_row_for_frame_flip) { + ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + 2 * DPTEBytesPerRow) * + BandwidthAvailableForImmediateFlip / TotImmediateFlipBytes; + } else { + ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + DPTEBytesPerRow) * + BandwidthAvailableForImmediateFlip / TotImmediateFlipBytes; + } + if (GPUVMEnable == true) { + TimeForFetchingMetaPTEImmediateFlip = dml_max3(Tno_bw + PDEAndMetaPTEBytesPerFrame * + HostVMInefficiencyFactor / ImmediateFlipBW, + UrgentExtraLatency + UrgentLatency * + (GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1), + LineTime / 4.0); + } else { + TimeForFetchingMetaPTEImmediateFlip = 0; + } + if ((GPUVMEnable == true || DCCEnable == true)) { + TimeForFetchingRowInVBlankImmediateFlip = dml_max3( + (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / ImmediateFlipBW, + UrgentLatency * (HostVMDynamicLevelsTrips + 1), LineTime / 4.0); + } else { + TimeForFetchingRowInVBlankImmediateFlip = 0; + } + + *DestinationLinesToRequestVMInImmediateFlip = + dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1.0) / 4.0; + *DestinationLinesToRequestRowInImmediateFlip = + dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1.0) / 4.0; + + if (GPUVMEnable == true) { + *final_flip_bw = dml_max(PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / + (*DestinationLinesToRequestVMInImmediateFlip * LineTime), + (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / + (*DestinationLinesToRequestRowInImmediateFlip * LineTime)); + } else if ((GPUVMEnable == true || DCCEnable == true)) { + *final_flip_bw = (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / + (*DestinationLinesToRequestRowInImmediateFlip * LineTime); + } else { + *final_flip_bw = 0; + } + } else { + TimeForFetchingMetaPTEImmediateFlip = 0; + TimeForFetchingRowInVBlankImmediateFlip = 0; + *DestinationLinesToRequestVMInImmediateFlip = 0; + *DestinationLinesToRequestRowInImmediateFlip = 0; + *final_flip_bw = 0; + } + + if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_rgbe_alpha) { + if (GPUVMEnable == true && DCCEnable != true) { + min_row_time = dml_min(dpte_row_height * + LineTime / VRatio, dpte_row_height_chroma * LineTime / VRatioChroma); + } else if (GPUVMEnable != true && DCCEnable == true) { + min_row_time = dml_min(meta_row_height * + LineTime / VRatio, meta_row_height_chroma * LineTime / VRatioChroma); + } else { + min_row_time = dml_min4(dpte_row_height * LineTime / VRatio, meta_row_height * + LineTime / VRatio, dpte_row_height_chroma * LineTime / + VRatioChroma, meta_row_height_chroma * LineTime / VRatioChroma); + } + } else { + if (GPUVMEnable == true && DCCEnable != true) { + min_row_time = dpte_row_height * LineTime / VRatio; + } else if (GPUVMEnable != true && DCCEnable == true) { + min_row_time = meta_row_height * LineTime / VRatio; + } else { + min_row_time = + dml_min(dpte_row_height * LineTime / VRatio, meta_row_height * LineTime / VRatio); + } + } + + if (*DestinationLinesToRequestVMInImmediateFlip >= 32 || *DestinationLinesToRequestRowInImmediateFlip >= 16 + || TimeForFetchingMetaPTEImmediateFlip + 2 * TimeForFetchingRowInVBlankImmediateFlip + > min_row_time) { + *ImmediateFlipSupportedForPipe = false; + } else { + *ImmediateFlipSupportedForPipe = true; + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: GPUVMEnable = %d\n", __func__, GPUVMEnable); + dml_print("DML::%s: DCCEnable = %d\n", __func__, DCCEnable); + dml_print("DML::%s: DestinationLinesToRequestVMInImmediateFlip = %f\n", + __func__, *DestinationLinesToRequestVMInImmediateFlip); + dml_print("DML::%s: DestinationLinesToRequestRowInImmediateFlip = %f\n", + __func__, *DestinationLinesToRequestRowInImmediateFlip); + dml_print("DML::%s: TimeForFetchingMetaPTEImmediateFlip = %f\n", __func__, TimeForFetchingMetaPTEImmediateFlip); + dml_print("DML::%s: TimeForFetchingRowInVBlankImmediateFlip = %f\n", + __func__, TimeForFetchingRowInVBlankImmediateFlip); + dml_print("DML::%s: min_row_time = %f\n", __func__, min_row_time); + dml_print("DML::%s: ImmediateFlipSupportedForPipe = %d\n", __func__, *ImmediateFlipSupportedForPipe); +#endif +} // CalculateFlipSchedule + +void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( + bool USRRetrainingRequiredFinal, + enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[], + unsigned int PrefetchMode, + unsigned int NumberOfActiveSurfaces, + unsigned int MaxLineBufferLines, + unsigned int LineBufferSize, + unsigned int WritebackInterfaceBufferSize, + double DCFCLK, + double ReturnBW, + bool SynchronizeTimingsFinal, + bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal, + bool DRRDisplay[], + unsigned int dpte_group_bytes[], + unsigned int meta_row_height[], + unsigned int meta_row_height_chroma[], + SOCParametersList mmSOCParameters, + unsigned int WritebackChunkSize, + double SOCCLK, + double DCFClkDeepSleep, + unsigned int DETBufferSizeY[], + unsigned int DETBufferSizeC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], + unsigned int LBBitPerPixel[], + double SwathWidthY[], + double SwathWidthC[], + double HRatio[], + double HRatioChroma[], + unsigned int VTaps[], + unsigned int VTapsChroma[], + double VRatio[], + double VRatioChroma[], + unsigned int HTotal[], + unsigned int VTotal[], + unsigned int VActive[], + double PixelClock[], + unsigned int BlendingAndTiming[], + unsigned int DPPPerSurface[], + double BytePerPixelDETY[], + double BytePerPixelDETC[], + double DSTXAfterScaler[], + double DSTYAfterScaler[], + bool WritebackEnable[], + enum source_format_class WritebackPixelFormat[], + double WritebackDestinationWidth[], + double WritebackDestinationHeight[], + double WritebackSourceHeight[], + bool UnboundedRequestEnabled, + unsigned int CompressedBufferSizeInkByte, + + /* Output */ + Watermarks *Watermark, + enum clock_change_support *DRAMClockChangeSupport, + double MaxActiveDRAMClockChangeLatencySupported[], + unsigned int SubViewportLinesNeededInMALL[], + enum dm_fclock_change_support *FCLKChangeSupport, + double *MinActiveFCLKChangeLatencySupported, + bool *USRRetrainingSupport, + double ActiveDRAMClockChangeLatencyMargin[]) +{ + unsigned int i, j, k; + unsigned int SurfaceWithMinActiveFCLKChangeMargin = 0; + unsigned int DRAMClockChangeSupportNumber = 0; + unsigned int LastSurfaceWithoutMargin; + unsigned int DRAMClockChangeMethod = 0; + bool FoundFirstSurfaceWithMinActiveFCLKChangeMargin = false; + double MinActiveFCLKChangeMargin = 0.; + double SecondMinActiveFCLKChangeMarginOneDisplayInVBLank = 0.; + double ActiveClockChangeLatencyHidingY; + double ActiveClockChangeLatencyHidingC; + double ActiveClockChangeLatencyHiding; + double EffectiveDETBufferSizeY; + double ActiveFCLKChangeLatencyMargin[DC__NUM_DPP__MAX]; + double USRRetrainingLatencyMargin[DC__NUM_DPP__MAX]; + double TotalPixelBW = 0.0; + bool SynchronizedSurfaces[DC__NUM_DPP__MAX][DC__NUM_DPP__MAX]; + double EffectiveLBLatencyHidingY; + double EffectiveLBLatencyHidingC; + double LinesInDETY[DC__NUM_DPP__MAX]; + double LinesInDETC[DC__NUM_DPP__MAX]; + unsigned int LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX]; + unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX]; + double FullDETBufferingTimeY; + double FullDETBufferingTimeC; + double WritebackDRAMClockChangeLatencyMargin; + double WritebackFCLKChangeLatencyMargin; + double WritebackLatencyHiding; + bool SameTimingForFCLKChange; + + unsigned int TotalActiveWriteback = 0; + unsigned int LBLatencyHidingSourceLinesY[DC__NUM_DPP__MAX]; + unsigned int LBLatencyHidingSourceLinesC[DC__NUM_DPP__MAX]; + + Watermark->UrgentWatermark = mmSOCParameters.UrgentLatency + mmSOCParameters.ExtraLatency; + Watermark->USRRetrainingWatermark = mmSOCParameters.UrgentLatency + mmSOCParameters.ExtraLatency + + mmSOCParameters.USRRetrainingLatency + mmSOCParameters.SMNLatency; + Watermark->DRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency + Watermark->UrgentWatermark; + Watermark->FCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency + Watermark->UrgentWatermark; + Watermark->StutterExitWatermark = mmSOCParameters.SRExitTime + mmSOCParameters.ExtraLatency + + 10 / DCFClkDeepSleep; + Watermark->StutterEnterPlusExitWatermark = mmSOCParameters.SREnterPlusExitTime + mmSOCParameters.ExtraLatency + + 10 / DCFClkDeepSleep; + Watermark->Z8StutterExitWatermark = mmSOCParameters.SRExitZ8Time + mmSOCParameters.ExtraLatency + + 10 / DCFClkDeepSleep; + Watermark->Z8StutterEnterPlusExitWatermark = mmSOCParameters.SREnterPlusExitZ8Time + + mmSOCParameters.ExtraLatency + 10 / DCFClkDeepSleep; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: UrgentLatency = %f\n", __func__, mmSOCParameters.UrgentLatency); + dml_print("DML::%s: ExtraLatency = %f\n", __func__, mmSOCParameters.ExtraLatency); + dml_print("DML::%s: DRAMClockChangeLatency = %f\n", __func__, mmSOCParameters.DRAMClockChangeLatency); + dml_print("DML::%s: UrgentWatermark = %f\n", __func__, Watermark->UrgentWatermark); + dml_print("DML::%s: USRRetrainingWatermark = %f\n", __func__, Watermark->USRRetrainingWatermark); + dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, Watermark->DRAMClockChangeWatermark); + dml_print("DML::%s: FCLKChangeWatermark = %f\n", __func__, Watermark->FCLKChangeWatermark); + dml_print("DML::%s: StutterExitWatermark = %f\n", __func__, Watermark->StutterExitWatermark); + dml_print("DML::%s: StutterEnterPlusExitWatermark = %f\n", __func__, Watermark->StutterEnterPlusExitWatermark); + dml_print("DML::%s: Z8StutterExitWatermark = %f\n", __func__, Watermark->Z8StutterExitWatermark); + dml_print("DML::%s: Z8StutterEnterPlusExitWatermark = %f\n", + __func__, Watermark->Z8StutterEnterPlusExitWatermark); +#endif + + + TotalActiveWriteback = 0; + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (WritebackEnable[k] == true) + TotalActiveWriteback = TotalActiveWriteback + 1; + } + + if (TotalActiveWriteback <= 1) { + Watermark->WritebackUrgentWatermark = mmSOCParameters.WritebackLatency; + } else { + Watermark->WritebackUrgentWatermark = mmSOCParameters.WritebackLatency + + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; + } + if (USRRetrainingRequiredFinal) + Watermark->WritebackUrgentWatermark = Watermark->WritebackUrgentWatermark + + mmSOCParameters.USRRetrainingLatency; + + if (TotalActiveWriteback <= 1) { + Watermark->WritebackDRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency + + mmSOCParameters.WritebackLatency; + Watermark->WritebackFCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency + + mmSOCParameters.WritebackLatency; + } else { + Watermark->WritebackDRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency + + mmSOCParameters.WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; + Watermark->WritebackFCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency + + mmSOCParameters.WritebackLatency + WritebackChunkSize * 1024 / 32 / SOCCLK; + } + + if (USRRetrainingRequiredFinal) + Watermark->WritebackDRAMClockChangeWatermark = Watermark->WritebackDRAMClockChangeWatermark + + mmSOCParameters.USRRetrainingLatency; + + if (USRRetrainingRequiredFinal) + Watermark->WritebackFCLKChangeWatermark = Watermark->WritebackFCLKChangeWatermark + + mmSOCParameters.USRRetrainingLatency; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: WritebackDRAMClockChangeWatermark = %f\n", + __func__, Watermark->WritebackDRAMClockChangeWatermark); + dml_print("DML::%s: WritebackFCLKChangeWatermark = %f\n", __func__, Watermark->WritebackFCLKChangeWatermark); + dml_print("DML::%s: WritebackUrgentWatermark = %f\n", __func__, Watermark->WritebackUrgentWatermark); + dml_print("DML::%s: USRRetrainingRequiredFinal = %d\n", __func__, USRRetrainingRequiredFinal); + dml_print("DML::%s: USRRetrainingLatency = %f\n", __func__, mmSOCParameters.USRRetrainingLatency); +#endif + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + TotalPixelBW = TotalPixelBW + DPPPerSurface[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k] + + SwathWidthC[k] * BytePerPixelDETC[k] * VRatioChroma[k]) / (HTotal[k] / PixelClock[k]); + } + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + + LBLatencyHidingSourceLinesY[k] = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) - (VTaps[k] - 1); + LBLatencyHidingSourceLinesC[k] = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(HRatioChroma[k], 1.0)), 1)) - (VTapsChroma[k] - 1); + + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d, MaxLineBufferLines = %d\n", __func__, k, MaxLineBufferLines); + dml_print("DML::%s: k=%d, LineBufferSize = %d\n", __func__, k, LineBufferSize); + dml_print("DML::%s: k=%d, LBBitPerPixel = %d\n", __func__, k, LBBitPerPixel[k]); + dml_print("DML::%s: k=%d, HRatio = %f\n", __func__, k, HRatio[k]); + dml_print("DML::%s: k=%d, VTaps = %d\n", __func__, k, VTaps[k]); +#endif + + EffectiveLBLatencyHidingY = LBLatencyHidingSourceLinesY[k] / VRatio[k] * (HTotal[k] / PixelClock[k]); + EffectiveLBLatencyHidingC = LBLatencyHidingSourceLinesC[k] / VRatioChroma[k] * (HTotal[k] / PixelClock[k]); + EffectiveDETBufferSizeY = DETBufferSizeY[k]; + + if (UnboundedRequestEnabled) { + EffectiveDETBufferSizeY = EffectiveDETBufferSizeY + + CompressedBufferSizeInkByte * 1024 + * (SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k]) + / (HTotal[k] / PixelClock[k]) / TotalPixelBW; + } + + LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k]; + LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); + FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k]; + + ActiveClockChangeLatencyHidingY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY + - (DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] / PixelClock[k]; + + if (NumberOfActiveSurfaces > 1) { + ActiveClockChangeLatencyHidingY = ActiveClockChangeLatencyHidingY + - (1 - 1 / NumberOfActiveSurfaces) * SwathHeightY[k] * HTotal[k] + / PixelClock[k] / VRatio[k]; + } + + if (BytePerPixelDETC[k] > 0) { + LinesInDETC[k] = DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k]; + LinesInDETCRoundedDownToSwath[k] = dml_floor(LinesInDETC[k], SwathHeightC[k]); + FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) + / VRatioChroma[k]; + ActiveClockChangeLatencyHidingC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC + - (DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] + / PixelClock[k]; + if (NumberOfActiveSurfaces > 1) { + ActiveClockChangeLatencyHidingC = ActiveClockChangeLatencyHidingC + - (1 - 1 / NumberOfActiveSurfaces) * SwathHeightC[k] * HTotal[k] + / PixelClock[k] / VRatioChroma[k]; + } + ActiveClockChangeLatencyHiding = dml_min(ActiveClockChangeLatencyHidingY, + ActiveClockChangeLatencyHidingC); + } else { + ActiveClockChangeLatencyHiding = ActiveClockChangeLatencyHidingY; + } + + ActiveDRAMClockChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - Watermark->UrgentWatermark + - Watermark->DRAMClockChangeWatermark; + ActiveFCLKChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - Watermark->UrgentWatermark + - Watermark->FCLKChangeWatermark; + USRRetrainingLatencyMargin[k] = ActiveClockChangeLatencyHiding - Watermark->USRRetrainingWatermark; + + if (WritebackEnable[k]) { + WritebackLatencyHiding = WritebackInterfaceBufferSize * 1024 + / (WritebackDestinationWidth[k] * WritebackDestinationHeight[k] + / (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k]) * 4); + if (WritebackPixelFormat[k] == dm_444_64) + WritebackLatencyHiding = WritebackLatencyHiding / 2; + + WritebackDRAMClockChangeLatencyMargin = WritebackLatencyHiding + - Watermark->WritebackDRAMClockChangeWatermark; + + WritebackFCLKChangeLatencyMargin = WritebackLatencyHiding + - Watermark->WritebackFCLKChangeWatermark; + + ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMargin[k], + WritebackFCLKChangeLatencyMargin); + ActiveFCLKChangeLatencyMargin[k] = dml_min(ActiveFCLKChangeLatencyMargin[k], + WritebackDRAMClockChangeLatencyMargin); + } + MaxActiveDRAMClockChangeLatencySupported[k] = + (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) ? + 0 : + (ActiveDRAMClockChangeLatencyMargin[k] + + mmSOCParameters.DRAMClockChangeLatency); + } + + for (i = 0; i < NumberOfActiveSurfaces; ++i) { + for (j = 0; j < NumberOfActiveSurfaces; ++j) { + if (i == j || + (BlendingAndTiming[i] == i && BlendingAndTiming[j] == i) || + (BlendingAndTiming[j] == j && BlendingAndTiming[i] == j) || + (BlendingAndTiming[i] == BlendingAndTiming[j] && BlendingAndTiming[i] != i) || + (SynchronizeTimingsFinal && PixelClock[i] == PixelClock[j] && + HTotal[i] == HTotal[j] && VTotal[i] == VTotal[j] && + VActive[i] == VActive[j]) || (SynchronizeDRRDisplaysForUCLKPStateChangeFinal && + (DRRDisplay[i] || DRRDisplay[j]))) { + SynchronizedSurfaces[i][j] = true; + } else { + SynchronizedSurfaces[i][j] = false; + } + } + } + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if ((UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) && + (!FoundFirstSurfaceWithMinActiveFCLKChangeMargin || + ActiveFCLKChangeLatencyMargin[k] < MinActiveFCLKChangeMargin)) { + FoundFirstSurfaceWithMinActiveFCLKChangeMargin = true; + MinActiveFCLKChangeMargin = ActiveFCLKChangeLatencyMargin[k]; + SurfaceWithMinActiveFCLKChangeMargin = k; + } + } + + *MinActiveFCLKChangeLatencySupported = MinActiveFCLKChangeMargin + mmSOCParameters.FCLKChangeLatency; + + SameTimingForFCLKChange = true; + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (!SynchronizedSurfaces[k][SurfaceWithMinActiveFCLKChangeMargin]) { + if ((UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) && + (SameTimingForFCLKChange || + ActiveFCLKChangeLatencyMargin[k] < + SecondMinActiveFCLKChangeMarginOneDisplayInVBLank)) { + SecondMinActiveFCLKChangeMarginOneDisplayInVBLank = ActiveFCLKChangeLatencyMargin[k]; + } + SameTimingForFCLKChange = false; + } + } + + if (MinActiveFCLKChangeMargin > 0) { + *FCLKChangeSupport = dm_fclock_change_vactive; + } else if ((SameTimingForFCLKChange || SecondMinActiveFCLKChangeMarginOneDisplayInVBLank > 0) && + (PrefetchMode <= 1)) { + *FCLKChangeSupport = dm_fclock_change_vblank; + } else { + *FCLKChangeSupport = dm_fclock_change_unsupported; + } + + *USRRetrainingSupport = true; + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if ((UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) && + (USRRetrainingLatencyMargin[k] < 0)) { + *USRRetrainingSupport = false; + } + } + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_full_frame && + UseMALLForPStateChange[k] != dm_use_mall_pstate_change_sub_viewport && + UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe && + ActiveDRAMClockChangeLatencyMargin[k] < 0) { + if (PrefetchMode > 0) { + DRAMClockChangeSupportNumber = 2; + } else if (DRAMClockChangeSupportNumber == 0) { + DRAMClockChangeSupportNumber = 1; + LastSurfaceWithoutMargin = k; + } else if (DRAMClockChangeSupportNumber == 1 && + !SynchronizedSurfaces[LastSurfaceWithoutMargin][k]) { + DRAMClockChangeSupportNumber = 2; + } + } + } + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame) + DRAMClockChangeMethod = 1; + else if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport) + DRAMClockChangeMethod = 2; + } + + if (DRAMClockChangeMethod == 0) { + if (DRAMClockChangeSupportNumber == 0) + *DRAMClockChangeSupport = dm_dram_clock_change_vactive; + else if (DRAMClockChangeSupportNumber == 1) + *DRAMClockChangeSupport = dm_dram_clock_change_vblank; + else + *DRAMClockChangeSupport = dm_dram_clock_change_unsupported; + } else if (DRAMClockChangeMethod == 1) { + if (DRAMClockChangeSupportNumber == 0) + *DRAMClockChangeSupport = dm_dram_clock_change_vactive_w_mall_full_frame; + else if (DRAMClockChangeSupportNumber == 1) + *DRAMClockChangeSupport = dm_dram_clock_change_vblank_w_mall_full_frame; + else + *DRAMClockChangeSupport = dm_dram_clock_change_unsupported; + } else { + if (DRAMClockChangeSupportNumber == 0) + *DRAMClockChangeSupport = dm_dram_clock_change_vactive_w_mall_sub_vp; + else if (DRAMClockChangeSupportNumber == 1) + *DRAMClockChangeSupport = dm_dram_clock_change_vblank_w_mall_sub_vp; + else + *DRAMClockChangeSupport = dm_dram_clock_change_unsupported; + } + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + unsigned int dst_y_pstate; + unsigned int src_y_pstate_l; + unsigned int src_y_pstate_c; + unsigned int src_y_ahead_l, src_y_ahead_c, sub_vp_lines_l, sub_vp_lines_c; + + dst_y_pstate = dml_ceil((mmSOCParameters.DRAMClockChangeLatency + mmSOCParameters.UrgentLatency) / (HTotal[k] / PixelClock[k]), 1); + src_y_pstate_l = dml_ceil(dst_y_pstate * VRatio[k], SwathHeightY[k]); + src_y_ahead_l = dml_floor(DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k], SwathHeightY[k]) + LBLatencyHidingSourceLinesY[k]; + sub_vp_lines_l = src_y_pstate_l + src_y_ahead_l + meta_row_height[k]; + +#ifdef __DML_VBA_DEBUG__ +dml_print("DML::%s: k=%d, DETBufferSizeY = %d\n", __func__, k, DETBufferSizeY[k]); +dml_print("DML::%s: k=%d, BytePerPixelDETY = %f\n", __func__, k, BytePerPixelDETY[k]); +dml_print("DML::%s: k=%d, SwathWidthY = %d\n", __func__, k, SwathWidthY[k]); +dml_print("DML::%s: k=%d, SwathHeightY = %d\n", __func__, k, SwathHeightY[k]); +dml_print("DML::%s: k=%d, LBLatencyHidingSourceLinesY = %d\n", __func__, k, LBLatencyHidingSourceLinesY[k]); +dml_print("DML::%s: k=%d, dst_y_pstate = %d\n", __func__, k, dst_y_pstate); +dml_print("DML::%s: k=%d, src_y_pstate_l = %d\n", __func__, k, src_y_pstate_l); +dml_print("DML::%s: k=%d, src_y_ahead_l = %d\n", __func__, k, src_y_ahead_l); +dml_print("DML::%s: k=%d, meta_row_height = %d\n", __func__, k, meta_row_height[k]); +dml_print("DML::%s: k=%d, sub_vp_lines_l = %d\n", __func__, k, sub_vp_lines_l); +#endif + SubViewportLinesNeededInMALL[k] = sub_vp_lines_l; + + if (BytePerPixelDETC[k] > 0) { + src_y_pstate_c = dml_ceil(dst_y_pstate * VRatioChroma[k], SwathHeightC[k]); + src_y_ahead_c = dml_floor(DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k], SwathHeightC[k]) + LBLatencyHidingSourceLinesC[k]; + sub_vp_lines_c = src_y_pstate_c + src_y_ahead_c + meta_row_height_chroma[k]; + SubViewportLinesNeededInMALL[k] = dml_max(sub_vp_lines_l, sub_vp_lines_c); + +#ifdef __DML_VBA_DEBUG__ +dml_print("DML::%s: k=%d, src_y_pstate_c = %d\n", __func__, k, src_y_pstate_c); +dml_print("DML::%s: k=%d, src_y_ahead_c = %d\n", __func__, k, src_y_ahead_c); +dml_print("DML::%s: k=%d, meta_row_height_chroma = %d\n", __func__, k, meta_row_height_chroma[k]); +dml_print("DML::%s: k=%d, sub_vp_lines_c = %d\n", __func__, k, sub_vp_lines_c); +#endif + } + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: DRAMClockChangeSupport = %d\n", __func__, *DRAMClockChangeSupport); + dml_print("DML::%s: FCLKChangeSupport = %d\n", __func__, *FCLKChangeSupport); + dml_print("DML::%s: MinActiveFCLKChangeLatencySupported = %f\n", + __func__, *MinActiveFCLKChangeLatencySupported); + dml_print("DML::%s: USRRetrainingSupport = %d\n", __func__, *USRRetrainingSupport); +#endif +} // CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport + +double dml32_CalculateWriteBackDISPCLK( + enum source_format_class WritebackPixelFormat, + double PixelClock, + double WritebackHRatio, + double WritebackVRatio, + unsigned int WritebackHTaps, + unsigned int WritebackVTaps, + unsigned int WritebackSourceWidth, + unsigned int WritebackDestinationWidth, + unsigned int HTotal, + unsigned int WritebackLineBufferSize, + double DISPCLKDPPCLKVCOSpeed) +{ + double DISPCLK_H, DISPCLK_V, DISPCLK_HB; + + DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / WritebackHRatio; + DISPCLK_V = PixelClock * (WritebackVTaps * dml_ceil(WritebackDestinationWidth / 6.0, 1) + 8.0) / HTotal; + DISPCLK_HB = PixelClock * WritebackVTaps * (WritebackDestinationWidth * + WritebackVTaps - WritebackLineBufferSize / 57.0) / 6.0 / WritebackSourceWidth; + return dml32_RoundToDFSGranularity(dml_max3(DISPCLK_H, DISPCLK_V, DISPCLK_HB), 1, DISPCLKDPPCLKVCOSpeed); +} + +void dml32_CalculateMinAndMaxPrefetchMode( + enum dm_prefetch_modes AllowForPStateChangeOrStutterInVBlankFinal, + unsigned int *MinPrefetchMode, + unsigned int *MaxPrefetchMode) +{ + if (AllowForPStateChangeOrStutterInVBlankFinal == dm_prefetch_support_none) { + *MinPrefetchMode = 3; + *MaxPrefetchMode = 3; + } else if (AllowForPStateChangeOrStutterInVBlankFinal == dm_prefetch_support_stutter) { + *MinPrefetchMode = 2; + *MaxPrefetchMode = 2; + } else if (AllowForPStateChangeOrStutterInVBlankFinal == dm_prefetch_support_fclk_and_stutter) { + *MinPrefetchMode = 1; + *MaxPrefetchMode = 1; + } else if (AllowForPStateChangeOrStutterInVBlankFinal == dm_prefetch_support_uclk_fclk_and_stutter) { + *MinPrefetchMode = 0; + *MaxPrefetchMode = 0; + } else if (AllowForPStateChangeOrStutterInVBlankFinal == + dm_prefetch_support_uclk_fclk_and_stutter_if_possible) { + *MinPrefetchMode = 0; + *MaxPrefetchMode = 3; + } else { + *MinPrefetchMode = 0; + *MaxPrefetchMode = 3; + } +} // CalculateMinAndMaxPrefetchMode + +void dml32_CalculatePixelDeliveryTimes( + unsigned int NumberOfActiveSurfaces, + double VRatio[], + double VRatioChroma[], + double VRatioPrefetchY[], + double VRatioPrefetchC[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[], + unsigned int DPPPerSurface[], + double HRatio[], + double HRatioChroma[], + double PixelClock[], + double PSCL_THROUGHPUT[], + double PSCL_THROUGHPUT_CHROMA[], + double Dppclk[], + unsigned int BytePerPixelC[], + enum dm_rotation_angle SourceRotation[], + unsigned int NumberOfCursors[], + unsigned int CursorWidth[][DC__NUM_CURSOR__MAX], + unsigned int CursorBPP[][DC__NUM_CURSOR__MAX], + unsigned int BlockWidth256BytesY[], + unsigned int BlockHeight256BytesY[], + unsigned int BlockWidth256BytesC[], + unsigned int BlockHeight256BytesC[], + + /* Output */ + double DisplayPipeLineDeliveryTimeLuma[], + double DisplayPipeLineDeliveryTimeChroma[], + double DisplayPipeLineDeliveryTimeLumaPrefetch[], + double DisplayPipeLineDeliveryTimeChromaPrefetch[], + double DisplayPipeRequestDeliveryTimeLuma[], + double DisplayPipeRequestDeliveryTimeChroma[], + double DisplayPipeRequestDeliveryTimeLumaPrefetch[], + double DisplayPipeRequestDeliveryTimeChromaPrefetch[], + double CursorRequestDeliveryTime[], + double CursorRequestDeliveryTimePrefetch[]) +{ + double req_per_swath_ub; + unsigned int k; + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d : HRatio = %f\n", __func__, k, HRatio[k]); + dml_print("DML::%s: k=%d : VRatio = %f\n", __func__, k, VRatio[k]); + dml_print("DML::%s: k=%d : HRatioChroma = %f\n", __func__, k, HRatioChroma[k]); + dml_print("DML::%s: k=%d : VRatioChroma = %f\n", __func__, k, VRatioChroma[k]); + dml_print("DML::%s: k=%d : swath_width_luma_ub = %d\n", __func__, k, swath_width_luma_ub[k]); + dml_print("DML::%s: k=%d : swath_width_chroma_ub = %d\n", __func__, k, swath_width_chroma_ub[k]); + dml_print("DML::%s: k=%d : PSCL_THROUGHPUT = %f\n", __func__, k, PSCL_THROUGHPUT[k]); + dml_print("DML::%s: k=%d : PSCL_THROUGHPUT_CHROMA = %f\n", __func__, k, PSCL_THROUGHPUT_CHROMA[k]); + dml_print("DML::%s: k=%d : DPPPerSurface = %d\n", __func__, k, DPPPerSurface[k]); + dml_print("DML::%s: k=%d : PixelClock = %f\n", __func__, k, PixelClock[k]); + dml_print("DML::%s: k=%d : Dppclk = %f\n", __func__, k, Dppclk[k]); +#endif + + if (VRatio[k] <= 1) { + DisplayPipeLineDeliveryTimeLuma[k] = + swath_width_luma_ub[k] * DPPPerSurface[k] / HRatio[k] / PixelClock[k]; + } else { + DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k]; + } + + if (BytePerPixelC[k] == 0) { + DisplayPipeLineDeliveryTimeChroma[k] = 0; + } else { + if (VRatioChroma[k] <= 1) { + DisplayPipeLineDeliveryTimeChroma[k] = + swath_width_chroma_ub[k] * DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k]; + } else { + DisplayPipeLineDeliveryTimeChroma[k] = + swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k]; + } + } + + if (VRatioPrefetchY[k] <= 1) { + DisplayPipeLineDeliveryTimeLumaPrefetch[k] = + swath_width_luma_ub[k] * DPPPerSurface[k] / HRatio[k] / PixelClock[k]; + } else { + DisplayPipeLineDeliveryTimeLumaPrefetch[k] = + swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k]; + } + + if (BytePerPixelC[k] == 0) { + DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0; + } else { + if (VRatioPrefetchC[k] <= 1) { + DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] * + DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k]; + } else { + DisplayPipeLineDeliveryTimeChromaPrefetch[k] = + swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k]; + } + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLuma = %f\n", + __func__, k, DisplayPipeLineDeliveryTimeLuma[k]); + dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLumaPrefetch = %f\n", + __func__, k, DisplayPipeLineDeliveryTimeLumaPrefetch[k]); + dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChroma = %f\n", + __func__, k, DisplayPipeLineDeliveryTimeChroma[k]); + dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChromaPrefetch = %f\n", + __func__, k, DisplayPipeLineDeliveryTimeChromaPrefetch[k]); +#endif + } + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (!IsVertical(SourceRotation[k])) + req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k]; + else + req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k]; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d : req_per_swath_ub = %f (Luma)\n", __func__, k, req_per_swath_ub); +#endif + + DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub; + DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = + DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub; + if (BytePerPixelC[k] == 0) { + DisplayPipeRequestDeliveryTimeChroma[k] = 0; + DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0; + } else { + if (!IsVertical(SourceRotation[k])) + req_per_swath_ub = swath_width_chroma_ub[k] / BlockWidth256BytesC[k]; + else + req_per_swath_ub = swath_width_chroma_ub[k] / BlockHeight256BytesC[k]; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d : req_per_swath_ub = %f (Chroma)\n", __func__, k, req_per_swath_ub); +#endif + DisplayPipeRequestDeliveryTimeChroma[k] = + DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub; + DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = + DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLuma = %f\n", + __func__, k, DisplayPipeRequestDeliveryTimeLuma[k]); + dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLumaPrefetch = %f\n", + __func__, k, DisplayPipeRequestDeliveryTimeLumaPrefetch[k]); + dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChroma = %f\n", + __func__, k, DisplayPipeRequestDeliveryTimeChroma[k]); + dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChromaPrefetch = %f\n", + __func__, k, DisplayPipeRequestDeliveryTimeChromaPrefetch[k]); +#endif + } + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + unsigned int cursor_req_per_width; + + cursor_req_per_width = dml_ceil((double) CursorWidth[k][0] * (double) CursorBPP[k][0] / + 256.0 / 8.0, 1.0); + if (NumberOfCursors[k] > 0) { + if (VRatio[k] <= 1) { + CursorRequestDeliveryTime[k] = (double) CursorWidth[k][0] / + HRatio[k] / PixelClock[k] / cursor_req_per_width; + } else { + CursorRequestDeliveryTime[k] = (double) CursorWidth[k][0] / + PSCL_THROUGHPUT[k] / Dppclk[k] / cursor_req_per_width; + } + if (VRatioPrefetchY[k] <= 1) { + CursorRequestDeliveryTimePrefetch[k] = (double) CursorWidth[k][0] / + HRatio[k] / PixelClock[k] / cursor_req_per_width; + } else { + CursorRequestDeliveryTimePrefetch[k] = (double) CursorWidth[k][0] / + PSCL_THROUGHPUT[k] / Dppclk[k] / cursor_req_per_width; + } + } else { + CursorRequestDeliveryTime[k] = 0; + CursorRequestDeliveryTimePrefetch[k] = 0; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d : NumberOfCursors = %d\n", + __func__, k, NumberOfCursors[k]); + dml_print("DML::%s: k=%d : CursorRequestDeliveryTime = %f\n", + __func__, k, CursorRequestDeliveryTime[k]); + dml_print("DML::%s: k=%d : CursorRequestDeliveryTimePrefetch = %f\n", + __func__, k, CursorRequestDeliveryTimePrefetch[k]); +#endif + } +} // CalculatePixelDeliveryTimes + +void dml32_CalculateMetaAndPTETimes( + bool use_one_row_for_frame[], + unsigned int NumberOfActiveSurfaces, + bool GPUVMEnable, + unsigned int MetaChunkSize, + unsigned int MinMetaChunkSizeBytes, + unsigned int HTotal[], + double VRatio[], + double VRatioChroma[], + double DestinationLinesToRequestRowInVBlank[], + double DestinationLinesToRequestRowInImmediateFlip[], + bool DCCEnable[], + double PixelClock[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], + enum dm_rotation_angle SourceRotation[], + unsigned int dpte_row_height[], + unsigned int dpte_row_height_chroma[], + unsigned int meta_row_width[], + unsigned int meta_row_width_chroma[], + unsigned int meta_row_height[], + unsigned int meta_row_height_chroma[], + unsigned int meta_req_width[], + unsigned int meta_req_width_chroma[], + unsigned int meta_req_height[], + unsigned int meta_req_height_chroma[], + unsigned int dpte_group_bytes[], + unsigned int PTERequestSizeY[], + unsigned int PTERequestSizeC[], + unsigned int PixelPTEReqWidthY[], + unsigned int PixelPTEReqHeightY[], + unsigned int PixelPTEReqWidthC[], + unsigned int PixelPTEReqHeightC[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], + + /* Output */ + double DST_Y_PER_PTE_ROW_NOM_L[], + double DST_Y_PER_PTE_ROW_NOM_C[], + double DST_Y_PER_META_ROW_NOM_L[], + double DST_Y_PER_META_ROW_NOM_C[], + double TimePerMetaChunkNominal[], + double TimePerChromaMetaChunkNominal[], + double TimePerMetaChunkVBlank[], + double TimePerChromaMetaChunkVBlank[], + double TimePerMetaChunkFlip[], + double TimePerChromaMetaChunkFlip[], + double time_per_pte_group_nom_luma[], + double time_per_pte_group_vblank_luma[], + double time_per_pte_group_flip_luma[], + double time_per_pte_group_nom_chroma[], + double time_per_pte_group_vblank_chroma[], + double time_per_pte_group_flip_chroma[]) +{ + unsigned int meta_chunk_width; + unsigned int min_meta_chunk_width; + unsigned int meta_chunk_per_row_int; + unsigned int meta_row_remainder; + unsigned int meta_chunk_threshold; + unsigned int meta_chunks_per_row_ub; + unsigned int meta_chunk_width_chroma; + unsigned int min_meta_chunk_width_chroma; + unsigned int meta_chunk_per_row_int_chroma; + unsigned int meta_row_remainder_chroma; + unsigned int meta_chunk_threshold_chroma; + unsigned int meta_chunks_per_row_ub_chroma; + unsigned int dpte_group_width_luma; + unsigned int dpte_groups_per_row_luma_ub; + unsigned int dpte_group_width_chroma; + unsigned int dpte_groups_per_row_chroma_ub; + unsigned int k; + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k]; + if (BytePerPixelC[k] == 0) + DST_Y_PER_PTE_ROW_NOM_C[k] = 0; + else + DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / VRatioChroma[k]; + DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k]; + if (BytePerPixelC[k] == 0) + DST_Y_PER_META_ROW_NOM_C[k] = 0; + else + DST_Y_PER_META_ROW_NOM_C[k] = meta_row_height_chroma[k] / VRatioChroma[k]; + } + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (DCCEnable[k] == true) { + meta_chunk_width = MetaChunkSize * 1024 * 256 / BytePerPixelY[k] / meta_row_height[k]; + min_meta_chunk_width = MinMetaChunkSizeBytes * 256 / BytePerPixelY[k] / meta_row_height[k]; + meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width; + meta_row_remainder = meta_row_width[k] % meta_chunk_width; + if (!IsVertical(SourceRotation[k])) + meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k]; + else + meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k]; + + if (meta_row_remainder <= meta_chunk_threshold) + meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; + else + meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; + + TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] * + HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub; + TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * + HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub; + TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * + HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub; + if (BytePerPixelC[k] == 0) { + TimePerChromaMetaChunkNominal[k] = 0; + TimePerChromaMetaChunkVBlank[k] = 0; + TimePerChromaMetaChunkFlip[k] = 0; + } else { + meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] / + meta_row_height_chroma[k]; + min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / + meta_row_height_chroma[k]; + meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] / + meta_chunk_width_chroma; + meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma; + if (!IsVertical(SourceRotation[k])) { + meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - + meta_req_width_chroma[k]; + } else { + meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - + meta_req_height_chroma[k]; + } + if (meta_row_remainder_chroma <= meta_chunk_threshold_chroma) + meta_chunks_per_row_ub_chroma = meta_chunk_per_row_int_chroma + 1; + else + meta_chunks_per_row_ub_chroma = meta_chunk_per_row_int_chroma + 2; + + TimePerChromaMetaChunkNominal[k] = meta_row_height_chroma[k] / VRatioChroma[k] * + HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma; + TimePerChromaMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * + HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma; + TimePerChromaMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * + HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma; + } + } else { + TimePerMetaChunkNominal[k] = 0; + TimePerMetaChunkVBlank[k] = 0; + TimePerMetaChunkFlip[k] = 0; + TimePerChromaMetaChunkNominal[k] = 0; + TimePerChromaMetaChunkVBlank[k] = 0; + TimePerChromaMetaChunkFlip[k] = 0; + } + } + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (GPUVMEnable == true) { + if (!IsVertical(SourceRotation[k])) { + dpte_group_width_luma = (double) dpte_group_bytes[k] / + (double) PTERequestSizeY[k] * PixelPTEReqWidthY[k]; + } else { + dpte_group_width_luma = (double) dpte_group_bytes[k] / + (double) PTERequestSizeY[k] * PixelPTEReqHeightY[k]; + } + + if (use_one_row_for_frame[k]) { + dpte_groups_per_row_luma_ub = dml_ceil((double) dpte_row_width_luma_ub[k] / + (double) dpte_group_width_luma / 2.0, 1.0); + } else { + dpte_groups_per_row_luma_ub = dml_ceil((double) dpte_row_width_luma_ub[k] / + (double) dpte_group_width_luma, 1.0); + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d, use_one_row_for_frame = %d\n", + __func__, k, use_one_row_for_frame[k]); + dml_print("DML::%s: k=%0d, dpte_group_bytes = %d\n", + __func__, k, dpte_group_bytes[k]); + dml_print("DML::%s: k=%0d, PTERequestSizeY = %d\n", + __func__, k, PTERequestSizeY[k]); + dml_print("DML::%s: k=%0d, PixelPTEReqWidthY = %d\n", + __func__, k, PixelPTEReqWidthY[k]); + dml_print("DML::%s: k=%0d, PixelPTEReqHeightY = %d\n", + __func__, k, PixelPTEReqHeightY[k]); + dml_print("DML::%s: k=%0d, dpte_row_width_luma_ub = %d\n", + __func__, k, dpte_row_width_luma_ub[k]); + dml_print("DML::%s: k=%0d, dpte_group_width_luma = %d\n", + __func__, k, dpte_group_width_luma); + dml_print("DML::%s: k=%0d, dpte_groups_per_row_luma_ub = %d\n", + __func__, k, dpte_groups_per_row_luma_ub); +#endif + + time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * + HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; + time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] * + HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; + time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * + HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; + if (BytePerPixelC[k] == 0) { + time_per_pte_group_nom_chroma[k] = 0; + time_per_pte_group_vblank_chroma[k] = 0; + time_per_pte_group_flip_chroma[k] = 0; + } else { + if (!IsVertical(SourceRotation[k])) { + dpte_group_width_chroma = (double) dpte_group_bytes[k] / + (double) PTERequestSizeC[k] * PixelPTEReqWidthC[k]; + } else { + dpte_group_width_chroma = (double) dpte_group_bytes[k] / + (double) PTERequestSizeC[k] * PixelPTEReqHeightC[k]; + } + + if (use_one_row_for_frame[k]) { + dpte_groups_per_row_chroma_ub = dml_ceil((double) dpte_row_width_chroma_ub[k] / + (double) dpte_group_width_chroma / 2.0, 1.0); + } else { + dpte_groups_per_row_chroma_ub = dml_ceil((double) dpte_row_width_chroma_ub[k] / + (double) dpte_group_width_chroma, 1.0); + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d, dpte_row_width_chroma_ub = %d\n", + __func__, k, dpte_row_width_chroma_ub[k]); + dml_print("DML::%s: k=%0d, dpte_group_width_chroma = %d\n", + __func__, k, dpte_group_width_chroma); + dml_print("DML::%s: k=%0d, dpte_groups_per_row_chroma_ub = %d\n", + __func__, k, dpte_groups_per_row_chroma_ub); +#endif + time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] * + HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; + time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] * + HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; + time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * + HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; + } + } else { + time_per_pte_group_nom_luma[k] = 0; + time_per_pte_group_vblank_luma[k] = 0; + time_per_pte_group_flip_luma[k] = 0; + time_per_pte_group_nom_chroma[k] = 0; + time_per_pte_group_vblank_chroma[k] = 0; + time_per_pte_group_flip_chroma[k] = 0; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d, DestinationLinesToRequestRowInVBlank = %f\n", + __func__, k, DestinationLinesToRequestRowInVBlank[k]); + dml_print("DML::%s: k=%0d, DestinationLinesToRequestRowInImmediateFlip = %f\n", + __func__, k, DestinationLinesToRequestRowInImmediateFlip[k]); + dml_print("DML::%s: k=%0d, DST_Y_PER_PTE_ROW_NOM_L = %f\n", + __func__, k, DST_Y_PER_PTE_ROW_NOM_L[k]); + dml_print("DML::%s: k=%0d, DST_Y_PER_PTE_ROW_NOM_C = %f\n", + __func__, k, DST_Y_PER_PTE_ROW_NOM_C[k]); + dml_print("DML::%s: k=%0d, DST_Y_PER_META_ROW_NOM_L = %f\n", + __func__, k, DST_Y_PER_META_ROW_NOM_L[k]); + dml_print("DML::%s: k=%0d, DST_Y_PER_META_ROW_NOM_C = %f\n", + __func__, k, DST_Y_PER_META_ROW_NOM_C[k]); + dml_print("DML::%s: k=%0d, TimePerMetaChunkNominal = %f\n", + __func__, k, TimePerMetaChunkNominal[k]); + dml_print("DML::%s: k=%0d, TimePerMetaChunkVBlank = %f\n", + __func__, k, TimePerMetaChunkVBlank[k]); + dml_print("DML::%s: k=%0d, TimePerMetaChunkFlip = %f\n", + __func__, k, TimePerMetaChunkFlip[k]); + dml_print("DML::%s: k=%0d, TimePerChromaMetaChunkNominal = %f\n", + __func__, k, TimePerChromaMetaChunkNominal[k]); + dml_print("DML::%s: k=%0d, TimePerChromaMetaChunkVBlank = %f\n", + __func__, k, TimePerChromaMetaChunkVBlank[k]); + dml_print("DML::%s: k=%0d, TimePerChromaMetaChunkFlip = %f\n", + __func__, k, TimePerChromaMetaChunkFlip[k]); + dml_print("DML::%s: k=%0d, time_per_pte_group_nom_luma = %f\n", + __func__, k, time_per_pte_group_nom_luma[k]); + dml_print("DML::%s: k=%0d, time_per_pte_group_vblank_luma = %f\n", + __func__, k, time_per_pte_group_vblank_luma[k]); + dml_print("DML::%s: k=%0d, time_per_pte_group_flip_luma = %f\n", + __func__, k, time_per_pte_group_flip_luma[k]); + dml_print("DML::%s: k=%0d, time_per_pte_group_nom_chroma = %f\n", + __func__, k, time_per_pte_group_nom_chroma[k]); + dml_print("DML::%s: k=%0d, time_per_pte_group_vblank_chroma = %f\n", + __func__, k, time_per_pte_group_vblank_chroma[k]); + dml_print("DML::%s: k=%0d, time_per_pte_group_flip_chroma = %f\n", + __func__, k, time_per_pte_group_flip_chroma[k]); +#endif + } +} // CalculateMetaAndPTETimes + +void dml32_CalculateVMGroupAndRequestTimes( + unsigned int NumberOfActiveSurfaces, + bool GPUVMEnable, + unsigned int GPUVMMaxPageTableLevels, + unsigned int HTotal[], + unsigned int BytePerPixelC[], + double DestinationLinesToRequestVMInVBlank[], + double DestinationLinesToRequestVMInImmediateFlip[], + bool DCCEnable[], + double PixelClock[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], + unsigned int vm_group_bytes[], + unsigned int dpde0_bytes_per_frame_ub_l[], + unsigned int dpde0_bytes_per_frame_ub_c[], + unsigned int meta_pte_bytes_per_frame_ub_l[], + unsigned int meta_pte_bytes_per_frame_ub_c[], + + /* Output */ + double TimePerVMGroupVBlank[], + double TimePerVMGroupFlip[], + double TimePerVMRequestVBlank[], + double TimePerVMRequestFlip[]) +{ + unsigned int k; + unsigned int num_group_per_lower_vm_stage; + unsigned int num_req_per_lower_vm_stage; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: NumberOfActiveSurfaces = %d\n", __func__, NumberOfActiveSurfaces); + dml_print("DML::%s: GPUVMEnable = %d\n", __func__, GPUVMEnable); +#endif + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d, DCCEnable = %d\n", __func__, k, DCCEnable[k]); + dml_print("DML::%s: k=%0d, vm_group_bytes = %d\n", __func__, k, vm_group_bytes[k]); + dml_print("DML::%s: k=%0d, dpde0_bytes_per_frame_ub_l = %d\n", + __func__, k, dpde0_bytes_per_frame_ub_l[k]); + dml_print("DML::%s: k=%0d, dpde0_bytes_per_frame_ub_c = %d\n", + __func__, k, dpde0_bytes_per_frame_ub_c[k]); + dml_print("DML::%s: k=%0d, meta_pte_bytes_per_frame_ub_l = %d\n", + __func__, k, meta_pte_bytes_per_frame_ub_l[k]); + dml_print("DML::%s: k=%0d, meta_pte_bytes_per_frame_ub_c = %d\n", + __func__, k, meta_pte_bytes_per_frame_ub_c[k]); +#endif + + if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) { + if (DCCEnable[k] == false) { + if (BytePerPixelC[k] > 0) { + num_group_per_lower_vm_stage = dml_ceil( + (double) (dpde0_bytes_per_frame_ub_l[k]) / + (double) (vm_group_bytes[k]), 1.0) + + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / + (double) (vm_group_bytes[k]), 1.0); + } else { + num_group_per_lower_vm_stage = dml_ceil( + (double) (dpde0_bytes_per_frame_ub_l[k]) / + (double) (vm_group_bytes[k]), 1.0); + } + } else { + if (GPUVMMaxPageTableLevels == 1) { + if (BytePerPixelC[k] > 0) { + num_group_per_lower_vm_stage = dml_ceil( + (double) (meta_pte_bytes_per_frame_ub_l[k]) / + (double) (vm_group_bytes[k]), 1.0) + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / + (double) (vm_group_bytes[k]), 1.0); + } else { + num_group_per_lower_vm_stage = dml_ceil( + (double) (meta_pte_bytes_per_frame_ub_l[k]) / + (double) (vm_group_bytes[k]), 1.0); + } + } else { + if (BytePerPixelC[k] > 0) { + num_group_per_lower_vm_stage = 2 + dml_ceil( + (double) (dpde0_bytes_per_frame_ub_l[k]) / + (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / + (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / + (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / + (double) (vm_group_bytes[k]), 1); + } else { + num_group_per_lower_vm_stage = 1 + dml_ceil( + (double) (dpde0_bytes_per_frame_ub_l[k]) / + (double) (vm_group_bytes[k]), 1) + dml_ceil( + (double) (meta_pte_bytes_per_frame_ub_l[k]) / + (double) (vm_group_bytes[k]), 1); + } + } + } + + if (DCCEnable[k] == false) { + if (BytePerPixelC[k] > 0) { + num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + + dpde0_bytes_per_frame_ub_c[k] / 64; + } else { + num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64; + } + } else { + if (GPUVMMaxPageTableLevels == 1) { + if (BytePerPixelC[k] > 0) { + num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64 + + meta_pte_bytes_per_frame_ub_c[k] / 64; + } else { + num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64; + } + } else { + if (BytePerPixelC[k] > 0) { + num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / + 64 + dpde0_bytes_per_frame_ub_c[k] / 64 + + meta_pte_bytes_per_frame_ub_l[k] / 64 + + meta_pte_bytes_per_frame_ub_c[k] / 64; + } else { + num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / + 64 + meta_pte_bytes_per_frame_ub_l[k] / 64; + } + } + } + + TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * + HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage; + TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * + HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage; + TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * + HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage; + TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * + HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage; + + if (GPUVMMaxPageTableLevels > 2) { + TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2; + TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2; + TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2; + TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2; + } + + } else { + TimePerVMGroupVBlank[k] = 0; + TimePerVMGroupFlip[k] = 0; + TimePerVMRequestVBlank[k] = 0; + TimePerVMRequestFlip[k] = 0; + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d, TimePerVMGroupVBlank = %f\n", __func__, k, TimePerVMGroupVBlank[k]); + dml_print("DML::%s: k=%0d, TimePerVMGroupFlip = %f\n", __func__, k, TimePerVMGroupFlip[k]); + dml_print("DML::%s: k=%0d, TimePerVMRequestVBlank = %f\n", __func__, k, TimePerVMRequestVBlank[k]); + dml_print("DML::%s: k=%0d, TimePerVMRequestFlip = %f\n", __func__, k, TimePerVMRequestFlip[k]); +#endif + } +} // CalculateVMGroupAndRequestTimes + +void dml32_CalculateDCCConfiguration( + bool DCCEnabled, + bool DCCProgrammingAssumesScanDirectionUnknown, + enum source_format_class SourcePixelFormat, + unsigned int SurfaceWidthLuma, + unsigned int SurfaceWidthChroma, + unsigned int SurfaceHeightLuma, + unsigned int SurfaceHeightChroma, + unsigned int nomDETInKByte, + unsigned int RequestHeight256ByteLuma, + unsigned int RequestHeight256ByteChroma, + enum dm_swizzle_mode TilingFormat, + unsigned int BytePerPixelY, + unsigned int BytePerPixelC, + double BytePerPixelDETY, + double BytePerPixelDETC, + enum dm_rotation_angle SourceRotation, + /* Output */ + unsigned int *MaxUncompressedBlockLuma, + unsigned int *MaxUncompressedBlockChroma, + unsigned int *MaxCompressedBlockLuma, + unsigned int *MaxCompressedBlockChroma, + unsigned int *IndependentBlockLuma, + unsigned int *IndependentBlockChroma) +{ + + enum RequestType RequestLuma; + enum RequestType RequestChroma; + + unsigned int segment_order_horz_contiguous_luma; + unsigned int segment_order_horz_contiguous_chroma; + unsigned int segment_order_vert_contiguous_luma; + unsigned int segment_order_vert_contiguous_chroma; + unsigned int req128_horz_wc_l; + unsigned int req128_horz_wc_c; + unsigned int req128_vert_wc_l; + unsigned int req128_vert_wc_c; + unsigned int MAS_vp_horz_limit; + unsigned int MAS_vp_vert_limit; + unsigned int max_vp_horz_width; + unsigned int max_vp_vert_height; + unsigned int eff_surf_width_l; + unsigned int eff_surf_width_c; + unsigned int eff_surf_height_l; + unsigned int eff_surf_height_c; + unsigned int full_swath_bytes_horz_wc_l; + unsigned int full_swath_bytes_horz_wc_c; + unsigned int full_swath_bytes_vert_wc_l; + unsigned int full_swath_bytes_vert_wc_c; + unsigned int DETBufferSizeForDCC = nomDETInKByte * 1024; + + unsigned int yuv420; + unsigned int horz_div_l; + unsigned int horz_div_c; + unsigned int vert_div_l; + unsigned int vert_div_c; + + unsigned int swath_buf_size; + double detile_buf_vp_horz_limit; + double detile_buf_vp_vert_limit; + + typedef enum { + REQ_256Bytes, + REQ_128BytesNonContiguous, + REQ_128BytesContiguous, + REQ_NA + } RequestType; + + yuv420 = ((SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || + SourcePixelFormat == dm_420_12) ? 1 : 0); + horz_div_l = 1; + horz_div_c = 1; + vert_div_l = 1; + vert_div_c = 1; + + if (BytePerPixelY == 1) + vert_div_l = 0; + if (BytePerPixelC == 1) + vert_div_c = 0; + + if (BytePerPixelC == 0) { + swath_buf_size = DETBufferSizeForDCC / 2 - 2 * 256; + detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma * + BytePerPixelY / (1 + horz_div_l)); + detile_buf_vp_vert_limit = (double) swath_buf_size / (256.0 / RequestHeight256ByteLuma / + (1 + vert_div_l)); + } else { + swath_buf_size = DETBufferSizeForDCC / 2 - 2 * 2 * 256; + detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma * + BytePerPixelY / (1 + horz_div_l) + (double) RequestHeight256ByteChroma * + BytePerPixelC / (1 + horz_div_c) / (1 + yuv420)); + detile_buf_vp_vert_limit = (double) swath_buf_size / (256.0 / RequestHeight256ByteLuma / + (1 + vert_div_l) + 256.0 / RequestHeight256ByteChroma / + (1 + vert_div_c) / (1 + yuv420)); + } + + if (SourcePixelFormat == dm_420_10) { + detile_buf_vp_horz_limit = 1.5 * detile_buf_vp_horz_limit; + detile_buf_vp_vert_limit = 1.5 * detile_buf_vp_vert_limit; + } + + detile_buf_vp_horz_limit = dml_floor(detile_buf_vp_horz_limit - 1, 16); + detile_buf_vp_vert_limit = dml_floor(detile_buf_vp_vert_limit - 1, 16); + + MAS_vp_horz_limit = SourcePixelFormat == dm_rgbe_alpha ? 3840 : 6144; + MAS_vp_vert_limit = SourcePixelFormat == dm_rgbe_alpha ? 3840 : (BytePerPixelY == 8 ? 3072 : 6144); + max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); + max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); + eff_surf_width_l = (SurfaceWidthLuma > max_vp_horz_width ? max_vp_horz_width : SurfaceWidthLuma); + eff_surf_width_c = eff_surf_width_l / (1 + yuv420); + eff_surf_height_l = (SurfaceHeightLuma > max_vp_vert_height ? max_vp_vert_height : SurfaceHeightLuma); + eff_surf_height_c = eff_surf_height_l / (1 + yuv420); + + full_swath_bytes_horz_wc_l = eff_surf_width_l * RequestHeight256ByteLuma * BytePerPixelY; + full_swath_bytes_vert_wc_l = eff_surf_height_l * 256 / RequestHeight256ByteLuma; + if (BytePerPixelC > 0) { + full_swath_bytes_horz_wc_c = eff_surf_width_c * RequestHeight256ByteChroma * BytePerPixelC; + full_swath_bytes_vert_wc_c = eff_surf_height_c * 256 / RequestHeight256ByteChroma; + } else { + full_swath_bytes_horz_wc_c = 0; + full_swath_bytes_vert_wc_c = 0; + } + + if (SourcePixelFormat == dm_420_10) { + full_swath_bytes_horz_wc_l = dml_ceil((double) full_swath_bytes_horz_wc_l * 2.0 / 3.0, 256.0); + full_swath_bytes_horz_wc_c = dml_ceil((double) full_swath_bytes_horz_wc_c * 2.0 / 3.0, 256.0); + full_swath_bytes_vert_wc_l = dml_ceil((double) full_swath_bytes_vert_wc_l * 2.0 / 3.0, 256.0); + full_swath_bytes_vert_wc_c = dml_ceil((double) full_swath_bytes_vert_wc_c * 2.0 / 3.0, 256.0); + } + + if (2 * full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c <= DETBufferSizeForDCC) { + req128_horz_wc_l = 0; + req128_horz_wc_c = 0; + } else if (full_swath_bytes_horz_wc_l < 1.5 * full_swath_bytes_horz_wc_c && 2 * full_swath_bytes_horz_wc_l + + full_swath_bytes_horz_wc_c <= DETBufferSizeForDCC) { + req128_horz_wc_l = 0; + req128_horz_wc_c = 1; + } else if (full_swath_bytes_horz_wc_l >= 1.5 * full_swath_bytes_horz_wc_c && full_swath_bytes_horz_wc_l + 2 * + full_swath_bytes_horz_wc_c <= DETBufferSizeForDCC) { + req128_horz_wc_l = 1; + req128_horz_wc_c = 0; + } else { + req128_horz_wc_l = 1; + req128_horz_wc_c = 1; + } + + if (2 * full_swath_bytes_vert_wc_l + 2 * full_swath_bytes_vert_wc_c <= DETBufferSizeForDCC) { + req128_vert_wc_l = 0; + req128_vert_wc_c = 0; + } else if (full_swath_bytes_vert_wc_l < 1.5 * full_swath_bytes_vert_wc_c && 2 * + full_swath_bytes_vert_wc_l + full_swath_bytes_vert_wc_c <= DETBufferSizeForDCC) { + req128_vert_wc_l = 0; + req128_vert_wc_c = 1; + } else if (full_swath_bytes_vert_wc_l >= 1.5 * full_swath_bytes_vert_wc_c && + full_swath_bytes_vert_wc_l + 2 * full_swath_bytes_vert_wc_c <= DETBufferSizeForDCC) { + req128_vert_wc_l = 1; + req128_vert_wc_c = 0; + } else { + req128_vert_wc_l = 1; + req128_vert_wc_c = 1; + } + + if (BytePerPixelY == 2) { + segment_order_horz_contiguous_luma = 0; + segment_order_vert_contiguous_luma = 1; + } else { + segment_order_horz_contiguous_luma = 1; + segment_order_vert_contiguous_luma = 0; + } + + if (BytePerPixelC == 2) { + segment_order_horz_contiguous_chroma = 0; + segment_order_vert_contiguous_chroma = 1; + } else { + segment_order_horz_contiguous_chroma = 1; + segment_order_vert_contiguous_chroma = 0; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: DCCEnabled = %d\n", __func__, DCCEnabled); + dml_print("DML::%s: nomDETInKByte = %d\n", __func__, nomDETInKByte); + dml_print("DML::%s: DETBufferSizeForDCC = %d\n", __func__, DETBufferSizeForDCC); + dml_print("DML::%s: req128_horz_wc_l = %d\n", __func__, req128_horz_wc_l); + dml_print("DML::%s: req128_horz_wc_c = %d\n", __func__, req128_horz_wc_c); + dml_print("DML::%s: full_swath_bytes_horz_wc_l = %d\n", __func__, full_swath_bytes_horz_wc_l); + dml_print("DML::%s: full_swath_bytes_vert_wc_c = %d\n", __func__, full_swath_bytes_vert_wc_c); + dml_print("DML::%s: segment_order_horz_contiguous_luma = %d\n", __func__, segment_order_horz_contiguous_luma); + dml_print("DML::%s: segment_order_horz_contiguous_chroma = %d\n", + __func__, segment_order_horz_contiguous_chroma); +#endif + + if (DCCProgrammingAssumesScanDirectionUnknown == true) { + if (req128_horz_wc_l == 0 && req128_vert_wc_l == 0) + RequestLuma = REQ_256Bytes; + else if ((req128_horz_wc_l == 1 && segment_order_horz_contiguous_luma == 0) || + (req128_vert_wc_l == 1 && segment_order_vert_contiguous_luma == 0)) + RequestLuma = REQ_128BytesNonContiguous; + else + RequestLuma = REQ_128BytesContiguous; + + if (req128_horz_wc_c == 0 && req128_vert_wc_c == 0) + RequestChroma = REQ_256Bytes; + else if ((req128_horz_wc_c == 1 && segment_order_horz_contiguous_chroma == 0) || + (req128_vert_wc_c == 1 && segment_order_vert_contiguous_chroma == 0)) + RequestChroma = REQ_128BytesNonContiguous; + else + RequestChroma = REQ_128BytesContiguous; + + } else if (!IsVertical(SourceRotation)) { + if (req128_horz_wc_l == 0) + RequestLuma = REQ_256Bytes; + else if (segment_order_horz_contiguous_luma == 0) + RequestLuma = REQ_128BytesNonContiguous; + else + RequestLuma = REQ_128BytesContiguous; + + if (req128_horz_wc_c == 0) + RequestChroma = REQ_256Bytes; + else if (segment_order_horz_contiguous_chroma == 0) + RequestChroma = REQ_128BytesNonContiguous; + else + RequestChroma = REQ_128BytesContiguous; + + } else { + if (req128_vert_wc_l == 0) + RequestLuma = REQ_256Bytes; + else if (segment_order_vert_contiguous_luma == 0) + RequestLuma = REQ_128BytesNonContiguous; + else + RequestLuma = REQ_128BytesContiguous; + + if (req128_vert_wc_c == 0) + RequestChroma = REQ_256Bytes; + else if (segment_order_vert_contiguous_chroma == 0) + RequestChroma = REQ_128BytesNonContiguous; + else + RequestChroma = REQ_128BytesContiguous; + } + + if (RequestLuma == (enum RequestType) REQ_256Bytes) { + *MaxUncompressedBlockLuma = 256; + *MaxCompressedBlockLuma = 256; + *IndependentBlockLuma = 0; + } else if (RequestLuma == (enum RequestType) REQ_128BytesContiguous) { + *MaxUncompressedBlockLuma = 256; + *MaxCompressedBlockLuma = 128; + *IndependentBlockLuma = 128; + } else { + *MaxUncompressedBlockLuma = 256; + *MaxCompressedBlockLuma = 64; + *IndependentBlockLuma = 64; + } + + if (RequestChroma == (enum RequestType) REQ_256Bytes) { + *MaxUncompressedBlockChroma = 256; + *MaxCompressedBlockChroma = 256; + *IndependentBlockChroma = 0; + } else if (RequestChroma == (enum RequestType) REQ_128BytesContiguous) { + *MaxUncompressedBlockChroma = 256; + *MaxCompressedBlockChroma = 128; + *IndependentBlockChroma = 128; + } else { + *MaxUncompressedBlockChroma = 256; + *MaxCompressedBlockChroma = 64; + *IndependentBlockChroma = 64; + } + + if (DCCEnabled != true || BytePerPixelC == 0) { + *MaxUncompressedBlockChroma = 0; + *MaxCompressedBlockChroma = 0; + *IndependentBlockChroma = 0; + } + + if (DCCEnabled != true) { + *MaxUncompressedBlockLuma = 0; + *MaxCompressedBlockLuma = 0; + *IndependentBlockLuma = 0; + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: MaxUncompressedBlockLuma = %d\n", __func__, *MaxUncompressedBlockLuma); + dml_print("DML::%s: MaxCompressedBlockLuma = %d\n", __func__, *MaxCompressedBlockLuma); + dml_print("DML::%s: IndependentBlockLuma = %d\n", __func__, *IndependentBlockLuma); + dml_print("DML::%s: MaxUncompressedBlockChroma = %d\n", __func__, *MaxUncompressedBlockChroma); + dml_print("DML::%s: MaxCompressedBlockChroma = %d\n", __func__, *MaxCompressedBlockChroma); + dml_print("DML::%s: IndependentBlockChroma = %d\n", __func__, *IndependentBlockChroma); +#endif + +} // CalculateDCCConfiguration + +void dml32_CalculateStutterEfficiency( + unsigned int CompressedBufferSizeInkByte, + enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[], + bool UnboundedRequestEnabled, + unsigned int MetaFIFOSizeInKEntries, + unsigned int ZeroSizeBufferEntries, + unsigned int PixelChunkSizeInKByte, + unsigned int NumberOfActiveSurfaces, + unsigned int ROBBufferSizeInKByte, + double TotalDataReadBandwidth, + double DCFCLK, + double ReturnBW, + unsigned int CompbufReservedSpace64B, + unsigned int CompbufReservedSpaceZs, + double SRExitTime, + double SRExitZ8Time, + bool SynchronizeTimingsFinal, + unsigned int BlendingAndTiming[], + double StutterEnterPlusExitWatermark, + double Z8StutterEnterPlusExitWatermark, + bool ProgressiveToInterlaceUnitInOPP, + bool Interlace[], + double MinTTUVBlank[], + unsigned int DPPPerSurface[], + unsigned int DETBufferSizeY[], + unsigned int BytePerPixelY[], + double BytePerPixelDETY[], + double SwathWidthY[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], + double NetDCCRateLuma[], + double NetDCCRateChroma[], + double DCCFractionOfZeroSizeRequestsLuma[], + double DCCFractionOfZeroSizeRequestsChroma[], + unsigned int HTotal[], + unsigned int VTotal[], + double PixelClock[], + double VRatio[], + enum dm_rotation_angle SourceRotation[], + unsigned int BlockHeight256BytesY[], + unsigned int BlockWidth256BytesY[], + unsigned int BlockHeight256BytesC[], + unsigned int BlockWidth256BytesC[], + unsigned int DCCYMaxUncompressedBlock[], + unsigned int DCCCMaxUncompressedBlock[], + unsigned int VActive[], + bool DCCEnable[], + bool WritebackEnable[], + double ReadBandwidthSurfaceLuma[], + double ReadBandwidthSurfaceChroma[], + double meta_row_bw[], + double dpte_row_bw[], + + /* Output */ + double *StutterEfficiencyNotIncludingVBlank, + double *StutterEfficiency, + unsigned int *NumberOfStutterBurstsPerFrame, + double *Z8StutterEfficiencyNotIncludingVBlank, + double *Z8StutterEfficiency, + unsigned int *Z8NumberOfStutterBurstsPerFrame, + double *StutterPeriod, + bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE) +{ + + bool FoundCriticalSurface = false; + unsigned int SwathSizeCriticalSurface = 0; + unsigned int LastChunkOfSwathSize; + unsigned int MissingPartOfLastSwathOfDETSize; + double LastZ8StutterPeriod = 0.0; + double LastStutterPeriod = 0.0; + unsigned int TotalNumberOfActiveOTG = 0; + double doublePixelClock; + unsigned int doubleHTotal; + unsigned int doubleVTotal; + bool SameTiming = true; + double DETBufferingTimeY; + double SwathWidthYCriticalSurface = 0.0; + double SwathHeightYCriticalSurface = 0.0; + double VActiveTimeCriticalSurface = 0.0; + double FrameTimeCriticalSurface = 0.0; + unsigned int BytePerPixelYCriticalSurface = 0; + double LinesToFinishSwathTransferStutterCriticalSurface = 0.0; + unsigned int DETBufferSizeYCriticalSurface = 0; + double MinTTUVBlankCriticalSurface = 0.0; + unsigned int BlockWidth256BytesYCriticalSurface = 0; + bool doublePlaneCriticalSurface = 0; + bool doublePipeCriticalSurface = 0; + double TotalCompressedReadBandwidth; + double TotalRowReadBandwidth; + double AverageDCCCompressionRate; + double EffectiveCompressedBufferSize; + double PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer; + double StutterBurstTime; + unsigned int TotalActiveWriteback; + double LinesInDETY; + double LinesInDETYRoundedDownToSwath; + double MaximumEffectiveCompressionLuma; + double MaximumEffectiveCompressionChroma; + double TotalZeroSizeRequestReadBandwidth; + double TotalZeroSizeCompressedReadBandwidth; + double AverageDCCZeroSizeFraction; + double AverageZeroSizeCompressionRate; + unsigned int k; + + TotalZeroSizeRequestReadBandwidth = 0; + TotalZeroSizeCompressedReadBandwidth = 0; + TotalRowReadBandwidth = 0; + TotalCompressedReadBandwidth = 0; + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) { + if (DCCEnable[k] == true) { + if ((IsVertical(SourceRotation[k]) && BlockWidth256BytesY[k] > SwathHeightY[k]) + || (!IsVertical(SourceRotation[k]) + && BlockHeight256BytesY[k] > SwathHeightY[k]) + || DCCYMaxUncompressedBlock[k] < 256) { + MaximumEffectiveCompressionLuma = 2; + } else { + MaximumEffectiveCompressionLuma = 4; + } + TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + + ReadBandwidthSurfaceLuma[k] + / dml_min(NetDCCRateLuma[k], + MaximumEffectiveCompressionLuma); +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d, ReadBandwidthSurfaceLuma = %f\n", + __func__, k, ReadBandwidthSurfaceLuma[k]); + dml_print("DML::%s: k=%0d, NetDCCRateLuma = %f\n", + __func__, k, NetDCCRateLuma[k]); + dml_print("DML::%s: k=%0d, MaximumEffectiveCompressionLuma = %f\n", + __func__, k, MaximumEffectiveCompressionLuma); +#endif + TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + + ReadBandwidthSurfaceLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k]; + TotalZeroSizeCompressedReadBandwidth = TotalZeroSizeCompressedReadBandwidth + + ReadBandwidthSurfaceLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k] + / MaximumEffectiveCompressionLuma; + + if (ReadBandwidthSurfaceChroma[k] > 0) { + if ((IsVertical(SourceRotation[k]) && BlockWidth256BytesC[k] > SwathHeightC[k]) + || (!IsVertical(SourceRotation[k]) + && BlockHeight256BytesC[k] > SwathHeightC[k]) + || DCCCMaxUncompressedBlock[k] < 256) { + MaximumEffectiveCompressionChroma = 2; + } else { + MaximumEffectiveCompressionChroma = 4; + } + TotalCompressedReadBandwidth = + TotalCompressedReadBandwidth + + ReadBandwidthSurfaceChroma[k] + / dml_min(NetDCCRateChroma[k], + MaximumEffectiveCompressionChroma); +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d, ReadBandwidthSurfaceChroma = %f\n", + __func__, k, ReadBandwidthSurfaceChroma[k]); + dml_print("DML::%s: k=%0d, NetDCCRateChroma = %f\n", + __func__, k, NetDCCRateChroma[k]); + dml_print("DML::%s: k=%0d, MaximumEffectiveCompressionChroma = %f\n", + __func__, k, MaximumEffectiveCompressionChroma); +#endif + TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + + ReadBandwidthSurfaceChroma[k] + * DCCFractionOfZeroSizeRequestsChroma[k]; + TotalZeroSizeCompressedReadBandwidth = TotalZeroSizeCompressedReadBandwidth + + ReadBandwidthSurfaceChroma[k] + * DCCFractionOfZeroSizeRequestsChroma[k] + / MaximumEffectiveCompressionChroma; + } + } else { + TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + + ReadBandwidthSurfaceLuma[k] + ReadBandwidthSurfaceChroma[k]; + } + TotalRowReadBandwidth = TotalRowReadBandwidth + + DPPPerSurface[k] * (meta_row_bw[k] + dpte_row_bw[k]); + } + } + + AverageDCCCompressionRate = TotalDataReadBandwidth / TotalCompressedReadBandwidth; + AverageDCCZeroSizeFraction = TotalZeroSizeRequestReadBandwidth / TotalDataReadBandwidth; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: UnboundedRequestEnabled = %d\n", __func__, UnboundedRequestEnabled); + dml_print("DML::%s: TotalCompressedReadBandwidth = %f\n", __func__, TotalCompressedReadBandwidth); + dml_print("DML::%s: TotalZeroSizeRequestReadBandwidth = %f\n", __func__, TotalZeroSizeRequestReadBandwidth); + dml_print("DML::%s: TotalZeroSizeCompressedReadBandwidth = %f\n", + __func__, TotalZeroSizeCompressedReadBandwidth); + dml_print("DML::%s: MaximumEffectiveCompressionLuma = %f\n", __func__, MaximumEffectiveCompressionLuma); + dml_print("DML::%s: MaximumEffectiveCompressionChroma = %f\n", __func__, MaximumEffectiveCompressionChroma); + dml_print("DML::%s: AverageDCCCompressionRate = %f\n", __func__, AverageDCCCompressionRate); + dml_print("DML::%s: AverageDCCZeroSizeFraction = %f\n", __func__, AverageDCCZeroSizeFraction); + dml_print("DML::%s: CompbufReservedSpace64B = %d\n", __func__, CompbufReservedSpace64B); + dml_print("DML::%s: CompbufReservedSpaceZs = %d\n", __func__, CompbufReservedSpaceZs); + dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, CompressedBufferSizeInkByte); +#endif + if (AverageDCCZeroSizeFraction == 1) { + AverageZeroSizeCompressionRate = TotalZeroSizeRequestReadBandwidth + / TotalZeroSizeCompressedReadBandwidth; + EffectiveCompressedBufferSize = (double) MetaFIFOSizeInKEntries * 1024 * 64 + * AverageZeroSizeCompressionRate + + ((double) ZeroSizeBufferEntries - CompbufReservedSpaceZs) * 64 + * AverageZeroSizeCompressionRate; + } else if (AverageDCCZeroSizeFraction > 0) { + AverageZeroSizeCompressionRate = TotalZeroSizeRequestReadBandwidth + / TotalZeroSizeCompressedReadBandwidth; + EffectiveCompressedBufferSize = dml_min( + (double) CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate, + (double) MetaFIFOSizeInKEntries * 1024 * 64 + / (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate + + 1 / AverageDCCCompressionRate)) + + dml_min(((double) ROBBufferSizeInKByte * 1024 - CompbufReservedSpace64B * 64) + * AverageDCCCompressionRate, + ((double) ZeroSizeBufferEntries - CompbufReservedSpaceZs) * 64 + / (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate)); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: min 1 = %f\n", __func__, + CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate); + dml_print("DML::%s: min 2 = %f\n", __func__, MetaFIFOSizeInKEntries * 1024 * 64 / + (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate + 1 / + AverageDCCCompressionRate)); + dml_print("DML::%s: min 3 = %f\n", __func__, (ROBBufferSizeInKByte * 1024 - + CompbufReservedSpace64B * 64) * AverageDCCCompressionRate); + dml_print("DML::%s: min 4 = %f\n", __func__, (ZeroSizeBufferEntries - CompbufReservedSpaceZs) * 64 / + (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate)); +#endif + } else { + EffectiveCompressedBufferSize = dml_min( + (double) CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate, + (double) MetaFIFOSizeInKEntries * 1024 * 64 * AverageDCCCompressionRate) + + ((double) ROBBufferSizeInKByte * 1024 - CompbufReservedSpace64B * 64) + * AverageDCCCompressionRate; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: min 1 = %f\n", __func__, + CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate); + dml_print("DML::%s: min 2 = %f\n", __func__, + MetaFIFOSizeInKEntries * 1024 * 64 * AverageDCCCompressionRate); +#endif + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: MetaFIFOSizeInKEntries = %d\n", __func__, MetaFIFOSizeInKEntries); + dml_print("DML::%s: AverageZeroSizeCompressionRate = %f\n", __func__, AverageZeroSizeCompressionRate); + dml_print("DML::%s: EffectiveCompressedBufferSize = %f\n", __func__, EffectiveCompressedBufferSize); +#endif + + *StutterPeriod = 0; + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) { + LinesInDETY = ((double) DETBufferSizeY[k] + + (UnboundedRequestEnabled == true ? EffectiveCompressedBufferSize : 0) + * ReadBandwidthSurfaceLuma[k] / TotalDataReadBandwidth) + / BytePerPixelDETY[k] / SwathWidthY[k]; + LinesInDETYRoundedDownToSwath = dml_floor(LinesInDETY, SwathHeightY[k]); + DETBufferingTimeY = LinesInDETYRoundedDownToSwath * ((double) HTotal[k] / PixelClock[k]) + / VRatio[k]; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d, DETBufferSizeY = %d\n", __func__, k, DETBufferSizeY[k]); + dml_print("DML::%s: k=%0d, BytePerPixelDETY = %f\n", __func__, k, BytePerPixelDETY[k]); + dml_print("DML::%s: k=%0d, SwathWidthY = %d\n", __func__, k, SwathWidthY[k]); + dml_print("DML::%s: k=%0d, ReadBandwidthSurfaceLuma = %f\n", + __func__, k, ReadBandwidthSurfaceLuma[k]); + dml_print("DML::%s: k=%0d, TotalDataReadBandwidth = %f\n", __func__, k, TotalDataReadBandwidth); + dml_print("DML::%s: k=%0d, LinesInDETY = %f\n", __func__, k, LinesInDETY); + dml_print("DML::%s: k=%0d, LinesInDETYRoundedDownToSwath = %f\n", + __func__, k, LinesInDETYRoundedDownToSwath); + dml_print("DML::%s: k=%0d, HTotal = %d\n", __func__, k, HTotal[k]); + dml_print("DML::%s: k=%0d, PixelClock = %f\n", __func__, k, PixelClock[k]); + dml_print("DML::%s: k=%0d, VRatio = %f\n", __func__, k, VRatio[k]); + dml_print("DML::%s: k=%0d, DETBufferingTimeY = %f\n", __func__, k, DETBufferingTimeY); + dml_print("DML::%s: k=%0d, PixelClock = %f\n", __func__, k, PixelClock[k]); +#endif + + if (!FoundCriticalSurface || DETBufferingTimeY < *StutterPeriod) { + bool isInterlaceTiming = Interlace[k] && !ProgressiveToInterlaceUnitInOPP; + + FoundCriticalSurface = true; + *StutterPeriod = DETBufferingTimeY; + FrameTimeCriticalSurface = ( + isInterlaceTiming ? + dml_floor((double) VTotal[k] / 2.0, 1.0) : VTotal[k]) + * (double) HTotal[k] / PixelClock[k]; + VActiveTimeCriticalSurface = ( + isInterlaceTiming ? + dml_floor((double) VActive[k] / 2.0, 1.0) : VActive[k]) + * (double) HTotal[k] / PixelClock[k]; + BytePerPixelYCriticalSurface = BytePerPixelY[k]; + SwathWidthYCriticalSurface = SwathWidthY[k]; + SwathHeightYCriticalSurface = SwathHeightY[k]; + BlockWidth256BytesYCriticalSurface = BlockWidth256BytesY[k]; + LinesToFinishSwathTransferStutterCriticalSurface = SwathHeightY[k] + - (LinesInDETY - LinesInDETYRoundedDownToSwath); + DETBufferSizeYCriticalSurface = DETBufferSizeY[k]; + MinTTUVBlankCriticalSurface = MinTTUVBlank[k]; + doublePlaneCriticalSurface = (ReadBandwidthSurfaceChroma[k] == 0); + doublePipeCriticalSurface = (DPPPerSurface[k] == 1); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d, FoundCriticalSurface = %d\n", + __func__, k, FoundCriticalSurface); + dml_print("DML::%s: k=%0d, StutterPeriod = %f\n", + __func__, k, *StutterPeriod); + dml_print("DML::%s: k=%0d, MinTTUVBlankCriticalSurface = %f\n", + __func__, k, MinTTUVBlankCriticalSurface); + dml_print("DML::%s: k=%0d, FrameTimeCriticalSurface = %f\n", + __func__, k, FrameTimeCriticalSurface); + dml_print("DML::%s: k=%0d, VActiveTimeCriticalSurface = %f\n", + __func__, k, VActiveTimeCriticalSurface); + dml_print("DML::%s: k=%0d, BytePerPixelYCriticalSurface = %d\n", + __func__, k, BytePerPixelYCriticalSurface); + dml_print("DML::%s: k=%0d, SwathWidthYCriticalSurface = %f\n", + __func__, k, SwathWidthYCriticalSurface); + dml_print("DML::%s: k=%0d, SwathHeightYCriticalSurface = %f\n", + __func__, k, SwathHeightYCriticalSurface); + dml_print("DML::%s: k=%0d, BlockWidth256BytesYCriticalSurface = %d\n", + __func__, k, BlockWidth256BytesYCriticalSurface); + dml_print("DML::%s: k=%0d, doublePlaneCriticalSurface = %d\n", + __func__, k, doublePlaneCriticalSurface); + dml_print("DML::%s: k=%0d, doublePipeCriticalSurface = %d\n", + __func__, k, doublePipeCriticalSurface); + dml_print("DML::%s: k=%0d, LinesToFinishSwathTransferStutterCriticalSurface = %f\n", + __func__, k, LinesToFinishSwathTransferStutterCriticalSurface); +#endif + } + } + } + + PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = dml_min(*StutterPeriod * TotalDataReadBandwidth, + EffectiveCompressedBufferSize); +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: ROBBufferSizeInKByte = %d\n", __func__, ROBBufferSizeInKByte); + dml_print("DML::%s: AverageDCCCompressionRate = %f\n", __func__, AverageDCCCompressionRate); + dml_print("DML::%s: StutterPeriod * TotalDataReadBandwidth = %f\n", + __func__, *StutterPeriod * TotalDataReadBandwidth); + dml_print("DML::%s: EffectiveCompressedBufferSize = %f\n", __func__, EffectiveCompressedBufferSize); + dml_print("DML::%s: PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = %f\n", __func__, + PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer); + dml_print("DML::%s: ReturnBW = %f\n", __func__, ReturnBW); + dml_print("DML::%s: TotalDataReadBandwidth = %f\n", __func__, TotalDataReadBandwidth); + dml_print("DML::%s: TotalRowReadBandwidth = %f\n", __func__, TotalRowReadBandwidth); + dml_print("DML::%s: DCFCLK = %f\n", __func__, DCFCLK); +#endif + + StutterBurstTime = PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer / AverageDCCCompressionRate + / ReturnBW + + (*StutterPeriod * TotalDataReadBandwidth + - PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (DCFCLK * 64) + + *StutterPeriod * TotalRowReadBandwidth / ReturnBW; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: Part 1 = %f\n", __func__, PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer / + AverageDCCCompressionRate / ReturnBW); + dml_print("DML::%s: StutterPeriod * TotalDataReadBandwidth = %f\n", + __func__, (*StutterPeriod * TotalDataReadBandwidth)); + dml_print("DML::%s: Part 2 = %f\n", __func__, (*StutterPeriod * TotalDataReadBandwidth - + PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (DCFCLK * 64)); + dml_print("DML::%s: Part 3 = %f\n", __func__, *StutterPeriod * TotalRowReadBandwidth / ReturnBW); + dml_print("DML::%s: StutterBurstTime = %f\n", __func__, StutterBurstTime); +#endif + StutterBurstTime = dml_max(StutterBurstTime, + LinesToFinishSwathTransferStutterCriticalSurface * BytePerPixelYCriticalSurface + * SwathWidthYCriticalSurface / ReturnBW); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: Time to finish residue swath=%f\n", + __func__, + LinesToFinishSwathTransferStutterCriticalSurface * + BytePerPixelYCriticalSurface * SwathWidthYCriticalSurface / ReturnBW); +#endif + + TotalActiveWriteback = 0; + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (WritebackEnable[k]) + TotalActiveWriteback = TotalActiveWriteback + 1; + } + + if (TotalActiveWriteback == 0) { +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: SRExitTime = %f\n", __func__, SRExitTime); + dml_print("DML::%s: SRExitZ8Time = %f\n", __func__, SRExitZ8Time); + dml_print("DML::%s: StutterBurstTime = %f (final)\n", __func__, StutterBurstTime); + dml_print("DML::%s: StutterPeriod = %f\n", __func__, *StutterPeriod); +#endif + *StutterEfficiencyNotIncludingVBlank = dml_max(0., + 1 - (SRExitTime + StutterBurstTime) / *StutterPeriod) * 100; + *Z8StutterEfficiencyNotIncludingVBlank = dml_max(0., + 1 - (SRExitZ8Time + StutterBurstTime) / *StutterPeriod) * 100; + *NumberOfStutterBurstsPerFrame = ( + *StutterEfficiencyNotIncludingVBlank > 0 ? + dml_ceil(VActiveTimeCriticalSurface / *StutterPeriod, 1) : 0); + *Z8NumberOfStutterBurstsPerFrame = ( + *Z8StutterEfficiencyNotIncludingVBlank > 0 ? + dml_ceil(VActiveTimeCriticalSurface / *StutterPeriod, 1) : 0); + } else { + *StutterEfficiencyNotIncludingVBlank = 0.; + *Z8StutterEfficiencyNotIncludingVBlank = 0.; + *NumberOfStutterBurstsPerFrame = 0; + *Z8NumberOfStutterBurstsPerFrame = 0; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: VActiveTimeCriticalSurface = %f\n", __func__, VActiveTimeCriticalSurface); + dml_print("DML::%s: StutterEfficiencyNotIncludingVBlank = %f\n", + __func__, *StutterEfficiencyNotIncludingVBlank); + dml_print("DML::%s: Z8StutterEfficiencyNotIncludingVBlank = %f\n", + __func__, *Z8StutterEfficiencyNotIncludingVBlank); + dml_print("DML::%s: NumberOfStutterBurstsPerFrame = %d\n", __func__, *NumberOfStutterBurstsPerFrame); + dml_print("DML::%s: Z8NumberOfStutterBurstsPerFrame = %d\n", __func__, *Z8NumberOfStutterBurstsPerFrame); +#endif + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) { + if (BlendingAndTiming[k] == k) { + if (TotalNumberOfActiveOTG == 0) { + doublePixelClock = PixelClock[k]; + doubleHTotal = HTotal[k]; + doubleVTotal = VTotal[k]; + } else if (doublePixelClock != PixelClock[k] || doubleHTotal != HTotal[k] + || doubleVTotal != VTotal[k]) { + SameTiming = false; + } + TotalNumberOfActiveOTG = TotalNumberOfActiveOTG + 1; + } + } + } + + if (*StutterEfficiencyNotIncludingVBlank > 0) { + LastStutterPeriod = VActiveTimeCriticalSurface - (*NumberOfStutterBurstsPerFrame - 1) * *StutterPeriod; + + if ((SynchronizeTimingsFinal || TotalNumberOfActiveOTG == 1) && SameTiming + && LastStutterPeriod + MinTTUVBlankCriticalSurface > StutterEnterPlusExitWatermark) { + *StutterEfficiency = (1 - (*NumberOfStutterBurstsPerFrame * SRExitTime + + StutterBurstTime * VActiveTimeCriticalSurface + / *StutterPeriod) / FrameTimeCriticalSurface) * 100; + } else { + *StutterEfficiency = *StutterEfficiencyNotIncludingVBlank; + } + } else { + *StutterEfficiency = 0; + } + + if (*Z8StutterEfficiencyNotIncludingVBlank > 0) { + LastZ8StutterPeriod = VActiveTimeCriticalSurface + - (*NumberOfStutterBurstsPerFrame - 1) * *StutterPeriod; + if ((SynchronizeTimingsFinal || TotalNumberOfActiveOTG == 1) && SameTiming && LastZ8StutterPeriod + + MinTTUVBlankCriticalSurface > Z8StutterEnterPlusExitWatermark) { + *Z8StutterEfficiency = (1 - (*NumberOfStutterBurstsPerFrame * SRExitZ8Time + StutterBurstTime + * VActiveTimeCriticalSurface / *StutterPeriod) / FrameTimeCriticalSurface) * 100; + } else { + *Z8StutterEfficiency = *Z8StutterEfficiencyNotIncludingVBlank; + } + } else { + *Z8StutterEfficiency = 0.; + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: LastZ8StutterPeriod = %f\n", __func__, LastZ8StutterPeriod); + dml_print("DML::%s: Z8StutterEnterPlusExitWatermark = %f\n", __func__, Z8StutterEnterPlusExitWatermark); + dml_print("DML::%s: StutterBurstTime = %f\n", __func__, StutterBurstTime); + dml_print("DML::%s: StutterPeriod = %f\n", __func__, *StutterPeriod); + dml_print("DML::%s: StutterEfficiency = %f\n", __func__, *StutterEfficiency); + dml_print("DML::%s: Z8StutterEfficiency = %f\n", __func__, *Z8StutterEfficiency); + dml_print("DML::%s: StutterEfficiencyNotIncludingVBlank = %f\n", + __func__, *StutterEfficiencyNotIncludingVBlank); + dml_print("DML::%s: Z8NumberOfStutterBurstsPerFrame = %d\n", __func__, *Z8NumberOfStutterBurstsPerFrame); +#endif + + SwathSizeCriticalSurface = BytePerPixelYCriticalSurface * SwathHeightYCriticalSurface + * dml_ceil(SwathWidthYCriticalSurface, BlockWidth256BytesYCriticalSurface); + LastChunkOfSwathSize = SwathSizeCriticalSurface % (PixelChunkSizeInKByte * 1024); + MissingPartOfLastSwathOfDETSize = dml_ceil(DETBufferSizeYCriticalSurface, SwathSizeCriticalSurface) + - DETBufferSizeYCriticalSurface; + + *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE = !(!UnboundedRequestEnabled && (NumberOfActiveSurfaces == 1) + && doublePlaneCriticalSurface && doublePipeCriticalSurface && (LastChunkOfSwathSize > 0) + && (LastChunkOfSwathSize <= 4096) && (MissingPartOfLastSwathOfDETSize > 0) + && (MissingPartOfLastSwathOfDETSize <= LastChunkOfSwathSize)); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: SwathSizeCriticalSurface = %d\n", __func__, SwathSizeCriticalSurface); + dml_print("DML::%s: LastChunkOfSwathSize = %d\n", __func__, LastChunkOfSwathSize); + dml_print("DML::%s: MissingPartOfLastSwathOfDETSize = %d\n", __func__, MissingPartOfLastSwathOfDETSize); + dml_print("DML::%s: DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE = %d\n", __func__, *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE); +#endif +} // CalculateStutterEfficiency + +void dml32_CalculateMaxDETAndMinCompressedBufferSize( + unsigned int ConfigReturnBufferSizeInKByte, + unsigned int ROBBufferSizeInKByte, + unsigned int MaxNumDPP, + bool nomDETInKByteOverrideEnable, // VBA_DELTA, allow DV to override default DET size + unsigned int nomDETInKByteOverrideValue, // VBA_DELTA + + /* Output */ + unsigned int *MaxTotalDETInKByte, + unsigned int *nomDETInKByte, + unsigned int *MinCompressedBufferSizeInKByte) +{ + bool det_buff_size_override_en = nomDETInKByteOverrideEnable; + unsigned int det_buff_size_override_val = nomDETInKByteOverrideValue; + + *MaxTotalDETInKByte = dml_ceil(((double)ConfigReturnBufferSizeInKByte + + (double) ROBBufferSizeInKByte) * 4.0 / 5.0, 64); + *nomDETInKByte = dml_floor((double) *MaxTotalDETInKByte / (double) MaxNumDPP, 64); + *MinCompressedBufferSizeInKByte = ConfigReturnBufferSizeInKByte - *MaxTotalDETInKByte; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: ConfigReturnBufferSizeInKByte = %0d\n", __func__, ConfigReturnBufferSizeInKByte); + dml_print("DML::%s: ROBBufferSizeInKByte = %0d\n", __func__, ROBBufferSizeInKByte); + dml_print("DML::%s: MaxNumDPP = %0d\n", __func__, MaxNumDPP); + dml_print("DML::%s: MaxTotalDETInKByte = %0d\n", __func__, *MaxTotalDETInKByte); + dml_print("DML::%s: nomDETInKByte = %0d\n", __func__, *nomDETInKByte); + dml_print("DML::%s: MinCompressedBufferSizeInKByte = %0d\n", __func__, *MinCompressedBufferSizeInKByte); +#endif + + if (det_buff_size_override_en) { + *nomDETInKByte = det_buff_size_override_val; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: nomDETInKByte = %0d (override)\n", __func__, *nomDETInKByte); +#endif + } +} // CalculateMaxDETAndMinCompressedBufferSize + +bool dml32_CalculateVActiveBandwithSupport(unsigned int NumberOfActiveSurfaces, + double ReturnBW, + bool NotUrgentLatencyHiding[], + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + double cursor_bw[], + double meta_row_bandwidth[], + double dpte_row_bandwidth[], + unsigned int NumberOfDPP[], + double UrgentBurstFactorLuma[], + double UrgentBurstFactorChroma[], + double UrgentBurstFactorCursor[]) +{ + unsigned int k; + bool NotEnoughUrgentLatencyHiding = false; + bool CalculateVActiveBandwithSupport_val = false; + double VActiveBandwith = 0; + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (NotUrgentLatencyHiding[k]) { + NotEnoughUrgentLatencyHiding = true; + } + } + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + VActiveBandwith = VActiveBandwith + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k] + NumberOfDPP[k] * meta_row_bandwidth[k] + NumberOfDPP[k] * dpte_row_bandwidth[k]; + } + + CalculateVActiveBandwithSupport_val = (VActiveBandwith <= ReturnBW) && !NotEnoughUrgentLatencyHiding; + +#ifdef __DML_VBA_DEBUG__ +dml_print("DML::%s: NotEnoughUrgentLatencyHiding = %d\n", __func__, NotEnoughUrgentLatencyHiding); +dml_print("DML::%s: VActiveBandwith = %f\n", __func__, VActiveBandwith); +dml_print("DML::%s: ReturnBW = %f\n", __func__, ReturnBW); +dml_print("DML::%s: CalculateVActiveBandwithSupport_val = %d\n", __func__, CalculateVActiveBandwithSupport_val); +#endif + return CalculateVActiveBandwithSupport_val; +} + +void dml32_CalculatePrefetchBandwithSupport(unsigned int NumberOfActiveSurfaces, + double ReturnBW, + bool NotUrgentLatencyHiding[], + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + double PrefetchBandwidthLuma[], + double PrefetchBandwidthChroma[], + double cursor_bw[], + double meta_row_bandwidth[], + double dpte_row_bandwidth[], + double cursor_bw_pre[], + double prefetch_vmrow_bw[], + unsigned int NumberOfDPP[], + double UrgentBurstFactorLuma[], + double UrgentBurstFactorChroma[], + double UrgentBurstFactorCursor[], + double UrgentBurstFactorLumaPre[], + double UrgentBurstFactorChromaPre[], + double UrgentBurstFactorCursorPre[], + + /* output */ + double *PrefetchBandwidth, + double *FractionOfUrgentBandwidth, + bool *PrefetchBandwidthSupport) +{ + unsigned int k; + bool NotEnoughUrgentLatencyHiding = false; + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (NotUrgentLatencyHiding[k]) { + NotEnoughUrgentLatencyHiding = true; + } + } + + *PrefetchBandwidth = 0; + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + *PrefetchBandwidth = *PrefetchBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k], + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k] + NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k]), + NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]); + } + + *PrefetchBandwidthSupport = (*PrefetchBandwidth <= ReturnBW) && !NotEnoughUrgentLatencyHiding; + *FractionOfUrgentBandwidth = *PrefetchBandwidth / ReturnBW; +} + +double dml32_CalculateBandwidthAvailableForImmediateFlip(unsigned int NumberOfActiveSurfaces, + double ReturnBW, + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + double PrefetchBandwidthLuma[], + double PrefetchBandwidthChroma[], + double cursor_bw[], + double cursor_bw_pre[], + unsigned int NumberOfDPP[], + double UrgentBurstFactorLuma[], + double UrgentBurstFactorChroma[], + double UrgentBurstFactorCursor[], + double UrgentBurstFactorLumaPre[], + double UrgentBurstFactorChromaPre[], + double UrgentBurstFactorCursorPre[]) +{ + unsigned int k; + double CalculateBandwidthAvailableForImmediateFlip_val = ReturnBW; + + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + CalculateBandwidthAvailableForImmediateFlip_val = CalculateBandwidthAvailableForImmediateFlip_val - dml_max(ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k], + NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]); + } + + return CalculateBandwidthAvailableForImmediateFlip_val; +} + +void dml32_CalculateImmediateFlipBandwithSupport(unsigned int NumberOfActiveSurfaces, + double ReturnBW, + enum immediate_flip_requirement ImmediateFlipRequirement[], + double final_flip_bw[], + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + double PrefetchBandwidthLuma[], + double PrefetchBandwidthChroma[], + double cursor_bw[], + double meta_row_bandwidth[], + double dpte_row_bandwidth[], + double cursor_bw_pre[], + double prefetch_vmrow_bw[], + unsigned int NumberOfDPP[], + double UrgentBurstFactorLuma[], + double UrgentBurstFactorChroma[], + double UrgentBurstFactorCursor[], + double UrgentBurstFactorLumaPre[], + double UrgentBurstFactorChromaPre[], + double UrgentBurstFactorCursorPre[], + + /* output */ + double *TotalBandwidth, + double *FractionOfUrgentBandwidth, + bool *ImmediateFlipBandwidthSupport) +{ + unsigned int k; + *TotalBandwidth = 0; + for (k = 0; k < NumberOfActiveSurfaces; ++k) { + if (ImmediateFlipRequirement[k] != dm_immediate_flip_not_required) { + *TotalBandwidth = *TotalBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k], + NumberOfDPP[k] * final_flip_bw[k] + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k], + NumberOfDPP[k] * (final_flip_bw[k] + PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]); + } else { + *TotalBandwidth = *TotalBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k], + NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k]) + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k], + NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]); + } + } + *ImmediateFlipBandwidthSupport = (*TotalBandwidth <= ReturnBW); + *FractionOfUrgentBandwidth = *TotalBandwidth / ReturnBW; +} diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h new file mode 100644 index 000000000000..72461b934ee0 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h @@ -0,0 +1,1175 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DML_DCN32_DISPLAY_MODE_VBA_UTIL_32_H__ +#define __DML_DCN32_DISPLAY_MODE_VBA_UTIL_32_H__ + +#include "../display_mode_enums.h" +#include "os_types.h" +#include "../dc_features.h" +#include "../display_mode_structs.h" + +unsigned int dml32_dscceComputeDelay( + unsigned int bpc, + double BPP, + unsigned int sliceWidth, + unsigned int numSlices, + enum output_format_class pixelFormat, + enum output_encoder_class Output); + +unsigned int dml32_dscComputeDelay(enum output_format_class pixelFormat, enum output_encoder_class Output); + +bool IsVertical(enum dm_rotation_angle Scan); + +void dml32_CalculateBytePerPixelAndBlockSizes( + enum source_format_class SourcePixelFormat, + enum dm_swizzle_mode SurfaceTiling, + + /*Output*/ + unsigned int *BytePerPixelY, + unsigned int *BytePerPixelC, + double *BytePerPixelDETY, + double *BytePerPixelDETC, + unsigned int *BlockHeight256BytesY, + unsigned int *BlockHeight256BytesC, + unsigned int *BlockWidth256BytesY, + unsigned int *BlockWidth256BytesC, + unsigned int *MacroTileHeightY, + unsigned int *MacroTileHeightC, + unsigned int *MacroTileWidthY, + unsigned int *MacroTileWidthC); + +void dml32_CalculateSinglePipeDPPCLKAndSCLThroughput( + double HRatio, + double HRatioChroma, + double VRatio, + double VRatioChroma, + double MaxDCHUBToPSCLThroughput, + double MaxPSCLToLBThroughput, + double PixelClock, + enum source_format_class SourcePixelFormat, + unsigned int HTaps, + unsigned int HTapsChroma, + unsigned int VTaps, + unsigned int VTapsChroma, + + /* output */ + double *PSCL_THROUGHPUT, + double *PSCL_THROUGHPUT_CHROMA, + double *DPPCLKUsingSingleDPP); + +void dml32_CalculateSwathAndDETConfiguration( + unsigned int DETSizeOverride[], + enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[], + unsigned int ConfigReturnBufferSizeInKByte, + unsigned int MaxTotalDETInKByte, + unsigned int MinCompressedBufferSizeInKByte, + double ForceSingleDPP, + unsigned int NumberOfActiveSurfaces, + unsigned int nomDETInKByte, + enum unbounded_requesting_policy UseUnboundedRequestingFinal, + unsigned int CompressedBufferSegmentSizeInkByteFinal, + enum output_encoder_class Output[], + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + double MaximumSwathWidthLuma[], + double MaximumSwathWidthChroma[], + enum dm_rotation_angle SourceRotation[], + bool ViewportStationary[], + enum source_format_class SourcePixelFormat[], + enum dm_swizzle_mode SurfaceTiling[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int ViewportXStart[], + unsigned int ViewportYStart[], + unsigned int ViewportXStartC[], + unsigned int ViewportYStartC[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], + enum odm_combine_mode ODMMode[], + unsigned int BlendingAndTiming[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], + double BytePerPixDETY[], + double BytePerPixDETC[], + unsigned int HActive[], + double HRatio[], + double HRatioChroma[], + unsigned int DPPPerSurface[], + + /* Output */ + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[], + double SwathWidth[], + double SwathWidthChroma[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], + unsigned int DETBufferSizeInKByte[], + unsigned int DETBufferSizeY[], + unsigned int DETBufferSizeC[], + bool *UnboundedRequestEnabled, + unsigned int *CompressedBufferSizeInkByte, + bool ViewportSizeSupportPerSurface[], + bool *ViewportSizeSupport); + +void dml32_CalculateSwathWidth( + bool ForceSingleDPP, + unsigned int NumberOfActiveSurfaces, + enum source_format_class SourcePixelFormat[], + enum dm_rotation_angle SourceScan[], + bool ViewportStationary[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int ViewportXStart[], + unsigned int ViewportYStart[], + unsigned int ViewportXStartC[], + unsigned int ViewportYStartC[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], + enum odm_combine_mode ODMMode[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], + unsigned int BlendingAndTiming[], + unsigned int HActive[], + double HRatio[], + unsigned int DPPPerSurface[], + + /* Output */ + double SwathWidthdoubleDPPY[], + double SwathWidthdoubleDPPC[], + double SwathWidthY[], // per-pipe + double SwathWidthC[], // per-pipe + unsigned int MaximumSwathHeightY[], + unsigned int MaximumSwathHeightC[], + unsigned int swath_width_luma_ub[], // per-pipe + unsigned int swath_width_chroma_ub[]); + +bool dml32_UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, + unsigned int TotalNumberOfActiveDPP, + bool NoChroma, + enum output_encoder_class Output); + +void dml32_CalculateDETBufferSize( + unsigned int DETSizeOverride[], + enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[], + bool ForceSingleDPP, + unsigned int NumberOfActiveSurfaces, + bool UnboundedRequestEnabled, + unsigned int nomDETInKByte, + unsigned int MaxTotalDETInKByte, + unsigned int ConfigReturnBufferSizeInKByte, + unsigned int MinCompressedBufferSizeInKByte, + unsigned int CompressedBufferSegmentSizeInkByteFinal, + enum source_format_class SourcePixelFormat[], + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + unsigned int RoundedUpMaxSwathSizeBytesY[], + unsigned int RoundedUpMaxSwathSizeBytesC[], + unsigned int DPPPerSurface[], + /* Output */ + unsigned int DETBufferSizeInKByte[], + unsigned int *CompressedBufferSizeInkByte); + +void dml32_CalculateODMMode( + unsigned int MaximumPixelsPerLinePerDSCUnit, + unsigned int HActive, + enum output_encoder_class Output, + enum odm_combine_policy ODMUse, + double StateDispclk, + double MaxDispclk, + bool DSCEnable, + unsigned int TotalNumberOfActiveDPP, + unsigned int MaxNumDPP, + double PixelClock, + double DISPCLKDPPCLKDSCCLKDownSpreading, + double DISPCLKRampingMargin, + double DISPCLKDPPCLKVCOSpeed, + + /* Output */ + bool *TotalAvailablePipesSupport, + unsigned int *NumberOfDPP, + enum odm_combine_mode *ODMMode, + double *RequiredDISPCLKPerSurface); + +double dml32_CalculateRequiredDispclk( + enum odm_combine_mode ODMMode, + double PixelClock, + double DISPCLKDPPCLKDSCCLKDownSpreading, + double DISPCLKRampingMargin, + double DISPCLKDPPCLKVCOSpeed, + double MaxDispclk); + +double dml32_RoundToDFSGranularity(double Clock, bool round_up, double VCOSpeed); + +void dml32_CalculateOutputLink( + double PHYCLKPerState, + double PHYCLKD18PerState, + double PHYCLKD32PerState, + double Downspreading, + bool IsMainSurfaceUsingTheIndicatedTiming, + enum output_encoder_class Output, + enum output_format_class OutputFormat, + unsigned int HTotal, + unsigned int HActive, + double PixelClockBackEnd, + double ForcedOutputLinkBPP, + unsigned int DSCInputBitPerComponent, + unsigned int NumberOfDSCSlices, + double AudioSampleRate, + unsigned int AudioSampleLayout, + enum odm_combine_mode ODMModeNoDSC, + enum odm_combine_mode ODMModeDSC, + bool DSCEnable, + unsigned int OutputLinkDPLanes, + enum dm_output_link_dp_rate OutputLinkDPRate, + + /* Output */ + bool *RequiresDSC, + double *RequiresFEC, + double *OutBpp, + enum dm_output_type *OutputType, + enum dm_output_rate *OutputRate, + unsigned int *RequiredSlots); + +void dml32_CalculateDPPCLK( + unsigned int NumberOfActiveSurfaces, + double DISPCLKDPPCLKDSCCLKDownSpreading, + double DISPCLKDPPCLKVCOSpeed, + double DPPCLKUsingSingleDPP[], + unsigned int DPPPerSurface[], + + /* output */ + double *GlobalDPPCLK, + double Dppclk[]); + +double dml32_TruncToValidBPP( + double LinkBitRate, + unsigned int Lanes, + unsigned int HTotal, + unsigned int HActive, + double PixelClock, + double DesiredBPP, + bool DSCEnable, + enum output_encoder_class Output, + enum output_format_class Format, + unsigned int DSCInputBitPerComponent, + unsigned int DSCSlices, + unsigned int AudioRate, + unsigned int AudioLayout, + enum odm_combine_mode ODMModeNoDSC, + enum odm_combine_mode ODMModeDSC, + /* Output */ + unsigned int *RequiredSlots); + +double dml32_RequiredDTBCLK( + bool DSCEnable, + double PixelClock, + enum output_format_class OutputFormat, + double OutputBpp, + unsigned int DSCSlices, + unsigned int HTotal, + unsigned int HActive, + unsigned int AudioRate, + unsigned int AudioLayout); + +unsigned int dml32_DSCDelayRequirement(bool DSCEnabled, + enum odm_combine_mode ODMMode, + unsigned int DSCInputBitPerComponent, + double OutputBpp, + unsigned int HActive, + unsigned int HTotal, + unsigned int NumberOfDSCSlices, + enum output_format_class OutputFormat, + enum output_encoder_class Output, + double PixelClock, + double PixelClockBackEnd); + +void dml32_CalculateSurfaceSizeInMall( + unsigned int NumberOfActiveSurfaces, + unsigned int MALLAllocatedForDCN, + enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[], + bool DCCEnable[], + bool ViewportStationary[], + unsigned int ViewportXStartY[], + unsigned int ViewportYStartY[], + unsigned int ViewportXStartC[], + unsigned int ViewportYStartC[], + unsigned int ViewportWidthY[], + unsigned int ViewportHeightY[], + unsigned int BytesPerPixelY[], + unsigned int ViewportWidthC[], + unsigned int ViewportHeightC[], + unsigned int BytesPerPixelC[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int ReadBlockWidthY[], + unsigned int ReadBlockWidthC[], + unsigned int ReadBlockHeightY[], + unsigned int ReadBlockHeightC[], + + /* Output */ + unsigned int SurfaceSizeInMALL[], + bool *ExceededMALLSize); + +void dml32_CalculateVMRowAndSwath( + unsigned int NumberOfActiveSurfaces, + DmlPipe myPipe[], + unsigned int SurfaceSizeInMALL[], + unsigned int PTEBufferSizeInRequestsLuma, + unsigned int PTEBufferSizeInRequestsChroma, + unsigned int DCCMetaBufferSizeBytes, + enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[], + enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[], + unsigned int MALLAllocatedForDCN, + double SwathWidthY[], + double SwathWidthC[], + bool GPUVMEnable, + bool HostVMEnable, + unsigned int HostVMMaxNonCachedPageTableLevels, + unsigned int GPUVMMaxPageTableLevels, + unsigned int GPUVMMinPageSizeKBytes[], + unsigned int HostVMMinPageSize, + + /* Output */ + bool PTEBufferSizeNotExceeded[], + bool DCCMetaBufferSizeNotExceeded[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], + unsigned int dpte_row_height_luma[], + unsigned int dpte_row_height_chroma[], + unsigned int dpte_row_height_linear_luma[], // VBA_DELTA + unsigned int dpte_row_height_linear_chroma[], // VBA_DELTA + unsigned int meta_req_width[], + unsigned int meta_req_width_chroma[], + unsigned int meta_req_height[], + unsigned int meta_req_height_chroma[], + unsigned int meta_row_width[], + unsigned int meta_row_width_chroma[], + unsigned int meta_row_height[], + unsigned int meta_row_height_chroma[], + unsigned int vm_group_bytes[], + unsigned int dpte_group_bytes[], + unsigned int PixelPTEReqWidthY[], + unsigned int PixelPTEReqHeightY[], + unsigned int PTERequestSizeY[], + unsigned int PixelPTEReqWidthC[], + unsigned int PixelPTEReqHeightC[], + unsigned int PTERequestSizeC[], + unsigned int dpde0_bytes_per_frame_ub_l[], + unsigned int meta_pte_bytes_per_frame_ub_l[], + unsigned int dpde0_bytes_per_frame_ub_c[], + unsigned int meta_pte_bytes_per_frame_ub_c[], + double PrefetchSourceLinesY[], + double PrefetchSourceLinesC[], + double VInitPreFillY[], + double VInitPreFillC[], + unsigned int MaxNumSwathY[], + unsigned int MaxNumSwathC[], + double meta_row_bw[], + double dpte_row_bw[], + double PixelPTEBytesPerRow[], + double PDEAndMetaPTEBytesFrame[], + double MetaRowByte[], + bool use_one_row_for_frame[], + bool use_one_row_for_frame_flip[], + bool UsesMALLForStaticScreen[], + bool PTE_BUFFER_MODE[], + unsigned int BIGK_FRAGMENT_SIZE[]); + +unsigned int dml32_CalculateVMAndRowBytes( + bool ViewportStationary, + bool DCCEnable, + unsigned int NumberOfDPPs, + unsigned int BlockHeight256Bytes, + unsigned int BlockWidth256Bytes, + enum source_format_class SourcePixelFormat, + unsigned int SurfaceTiling, + unsigned int BytePerPixel, + enum dm_rotation_angle SourceScan, + double SwathWidth, + unsigned int ViewportHeight, + unsigned int ViewportXStart, + unsigned int ViewportYStart, + bool GPUVMEnable, + bool HostVMEnable, + unsigned int HostVMMaxNonCachedPageTableLevels, + unsigned int GPUVMMaxPageTableLevels, + unsigned int GPUVMMinPageSizeKBytes, + unsigned int HostVMMinPageSize, + unsigned int PTEBufferSizeInRequests, + unsigned int Pitch, + unsigned int DCCMetaPitch, + unsigned int MacroTileWidth, + unsigned int MacroTileHeight, + + /* Output */ + unsigned int *MetaRowByte, + unsigned int *PixelPTEBytesPerRow, + unsigned int *dpte_row_width_ub, + unsigned int *dpte_row_height, + unsigned int *dpte_row_height_linear, + unsigned int *PixelPTEBytesPerRow_one_row_per_frame, + unsigned int *dpte_row_width_ub_one_row_per_frame, + unsigned int *dpte_row_height_one_row_per_frame, + unsigned int *MetaRequestWidth, + unsigned int *MetaRequestHeight, + unsigned int *meta_row_width, + unsigned int *meta_row_height, + unsigned int *PixelPTEReqWidth, + unsigned int *PixelPTEReqHeight, + unsigned int *PTERequestSize, + unsigned int *DPDE0BytesFrame, + unsigned int *MetaPTEBytesFrame); + +double dml32_CalculatePrefetchSourceLines( + double VRatio, + unsigned int VTaps, + bool Interlace, + bool ProgressiveToInterlaceUnitInOPP, + unsigned int SwathHeight, + enum dm_rotation_angle SourceRotation, + bool ViewportStationary, + double SwathWidth, + unsigned int ViewportHeight, + unsigned int ViewportXStart, + unsigned int ViewportYStart, + + /* Output */ + double *VInitPreFill, + unsigned int *MaxNumSwath); + +void dml32_CalculateMALLUseForStaticScreen( + unsigned int NumberOfActiveSurfaces, + unsigned int MALLAllocatedForDCNFinal, + enum dm_use_mall_for_static_screen_mode *UseMALLForStaticScreen, + unsigned int SurfaceSizeInMALL[], + bool one_row_per_frame_fits_in_buffer[], + + /* output */ + bool UsesMALLForStaticScreen[]); + +void dml32_CalculateRowBandwidth( + bool GPUVMEnable, + enum source_format_class SourcePixelFormat, + double VRatio, + double VRatioChroma, + bool DCCEnable, + double LineTime, + unsigned int MetaRowByteLuma, + unsigned int MetaRowByteChroma, + unsigned int meta_row_height_luma, + unsigned int meta_row_height_chroma, + unsigned int PixelPTEBytesPerRowLuma, + unsigned int PixelPTEBytesPerRowChroma, + unsigned int dpte_row_height_luma, + unsigned int dpte_row_height_chroma, + /* Output */ + double *meta_row_bw, + double *dpte_row_bw); + +double dml32_CalculateUrgentLatency( + double UrgentLatencyPixelDataOnly, + double UrgentLatencyPixelMixedWithVMData, + double UrgentLatencyVMDataOnly, + bool DoUrgentLatencyAdjustment, + double UrgentLatencyAdjustmentFabricClockComponent, + double UrgentLatencyAdjustmentFabricClockReference, + double FabricClock); + +void dml32_CalculateUrgentBurstFactor( + enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange, + unsigned int swath_width_luma_ub, + unsigned int swath_width_chroma_ub, + unsigned int SwathHeightY, + unsigned int SwathHeightC, + double LineTime, + double UrgentLatency, + double CursorBufferSize, + unsigned int CursorWidth, + unsigned int CursorBPP, + double VRatio, + double VRatioC, + double BytePerPixelInDETY, + double BytePerPixelInDETC, + unsigned int DETBufferSizeY, + unsigned int DETBufferSizeC, + /* Output */ + double *UrgentBurstFactorCursor, + double *UrgentBurstFactorLuma, + double *UrgentBurstFactorChroma, + bool *NotEnoughUrgentLatencyHiding); + +void dml32_CalculateDCFCLKDeepSleep( + unsigned int NumberOfActiveSurfaces, + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], + double VRatio[], + double VRatioChroma[], + double SwathWidthY[], + double SwathWidthC[], + unsigned int DPPPerSurface[], + double HRatio[], + double HRatioChroma[], + double PixelClock[], + double PSCL_THROUGHPUT[], + double PSCL_THROUGHPUT_CHROMA[], + double Dppclk[], + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + unsigned int ReturnBusWidth, + + /* Output */ + double *DCFClkDeepSleep); + +double dml32_CalculateWriteBackDelay( + enum source_format_class WritebackPixelFormat, + double WritebackHRatio, + double WritebackVRatio, + unsigned int WritebackVTaps, + unsigned int WritebackDestinationWidth, + unsigned int WritebackDestinationHeight, + unsigned int WritebackSourceHeight, + unsigned int HTotal); + +void dml32_UseMinimumDCFCLK( + enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[], + bool DRRDisplay[], + bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal, + unsigned int MaxInterDCNTileRepeaters, + unsigned int MaxPrefetchMode, + double DRAMClockChangeLatencyFinal, + double FCLKChangeLatency, + double SREnterPlusExitTime, + unsigned int ReturnBusWidth, + unsigned int RoundTripPingLatencyCycles, + unsigned int ReorderingBytes, + unsigned int PixelChunkSizeInKByte, + unsigned int MetaChunkSize, + bool GPUVMEnable, + unsigned int GPUVMMaxPageTableLevels, + bool HostVMEnable, + unsigned int NumberOfActiveSurfaces, + double HostVMMinPageSize, + unsigned int HostVMMaxNonCachedPageTableLevels, + bool DynamicMetadataVMEnabled, + bool ImmediateFlipRequirement, + bool ProgressiveToInterlaceUnitInOPP, + double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation, + double PercentOfIdealSDPPortBWReceivedAfterUrgLatency, + unsigned int VTotal[], + unsigned int VActive[], + unsigned int DynamicMetadataTransmittedBytes[], + unsigned int DynamicMetadataLinesBeforeActiveRequired[], + bool Interlace[], + double RequiredDPPCLKPerSurface[][2][DC__NUM_DPP__MAX], + double RequiredDISPCLK[][2], + double UrgLatency[], + unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX], + double ProjectedDCFClkDeepSleep[][2], + double MaximumVStartup[][2][DC__NUM_DPP__MAX], + unsigned int TotalNumberOfActiveDPP[][2], + unsigned int TotalNumberOfDCCActiveDPP[][2], + unsigned int dpte_group_bytes[], + double PrefetchLinesY[][2][DC__NUM_DPP__MAX], + double PrefetchLinesC[][2][DC__NUM_DPP__MAX], + unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX], + unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], + unsigned int HTotal[], + double PixelClock[], + double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX], + double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX], + double MetaRowBytes[][2][DC__NUM_DPP__MAX], + bool DynamicMetadataEnable[], + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + double DCFCLKPerState[], + /* Output */ + double DCFCLKState[][2]); + +unsigned int dml32_CalculateExtraLatencyBytes(unsigned int ReorderingBytes, + unsigned int TotalNumberOfActiveDPP, + unsigned int PixelChunkSizeInKByte, + unsigned int TotalNumberOfDCCActiveDPP, + unsigned int MetaChunkSize, + bool GPUVMEnable, + bool HostVMEnable, + unsigned int NumberOfActiveSurfaces, + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], + double HostVMInefficiencyFactor, + double HostVMMinPageSize, + unsigned int HostVMMaxNonCachedPageTableLevels); + +void dml32_CalculateVUpdateAndDynamicMetadataParameters( + unsigned int MaxInterDCNTileRepeaters, + double Dppclk, + double Dispclk, + double DCFClkDeepSleep, + double PixelClock, + unsigned int HTotal, + unsigned int VBlank, + unsigned int DynamicMetadataTransmittedBytes, + unsigned int DynamicMetadataLinesBeforeActiveRequired, + unsigned int InterlaceEnable, + bool ProgressiveToInterlaceUnitInOPP, + double *TSetup, + double *Tdmbf, + double *Tdmec, + double *Tdmsks, + unsigned int *VUpdateOffsetPix, + double *VUpdateWidthPix, + double *VReadyOffsetPix); + +double dml32_CalculateTWait( + unsigned int PrefetchMode, + enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange, + bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal, + bool DRRDisplay, + double DRAMClockChangeLatency, + double FCLKChangeLatency, + double UrgentLatency, + double SREnterPlusExitTime); + +double dml32_get_return_bw_mbps(const soc_bounding_box_st *soc, + const int VoltageLevel, + const bool HostVMEnable, + const double DCFCLK, + const double FabricClock, + const double DRAMSpeed); + +double dml32_get_return_bw_mbps_vm_only(const soc_bounding_box_st *soc, + const int VoltageLevel, + const double DCFCLK, + const double FabricClock, + const double DRAMSpeed); + +double dml32_CalculateExtraLatency( + unsigned int RoundTripPingLatencyCycles, + unsigned int ReorderingBytes, + double DCFCLK, + unsigned int TotalNumberOfActiveDPP, + unsigned int PixelChunkSizeInKByte, + unsigned int TotalNumberOfDCCActiveDPP, + unsigned int MetaChunkSize, + double ReturnBW, + bool GPUVMEnable, + bool HostVMEnable, + unsigned int NumberOfActiveSurfaces, + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], + double HostVMInefficiencyFactor, + double HostVMMinPageSize, + unsigned int HostVMMaxNonCachedPageTableLevels); + +bool dml32_CalculatePrefetchSchedule( + double HostVMInefficiencyFactor, + DmlPipe *myPipe, + unsigned int DSCDelay, + double DPPCLKDelaySubtotalPlusCNVCFormater, + double DPPCLKDelaySCL, + double DPPCLKDelaySCLLBOnly, + double DPPCLKDelayCNVCCursor, + double DISPCLKDelaySubtotal, + unsigned int DPP_RECOUT_WIDTH, + enum output_format_class OutputFormat, + unsigned int MaxInterDCNTileRepeaters, + unsigned int VStartup, + unsigned int MaxVStartup, + unsigned int GPUVMPageTableLevels, + bool GPUVMEnable, + bool HostVMEnable, + unsigned int HostVMMaxNonCachedPageTableLevels, + double HostVMMinPageSize, + bool DynamicMetadataEnable, + bool DynamicMetadataVMEnabled, + int DynamicMetadataLinesBeforeActiveRequired, + unsigned int DynamicMetadataTransmittedBytes, + double UrgentLatency, + double UrgentExtraLatency, + double TCalc, + unsigned int PDEAndMetaPTEBytesFrame, + unsigned int MetaRowByte, + unsigned int PixelPTEBytesPerRow, + double PrefetchSourceLinesY, + unsigned int SwathWidthY, + unsigned int VInitPreFillY, + unsigned int MaxNumSwathY, + double PrefetchSourceLinesC, + unsigned int SwathWidthC, + unsigned int VInitPreFillC, + unsigned int MaxNumSwathC, + unsigned int swath_width_luma_ub, + unsigned int swath_width_chroma_ub, + unsigned int SwathHeightY, + unsigned int SwathHeightC, + double TWait, + /* Output */ + double *DSTXAfterScaler, + double *DSTYAfterScaler, + double *DestinationLinesForPrefetch, + double *PrefetchBandwidth, + double *DestinationLinesToRequestVMInVBlank, + double *DestinationLinesToRequestRowInVBlank, + double *VRatioPrefetchY, + double *VRatioPrefetchC, + double *RequiredPrefetchPixDataBWLuma, + double *RequiredPrefetchPixDataBWChroma, + bool *NotEnoughTimeForDynamicMetadata, + double *Tno_bw, + double *prefetch_vmrow_bw, + double *Tdmdl_vm, + double *Tdmdl, + double *TSetup, + unsigned int *VUpdateOffsetPix, + double *VUpdateWidthPix, + double *VReadyOffsetPix); + +void dml32_CalculateFlipSchedule( + double HostVMInefficiencyFactor, + double UrgentExtraLatency, + double UrgentLatency, + unsigned int GPUVMMaxPageTableLevels, + bool HostVMEnable, + unsigned int HostVMMaxNonCachedPageTableLevels, + bool GPUVMEnable, + double HostVMMinPageSize, + double PDEAndMetaPTEBytesPerFrame, + double MetaRowBytes, + double DPTEBytesPerRow, + double BandwidthAvailableForImmediateFlip, + unsigned int TotImmediateFlipBytes, + enum source_format_class SourcePixelFormat, + double LineTime, + double VRatio, + double VRatioChroma, + double Tno_bw, + bool DCCEnable, + unsigned int dpte_row_height, + unsigned int meta_row_height, + unsigned int dpte_row_height_chroma, + unsigned int meta_row_height_chroma, + bool use_one_row_for_frame_flip, + + /* Output */ + double *DestinationLinesToRequestVMInImmediateFlip, + double *DestinationLinesToRequestRowInImmediateFlip, + double *final_flip_bw, + bool *ImmediateFlipSupportedForPipe); + +void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( + bool USRRetrainingRequiredFinal, + enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[], + unsigned int PrefetchMode, + unsigned int NumberOfActiveSurfaces, + unsigned int MaxLineBufferLines, + unsigned int LineBufferSize, + unsigned int WritebackInterfaceBufferSize, + double DCFCLK, + double ReturnBW, + bool SynchronizeTimingsFinal, + bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal, + bool DRRDisplay[], + unsigned int dpte_group_bytes[], + unsigned int meta_row_height[], + unsigned int meta_row_height_chroma[], + SOCParametersList mmSOCParameters, + unsigned int WritebackChunkSize, + double SOCCLK, + double DCFClkDeepSleep, + unsigned int DETBufferSizeY[], + unsigned int DETBufferSizeC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], + unsigned int LBBitPerPixel[], + double SwathWidthY[], + double SwathWidthC[], + double HRatio[], + double HRatioChroma[], + unsigned int VTaps[], + unsigned int VTapsChroma[], + double VRatio[], + double VRatioChroma[], + unsigned int HTotal[], + unsigned int VTotal[], + unsigned int VActive[], + double PixelClock[], + unsigned int BlendingAndTiming[], + unsigned int DPPPerSurface[], + double BytePerPixelDETY[], + double BytePerPixelDETC[], + double DSTXAfterScaler[], + double DSTYAfterScaler[], + bool WritebackEnable[], + enum source_format_class WritebackPixelFormat[], + double WritebackDestinationWidth[], + double WritebackDestinationHeight[], + double WritebackSourceHeight[], + bool UnboundedRequestEnabled, + unsigned int CompressedBufferSizeInkByte, + + /* Output */ + Watermarks *Watermark, + enum clock_change_support *DRAMClockChangeSupport, + double MaxActiveDRAMClockChangeLatencySupported[], + unsigned int SubViewportLinesNeededInMALL[], + enum dm_fclock_change_support *FCLKChangeSupport, + double *MinActiveFCLKChangeLatencySupported, + bool *USRRetrainingSupport, + double ActiveDRAMClockChangeLatencyMargin[]); + +double dml32_CalculateWriteBackDISPCLK( + enum source_format_class WritebackPixelFormat, + double PixelClock, + double WritebackHRatio, + double WritebackVRatio, + unsigned int WritebackHTaps, + unsigned int WritebackVTaps, + unsigned int WritebackSourceWidth, + unsigned int WritebackDestinationWidth, + unsigned int HTotal, + unsigned int WritebackLineBufferSize, + double DISPCLKDPPCLKVCOSpeed); + +void dml32_CalculateMinAndMaxPrefetchMode( + enum dm_prefetch_modes AllowForPStateChangeOrStutterInVBlankFinal, + unsigned int *MinPrefetchMode, + unsigned int *MaxPrefetchMode); + +void dml32_CalculatePixelDeliveryTimes( + unsigned int NumberOfActiveSurfaces, + double VRatio[], + double VRatioChroma[], + double VRatioPrefetchY[], + double VRatioPrefetchC[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[], + unsigned int DPPPerSurface[], + double HRatio[], + double HRatioChroma[], + double PixelClock[], + double PSCL_THROUGHPUT[], + double PSCL_THROUGHPUT_CHROMA[], + double Dppclk[], + unsigned int BytePerPixelC[], + enum dm_rotation_angle SourceRotation[], + unsigned int NumberOfCursors[], + unsigned int CursorWidth[][DC__NUM_CURSOR__MAX], + unsigned int CursorBPP[][DC__NUM_CURSOR__MAX], + unsigned int BlockWidth256BytesY[], + unsigned int BlockHeight256BytesY[], + unsigned int BlockWidth256BytesC[], + unsigned int BlockHeight256BytesC[], + + /* Output */ + double DisplayPipeLineDeliveryTimeLuma[], + double DisplayPipeLineDeliveryTimeChroma[], + double DisplayPipeLineDeliveryTimeLumaPrefetch[], + double DisplayPipeLineDeliveryTimeChromaPrefetch[], + double DisplayPipeRequestDeliveryTimeLuma[], + double DisplayPipeRequestDeliveryTimeChroma[], + double DisplayPipeRequestDeliveryTimeLumaPrefetch[], + double DisplayPipeRequestDeliveryTimeChromaPrefetch[], + double CursorRequestDeliveryTime[], + double CursorRequestDeliveryTimePrefetch[]); + +void dml32_CalculateMetaAndPTETimes( + bool use_one_row_for_frame[], + unsigned int NumberOfActiveSurfaces, + bool GPUVMEnable, + unsigned int MetaChunkSize, + unsigned int MinMetaChunkSizeBytes, + unsigned int HTotal[], + double VRatio[], + double VRatioChroma[], + double DestinationLinesToRequestRowInVBlank[], + double DestinationLinesToRequestRowInImmediateFlip[], + bool DCCEnable[], + double PixelClock[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], + enum dm_rotation_angle SourceRotation[], + unsigned int dpte_row_height[], + unsigned int dpte_row_height_chroma[], + unsigned int meta_row_width[], + unsigned int meta_row_width_chroma[], + unsigned int meta_row_height[], + unsigned int meta_row_height_chroma[], + unsigned int meta_req_width[], + unsigned int meta_req_width_chroma[], + unsigned int meta_req_height[], + unsigned int meta_req_height_chroma[], + unsigned int dpte_group_bytes[], + unsigned int PTERequestSizeY[], + unsigned int PTERequestSizeC[], + unsigned int PixelPTEReqWidthY[], + unsigned int PixelPTEReqHeightY[], + unsigned int PixelPTEReqWidthC[], + unsigned int PixelPTEReqHeightC[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], + + /* Output */ + double DST_Y_PER_PTE_ROW_NOM_L[], + double DST_Y_PER_PTE_ROW_NOM_C[], + double DST_Y_PER_META_ROW_NOM_L[], + double DST_Y_PER_META_ROW_NOM_C[], + double TimePerMetaChunkNominal[], + double TimePerChromaMetaChunkNominal[], + double TimePerMetaChunkVBlank[], + double TimePerChromaMetaChunkVBlank[], + double TimePerMetaChunkFlip[], + double TimePerChromaMetaChunkFlip[], + double time_per_pte_group_nom_luma[], + double time_per_pte_group_vblank_luma[], + double time_per_pte_group_flip_luma[], + double time_per_pte_group_nom_chroma[], + double time_per_pte_group_vblank_chroma[], + double time_per_pte_group_flip_chroma[]); + +void dml32_CalculateVMGroupAndRequestTimes( + unsigned int NumberOfActiveSurfaces, + bool GPUVMEnable, + unsigned int GPUVMMaxPageTableLevels, + unsigned int HTotal[], + unsigned int BytePerPixelC[], + double DestinationLinesToRequestVMInVBlank[], + double DestinationLinesToRequestVMInImmediateFlip[], + bool DCCEnable[], + double PixelClock[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], + unsigned int vm_group_bytes[], + unsigned int dpde0_bytes_per_frame_ub_l[], + unsigned int dpde0_bytes_per_frame_ub_c[], + unsigned int meta_pte_bytes_per_frame_ub_l[], + unsigned int meta_pte_bytes_per_frame_ub_c[], + + /* Output */ + double TimePerVMGroupVBlank[], + double TimePerVMGroupFlip[], + double TimePerVMRequestVBlank[], + double TimePerVMRequestFlip[]); + +void dml32_CalculateDCCConfiguration( + bool DCCEnabled, + bool DCCProgrammingAssumesScanDirectionUnknown, + enum source_format_class SourcePixelFormat, + unsigned int SurfaceWidthLuma, + unsigned int SurfaceWidthChroma, + unsigned int SurfaceHeightLuma, + unsigned int SurfaceHeightChroma, + unsigned int nomDETInKByte, + unsigned int RequestHeight256ByteLuma, + unsigned int RequestHeight256ByteChroma, + enum dm_swizzle_mode TilingFormat, + unsigned int BytePerPixelY, + unsigned int BytePerPixelC, + double BytePerPixelDETY, + double BytePerPixelDETC, + enum dm_rotation_angle SourceRotation, + /* Output */ + unsigned int *MaxUncompressedBlockLuma, + unsigned int *MaxUncompressedBlockChroma, + unsigned int *MaxCompressedBlockLuma, + unsigned int *MaxCompressedBlockChroma, + unsigned int *IndependentBlockLuma, + unsigned int *IndependentBlockChroma); + +void dml32_CalculateStutterEfficiency( + unsigned int CompressedBufferSizeInkByte, + enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[], + bool UnboundedRequestEnabled, + unsigned int MetaFIFOSizeInKEntries, + unsigned int ZeroSizeBufferEntries, + unsigned int PixelChunkSizeInKByte, + unsigned int NumberOfActiveSurfaces, + unsigned int ROBBufferSizeInKByte, + double TotalDataReadBandwidth, + double DCFCLK, + double ReturnBW, + unsigned int CompbufReservedSpace64B, + unsigned int CompbufReservedSpaceZs, + double SRExitTime, + double SRExitZ8Time, + bool SynchronizeTimingsFinal, + unsigned int BlendingAndTiming[], + double StutterEnterPlusExitWatermark, + double Z8StutterEnterPlusExitWatermark, + bool ProgressiveToInterlaceUnitInOPP, + bool Interlace[], + double MinTTUVBlank[], + unsigned int DPPPerSurface[], + unsigned int DETBufferSizeY[], + unsigned int BytePerPixelY[], + double BytePerPixelDETY[], + double SwathWidthY[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], + double NetDCCRateLuma[], + double NetDCCRateChroma[], + double DCCFractionOfZeroSizeRequestsLuma[], + double DCCFractionOfZeroSizeRequestsChroma[], + unsigned int HTotal[], + unsigned int VTotal[], + double PixelClock[], + double VRatio[], + enum dm_rotation_angle SourceRotation[], + unsigned int BlockHeight256BytesY[], + unsigned int BlockWidth256BytesY[], + unsigned int BlockHeight256BytesC[], + unsigned int BlockWidth256BytesC[], + unsigned int DCCYMaxUncompressedBlock[], + unsigned int DCCCMaxUncompressedBlock[], + unsigned int VActive[], + bool DCCEnable[], + bool WritebackEnable[], + double ReadBandwidthSurfaceLuma[], + double ReadBandwidthSurfaceChroma[], + double meta_row_bw[], + double dpte_row_bw[], + + /* Output */ + double *StutterEfficiencyNotIncludingVBlank, + double *StutterEfficiency, + unsigned int *NumberOfStutterBurstsPerFrame, + double *Z8StutterEfficiencyNotIncludingVBlank, + double *Z8StutterEfficiency, + unsigned int *Z8NumberOfStutterBurstsPerFrame, + double *StutterPeriod, + bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE); + +void dml32_CalculateMaxDETAndMinCompressedBufferSize( + unsigned int ConfigReturnBufferSizeInKByte, + unsigned int ROBBufferSizeInKByte, + unsigned int MaxNumDPP, + bool nomDETInKByteOverrideEnable, // VBA_DELTA, allow DV to override default DET size + unsigned int nomDETInKByteOverrideValue, // VBA_DELTA + + /* Output */ + unsigned int *MaxTotalDETInKByte, + unsigned int *nomDETInKByte, + unsigned int *MinCompressedBufferSizeInKByte); + +bool dml32_CalculateVActiveBandwithSupport(unsigned int NumberOfActiveSurfaces, + double ReturnBW, + bool NotUrgentLatencyHiding[], + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + double cursor_bw[], + double meta_row_bandwidth[], + double dpte_row_bandwidth[], + unsigned int NumberOfDPP[], + double UrgentBurstFactorLuma[], + double UrgentBurstFactorChroma[], + double UrgentBurstFactorCursor[]); + +void dml32_CalculatePrefetchBandwithSupport(unsigned int NumberOfActiveSurfaces, + double ReturnBW, + bool NotUrgentLatencyHiding[], + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + double PrefetchBandwidthLuma[], + double PrefetchBandwidthChroma[], + double cursor_bw[], + double meta_row_bandwidth[], + double dpte_row_bandwidth[], + double cursor_bw_pre[], + double prefetch_vmrow_bw[], + unsigned int NumberOfDPP[], + double UrgentBurstFactorLuma[], + double UrgentBurstFactorChroma[], + double UrgentBurstFactorCursor[], + double UrgentBurstFactorLumaPre[], + double UrgentBurstFactorChromaPre[], + double UrgentBurstFactorCursorPre[], + + /* output */ + double *PrefetchBandwidth, + double *FractionOfUrgentBandwidth, + bool *PrefetchBandwidthSupport); + +double dml32_CalculateBandwidthAvailableForImmediateFlip(unsigned int NumberOfActiveSurfaces, + double ReturnBW, + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + double PrefetchBandwidthLuma[], + double PrefetchBandwidthChroma[], + double cursor_bw[], + double cursor_bw_pre[], + unsigned int NumberOfDPP[], + double UrgentBurstFactorLuma[], + double UrgentBurstFactorChroma[], + double UrgentBurstFactorCursor[], + double UrgentBurstFactorLumaPre[], + double UrgentBurstFactorChromaPre[], + double UrgentBurstFactorCursorPre[]); + +void dml32_CalculateImmediateFlipBandwithSupport(unsigned int NumberOfActiveSurfaces, + double ReturnBW, + enum immediate_flip_requirement ImmediateFlipRequirement[], + double final_flip_bw[], + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + double PrefetchBandwidthLuma[], + double PrefetchBandwidthChroma[], + double cursor_bw[], + double meta_row_bandwidth[], + double dpte_row_bandwidth[], + double cursor_bw_pre[], + double prefetch_vmrow_bw[], + unsigned int NumberOfDPP[], + double UrgentBurstFactorLuma[], + double UrgentBurstFactorChroma[], + double UrgentBurstFactorCursor[], + double UrgentBurstFactorLumaPre[], + double UrgentBurstFactorChromaPre[], + double UrgentBurstFactorCursorPre[], + + /* output */ + double *TotalBandwidth, + double *FractionOfUrgentBandwidth, + bool *ImmediateFlipBandwidthSupport); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c new file mode 100644 index 000000000000..269bdfc4bc40 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c @@ -0,0 +1,616 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + + +#include "../display_mode_lib.h" +#include "../display_mode_vba.h" +#include "../dml_inline_defs.h" +#include "display_rq_dlg_calc_32.h" + +static bool is_dual_plane(enum source_format_class source_format) +{ + bool ret_val = 0; + + if ((source_format == dm_420_12) || (source_format == dm_420_8) || (source_format == dm_420_10) + || (source_format == dm_rgbe_alpha)) + ret_val = 1; + + return ret_val; +} + +void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, + struct display_mode_lib *mode_lib, + const display_e2e_pipe_params_st *e2e_pipe_param, + const unsigned int num_pipes, + const unsigned int pipe_idx) +{ + const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; + bool dual_plane = is_dual_plane((enum source_format_class) (src->source_format)); + double stored_swath_l_bytes; + double stored_swath_c_bytes; + bool is_phantom_pipe; + uint32_t pixel_chunk_bytes = 0; + uint32_t min_pixel_chunk_bytes = 0; + uint32_t meta_chunk_bytes = 0; + uint32_t min_meta_chunk_bytes = 0; + uint32_t dpte_group_bytes = 0; + uint32_t mpte_group_bytes = 0; + + uint32_t p1_pixel_chunk_bytes = 0; + uint32_t p1_min_pixel_chunk_bytes = 0; + uint32_t p1_meta_chunk_bytes = 0; + uint32_t p1_min_meta_chunk_bytes = 0; + uint32_t p1_dpte_group_bytes = 0; + uint32_t p1_mpte_group_bytes = 0; + + unsigned int detile_buf_size_in_bytes; + unsigned int detile_buf_plane1_addr; + unsigned int pte_row_height_linear; + + memset(rq_regs, 0, sizeof(*rq_regs)); + + dml_print("DML_DLG::%s: Calculation for pipe[%d] start, num_pipes=%d\n", __func__, pipe_idx, num_pipes); + + pixel_chunk_bytes = get_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; // From VBA + min_pixel_chunk_bytes = get_min_pixel_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // From VBA + + if (pixel_chunk_bytes == 64 * 1024) + min_pixel_chunk_bytes = 0; + + meta_chunk_bytes = get_meta_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; // From VBA + min_meta_chunk_bytes = get_min_meta_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // From VBA + + dpte_group_bytes = get_dpte_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + mpte_group_bytes = get_vm_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + + p1_pixel_chunk_bytes = pixel_chunk_bytes; + p1_min_pixel_chunk_bytes = min_pixel_chunk_bytes; + p1_meta_chunk_bytes = meta_chunk_bytes; + p1_min_meta_chunk_bytes = min_meta_chunk_bytes; + p1_dpte_group_bytes = dpte_group_bytes; + p1_mpte_group_bytes = mpte_group_bytes; + + if ((enum source_format_class) src->source_format == dm_rgbe_alpha) + p1_pixel_chunk_bytes = get_alpha_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; + + rq_regs->rq_regs_l.chunk_size = dml_log2(pixel_chunk_bytes) - 10; + rq_regs->rq_regs_c.chunk_size = dml_log2(p1_pixel_chunk_bytes) - 10; + + if (min_pixel_chunk_bytes == 0) + rq_regs->rq_regs_l.min_chunk_size = 0; + else + rq_regs->rq_regs_l.min_chunk_size = dml_log2(min_pixel_chunk_bytes) - 8 + 1; + + if (p1_min_pixel_chunk_bytes == 0) + rq_regs->rq_regs_c.min_chunk_size = 0; + else + rq_regs->rq_regs_c.min_chunk_size = dml_log2(p1_min_pixel_chunk_bytes) - 8 + 1; + + rq_regs->rq_regs_l.meta_chunk_size = dml_log2(meta_chunk_bytes) - 10; + rq_regs->rq_regs_c.meta_chunk_size = dml_log2(p1_meta_chunk_bytes) - 10; + + if (min_meta_chunk_bytes == 0) + rq_regs->rq_regs_l.min_meta_chunk_size = 0; + else + rq_regs->rq_regs_l.min_meta_chunk_size = dml_log2(min_meta_chunk_bytes) - 6 + 1; + + if (min_meta_chunk_bytes == 0) + rq_regs->rq_regs_c.min_meta_chunk_size = 0; + else + rq_regs->rq_regs_c.min_meta_chunk_size = dml_log2(p1_min_meta_chunk_bytes) - 6 + 1; + + rq_regs->rq_regs_l.dpte_group_size = dml_log2(dpte_group_bytes) - 6; + rq_regs->rq_regs_l.mpte_group_size = dml_log2(mpte_group_bytes) - 6; + rq_regs->rq_regs_c.dpte_group_size = dml_log2(p1_dpte_group_bytes) - 6; + rq_regs->rq_regs_c.mpte_group_size = dml_log2(p1_mpte_group_bytes) - 6; + + detile_buf_size_in_bytes = get_det_buffer_size_kbytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * 1024; + detile_buf_plane1_addr = 0; + pte_row_height_linear = get_dpte_row_height_linear_l(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx); + + if (src->sw_mode == dm_sw_linear) + ASSERT(pte_row_height_linear >= 8); + + rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(pte_row_height_linear), 1) - 3; + + if (dual_plane) { + unsigned int p1_pte_row_height_linear = get_dpte_row_height_linear_c(mode_lib, e2e_pipe_param, + num_pipes, pipe_idx); + ; + if (src->sw_mode == dm_sw_linear) + ASSERT(p1_pte_row_height_linear >= 8); + + rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(p1_pte_row_height_linear), 1) - 3; + } + + rq_regs->rq_regs_l.swath_height = dml_log2(get_swath_height_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); + rq_regs->rq_regs_c.swath_height = dml_log2(get_swath_height_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); + + // FIXME: take the max between luma, chroma chunk size? + // okay for now, as we are setting pixel_chunk_bytes to 8kb anyways + if (pixel_chunk_bytes >= 32 * 1024 || (dual_plane && p1_pixel_chunk_bytes >= 32 * 1024)) { //32kb + rq_regs->drq_expansion_mode = 0; + } else { + rq_regs->drq_expansion_mode = 2; + } + rq_regs->prq_expansion_mode = 1; + rq_regs->mrq_expansion_mode = 1; + rq_regs->crq_expansion_mode = 1; + + stored_swath_l_bytes = get_det_stored_buffer_size_l_bytes(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx); + stored_swath_c_bytes = get_det_stored_buffer_size_c_bytes(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx); + is_phantom_pipe = get_is_phantom_pipe(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + + // Note: detile_buf_plane1_addr is in unit of 1KB + if (dual_plane) { + if (is_phantom_pipe) { + detile_buf_plane1_addr = ((1024.0 * 1024.0) / 2.0 / 1024.0); // half to chroma + } else { + if (stored_swath_l_bytes / stored_swath_c_bytes <= 1.5) { + detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma +#ifdef __DML_RQ_DLG_CALC_DEBUG__ + dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d (1/2 to chroma)\n", + __func__, detile_buf_plane1_addr); +#endif + } else { + detile_buf_plane1_addr = + dml_round_to_multiple( + (unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), + 1024, 0) / 1024.0; // 2/3 to luma +#ifdef __DML_RQ_DLG_CALC_DEBUG__ + dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d (1/3 chroma)\n", + __func__, detile_buf_plane1_addr); +#endif + } + } + } + rq_regs->plane1_base_address = detile_buf_plane1_addr; + +#ifdef __DML_RQ_DLG_CALC_DEBUG__ + dml_print("DML_DLG: %s: is_phantom_pipe = %d\n", __func__, is_phantom_pipe); + dml_print("DML_DLG: %s: stored_swath_l_bytes = %f\n", __func__, stored_swath_l_bytes); + dml_print("DML_DLG: %s: stored_swath_c_bytes = %f\n", __func__, stored_swath_c_bytes); + dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %d\n", __func__, detile_buf_size_in_bytes); + dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d\n", __func__, detile_buf_plane1_addr); + dml_print("DML_DLG: %s: plane1_base_address = %d\n", __func__, rq_regs->plane1_base_address); +#endif + print__rq_regs_st(mode_lib, rq_regs); + dml_print("DML_DLG::%s: Calculation for pipe[%d] done, num_pipes=%d\n", __func__, pipe_idx, num_pipes); +} + +void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, + display_dlg_regs_st *dlg_regs, + display_ttu_regs_st *ttu_regs, + display_e2e_pipe_params_st *e2e_pipe_param, + const unsigned int num_pipes, + const unsigned int pipe_idx) +{ + const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; + const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; + const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; + double refcyc_per_req_delivery_pre_cur0 = 0.; + double refcyc_per_req_delivery_cur0 = 0.; + double refcyc_per_req_delivery_pre_c = 0.; + double refcyc_per_req_delivery_c = 0.; + double refcyc_per_req_delivery_pre_l; + double refcyc_per_req_delivery_l; + double refcyc_per_line_delivery_pre_c = 0.; + double refcyc_per_line_delivery_c = 0.; + double refcyc_per_line_delivery_pre_l; + double refcyc_per_line_delivery_l; + double min_ttu_vblank; + double vratio_pre_l; + double vratio_pre_c; + unsigned int min_dst_y_next_start; + unsigned int htotal = dst->htotal; + unsigned int hblank_end = dst->hblank_end; + unsigned int vblank_end = dst->vblank_end; + bool interlaced = dst->interlaced; + double pclk_freq_in_mhz = dst->pixel_rate_mhz; + unsigned int vready_after_vcount0; + double refclk_freq_in_mhz = clks->refclk_mhz; + double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; + bool dual_plane = 0; + unsigned int pipe_index_in_combine[DC__NUM_PIPES__MAX]; + int unsigned dst_x_after_scaler; + int unsigned dst_y_after_scaler; + double dst_y_prefetch; + double dst_y_per_vm_vblank; + double dst_y_per_row_vblank; + double dst_y_per_vm_flip; + double dst_y_per_row_flip; + double max_dst_y_per_vm_vblank = 32.0; + double max_dst_y_per_row_vblank = 16.0; + + double dst_y_per_pte_row_nom_l; + double dst_y_per_pte_row_nom_c; + double dst_y_per_meta_row_nom_l; + double dst_y_per_meta_row_nom_c; + double refcyc_per_pte_group_nom_l; + double refcyc_per_pte_group_nom_c; + double refcyc_per_pte_group_vblank_l; + double refcyc_per_pte_group_vblank_c; + double refcyc_per_pte_group_flip_l; + double refcyc_per_pte_group_flip_c; + double refcyc_per_meta_chunk_nom_l; + double refcyc_per_meta_chunk_nom_c; + double refcyc_per_meta_chunk_vblank_l; + double refcyc_per_meta_chunk_vblank_c; + double refcyc_per_meta_chunk_flip_l; + double refcyc_per_meta_chunk_flip_c; + + memset(dlg_regs, 0, sizeof(*dlg_regs)); + memset(ttu_regs, 0, sizeof(*ttu_regs)); + dml_print("DML_DLG::%s: Calculation for pipe[%d] starts, num_pipes=%d\n", __func__, pipe_idx, num_pipes); + dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); + dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); + dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", __func__, ref_freq_to_pix_freq); + dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced); + ASSERT(ref_freq_to_pix_freq < 4.0); + + dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); + dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8)); + dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits + + min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + + dml_print("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, min_ttu_vblank); + dml_print("DML_DLG: %s: min_dst_y_next_start = %d\n", __func__, min_dst_y_next_start); + dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", __func__, ref_freq_to_pix_freq); + + dual_plane = is_dual_plane((enum source_format_class) (src->source_format)); + + vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx); // From VBA + dlg_regs->vready_after_vcount0 = vready_after_vcount0; + + dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, dlg_regs->vready_after_vcount0); + + dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + + // do some adjustment on the dst_after scaler to account for odm combine mode + dml_print("DML_DLG: %s: input dst_x_after_scaler = %d\n", __func__, dst_x_after_scaler); + dml_print("DML_DLG: %s: input dst_y_after_scaler = %d\n", __func__, dst_y_after_scaler); + + // need to figure out which side of odm combine we're in + if (dst->odm_combine == dm_odm_combine_mode_2to1 || dst->odm_combine == dm_odm_combine_mode_4to1) { + // figure out which pipes go together + bool visited[DC__NUM_PIPES__MAX]; + unsigned int i, j, k; + + for (k = 0; k < num_pipes; ++k) { + visited[k] = false; + pipe_index_in_combine[k] = 0; + } + + for (i = 0; i < num_pipes; i++) { + if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) { + + unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp; + unsigned int grp_idx = 0; + + for (j = i; j < num_pipes; j++) { + if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp + && e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) { + pipe_index_in_combine[j] = grp_idx; + dml_print("DML_DLG: %s: pipe[%d] is in grp %d idx %d\n", + __func__, j, grp, grp_idx); + grp_idx++; + visited[j] = true; + } + } + } + } + } + + if (dst->odm_combine == dm_odm_combine_mode_disabled) { + // FIXME how about ODM split?? + dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end * ref_freq_to_pix_freq); + } else { + if (dst->odm_combine == dm_odm_combine_mode_2to1 || dst->odm_combine == dm_odm_combine_mode_4to1) { + // TODO: We should really check that 4to1 is supported before setting it to 4 + unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); + unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx]; + + dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end + + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq); + } + } + ASSERT(dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); + + dml_print("DML_DLG: %s: htotal= %d\n", __func__, htotal); + dml_print("DML_DLG: %s: dst_x_after_scaler[%d]= %d\n", __func__, pipe_idx, dst_x_after_scaler); + dml_print("DML_DLG: %s: dst_y_after_scaler[%d] = %d\n", __func__, pipe_idx, dst_y_after_scaler); + + dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + // From VBA + dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + // From VBA + dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + + // magic! + if (htotal <= 75) { + max_dst_y_per_vm_vblank = 100.0; + max_dst_y_per_row_vblank = 100.0; + } + + dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch); + dml_print("DML_DLG: %s: dst_y_per_vm_flip = %3.2f\n", __func__, dst_y_per_vm_flip); + dml_print("DML_DLG: %s: dst_y_per_row_flip = %3.2f\n", __func__, dst_y_per_row_flip); + dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank); + dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank); + + ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); + ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank); + ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank)); + + vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + + dml_print("DML_DLG: %s: vratio_pre_l = %3.2f\n", __func__, vratio_pre_l); + dml_print("DML_DLG: %s: vratio_pre_c = %3.2f\n", __func__, vratio_pre_c); + + // Active + refcyc_per_line_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + refcyc_per_line_delivery_l = get_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz; // From VBA + + dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, refcyc_per_line_delivery_pre_l); + dml_print("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n", __func__, refcyc_per_line_delivery_l); + + if (dual_plane) { + refcyc_per_line_delivery_pre_c = get_refcyc_per_line_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, + num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + refcyc_per_line_delivery_c = get_refcyc_per_line_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz; // From VBA + + dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", + __func__, refcyc_per_line_delivery_pre_c); + dml_print("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n", + __func__, refcyc_per_line_delivery_c); + } + + if (src->dynamic_metadata_enable && src->gpuvm) + dlg_regs->refcyc_per_vm_dmdata = get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz; // From VBA + + dlg_regs->dmdata_dl_delta = get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) + * refclk_freq_in_mhz; // From VBA + + refcyc_per_req_delivery_pre_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + refcyc_per_req_delivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz; // From VBA + + dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, refcyc_per_req_delivery_pre_l); + dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", __func__, refcyc_per_req_delivery_l); + + if (dual_plane) { + refcyc_per_req_delivery_pre_c = get_refcyc_per_req_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, + num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + refcyc_per_req_delivery_c = get_refcyc_per_req_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz; // From VBA + + dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", + __func__, refcyc_per_req_delivery_pre_c); + dml_print("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n", __func__, refcyc_per_req_delivery_c); + } + + // TTU - Cursor + ASSERT(src->num_cursors <= 1); + if (src->num_cursors > 0) { + refcyc_per_req_delivery_pre_cur0 = get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, + e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + refcyc_per_req_delivery_cur0 = get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param, + num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + + dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f\n", + __func__, refcyc_per_req_delivery_pre_cur0); + dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur0 = %3.2f\n", + __func__, refcyc_per_req_delivery_cur0); + } + + // Assign to register structures + dlg_regs->min_dst_y_next_start = min_dst_y_next_start * dml_pow(2, 2); + ASSERT(dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); + + dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line + dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk + dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); + dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); + dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); + dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); + dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); + + dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); + dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); + + dml_print("DML_DLG: %s: dlg_regs->dst_y_per_vm_vblank = 0x%x\n", __func__, dlg_regs->dst_y_per_vm_vblank); + dml_print("DML_DLG: %s: dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, dlg_regs->dst_y_per_row_vblank); + dml_print("DML_DLG: %s: dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, dlg_regs->dst_y_per_vm_flip); + dml_print("DML_DLG: %s: dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, dlg_regs->dst_y_per_row_flip); + + dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, + num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz; // From VBA + dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA + dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA + + // From VBA + dst_y_per_pte_row_nom_l = get_dst_y_per_pte_row_nom_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + // From VBA + dst_y_per_pte_row_nom_c = get_dst_y_per_pte_row_nom_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + // From VBA + dst_y_per_meta_row_nom_l = get_dst_y_per_meta_row_nom_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + // From VBA + dst_y_per_meta_row_nom_c = get_dst_y_per_meta_row_nom_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + + refcyc_per_pte_group_nom_l = get_refcyc_per_pte_group_nom_l_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz; // From VBA + refcyc_per_pte_group_nom_c = get_refcyc_per_pte_group_nom_c_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz; // From VBA + refcyc_per_pte_group_vblank_l = get_refcyc_per_pte_group_vblank_l_in_us(mode_lib, e2e_pipe_param, + num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + refcyc_per_pte_group_vblank_c = get_refcyc_per_pte_group_vblank_c_in_us(mode_lib, e2e_pipe_param, + num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + refcyc_per_pte_group_flip_l = get_refcyc_per_pte_group_flip_l_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz; // From VBA + refcyc_per_pte_group_flip_c = get_refcyc_per_pte_group_flip_c_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz; // From VBA + + refcyc_per_meta_chunk_nom_l = get_refcyc_per_meta_chunk_nom_l_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz; // From VBA + refcyc_per_meta_chunk_nom_c = get_refcyc_per_meta_chunk_nom_c_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz; // From VBA + refcyc_per_meta_chunk_vblank_l = get_refcyc_per_meta_chunk_vblank_l_in_us(mode_lib, e2e_pipe_param, + num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + refcyc_per_meta_chunk_vblank_c = get_refcyc_per_meta_chunk_vblank_c_in_us(mode_lib, e2e_pipe_param, + num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + refcyc_per_meta_chunk_flip_l = get_refcyc_per_meta_chunk_flip_l_in_us(mode_lib, e2e_pipe_param, + num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + refcyc_per_meta_chunk_flip_c = get_refcyc_per_meta_chunk_flip_c_in_us(mode_lib, e2e_pipe_param, + num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + + dlg_regs->dst_y_per_pte_row_nom_l = dst_y_per_pte_row_nom_l * dml_pow(2, 2); + dlg_regs->dst_y_per_pte_row_nom_c = dst_y_per_pte_row_nom_c * dml_pow(2, 2); + dlg_regs->dst_y_per_meta_row_nom_l = dst_y_per_meta_row_nom_l * dml_pow(2, 2); + dlg_regs->dst_y_per_meta_row_nom_c = dst_y_per_meta_row_nom_c * dml_pow(2, 2); + dlg_regs->refcyc_per_pte_group_nom_l = refcyc_per_pte_group_nom_l; + dlg_regs->refcyc_per_pte_group_nom_c = refcyc_per_pte_group_nom_c; + dlg_regs->refcyc_per_pte_group_vblank_l = refcyc_per_pte_group_vblank_l; + dlg_regs->refcyc_per_pte_group_vblank_c = refcyc_per_pte_group_vblank_c; + dlg_regs->refcyc_per_pte_group_flip_l = refcyc_per_pte_group_flip_l; + dlg_regs->refcyc_per_pte_group_flip_c = refcyc_per_pte_group_flip_c; + dlg_regs->refcyc_per_meta_chunk_nom_l = refcyc_per_meta_chunk_nom_l; + dlg_regs->refcyc_per_meta_chunk_nom_c = refcyc_per_meta_chunk_nom_c; + dlg_regs->refcyc_per_meta_chunk_vblank_l = refcyc_per_meta_chunk_vblank_l; + dlg_regs->refcyc_per_meta_chunk_vblank_c = refcyc_per_meta_chunk_vblank_c; + dlg_regs->refcyc_per_meta_chunk_flip_l = refcyc_per_meta_chunk_flip_l; + dlg_regs->refcyc_per_meta_chunk_flip_c = refcyc_per_meta_chunk_flip_c; + dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1); + dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, 1); + dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, 1); + dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, 1); + + dlg_regs->chunk_hdl_adjust_cur0 = 3; + dlg_regs->dst_y_offset_cur0 = 0; + dlg_regs->chunk_hdl_adjust_cur1 = 3; + dlg_regs->dst_y_offset_cur1 = 0; + + dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off + + ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10)); + ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l * dml_pow(2, 10)); + ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10)); + ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c * dml_pow(2, 10)); + ttu_regs->refcyc_per_req_delivery_pre_cur0 = + (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); + ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10)); + ttu_regs->refcyc_per_req_delivery_pre_cur1 = 0; + ttu_regs->refcyc_per_req_delivery_cur1 = 0; + ttu_regs->qos_level_low_wm = 0; + + ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal * ref_freq_to_pix_freq); + + ttu_regs->qos_level_flip = 14; + ttu_regs->qos_level_fixed_l = 8; + ttu_regs->qos_level_fixed_c = 8; + ttu_regs->qos_level_fixed_cur0 = 8; + ttu_regs->qos_ramp_disable_l = 0; + ttu_regs->qos_ramp_disable_c = 0; + ttu_regs->qos_ramp_disable_cur0 = 0; + ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; + + // CHECK for HW registers' range, assert or clamp + ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); + ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); + ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); + ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); + if (dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23)) + dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; + + if (dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23)) + dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; + + if (dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23)) + dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; + + if (dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23)) + dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; + + ASSERT(dlg_regs->dst_y_after_scaler < (unsigned int) 8); + ASSERT(dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); + ASSERT(dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17)); + if (dual_plane) { + if (dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { + // FIXME what so special about chroma, can we just assert? + dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u > register max U15.2 %u\n", + __func__, dlg_regs->dst_y_per_pte_row_nom_c, (unsigned int)dml_pow(2, 17) - 1); + } + } + ASSERT(dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17)); + ASSERT(dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17)); + + if (dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) + dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; + if (dual_plane) { + if (dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) + dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; + } + ASSERT(dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13)); + if (dual_plane) { + ASSERT(dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13)); + } + + if (dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) + dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; + if (dual_plane) { + if (dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) + dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; + } + ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); + ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_c < (unsigned int)dml_pow(2, 13)); + ASSERT(dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); + ASSERT(dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13)); + ASSERT(dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); + ASSERT(dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13)); + ASSERT(ttu_regs->qos_level_low_wm < dml_pow(2, 14)); + ASSERT(ttu_regs->qos_level_high_wm < dml_pow(2, 14)); + ASSERT(ttu_regs->min_ttu_vblank < dml_pow(2, 24)); + + print__ttu_regs_st(mode_lib, ttu_regs); + print__dlg_regs_st(mode_lib, dlg_regs); + dml_print("DML_DLG::%s: Calculation for pipe[%d] done, num_pipes=%d\n", __func__, pipe_idx, num_pipes); +} + diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.h new file mode 100644 index 000000000000..ebee365293cd --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.h @@ -0,0 +1,70 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DML32_DISPLAY_RQ_DLG_CALC_H__ +#define __DML32_DISPLAY_RQ_DLG_CALC_H__ + +#include "../display_rq_dlg_helpers.h" + +struct display_mode_lib; + +/* +* Function: dml_rq_dlg_get_rq_reg +* Main entry point for test to get the register values out of this DML class. +* This function calls and functions to calculate +* and then populate the rq_regs struct +* Input: +* pipe_param - pipe source configuration (e.g. vp, pitch, scaling, dest, etc.) +* Output: +* rq_regs - struct that holds all the RQ registers field value. +* See also: +*/ +void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, + struct display_mode_lib *mode_lib, + const display_e2e_pipe_params_st *e2e_pipe_param, + const unsigned int num_pipes, + const unsigned int pipe_idx); + +/* +* Function: dml_rq_dlg_get_dlg_reg +* Calculate and return DLG and TTU register struct given the system setting +* Output: +* dlg_regs - output DLG register struct +* ttu_regs - output DLG TTU register struct +* Input: +* e2e_pipe_param - "compacted" array of e2e pipe param struct +* num_pipes - num of active "pipe" or "route" +* pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg +* cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered. +* Added for legacy or unrealistic timing tests. +*/ +void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, + display_dlg_regs_st *dlg_regs, + display_ttu_regs_st *ttu_regs, + display_e2e_pipe_params_st *e2e_pipe_param, + const unsigned int num_pipes, + const unsigned int pipe_idx); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h index edb9f7567d6d..f394b3f3922a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h @@ -26,7 +26,11 @@ #define __DISPLAY_MODE_ENUMS_H__ enum output_encoder_class { - dm_dp = 0, dm_hdmi = 1, dm_wb = 2, dm_edp + dm_dp = 0, + dm_hdmi = 1, + dm_wb = 2, + dm_edp = 3, + dm_dp2p0 = 5, }; enum output_format_class { dm_444 = 0, dm_420 = 1, dm_n422, dm_s422 @@ -105,6 +109,10 @@ enum clock_change_support { dm_dram_clock_change_uninitialized = 0, dm_dram_clock_change_vactive, dm_dram_clock_change_vblank, + dm_dram_clock_change_vactive_w_mall_full_frame, + dm_dram_clock_change_vactive_w_mall_sub_vp, + dm_dram_clock_change_vblank_w_mall_full_frame, + dm_dram_clock_change_vblank_w_mall_sub_vp, dm_dram_clock_change_unsupported }; @@ -169,6 +177,9 @@ enum odm_combine_mode { dm_odm_combine_mode_disabled, dm_odm_combine_mode_2to1, dm_odm_combine_mode_4to1, + dm_odm_split_mode_1to2, + dm_odm_mode_mso_1to2, + dm_odm_mode_mso_1to4 }; enum odm_combine_policy { @@ -176,11 +187,15 @@ enum odm_combine_policy { dm_odm_combine_policy_none, dm_odm_combine_policy_2to1, dm_odm_combine_policy_4to1, + dm_odm_split_policy_1to2, + dm_odm_mso_policy_1to2, + dm_odm_mso_policy_1to4, }; enum immediate_flip_requirement { dm_immediate_flip_not_required, dm_immediate_flip_required, + dm_immediate_flip_opportunistic, }; enum unbounded_requesting_policy { @@ -189,4 +204,75 @@ enum unbounded_requesting_policy { dm_unbounded_requesting_disable }; +enum dm_rotation_angle { + dm_rotation_0, + dm_rotation_90, + dm_rotation_180, + dm_rotation_270, + dm_rotation_0m, + dm_rotation_90m, + dm_rotation_180m, + dm_rotation_270m, +}; + +enum dm_use_mall_for_pstate_change_mode { + dm_use_mall_pstate_change_disable, + dm_use_mall_pstate_change_full_frame, + dm_use_mall_pstate_change_sub_viewport, + dm_use_mall_pstate_change_phantom_pipe +}; + +enum dm_use_mall_for_static_screen_mode { + dm_use_mall_static_screen_disable, + dm_use_mall_static_screen_optimize, + dm_use_mall_static_screen_enable, +}; + +enum dm_output_link_dp_rate { + dm_dp_rate_na, + dm_dp_rate_hbr, + dm_dp_rate_hbr2, + dm_dp_rate_hbr3, + dm_dp_rate_uhbr10, + dm_dp_rate_uhbr13p5, + dm_dp_rate_uhbr20, +}; + +enum dm_fclock_change_support { + dm_fclock_change_vactive, + dm_fclock_change_vblank, + dm_fclock_change_unsupported, +}; + +enum dm_prefetch_modes { + dm_prefetch_support_uclk_fclk_and_stutter_if_possible, + dm_prefetch_support_uclk_fclk_and_stutter, + dm_prefetch_support_fclk_and_stutter, + dm_prefetch_support_stutter, + dm_prefetch_support_none, +}; +enum dm_output_type { + dm_output_type_unknown, + dm_output_type_dp, + dm_output_type_edp, + dm_output_type_dp2p0, + dm_output_type_hdmi, + dm_output_type_hdmifrl, +}; + +enum dm_output_rate { + dm_output_rate_unknown, + dm_output_rate_dp_rate_hbr, + dm_output_rate_dp_rate_hbr2, + dm_output_rate_dp_rate_hbr3, + dm_output_rate_dp_rate_uhbr10, + dm_output_rate_dp_rate_uhbr13p5, + dm_output_rate_dp_rate_uhbr20, + dm_output_rate_hdmi_rate_3x3, + dm_output_rate_hdmi_rate_6x3, + dm_output_rate_hdmi_rate_6x4, + dm_output_rate_hdmi_rate_8x4, + dm_output_rate_hdmi_rate_10x4, + dm_output_rate_hdmi_rate_12x4, +}; #endif diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c index 30db51fbd8cd..5d27ff0ebb5f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c @@ -35,6 +35,8 @@ #include "dcn30/display_rq_dlg_calc_30.h" #include "dcn31/display_mode_vba_31.h" #include "dcn31/display_rq_dlg_calc_31.h" +#include "dcn32/display_mode_vba_32.h" +#include "dcn32/display_rq_dlg_calc_32.h" #include "dml_logger.h" const struct dml_funcs dml20_funcs = { @@ -72,6 +74,13 @@ const struct dml_funcs dml31_funcs = { .rq_dlg_get_rq_reg = dml31_rq_dlg_get_rq_reg }; +const struct dml_funcs dml32_funcs = { + .validate = dml32_ModeSupportAndSystemConfigurationFull, + .recalculate = dml32_recalculate, + .rq_dlg_get_dlg_reg_v2 = dml32_rq_dlg_get_dlg_reg, + .rq_dlg_get_rq_reg_v2 = dml32_rq_dlg_get_rq_reg +}; + void dml_init_instance(struct display_mode_lib *lib, const struct _vcs_dpi_soc_bounding_box_st *soc_bb, const struct _vcs_dpi_ip_params_st *ip_params, @@ -98,6 +107,9 @@ void dml_init_instance(struct display_mode_lib *lib, case DML_PROJECT_DCN31_FPGA: lib->funcs = dml31_funcs; break; + case DML_PROJECT_DCN32: + lib->funcs = dml32_funcs; + break; default: break; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h index d76251fd1566..2bdd6ed22611 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h @@ -41,6 +41,7 @@ enum dml_project { DML_PROJECT_DCN30, DML_PROJECT_DCN31, DML_PROJECT_DCN31_FPGA, + DML_PROJECT_DCN32, }; struct display_mode_lib; @@ -62,6 +63,20 @@ struct dml_funcs { struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_pipe_params_st *pipe_param); + // DLG interfaces have different function parameters in DCN32. + // Create new function pointers to address the changes + void (*rq_dlg_get_dlg_reg_v2)( + struct display_mode_lib *mode_lib, + display_dlg_regs_st *dlg_regs, + display_ttu_regs_st *ttu_regs, + display_e2e_pipe_params_st *e2e_pipe_param, + const unsigned int num_pipes, + const unsigned int pipe_idx); + void (*rq_dlg_get_rq_reg_v2)(display_rq_regs_st *rq_regs, + struct display_mode_lib *mode_lib, + const display_e2e_pipe_params_st *e2e_pipe_param, + const unsigned int num_pipes, + const unsigned int pipe_idx); void (*recalculate)(struct display_mode_lib *mode_lib); void (*validate)(struct display_mode_lib *mode_lib); }; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h index 2df660cd8801..967d3e1ce886 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h @@ -54,12 +54,102 @@ typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st; typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st; typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st; +typedef struct { + double UrgentWatermark; + double WritebackUrgentWatermark; + double DRAMClockChangeWatermark; + double FCLKChangeWatermark; + double WritebackDRAMClockChangeWatermark; + double WritebackFCLKChangeWatermark; + double StutterExitWatermark; + double StutterEnterPlusExitWatermark; + double Z8StutterExitWatermark; + double Z8StutterEnterPlusExitWatermark; + double USRRetrainingWatermark; +} Watermarks; + +typedef struct { + double UrgentLatency; + double ExtraLatency; + double WritebackLatency; + double DRAMClockChangeLatency; + double FCLKChangeLatency; + double SRExitTime; + double SREnterPlusExitTime; + double SRExitZ8Time; + double SREnterPlusExitZ8Time; + double USRRetrainingLatencyPlusSMNLatency; +} Latencies; + +typedef struct { + double Dppclk; + double Dispclk; + double PixelClock; + double DCFClkDeepSleep; + unsigned int DPPPerSurface; + bool ScalerEnabled; + enum dm_rotation_angle SourceRotation; + unsigned int ViewportHeight; + unsigned int ViewportHeightChroma; + unsigned int BlockWidth256BytesY; + unsigned int BlockHeight256BytesY; + unsigned int BlockWidth256BytesC; + unsigned int BlockHeight256BytesC; + unsigned int BlockWidthY; + unsigned int BlockHeightY; + unsigned int BlockWidthC; + unsigned int BlockHeightC; + unsigned int InterlaceEnable; + unsigned int NumberOfCursors; + unsigned int VBlank; + unsigned int HTotal; + unsigned int HActive; + bool DCCEnable; + enum odm_combine_mode ODMMode; + enum source_format_class SourcePixelFormat; + enum dm_swizzle_mode SurfaceTiling; + unsigned int BytePerPixelY; + unsigned int BytePerPixelC; + bool ProgressiveToInterlaceUnitInOPP; + double VRatio; + double VRatioChroma; + unsigned int VTaps; + unsigned int VTapsChroma; + unsigned int PitchY; + unsigned int DCCMetaPitchY; + unsigned int PitchC; + unsigned int DCCMetaPitchC; + bool ViewportStationary; + unsigned int ViewportXStart; + unsigned int ViewportYStart; + unsigned int ViewportXStartC; + unsigned int ViewportYStartC; + bool FORCE_ONE_ROW_FOR_FRAME; + unsigned int SwathHeightY; + unsigned int SwathHeightC; +} DmlPipe; + +typedef struct { + double UrgentLatency; + double ExtraLatency; + double WritebackLatency; + double DRAMClockChangeLatency; + double FCLKChangeLatency; + double SRExitTime; + double SREnterPlusExitTime; + double SRExitZ8Time; + double SREnterPlusExitZ8Time; + double USRRetrainingLatency; + double SMNLatency; +} SOCParametersList; + struct _vcs_dpi_voltage_scaling_st { int state; double dscclk_mhz; double dcfclk_mhz; double socclk_mhz; double phyclk_d18_mhz; + double phyclk_d32_mhz; double dram_speed_mts; double fabricclk_mhz; double dispclk_mhz; @@ -80,6 +170,15 @@ struct _vcs_dpi_soc_bounding_box_st { double urgent_latency_pixel_data_only_us; double urgent_latency_pixel_mixed_with_vm_data_us; double urgent_latency_vm_data_only_us; + double usr_retraining_latency_us; + double smn_latency_us; + double fclk_change_latency_us; + double mall_allocated_for_dcn_mbytes; + double pct_ideal_fabric_bw_after_urgent; + double pct_ideal_dram_bw_after_urgent_strobe; + double max_avg_fabric_bw_use_normal_percent; + double max_avg_dram_bw_use_normal_strobe_percent; + enum dm_prefetch_modes allow_for_pstate_or_stutter_in_vblank_final; double writeback_latency_us; double ideal_dram_bw_after_urgent_percent; double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly @@ -148,6 +247,9 @@ struct _vcs_dpi_ip_params_st { unsigned int dpp_output_buffer_pixels; unsigned int opp_output_buffer_lines; unsigned int pixel_chunk_size_kbytes; + unsigned int alpha_pixel_chunk_size_kbytes; + unsigned int min_pixel_chunk_size_bytes; + unsigned int dcc_meta_buffer_size_bytes; unsigned char pte_enable; unsigned int pte_chunk_size_kbytes; unsigned int meta_chunk_size_kbytes; @@ -168,6 +270,7 @@ struct _vcs_dpi_ip_params_st { double writeback_min_hscl_ratio; double writeback_min_vscl_ratio; unsigned int maximum_dsc_bits_per_component; + unsigned int maximum_pixels_per_line_per_dsc_unit; unsigned int writeback_max_hscl_taps; unsigned int writeback_max_vscl_taps; unsigned int writeback_line_buffer_luma_buffer_size; @@ -224,6 +327,8 @@ struct _vcs_dpi_ip_params_st { unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; unsigned int bug_forcing_LC_req_same_size_fixed; unsigned int number_of_cursors; + unsigned int max_num_dp2p0_outputs; + unsigned int max_num_dp2p0_streams; }; struct _vcs_dpi_display_xfc_params_st { @@ -250,6 +355,7 @@ struct _vcs_dpi_display_pipe_source_params_st { bool hostvm_levels_force_en; unsigned int hostvm_levels_force; int source_scan; + int source_rotation; // new in dml32 int sw_mode; int macro_tile_size; unsigned int surface_width_y; @@ -264,6 +370,15 @@ struct _vcs_dpi_display_pipe_source_params_st { unsigned int viewport_height_c; unsigned int viewport_width_max; unsigned int viewport_height_max; + unsigned int viewport_x_y; + unsigned int viewport_x_c; + bool viewport_stationary; + unsigned int dcc_rate_luma; + unsigned int gpuvm_min_page_size_kbytes; + unsigned int use_mall_for_pstate_change; + unsigned int use_mall_for_static_screen; + bool force_one_row_for_frame; + bool pte_buffer_mode; unsigned int data_pitch; unsigned int data_pitch_c; unsigned int meta_pitch; @@ -296,10 +411,17 @@ struct writeback_st { int wb_vtaps_luma; int wb_htaps_chroma; int wb_vtaps_chroma; + unsigned int wb_htaps; + unsigned int wb_vtaps; double wb_hratio; double wb_vratio; }; +struct display_audio_params_st { + unsigned int audio_sample_rate_khz; + int audio_sample_layout; +}; + struct _vcs_dpi_display_output_params_st { int dp_lanes; double output_bpp; @@ -313,6 +435,11 @@ struct _vcs_dpi_display_output_params_st { int dsc_slices; int max_audio_sample_rate; struct writeback_st wb; + struct display_audio_params_st audio; + unsigned int output_bpc; + int dp_rate; + unsigned int dp_multistream_id; + bool dp_multistream_en; }; struct _vcs_dpi_scaler_ratio_depth_st { @@ -361,6 +488,8 @@ struct _vcs_dpi_display_pipe_dest_params_st { unsigned char use_maximum_vstartup; unsigned int vtotal_max; unsigned int vtotal_min; + unsigned int refresh_rate; + bool synchronize_timings; }; struct _vcs_dpi_display_pipe_params_st { @@ -558,6 +687,9 @@ struct _vcs_dpi_display_arb_params_st { int max_req_outstanding; int min_req_outstanding; int sat_level_us; + int hvm_min_req_outstand_commit_threshold; + int hvm_max_qos_commit_threshold; + int compbuf_reserved_space_kbytes; }; #endif /*__DISPLAY_MODE_STRUCTS_H__*/ diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c index c0740dbdcc2e..2676710a5f2b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c @@ -110,6 +110,15 @@ dml_get_attr_func(return_bw, mode_lib->vba.ReturnBW); dml_get_attr_func(tcalc, mode_lib->vba.TCalc); dml_get_attr_func(fraction_of_urgent_bandwidth, mode_lib->vba.FractionOfUrgentBandwidth); dml_get_attr_func(fraction_of_urgent_bandwidth_imm_flip, mode_lib->vba.FractionOfUrgentBandwidthImmediateFlip); +dml_get_attr_func(cstate_max_cap_mode, mode_lib->vba.DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE); +dml_get_attr_func(comp_buffer_size_kbytes, mode_lib->vba.CompressedBufferSizeInkByte); +dml_get_attr_func(pixel_chunk_size_in_kbyte, mode_lib->vba.PixelChunkSizeInKByte); +dml_get_attr_func(alpha_pixel_chunk_size_in_kbyte, mode_lib->vba.AlphaPixelChunkSizeInKByte); +dml_get_attr_func(meta_chunk_size_in_kbyte, mode_lib->vba.MetaChunkSize); +dml_get_attr_func(min_pixel_chunk_size_in_byte, mode_lib->vba.MinPixelChunkSizeBytes); +dml_get_attr_func(min_meta_chunk_size_in_byte, mode_lib->vba.MinMetaChunkSizeBytes); +dml_get_attr_func(fclk_watermark, mode_lib->vba.Watermark.FCLKChangeWatermark); +dml_get_attr_func(usr_retraining_watermark, mode_lib->vba.Watermark.USRRetrainingWatermark); #define dml_get_pipe_attr_func(attr, var) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe) \ {\ @@ -165,6 +174,27 @@ dml_get_pipe_attr_func(vupdate_width, mode_lib->vba.VUpdateWidthPix); dml_get_pipe_attr_func(vready_offset, mode_lib->vba.VReadyOffsetPix); dml_get_pipe_attr_func(vready_at_or_after_vsync, mode_lib->vba.VREADY_AT_OR_AFTER_VSYNC); dml_get_pipe_attr_func(min_dst_y_next_start, mode_lib->vba.MIN_DST_Y_NEXT_START); +dml_get_pipe_attr_func(dst_y_per_pte_row_nom_l, mode_lib->vba.DST_Y_PER_PTE_ROW_NOM_L); +dml_get_pipe_attr_func(dst_y_per_pte_row_nom_c, mode_lib->vba.DST_Y_PER_PTE_ROW_NOM_C); +dml_get_pipe_attr_func(dst_y_per_meta_row_nom_l, mode_lib->vba.DST_Y_PER_META_ROW_NOM_L); +dml_get_pipe_attr_func(dst_y_per_meta_row_nom_c, mode_lib->vba.DST_Y_PER_META_ROW_NOM_C); +dml_get_pipe_attr_func(refcyc_per_pte_group_nom_l_in_us, mode_lib->vba.time_per_pte_group_nom_luma); +dml_get_pipe_attr_func(refcyc_per_pte_group_nom_c_in_us, mode_lib->vba.time_per_pte_group_nom_chroma); +dml_get_pipe_attr_func(refcyc_per_pte_group_vblank_l_in_us, mode_lib->vba.time_per_pte_group_vblank_luma); +dml_get_pipe_attr_func(refcyc_per_pte_group_vblank_c_in_us, mode_lib->vba.time_per_pte_group_vblank_chroma); +dml_get_pipe_attr_func(refcyc_per_pte_group_flip_l_in_us, mode_lib->vba.time_per_pte_group_flip_luma); +dml_get_pipe_attr_func(refcyc_per_pte_group_flip_c_in_us, mode_lib->vba.time_per_pte_group_flip_chroma); +dml_get_pipe_attr_func(vstartup_calculated, mode_lib->vba.VStartup); +dml_get_pipe_attr_func(dpte_row_height_linear_c, mode_lib->vba.dpte_row_height_linear_chroma); +dml_get_pipe_attr_func(swath_height_l, mode_lib->vba.SwathHeightY); +dml_get_pipe_attr_func(swath_height_c, mode_lib->vba.SwathHeightC); +dml_get_pipe_attr_func(det_stored_buffer_size_l_bytes, mode_lib->vba.DETBufferSizeY); +dml_get_pipe_attr_func(det_stored_buffer_size_c_bytes, mode_lib->vba.DETBufferSizeC); +dml_get_pipe_attr_func(dpte_group_size_in_bytes, mode_lib->vba.dpte_group_bytes); +dml_get_pipe_attr_func(vm_group_size_in_bytes, mode_lib->vba.vm_group_bytes); +dml_get_pipe_attr_func(dpte_row_height_linear_l, mode_lib->vba.dpte_row_height_linear); +dml_get_pipe_attr_func(pte_buffer_mode, mode_lib->vba.PTE_BUFFER_MODE); +dml_get_pipe_attr_func(subviewport_lines_needed_in_mall, mode_lib->vba.SubViewportLinesNeededInMALL); double get_total_immediate_flip_bytes( struct display_mode_lib *mode_lib, @@ -202,6 +232,67 @@ double get_total_prefetch_bw( return total_prefetch_bw; } +unsigned int get_total_surface_size_in_mall_bytes( + struct display_mode_lib *mode_lib, + const display_e2e_pipe_params_st *pipes, + unsigned int num_pipes) +{ + unsigned int k; + unsigned int size = 0.0; + recalculate_params(mode_lib, pipes, num_pipes); + for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) + size += mode_lib->vba.SurfaceSizeInMALL[k]; + return size; +} + +unsigned int get_pipe_idx(struct display_mode_lib *mode_lib, unsigned int plane_idx) +{ + int pipe_idx = -1; + int i; + + ASSERT(plane_idx < DC__NUM_DPP__MAX); + + for (i = 0; i < DC__NUM_DPP__MAX ; i++) { + if (plane_idx == mode_lib->vba.pipe_plane[i]) { + pipe_idx = i; + break; + } + } + ASSERT(pipe_idx >= 0); + + return pipe_idx; +} + + +double get_det_buffer_size_kbytes(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, + unsigned int num_pipes, unsigned int pipe_idx) +{ + unsigned int plane_idx; + double det_buf_size_kbytes; + + recalculate_params(mode_lib, pipes, num_pipes); + plane_idx = mode_lib->vba.pipe_plane[pipe_idx]; + + dml_print("DML::%s: num_pipes=%d pipe_idx=%d plane_idx=%0d\n", __func__, num_pipes, pipe_idx, plane_idx); + det_buf_size_kbytes = mode_lib->vba.DETBufferSizeInKByte[plane_idx]; // per hubp DET buffer size + + dml_print("DML::%s: det_buf_size_kbytes=%3.2f\n", __func__, det_buf_size_kbytes); + + return det_buf_size_kbytes; +} + +bool get_is_phantom_pipe(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, + unsigned int num_pipes, unsigned int pipe_idx) +{ + unsigned int plane_idx; + + recalculate_params(mode_lib, pipes, num_pipes); + plane_idx = mode_lib->vba.pipe_plane[pipe_idx]; + dml_print("DML::%s: num_pipes=%d pipe_idx=%d UseMALLForPStateChange=%0d\n", __func__, num_pipes, pipe_idx, + mode_lib->vba.UsesMALLForPStateChange[plane_idx]); + return (mode_lib->vba.UsesMALLForPStateChange[plane_idx] == dm_use_mall_pstate_change_phantom_pipe); +} + static void fetch_socbb_params(struct display_mode_lib *mode_lib) { soc_bounding_box_st *soc = &mode_lib->vba.soc; @@ -241,6 +332,22 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib) soc->max_avg_sdp_bw_use_normal_percent; mode_lib->vba.SRExitZ8Time = soc->sr_exit_z8_time_us; mode_lib->vba.SREnterPlusExitZ8Time = soc->sr_enter_plus_exit_z8_time_us; + mode_lib->vba.FCLKChangeLatency = soc->fclk_change_latency_us; + mode_lib->vba.USRRetrainingLatency = soc->usr_retraining_latency_us; + mode_lib->vba.SMNLatency = soc->smn_latency_us; + mode_lib->vba.MALLAllocatedForDCNFinal = soc->mall_allocated_for_dcn_mbytes; + + mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE = soc->pct_ideal_dram_bw_after_urgent_strobe; + mode_lib->vba.MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation = + soc->max_avg_fabric_bw_use_normal_percent; + mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE = + soc->max_avg_dram_bw_use_normal_strobe_percent; + + mode_lib->vba.DRAMClockChangeRequirementFinal = 1; + mode_lib->vba.FCLKChangeRequirementFinal = 1; + mode_lib->vba.USRRetrainingRequiredFinal = 1; + mode_lib->vba.ConfigurableDETSizeEnFinal = 0; + mode_lib->vba.AllowForPStateChangeOrStutterInVBlankFinal = soc->allow_for_pstate_or_stutter_in_vblank_final; mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us; mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us; mode_lib->vba.DRAMClockChangeSupportsVActive = !soc->disable_dram_clock_change_vactive_support || @@ -283,6 +390,7 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib) mode_lib->vba.SOCCLKPerState[i] = soc->clock_limits[i].socclk_mhz; mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; mode_lib->vba.PHYCLKD18PerState[i] = soc->clock_limits[i].phyclk_d18_mhz; + mode_lib->vba.PHYCLKD32PerState[i] = soc->clock_limits[i].phyclk_d32_mhz; mode_lib->vba.MaxDppclk[i] = soc->clock_limits[i].dppclk_mhz; mode_lib->vba.MaxDSCCLK[i] = soc->clock_limits[i].dscclk_mhz; mode_lib->vba.DRAMSpeedPerState[i] = soc->clock_limits[i].dram_speed_mts; @@ -325,6 +433,18 @@ static void fetch_ip_params(struct display_mode_lib *mode_lib) mode_lib->vba.COMPBUF_RESERVED_SPACE_ZS = ip->compbuf_reserved_space_zs; mode_lib->vba.MaximumDSCBitsPerComponent = ip->maximum_dsc_bits_per_component; mode_lib->vba.DSC422NativeSupport = ip->dsc422_native_support; + /* In DCN3.2, nomDETInKByte should be initialized correctly. */ + mode_lib->vba.nomDETInKByte = ip->det_buffer_size_kbytes; + mode_lib->vba.CompbufReservedSpace64B = ip->compbuf_reserved_space_64b; + mode_lib->vba.CompbufReservedSpaceZs = ip->compbuf_reserved_space_zs; + mode_lib->vba.CompressedBufferSegmentSizeInkByteFinal = ip->compressed_buffer_segment_size_in_kbytes; + mode_lib->vba.LineBufferSizeFinal = ip->line_buffer_size_bits; + mode_lib->vba.AlphaPixelChunkSizeInKByte = ip->alpha_pixel_chunk_size_kbytes; // not ysed + mode_lib->vba.MinPixelChunkSizeBytes = ip->min_pixel_chunk_size_bytes; // not used + mode_lib->vba.MaximumPixelsPerLinePerDSCUnit = ip->maximum_pixels_per_line_per_dsc_unit; + mode_lib->vba.MaxNumDP2p0Outputs = ip->max_num_dp2p0_outputs; + mode_lib->vba.MaxNumDP2p0Streams = ip->max_num_dp2p0_streams; + mode_lib->vba.DCCMetaBufferSizeBytes = ip->dcc_meta_buffer_size_bytes; mode_lib->vba.PixelChunkSizeInKByte = ip->pixel_chunk_size_kbytes; mode_lib->vba.MetaChunkSize = ip->meta_chunk_size_kbytes; @@ -399,6 +519,7 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) visited[k] = false; mode_lib->vba.NumberOfActivePlanes = 0; + mode_lib->vba.NumberOfActiveSurfaces = 0; mode_lib->vba.ImmediateFlipSupport = false; for (j = 0; j < mode_lib->vba.cache_num_pipes; ++j) { display_pipe_source_params_st *src = &pipes[j].pipe.src; @@ -429,6 +550,21 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) src->viewport_y_y; mode_lib->vba.ViewportYStartC[mode_lib->vba.NumberOfActivePlanes] = src->viewport_y_c; + mode_lib->vba.SourceRotation[mode_lib->vba.NumberOfActiveSurfaces] = src->source_rotation; + mode_lib->vba.ViewportXStartY[mode_lib->vba.NumberOfActiveSurfaces] = src->viewport_x_y; + mode_lib->vba.ViewportXStartC[mode_lib->vba.NumberOfActiveSurfaces] = src->viewport_x_c; + // TODO: Assign correct value to viewport_stationary + mode_lib->vba.ViewportStationary[mode_lib->vba.NumberOfActivePlanes] = + src->viewport_stationary; + mode_lib->vba.UsesMALLForPStateChange[mode_lib->vba.NumberOfActivePlanes] = src->use_mall_for_pstate_change; + mode_lib->vba.UseMALLForStaticScreen[mode_lib->vba.NumberOfActivePlanes] = src->use_mall_for_static_screen; + mode_lib->vba.GPUVMMinPageSizeKBytes[mode_lib->vba.NumberOfActivePlanes] = src->gpuvm_min_page_size_kbytes; + mode_lib->vba.RefreshRate[mode_lib->vba.NumberOfActivePlanes] = dst->refresh_rate; //todo remove this + mode_lib->vba.OutputLinkDPRate[mode_lib->vba.NumberOfActivePlanes] = dout->dp_rate; + mode_lib->vba.ODMUse[mode_lib->vba.NumberOfActivePlanes] = dst->odm_combine; + //TODO: Need to assign correct values to dp_multistream vars + mode_lib->vba.OutputMultistreamEn[mode_lib->vba.NumberOfActiveSurfaces] = dout->dp_multistream_en; + mode_lib->vba.OutputMultistreamId[mode_lib->vba.NumberOfActiveSurfaces] = dout->dp_multistream_id; mode_lib->vba.PitchY[mode_lib->vba.NumberOfActivePlanes] = src->data_pitch; mode_lib->vba.SurfaceWidthY[mode_lib->vba.NumberOfActivePlanes] = src->surface_width_y; mode_lib->vba.SurfaceHeightY[mode_lib->vba.NumberOfActivePlanes] = src->surface_height_y; @@ -677,6 +813,7 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) } mode_lib->vba.NumberOfActivePlanes++; + mode_lib->vba.NumberOfActiveSurfaces++; } // handle overlays through BlendingAndTiming @@ -702,6 +839,8 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) } } + mode_lib->vba.SynchronizeTimingsFinal = pipes[0].pipe.dest.synchronize_timings; + mode_lib->vba.DCCProgrammingAssumesScanDirectionUnknownFinal = false; mode_lib->vba.UseUnboundedRequesting = dm_unbounded_requesting; for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) { if (pipes[k].pipe.src.unbounded_req_mode == 0) @@ -745,6 +884,32 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) mode_lib->vba.GPUVMEnable = mode_lib->vba.GPUVMEnable && !!ip->gpuvm_enable; mode_lib->vba.HostVMEnable = mode_lib->vba.HostVMEnable && !!ip->hostvm_enable; + + for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) { + mode_lib->vba.ForceOneRowForFrame[k] = pipes[k].pipe.src.force_one_row_for_frame; + mode_lib->vba.PteBufferMode[k] = pipes[k].pipe.src.pte_buffer_mode; + + if (mode_lib->vba.PteBufferMode[k] == 0 && mode_lib->vba.GPUVMEnable) { + if (mode_lib->vba.ForceOneRowForFrame[k] || + (mode_lib->vba.GPUVMMinPageSizeKBytes[k] > 64*1024) || + (mode_lib->vba.UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_disable) || + (mode_lib->vba.UseMALLForStaticScreen[k] != dm_use_mall_static_screen_disable)) { +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: ERROR: Invalid PteBufferMode=%d for plane %0d!\n", + __func__, mode_lib->vba.PteBufferMode[k], k); + dml_print("DML::%s: - ForceOneRowForFrame = %d\n", + __func__, mode_lib->vba.ForceOneRowForFrame[k]); + dml_print("DML::%s: - GPUVMMinPageSizeKBytes = %d\n", + __func__, mode_lib->vba.GPUVMMinPageSizeKBytes[k]); + dml_print("DML::%s: - UseMALLForPStateChange = %d\n", + __func__, (int) mode_lib->vba.UsesMALLForPStateChange[k]); + dml_print("DML::%s: - UseMALLForStaticScreen = %d\n", + __func__, (int) mode_lib->vba.UseMALLForStaticScreen[k]); +#endif + ASSERT(0); + } + } + } } /** @@ -896,6 +1061,7 @@ void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib) soc_bounding_box_st *soc = &mode_lib->vba.soc; unsigned int k; unsigned int total_pipes = 0; + unsigned int pipe_idx = 0; mode_lib->vba.VoltageLevel = mode_lib->vba.cache_pipes[0].clks_cfg.voltage; mode_lib->vba.ReturnBW = mode_lib->vba.ReturnBWPerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb]; @@ -917,6 +1083,11 @@ void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib) // Total Available Pipes Support Check for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { total_pipes += mode_lib->vba.DPPPerPlane[k]; + pipe_idx = get_pipe_idx(mode_lib, k); + if (mode_lib->vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz > 0.0) + mode_lib->vba.DPPCLK[k] = mode_lib->vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz; + else + mode_lib->vba.DPPCLK[k] = soc->clock_limits[mode_lib->vba.VoltageLevel].dppclk_mhz; } ASSERT(total_pipes <= DC__NUM_DPP__MAX); } diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 0603b32971a6..ddf8b19c490e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -58,6 +58,15 @@ dml_get_attr_decl(return_bw); dml_get_attr_decl(tcalc); dml_get_attr_decl(fraction_of_urgent_bandwidth); dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip); +dml_get_attr_decl(cstate_max_cap_mode); +dml_get_attr_decl(comp_buffer_size_kbytes); +dml_get_attr_decl(pixel_chunk_size_in_kbyte); +dml_get_attr_decl(alpha_pixel_chunk_size_in_kbyte); +dml_get_attr_decl(meta_chunk_size_in_kbyte); +dml_get_attr_decl(min_pixel_chunk_size_in_byte); +dml_get_attr_decl(min_meta_chunk_size_in_byte); +dml_get_attr_decl(fclk_watermark); +dml_get_attr_decl(usr_retraining_watermark); #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe) @@ -75,6 +84,26 @@ dml_get_pipe_attr_decl(dst_y_per_row_vblank); dml_get_pipe_attr_decl(dst_y_prefetch); dml_get_pipe_attr_decl(dst_y_per_vm_flip); dml_get_pipe_attr_decl(dst_y_per_row_flip); +dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_l); +dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_c); +dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_l); +dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_c); +dml_get_pipe_attr_decl(dpte_row_height_linear_c); +dml_get_pipe_attr_decl(swath_height_l); +dml_get_pipe_attr_decl(swath_height_c); +dml_get_pipe_attr_decl(det_stored_buffer_size_l_bytes); +dml_get_pipe_attr_decl(det_stored_buffer_size_c_bytes); +dml_get_pipe_attr_decl(dpte_group_size_in_bytes); +dml_get_pipe_attr_decl(vm_group_size_in_bytes); +dml_get_pipe_attr_decl(det_buffer_size_kbytes); +dml_get_pipe_attr_decl(dpte_row_height_linear_l); +dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_l_in_us); +dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_c_in_us); +dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_l_in_us); +dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_c_in_us); +dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_l_in_us); +dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_c_in_us); +dml_get_pipe_attr_decl(pte_buffer_mode); dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank); dml_get_pipe_attr_decl(refcyc_per_vm_group_flip); dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank); @@ -108,6 +137,8 @@ dml_get_pipe_attr_decl(vupdate_width); dml_get_pipe_attr_decl(vready_offset); dml_get_pipe_attr_decl(vready_at_or_after_vsync); dml_get_pipe_attr_decl(min_dst_y_next_start); +dml_get_pipe_attr_decl(vstartup_calculated); +dml_get_pipe_attr_decl(subviewport_lines_needed_in_mall); double get_total_immediate_flip_bytes( struct display_mode_lib *mode_lib, @@ -126,6 +157,16 @@ unsigned int dml_get_voltage_level( const display_e2e_pipe_params_st *pipes, unsigned int num_pipes); +unsigned int get_total_surface_size_in_mall_bytes( + struct display_mode_lib *mode_lib, + const display_e2e_pipe_params_st *pipes, + unsigned int num_pipes); +unsigned int get_pipe_idx(struct display_mode_lib *mode_lib, unsigned int plane_idx); + +bool get_is_phantom_pipe(struct display_mode_lib *mode_lib, + const display_e2e_pipe_params_st *pipes, + unsigned int num_pipes, + unsigned int pipe_idx); void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib); bool Calculate256BBlockSizes( @@ -138,6 +179,39 @@ bool Calculate256BBlockSizes( unsigned int *BlockWidth256BytesY, unsigned int *BlockWidth256BytesC); +struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation { + unsigned int dummy_integer_array[2][DC__NUM_DPP__MAX]; + double dummy_single_array[2][DC__NUM_DPP__MAX]; + unsigned int dummy_long_array[2][DC__NUM_DPP__MAX]; + double dummy_double_array[2][DC__NUM_DPP__MAX]; + bool dummy_boolean_array[DC__NUM_DPP__MAX]; + bool dummy_boolean; + bool dummy_boolean2; + enum output_encoder_class dummy_output_encoder_array[DC__NUM_DPP__MAX]; + DmlPipe SurfaceParameters[DC__NUM_DPP__MAX]; + bool dummy_boolean_array2[2][DC__NUM_DPP__MAX]; + unsigned int ReorderBytes; + unsigned int VMDataOnlyReturnBW; + double HostVMInefficiencyFactor; +}; + +struct dml32_ModeSupportAndSystemConfigurationFull { + unsigned int dummy_integer_array[8][DC__NUM_DPP__MAX]; + double dummy_double_array[2][DC__NUM_DPP__MAX]; + DmlPipe SurfParameters[DC__NUM_DPP__MAX]; + double dummy_single[5]; + double dummy_single2[5]; + SOCParametersList mSOCParameters; + unsigned int MaximumSwathWidthSupportLuma; + unsigned int MaximumSwathWidthSupportChroma; +}; + +struct dummy_vars { + struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation + DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation; + struct dml32_ModeSupportAndSystemConfigurationFull dml32_ModeSupportAndSystemConfigurationFull; +}; + struct vba_vars_st { ip_params_st ip; soc_bounding_box_st soc; @@ -154,6 +228,7 @@ struct vba_vars_st { double DISPCLKWithRampingRoundedToDFSGranularity; double DISPCLKWithoutRampingRoundedToDFSGranularity; double MaxDispclkRoundedToDFSGranularity; + double MaxDppclkRoundedToDFSGranularity; bool DCCEnabledAnyPlane; double ReturnBandwidthToDCN; unsigned int TotalActiveDPP; @@ -169,6 +244,8 @@ struct vba_vars_st { double NextMaxVStartup; double VBlankTime; double SmallestVBlank; + enum dm_prefetch_modes AllowForPStateChangeOrStutterInVBlankFinal; // Mode Support only + double DCFCLKDeepSleepPerSurface[DC__NUM_DPP__MAX]; double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX]; double EffectiveDETPlusLBLinesLuma; double EffectiveDETPlusLBLinesChroma; @@ -212,6 +289,14 @@ struct vba_vars_st { double UrgentLatencyPixelMixedWithVMData; double UrgentLatencyVMDataOnly; double UrgentLatency; // max of the above three + double USRRetrainingLatency; + double SMNLatency; + double FCLKChangeLatency; + unsigned int MALLAllocatedForDCNFinal; + double DefaultGPUVMMinPageSizeKBytes; // Default for the project + double MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation; + double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE; + double PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE; double WritebackLatency; double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support @@ -284,6 +369,14 @@ struct vba_vars_st { double DPPCLKDelayCNVCCursor; double DISPCLKDelaySubtotal; bool ProgressiveToInterlaceUnitInOPP; + unsigned int CompressedBufferSegmentSizeInkByteFinal; + unsigned int CompbufReservedSpace64B; + unsigned int CompbufReservedSpaceZs; + unsigned int LineBufferSizeFinal; + unsigned int MaximumPixelsPerLinePerDSCUnit; + unsigned int AlphaPixelChunkSizeInKByte; + double MinPixelChunkSizeBytes; + unsigned int DCCMetaBufferSizeBytes; // Pipe/Plane Parameters int VoltageLevel; double FabricClock; @@ -291,6 +384,23 @@ struct vba_vars_st { double DISPCLK; double SOCCLK; double DCFCLK; + unsigned int MaxTotalDETInKByte; + unsigned int MinCompressedBufferSizeInKByte; + unsigned int NumberOfActiveSurfaces; + bool ViewportStationary[DC__NUM_DPP__MAX]; + unsigned int RefreshRate[DC__NUM_DPP__MAX]; + double OutputBPP[DC__NUM_DPP__MAX]; + unsigned int GPUVMMinPageSizeKBytes[DC__NUM_DPP__MAX]; + bool SynchronizeTimingsFinal; + bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal; + bool ForceOneRowForFrame[DC__NUM_DPP__MAX]; + unsigned int ViewportXStartY[DC__NUM_DPP__MAX]; + unsigned int ViewportXStartC[DC__NUM_DPP__MAX]; + enum dm_rotation_angle SourceRotation[DC__NUM_DPP__MAX]; + bool DRRDisplay[DC__NUM_DPP__MAX]; + bool PteBufferMode[DC__NUM_DPP__MAX]; + enum dm_output_type OutputType[DC__NUM_DPP__MAX]; + enum dm_output_rate OutputRate[DC__NUM_DPP__MAX]; unsigned int NumberOfActivePlanes; unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX]; @@ -392,6 +502,12 @@ struct vba_vars_st { double StutterEfficiencyNotIncludingVBlank; double NonUrgentLatencyTolerance; double MinActiveDRAMClockChangeLatencySupported; + double Z8StutterEfficiencyBestCase; + unsigned int Z8NumberOfStutterBurstsPerFrameBestCase; + double Z8StutterEfficiencyNotIncludingVBlankBestCase; + double StutterPeriodBestCase; + Watermarks Watermark; + bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE; // These are the clocks calcuated by the library but they are not actually // used explicitly. They are fetched by tests and then possibly used. The @@ -399,6 +515,10 @@ struct vba_vars_st { double DISPCLK_calculated; double DPPCLK_calculated[DC__NUM_DPP__MAX]; + bool ImmediateFlipSupportedSurface[DC__NUM_DPP__MAX]; + + bool Use_One_Row_For_Frame[DC__NUM_DPP__MAX]; + bool Use_One_Row_For_Frame_Flip[DC__NUM_DPP__MAX]; unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX]; double VUpdateWidthPix[DC__NUM_DPP__MAX]; double VReadyOffsetPix[DC__NUM_DPP__MAX]; @@ -429,6 +549,7 @@ struct vba_vars_st { double DRAMSpeedPerState[DC__VOLTAGE_STATES]; double MaxDispclk[DC__VOLTAGE_STATES]; int VoltageOverrideLevel; + double PHYCLKD32PerState[DC__VOLTAGE_STATES]; /*outputs*/ bool ScaleRatioAndTapsSupport; @@ -452,6 +573,51 @@ struct vba_vars_st { bool PitchSupport; enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES]; + /* Mode Support Reason */ + bool P2IWith420; + bool DSCOnlyIfNecessaryWithBPP; + bool DSC422NativeNotSupported; + bool LinkRateDoesNotMatchDPVersion; + bool LinkRateForMultistreamNotIndicated; + bool BPPForMultistreamNotIndicated; + bool MultistreamWithHDMIOreDP; + bool MSOOrODMSplitWithNonDPLink; + bool NotEnoughLanesForMSO; + bool ViewportExceedsSurface; + + bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified; + bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe; + bool InvalidCombinationOfMALLUseForPStateAndStaticScreen; + bool InvalidCombinationOfMALLUseForPState; + + enum dm_output_link_dp_rate OutputLinkDPRate[DC__NUM_DPP__MAX]; + double PrefetchLinesYThisState[DC__NUM_DPP__MAX]; + double PrefetchLinesCThisState[DC__NUM_DPP__MAX]; + double meta_row_bandwidth_this_state[DC__NUM_DPP__MAX]; + double dpte_row_bandwidth_this_state[DC__NUM_DPP__MAX]; + double DPTEBytesPerRowThisState[DC__NUM_DPP__MAX]; + double PDEAndMetaPTEBytesPerFrameThisState[DC__NUM_DPP__MAX]; + double MetaRowBytesThisState[DC__NUM_DPP__MAX]; + bool use_one_row_for_frame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; + bool use_one_row_for_frame_flip[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; + bool use_one_row_for_frame_this_state[DC__NUM_DPP__MAX]; + bool use_one_row_for_frame_flip_this_state[DC__NUM_DPP__MAX]; + + unsigned int OutputTypeAndRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; + double RequiredDISPCLKPerSurface[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; + unsigned int MicroTileHeightY[DC__NUM_DPP__MAX]; + unsigned int MicroTileHeightC[DC__NUM_DPP__MAX]; + unsigned int MicroTileWidthY[DC__NUM_DPP__MAX]; + unsigned int MicroTileWidthC[DC__NUM_DPP__MAX]; + bool ImmediateFlipRequiredFinal; + bool DCCProgrammingAssumesScanDirectionUnknownFinal; + bool EnoughWritebackUnits; + bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES]; + bool NumberOfDP2p0Support; + unsigned int MaxNumDP2p0Streams; + unsigned int MaxNumDP2p0Outputs; + enum dm_output_type OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; + enum dm_output_rate OutputRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; double WritebackLineBufferLumaBufferSize; double WritebackLineBufferChromaBufferSize; double WritebackMinHSCLRatio; @@ -647,6 +813,7 @@ struct vba_vars_st { double dummy7[DC__NUM_DPP__MAX]; double dummy8[DC__NUM_DPP__MAX]; double dummy13[DC__NUM_DPP__MAX]; + double dummy_double_array[2][DC__NUM_DPP__MAX]; unsigned int dummyinteger1ms[DC__NUM_DPP__MAX]; double dummyinteger2ms[DC__NUM_DPP__MAX]; unsigned int dummyinteger3[DC__NUM_DPP__MAX]; @@ -666,6 +833,9 @@ struct vba_vars_st { unsigned int dummyintegerarr2[DC__NUM_DPP__MAX]; unsigned int dummyintegerarr3[DC__NUM_DPP__MAX]; unsigned int dummyintegerarr4[DC__NUM_DPP__MAX]; + unsigned int dummy_integer_array[8][DC__NUM_DPP__MAX]; + unsigned int dummy_integer_array22[22][DC__NUM_DPP__MAX]; + bool dummysinglestring; bool SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX]; double PlaneRequiredDISPCLKWithODMCombine2To1; @@ -896,8 +1066,8 @@ struct vba_vars_st { double meta_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; double DETBufferSizeYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; double DETBufferSizeCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; - int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; - int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; + unsigned int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; + unsigned int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES][2]; unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; @@ -972,6 +1142,74 @@ struct vba_vars_st { int Z8NumberOfStutterBurstsPerFrame; unsigned int MaximumDSCBitsPerComponent; unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2]; + double UrgentLatencyWithUSRRetraining; + double UrgLatencyWithUSRRetraining[DC__VOLTAGE_STATES]; + double ReadBandwidthSurfaceLuma[DC__NUM_DPP__MAX]; + double ReadBandwidthSurfaceChroma[DC__NUM_DPP__MAX]; + double SurfaceRequiredDISPCLKWithoutODMCombine; + double SurfaceRequiredDISPCLK; + double SurfaceRequiredDISPCLKWithODMCombine2To1; + double SurfaceRequiredDISPCLKWithODMCombine4To1; + double MinActiveFCLKChangeLatencySupported; + double dummy14; + double dummy15; + int MinVoltageLevel; + int MaxVoltageLevel; + unsigned int TotalNumberOfSingleDPPSurfaces[DC__VOLTAGE_STATES][2]; + unsigned int CompressedBufferSizeInkByteAllStates[DC__VOLTAGE_STATES][2]; + unsigned int DETBufferSizeInKByteAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; + unsigned int DETBufferSizeInKByteThisState[DC__NUM_DPP__MAX]; + unsigned int SurfaceSizeInMALL[DC__NUM_DPP__MAX]; + bool ExceededMALLSize; + bool PTE_BUFFER_MODE[DC__NUM_DPP__MAX]; + unsigned int BIGK_FRAGMENT_SIZE[DC__NUM_DPP__MAX]; + unsigned int dummyinteger33; + unsigned int CompressedBufferSizeInkByteThisState; + enum dm_fclock_change_support FCLKChangeSupport[DC__VOLTAGE_STATES][2]; + Latencies myLatency; + Latencies mLatency; + Watermarks DummyWatermark; + bool USRRetrainingSupport[DC__VOLTAGE_STATES][2]; + bool dummyBooleanvector1[DC__NUM_DPP__MAX]; + bool dummyBooleanvector2[DC__NUM_DPP__MAX]; + enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[DC__NUM_DPP__MAX]; + bool NotEnoughUrgentLatencyHiding_dml32[DC__VOLTAGE_STATES][2]; + bool UnboundedRequestEnabledAllStates[DC__VOLTAGE_STATES][2]; + bool SingleDPPViewportSizeSupportPerSurface[DC__NUM_DPP__MAX]; + enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[DC__NUM_DPP__MAX]; + bool UnboundedRequestEnabledThisState; + bool DRAMClockChangeRequirementFinal; + bool FCLKChangeRequirementFinal; + bool USRRetrainingRequiredFinal; + bool MALLUseFinal; + bool ConfigurableDETSizeEnFinal; + bool dummyboolean; + unsigned int DETSizeOverride[DC__NUM_DPP__MAX]; + unsigned int nomDETInKByte; + enum mpc_combine_affinity MPCCombineUse[DC__NUM_DPP__MAX]; + bool MPCCombineMethodIncompatible; + unsigned int RequiredSlots[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; + bool ExceededMultistreamSlots[DC__VOLTAGE_STATES]; + enum odm_combine_policy ODMUse[DC__NUM_DPP__MAX]; + unsigned int OutputMultistreamId[DC__NUM_DPP__MAX]; + bool OutputMultistreamEn[DC__NUM_DPP__MAX]; + bool UsesMALLForStaticScreen[DC__NUM_DPP__MAX]; + double MaxActiveDRAMClockChangeLatencySupported[DC__NUM_DPP__MAX]; + double WritebackAllowFCLKChangeEndPosition[DC__NUM_DPP__MAX]; + bool PTEBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32 + bool DCCMetaBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32 + bool NotEnoughDSCSlices[DC__VOLTAGE_STATES]; + bool PixelsPerLinePerDSCUnitSupport[DC__VOLTAGE_STATES]; + bool DCCMetaBufferSizeNotExceeded[DC__VOLTAGE_STATES][2]; + unsigned int dpte_row_height_linear[DC__NUM_DPP__MAX]; + unsigned int dpte_row_height_linear_chroma[DC__NUM_DPP__MAX]; + unsigned int BlockHeightY[DC__NUM_DPP__MAX]; + unsigned int BlockHeightC[DC__NUM_DPP__MAX]; + unsigned int BlockWidthY[DC__NUM_DPP__MAX]; + unsigned int BlockWidthC[DC__NUM_DPP__MAX]; + unsigned int SubViewportLinesNeededInMALL[DC__NUM_DPP__MAX]; + bool VActiveBandwithSupport[DC__VOLTAGE_STATES][2]; + struct dummy_vars dummy_vars; }; bool CalculateMinAndMaxPrefetchMode( diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c index d2273674e872..b4b51e51fc25 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c @@ -23,7 +23,6 @@ * */ -#include "dml_wrapper.h" #include "resource.h" #include "core_types.h" #include "dsc.h" @@ -86,25 +85,6 @@ static void get_pixel_clock_parameters( } -static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) -{ - get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); - - if (pipe_ctx->clock_source) - pipe_ctx->clock_source->funcs->get_pix_clk_dividers( - pipe_ctx->clock_source, - &pipe_ctx->stream_res.pix_clk_params, - &pipe_ctx->pll_settings); - - pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; - - resource_build_bit_depth_reduction_params(pipe_ctx->stream, - &pipe_ctx->stream->bit_depth_params); - build_clamping_params(pipe_ctx->stream); - - return DC_OK; -} - static void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, struct bit_depth_reduction_params *fmt_bit_depth) { @@ -231,6 +211,30 @@ static void resource_build_bit_depth_reduction_params(struct dc_stream_state *st fmt_bit_depth->pixel_encoding = pixel_encoding; } +/* Move this after the above function as VS complains about + * declaration issues for resource_build_bit_depth_reduction_params. + */ + +static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) +{ + + get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); + + if (pipe_ctx->clock_source) + pipe_ctx->clock_source->funcs->get_pix_clk_dividers( + pipe_ctx->clock_source, + &pipe_ctx->stream_res.pix_clk_params, + &pipe_ctx->pll_settings); + + pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; + + resource_build_bit_depth_reduction_params(pipe_ctx->stream, + &pipe_ctx->stream->bit_depth_params); + build_clamping_params(pipe_ctx->stream); + + return DC_OK; +} + bool dml_validate_dsc(struct dc *dc, struct dc_state *new_ctx) { int i; @@ -1130,7 +1134,7 @@ static int dml_populate_dml_pipes_from_context( { int i, pipe_cnt; struct resource_context *res_ctx = &context->res_ctx; - struct pipe_ctx *pipe; + struct pipe_ctx *pipe = NULL; // Fix potentially uninitialized error from VS populate_dml_pipes_from_context_base(dc, context, pipes, fast_validate); @@ -1296,6 +1300,7 @@ static void dml_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us; context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; + context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us; } } @@ -1593,11 +1598,8 @@ static void dml_calculate_dlg_params( context->bw_ctx.bw.dcn.clk.z9_support = DCN_Z9_SUPPORT_ALLOW; */ context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); - /* TODO : Uncomment the below line and make changes - * as per DML nomenclature once it is available. - * context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = context->bw_ctx.dml.vba.fclk_pstate_support; - */ - + context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = + context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; @@ -1699,12 +1701,11 @@ static void dml_calculate_wm_and_dlg( context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - //context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_wm_fclk_pstate(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; //context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_wm_usr_retraining(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; /* Temporary, to have some fclk_pstate_change_ns and usr_retraining_ns wm values until DML is implemented */ - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns / 4; - context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns / 8; + //context->bw_ctx.bw.dcn.watermarks.b.usr_retraining = context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns / 8; /* Set D: * All clocks min. @@ -1736,13 +1737,11 @@ static void dml_calculate_wm_and_dlg( context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - //context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_wm_fclk_pstate(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; //context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_wm_usr_retraining(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; /* Temporary, to have some fclk_pstate_change_ns and usr_retraining_ns wm values until DML is implemented */ - context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns / 4; - context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns / 8; - + //context->bw_ctx.bw.dcn.watermarks.d.usr_retraining = context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns / 8; /* Set C, for Dummy P-State: * All clocks min. * DCFCLK: Min, as reported by PM FW, when available @@ -1773,13 +1772,11 @@ static void dml_calculate_wm_and_dlg( context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - //context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_fclk_pstate(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; //context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_wm_usr_retraining(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; /* Temporary, to have some fclk_pstate_change_ns and usr_retraining_ns wm values until DML is implemented */ - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns / 4; - context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns / 8; - + //context->bw_ctx.bw.dcn.watermarks.c.usr_retraining = context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns / 8; if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) { /* The only difference between A and C is p-state latency, if p-state is not supported * with full p-state latency we want to calculate DLG based on dummy p-state latency, -- cgit v1.2.3 From 265280b99822e5562eb431b102f2ba773c7b2a0a Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Mon, 21 Feb 2022 17:01:06 -0500 Subject: drm/amd/display: add CLKMGR changes for DCN32/321 Add support for managing DCN3.2.x clocks. v2: squash in smu interface updates (Alex) v3: Drop unused SMU header (Alex) Signed-off-by: Aurabindo Pillai Acked-by: Jerry Zuo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile | 35 + drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 17 +- .../amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 15 +- .../amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h | 60 + .../gpu/drm/amd/display/dc/clk_mgr/dcn32/dalsmc.h | 65 + .../amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 628 ++++++ .../amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h | 39 + .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c | 117 + .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h | 49 + .../amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h | 108 + drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 3 + drivers/gpu/drm/amd/display/dc/dc.h | 3 + .../drm/amd/display/dc/dcn321/dcn321_resource.c | 2325 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 2 + .../drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 45 +- 15 files changed, 3506 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dalsmc.h create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h create mode 100644 drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile index 817871917632..c935c10b5f4f 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile @@ -172,4 +172,39 @@ AMD_DAL_CLK_MGR_DCN316 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn316/,$(CLK_MGR_ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN316) +############################################################################### +# DCN32 +############################################################################### +CLK_MGR_DCN32 = dcn32_clk_mgr.o dcn32_clk_mgr_smu_msg.o + +AMD_DAL_CLK_MGR_DCN32 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn32/,$(CLK_MGR_DCN32)) + +ifdef CONFIG_X86 +CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -msse +endif + +ifdef CONFIG_PPC64 +CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mhard-float -maltivec +endif + +ifdef CONFIG_CC_IS_GCC +ifeq ($(call cc-ifversion, -lt, 0701, y), y) +IS_OLD_GCC = 1 +endif +CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mhard-float +endif + +ifdef CONFIG_X86 +ifdef IS_OLD_GCC +# Stack alignment mismatch, proceed with caution. +# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 +# (8B stack alignment). +CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mpreferred-stack-boundary=4 +else +CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -msse2 +endif +endif + +AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN32) + endif diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index 772bffda68cc..e803e59abd56 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -45,6 +45,7 @@ #include "dcn31/dcn31_clk_mgr.h" #include "dcn315/dcn315_clk_mgr.h" #include "dcn316/dcn316_clk_mgr.h" +#include "dcn32/dcn32_clk_mgr.h" int clk_mgr_helper_get_active_display_cnt( @@ -316,8 +317,19 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p return &clk_mgr->base.base; } break; -#endif + case AMDGPU_FAMILY_GC_11_0_0: { + struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); + + if (clk_mgr == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); + return &clk_mgr->base; + break; +#endif + } default: ASSERT(0); /* Unknown Asic */ break; @@ -360,6 +372,9 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) dcn316_clk_mgr_destroy(clk_mgr); break; + case AMDGPU_FAMILY_GC_11_0_0: + dcn32_clk_mgr_destroy(clk_mgr); + break; default: break; } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c index 5ed6a93d1708..914708cefc79 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c @@ -129,7 +129,7 @@ static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr) /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */ clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true; - clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dummy_pstate_latency_us; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 0; clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us; clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE; @@ -137,6 +137,14 @@ static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr) clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF; clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz; clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF; + clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = 1600; + clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38; + clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = 8000; + clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9; + clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = 10000; + clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8; + clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = 16000; + clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5; /* Set D - MALL - SR enter and exit times adjusted for MALL */ clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true; @@ -517,6 +525,8 @@ static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct d if (!clk_mgr->smu_present) return; + /* TODO - DP2.0 HW: calculate link 128b/132 link rate in clock manager with new formula */ + clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ; for (i = 0; i < MAX_PIPES * 2; i++) { @@ -620,7 +630,8 @@ void dcn3_clk_mgr_construct( void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr) { - kfree(clk_mgr->base.bw_params); + if (clk_mgr->base.bw_params) + kfree(clk_mgr->base.bw_params); if (clk_mgr->wm_range_table) dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART, diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h index dd4a0bd72458..2cd95ec38266 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h @@ -26,6 +26,66 @@ #ifndef __DCN30_CLK_MGR_H__ #define __DCN30_CLK_MGR_H__ +//CLK1_CLK_PLL_REQ +#ifndef CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT +#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 +#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc +#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 +#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL +#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L +#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L +//CLK1_CLK0_DFS_CNTL +#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER__SHIFT 0x0 +#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER_MASK 0x0000007FL +/*DPREF clock related*/ +#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 +#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL +#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 +#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL +#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 +#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL +#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 +#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL + +//CLK3_0_CLK3_CLK_PLL_REQ +#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 +#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc +#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 +#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL +#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L +#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L + +#define mmCLK0_CLK2_DFS_CNTL 0x16C55 +#define mmCLK00_CLK0_CLK2_DFS_CNTL 0x16C55 +#define mmCLK01_CLK0_CLK2_DFS_CNTL 0x16E55 +#define mmCLK02_CLK0_CLK2_DFS_CNTL 0x17055 + +#define mmCLK0_CLK3_DFS_CNTL 0x16C60 +#define mmCLK00_CLK0_CLK3_DFS_CNTL 0x16C60 +#define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E60 +#define mmCLK02_CLK0_CLK3_DFS_CNTL 0x17060 +#define mmCLK03_CLK0_CLK3_DFS_CNTL 0x17260 + +#define mmCLK0_CLK_PLL_REQ 0x16C10 +#define mmCLK00_CLK0_CLK_PLL_REQ 0x16C10 +#define mmCLK01_CLK0_CLK_PLL_REQ 0x16E10 +#define mmCLK02_CLK0_CLK_PLL_REQ 0x17010 +#define mmCLK03_CLK0_CLK_PLL_REQ 0x17210 + +#define mmCLK1_CLK_PLL_REQ 0x1B00D +#define mmCLK10_CLK1_CLK_PLL_REQ 0x1B00D +#define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D +#define mmCLK12_CLK1_CLK_PLL_REQ 0x1B40D +#define mmCLK13_CLK1_CLK_PLL_REQ 0x1B60D + +#define mmCLK2_CLK_PLL_REQ 0x17E0D + +/*AMCLK*/ + +#define mmCLK11_CLK1_CLK0_DFS_CNTL 0x1B23F +#define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D + +#endif void dcn3_init_clocks(struct clk_mgr *clk_mgr_base); void dcn3_clk_mgr_construct(struct dc_context *ctx, diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dalsmc.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dalsmc.h new file mode 100644 index 000000000000..c427be6add8a --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dalsmc.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#ifndef DALSMC_H +#define DALSMC_H + +#define DALSMC_VERSION 0x1 + +// SMU Response Codes: +#define DALSMC_Result_OK 0x1 +#define DALSMC_Result_Failed 0xFF +#define DALSMC_Result_UnknownCmd 0xFE +#define DALSMC_Result_CmdRejectedPrereq 0xFD +#define DALSMC_Result_CmdRejectedBusy 0xFC + +// Message Definitions: +#define DALSMC_MSG_TestMessage 0x1 +#define DALSMC_MSG_GetSmuVersion 0x2 +#define DALSMC_MSG_GetDriverIfVersion 0x3 +#define DALSMC_MSG_GetMsgHeaderVersion 0x4 +#define DALSMC_MSG_SetDalDramAddrHigh 0x5 +#define DALSMC_MSG_SetDalDramAddrLow 0x6 +#define DALSMC_MSG_TransferTableSmu2Dram 0x7 +#define DALSMC_MSG_TransferTableDram2Smu 0x8 +#define DALSMC_MSG_SetHardMinByFreq 0x9 +#define DALSMC_MSG_SetHardMaxByFreq 0xA +#define DALSMC_MSG_GetDpmFreqByIndex 0xB +#define DALSMC_MSG_GetDcModeMaxDpmFreq 0xC +#define DALSMC_MSG_SetMinDeepSleepDcfclk 0xD +#define DALSMC_MSG_NumOfDisplays 0xE +#define DALSMC_MSG_SetExternalClientDfCstateAllow 0xF +#define DALSMC_MSG_BacoAudioD3PME 0x10 +#define DALSMC_MSG_SetFclkSwitchAllow 0x11 +#define DALSMC_MSG_SetCabForUclkPstate 0x12 +#define DALSMC_MSG_SetWorstCaseUclkLatency 0x13 +#define DALSMC_Message_Count 0x14 + +typedef enum { + FCLK_SWITCH_DISALLOW, + FCLK_SWITCH_ALLOW, +} FclkSwitchAllow_e; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c new file mode 100644 index 000000000000..419cc83b3d21 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -0,0 +1,628 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dccg.h" +#include "clk_mgr_internal.h" + +#include "dcn32/dcn32_clk_mgr_smu_msg.h" +#include "dcn20/dcn20_clk_mgr.h" +#include "dce100/dce_clk_mgr.h" +#include "reg_helper.h" +#include "core_types.h" +#include "dm_helpers.h" + +#include "atomfirmware.h" +#include "smu13_driver_if.h" + +#include "dcn/dcn_3_2_0_offset.h" +#include "dcn/dcn_3_2_0_sh_mask.h" + +#include "dcn32/dcn32_clk_mgr.h" + +#define DCN_BASE__INST0_SEG1 0x000000C0 + +#define mmCLK1_CLK_PLL_REQ 0x16E37 +#define mmCLK1_CLK0_DFS_CNTL 0x16E69 +#define mmCLK1_CLK1_DFS_CNTL 0x16E6C +#define mmCLK1_CLK2_DFS_CNTL 0x16E6F +#define mmCLK1_CLK3_DFS_CNTL 0x16E72 +#define mmCLK1_CLK4_DFS_CNTL 0x16E75 + +#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffUL +#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000UL +#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000UL +#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000 +#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c +#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010 + +#define mmCLK01_CLK0_CLK_PLL_REQ 0x16E37 +#define mmCLK01_CLK0_CLK0_DFS_CNTL 0x16E64 +#define mmCLK01_CLK0_CLK1_DFS_CNTL 0x16E67 +#define mmCLK01_CLK0_CLK2_DFS_CNTL 0x16E6A +#define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E6D +#define mmCLK01_CLK0_CLK4_DFS_CNTL 0x16E70 + +#define CLK0_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffL +#define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000L +#define CLK0_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000L +#define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000 +#define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c +#define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010 + +#undef FN +#define FN(reg_name, field_name) \ + clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name + +#define REG(reg) \ + (clk_mgr->regs->reg) + +#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg + +#define BASE(seg) BASE_INNER(seg) + +#define SR(reg_name)\ + .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ + reg ## reg_name + +#define CLK_SR_DCN32(reg_name)\ + .reg_name = mm ## reg_name + +static const struct clk_mgr_registers clk_mgr_regs_dcn32 = { + CLK_REG_LIST_DCN32() +}; + +static const struct clk_mgr_shift clk_mgr_shift_dcn32 = { + CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT) +}; + +static const struct clk_mgr_mask clk_mgr_mask_dcn32 = { + CLK_COMMON_MASK_SH_LIST_DCN32(_MASK) +}; + + +#define CLK_SR_DCN321(reg_name, block, inst)\ + .reg_name = mm ## block ## _ ## reg_name + +static const struct clk_mgr_registers clk_mgr_regs_dcn321 = { + CLK_REG_LIST_DCN321() +}; + +static const struct clk_mgr_shift clk_mgr_shift_dcn321 = { + CLK_COMMON_MASK_SH_LIST_DCN321(__SHIFT) +}; + +static const struct clk_mgr_mask clk_mgr_mask_dcn321 = { + CLK_COMMON_MASK_SH_LIST_DCN321(_MASK) +}; + + +/* Query SMU for all clock states for a particular clock */ +static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0, + unsigned int *num_levels) +{ + unsigned int i; + char *entry_i = (char *)entry_0; + + uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF); + + if (ret & (1 << 31)) + /* fine-grained, only min and max */ + *num_levels = 2; + else + /* discrete, a number of fixed states */ + /* will set num_levels to 0 on failure */ + *num_levels = ret & 0xFF; + + /* if the initial message failed, num_levels will be 0 */ + for (i = 0; i < *num_levels; i++) { + *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF); + entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); + } +} + +static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr) +{ + /* defaults */ + double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; + double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us; + double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; + double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; + /* For min clocks use as reported by PM FW and report those as min */ + uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; + uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; + uint16_t setb_min_uclk_mhz = min_uclk_mhz; + uint16_t setb_min_dcfclk_mhz = min_dcfclk_mhz; + /* For Set B ranges use min clocks state 2 when available, and report those to PM FW */ + if (clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz) + setb_min_dcfclk_mhz = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; + if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) + setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; + + /* Set A - Normal - default values */ + clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; + + /* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */ + clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_latency_us; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = setb_min_dcfclk_mhz; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF; + + /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */ + /* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */ + if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) { + clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 38; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF; + clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16; + clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38; + clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16; + clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9; + clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16; + clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8; + clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16; + clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5; + } + /* Set D - MALL - SR enter and exit time specific to MALL, TBD after bringup or later phase for now use DRAM values / 2 */ + /* For MALL DRAM clock change latency is N/A, for watermak calculations use lowest value dummy P state latency */ + clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD + clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD + clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz; + clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF; +} + +void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + unsigned int num_levels; + + memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); + clk_mgr_base->clks.p_state_change_support = true; + clk_mgr_base->clks.prev_p_state_change_support = true; + clk_mgr_base->clks.fclk_prev_p_state_change_support = true; + clk_mgr->smu_present = false; + + if (!clk_mgr_base->bw_params) + return; + + if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver)) + clk_mgr->smu_present = true; + + if (!clk_mgr->smu_present) + return; + + dcn30_smu_check_driver_if_version(clk_mgr); + dcn30_smu_check_msg_header_version(clk_mgr); + + /* DCFCLK */ + dcn32_init_single_clock(clk_mgr, PPCLK_DCFCLK, + &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, + &num_levels); + + /* SOCCLK */ + dcn32_init_single_clock(clk_mgr, PPCLK_SOCCLK, + &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, + &num_levels); + /* DTBCLK */ + dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK, + &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, + &num_levels); + + /* DISPCLK */ + dcn32_init_single_clock(clk_mgr, PPCLK_DISPCLK, + &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, + &num_levels); + + + /* Get UCLK, update bounding box */ + clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base); + + /* WM range table */ + dcn32_build_wm_range_table(clk_mgr); +} + +static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, + struct dc_state *context, + bool safe_to_lower) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; + struct dc *dc = clk_mgr_base->ctx->dc; + int display_count; + bool update_dppclk = false; + bool update_dispclk = false; + bool enter_display_off = false; + bool dpp_clock_lowered = false; + struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; + bool force_reset = false; + bool update_uclk = false; + bool p_state_change_support; + bool fclk_p_state_change_support; + int total_plane_count; + + if (dc->work_arounds.skip_clock_update) + return; + + if (clk_mgr_base->clks.dispclk_khz == 0 || + (dc->debug.force_clock_mode & 0x1)) { + /* This is from resume or boot up, if forced_clock cfg option used, + * we bypass program dispclk and DPPCLK, but need set them for S3. + */ + force_reset = true; + + dcn2_read_clocks_from_hw_dentist(clk_mgr_base); + + /* Force_clock_mode 0x1: force reset the clock even it is the same clock + * as long as it is in Passive level. + */ + } + display_count = clk_mgr_helper_get_active_display_cnt(dc, context); + + if (display_count == 0) + enter_display_off = true; + + if (enter_display_off == safe_to_lower) + dcn30_smu_set_num_of_displays(clk_mgr, display_count); + + if (dc->debug.force_min_dcfclk_mhz > 0) + new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? + new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); + + if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { + clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz)); + } + + if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { + clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; + dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz)); + } + + if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) + /* We don't actually care about socclk, don't notify SMU of hard min */ + clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; + + clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; + clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support; + + total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context); + p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0); + fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0); + if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) { + clk_mgr_base->clks.p_state_change_support = p_state_change_support; + + /* to disable P-State switching, set UCLK min = max */ + if (!clk_mgr_base->clks.p_state_change_support) + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, + clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); + } + + if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) { + clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support; + + /* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */ + if (!clk_mgr_base->clks.fclk_p_state_change_support) { + /* Handle code for sending a message to PMFW that FCLK P-state change is not supported */ + dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED); + } + } + + /* Always update saved value, even if new value not set due to P-State switching unsupported */ + if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { + clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; + update_uclk = true; + } + + /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */ + if (clk_mgr_base->clks.p_state_change_support && + (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support)) + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); + + if (clk_mgr_base->clks.fclk_p_state_change_support && + (update_uclk || !clk_mgr_base->clks.fclk_prev_p_state_change_support)) { + /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */ + dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED); + } + + if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) { + if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz) + dpp_clock_lowered = true; + + clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz)); + update_dppclk = true; + } + + if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { + clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz)); + update_dispclk = true; + } + + if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { + if (dpp_clock_lowered) { + /* if clock is being lowered, increase DTO before lowering refclk */ + dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); + dcn20_update_clocks_update_dentist(clk_mgr, context); + } else { + /* if clock is being raised, increase refclk before lowering DTO */ + if (update_dppclk || update_dispclk) + dcn20_update_clocks_update_dentist(clk_mgr, context); + /* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures + * that we do not lower dto when it is not safe to lower. We do not need to + * compare the current and new dppclk before calling this function. + */ + dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); + } + } + + if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) + /*update dmcu for wait_loop count*/ + dmcu->funcs->set_psr_wait_loop(dmcu, + clk_mgr_base->clks.dispclk_khz / 1000 / 7); +} + +void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr) +{ + struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; + int ss_info_num = bp->funcs->get_ss_entry_number( + bp, AS_SIGNAL_TYPE_GPU_PLL); + + if (ss_info_num) { + struct spread_spectrum_info info = { { 0 } }; + enum bp_result result = bp->funcs->get_spread_spectrum_info( + bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info); + + /* SSInfo.spreadSpectrumPercentage !=0 would be sign + * that SS is enabled + */ + if (result == BP_RESULT_OK && + info.spread_spectrum_percentage != 0) { + clk_mgr->ss_on_dprefclk = true; + clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider; + + if (info.type.CENTER_MODE == 0) { + /* Currently for DP Reference clock we + * need only SS percentage for + * downspread + */ + clk_mgr->dprefclk_ss_percentage = + info.spread_spectrum_percentage; + } + } + } +} +static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table; + + if (!clk_mgr->smu_present) + return; + + if (!table) + return; + + memset(table, 0, sizeof(*table)); + + dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32); + dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF); + dcn32_smu_transfer_wm_table_dram_2_smu(clk_mgr); +} + +/* Set min memclk to minimum, either constrained by the current mode or DPM0 */ +static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + + if (!clk_mgr->smu_present) + return; + + if (current_mode) { + if (clk_mgr_base->clks.p_state_change_support) + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, + khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); + else + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, + clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); + } else { + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, + clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); + } +} + +/* Set max memclk to highest DPM value */ +static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + + if (!clk_mgr->smu_present) + return; + + dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, + clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); +} + +/* Get current memclk states, update bounding box */ +static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + unsigned int num_levels; + + if (!clk_mgr->smu_present) + return; + + /* Refresh memclk states */ + dcn32_init_single_clock(clk_mgr, PPCLK_UCLK, + &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz, + &num_levels); + clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1; + + /* Refresh bounding box */ + clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box( + clk_mgr->base.ctx->dc, clk_mgr_base->bw_params); +} + +static bool dcn32_are_clock_states_equal(struct dc_clocks *a, + struct dc_clocks *b) +{ + if (a->dispclk_khz != b->dispclk_khz) + return false; + else if (a->dppclk_khz != b->dppclk_khz) + return false; + else if (a->dcfclk_khz != b->dcfclk_khz) + return false; + else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) + return false; + else if (a->dramclk_khz != b->dramclk_khz) + return false; + else if (a->p_state_change_support != b->p_state_change_support) + return false; + else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support) + return false; + + return true; +} + +static void dcn32_enable_pme_wa(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + + if (!clk_mgr->smu_present) + return; + + dcn30_smu_set_pme_workaround(clk_mgr); +} + +static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + return clk_mgr->smu_present; +} + + +static struct clk_mgr_funcs dcn32_funcs = { + .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, + .update_clocks = dcn32_update_clocks, + .init_clocks = dcn32_init_clocks, + .notify_wm_ranges = dcn32_notify_wm_ranges, + .set_hard_min_memclk = dcn32_set_hard_min_memclk, + .set_hard_max_memclk = dcn32_set_hard_max_memclk, + .get_memclk_states_from_smu = dcn32_get_memclk_states_from_smu, + .are_clock_states_equal = dcn32_are_clock_states_equal, + .enable_pme_wa = dcn32_enable_pme_wa, + .is_smu_present = dcn32_is_smu_present, +}; + +void dcn32_clk_mgr_construct( + struct dc_context *ctx, + struct clk_mgr_internal *clk_mgr, + struct pp_smu_funcs *pp_smu, + struct dccg *dccg) +{ + clk_mgr->base.ctx = ctx; + clk_mgr->base.funcs = &dcn32_funcs; + if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) { + clk_mgr->regs = &clk_mgr_regs_dcn321; + clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn321; + clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn321; + } else { + clk_mgr->regs = &clk_mgr_regs_dcn32; + clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn32; + clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn32; + } + + clk_mgr->dccg = dccg; + clk_mgr->dfs_bypass_disp_clk = 0; + + clk_mgr->dprefclk_ss_percentage = 0; + clk_mgr->dprefclk_ss_divider = 1000; + clk_mgr->ss_on_dprefclk = false; + clk_mgr->dfs_ref_freq_khz = 100000; + + clk_mgr->base.dprefclk_khz = 717000; /* Changed as per DCN3.2_clock_frequency doc */ + clk_mgr->dccg->ref_dtbclk_khz = 477800; + + /* integer part is now VCO frequency in kHz */ + clk_mgr->base.dentist_vco_freq_khz = 4300000;//dcn32_get_vco_frequency_from_reg(clk_mgr); + /* in case we don't get a value from the register, use default */ + if (clk_mgr->base.dentist_vco_freq_khz == 0) + clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */ + + if (clk_mgr->base.boot_snapshot.dprefclk != 0) { + //ASSERT(clk_mgr->base.dprefclk_khz == clk_mgr->base.boot_snapshot.dprefclk); + //clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk; + } + dcn32_clock_read_ss_info(clk_mgr); + + clk_mgr->dfs_bypass_enabled = false; + + clk_mgr->smu_present = false; + + clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL); + + /* need physical address of table to give to PMFW */ + clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx, + DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t), + &clk_mgr->wm_range_table_addr); +} + +void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr) +{ + if (clk_mgr->base.bw_params) + kfree(clk_mgr->base.bw_params); + + if (clk_mgr->wm_range_table) + dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART, + clk_mgr->wm_range_table); +} + diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h new file mode 100644 index 000000000000..57e09c7c95f5 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h @@ -0,0 +1,39 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#ifndef __DCN32_CLK_MGR_H_ +#define __DCN32_CLK_MGR_H_ + +void dcn32_init_clocks(struct clk_mgr *clk_mgr_base); + +void dcn32_clk_mgr_construct(struct dc_context *ctx, + struct clk_mgr_internal *clk_mgr, + struct pp_smu_funcs *pp_smu, + struct dccg *dccg); + +void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr); + + + +#endif /* __DCN32_CLK_MGR_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c new file mode 100644 index 000000000000..35e8afe6db93 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c @@ -0,0 +1,117 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dcn32_clk_mgr_smu_msg.h" + +#include "clk_mgr_internal.h" +#include "reg_helper.h" + +#define mmDAL_MSG_REG 0x1628A +#define mmDAL_ARG_REG 0x16273 +#define mmDAL_RESP_REG 0x16274 + +#define DALSMC_MSG_TransferTableDram2Smu 0x8 + +#define REG(reg_name) \ + mm ## reg_name + +#include "logger_types.h" +#include "dalsmc.h" +#include "smu13_driver_if.h" + +#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } + + +/* + * Function to be used instead of REG_WAIT macro because the wait ends when + * the register is NOT EQUAL to zero, and because the translation in msg_if.h + * won't work with REG_WAIT. + */ +static uint32_t dcn32_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries) +{ + uint32_t reg = 0; + + do { + reg = REG_READ(DAL_RESP_REG); + if (reg) + break; + + if (delay_us >= 1000) + msleep(delay_us/1000); + else if (delay_us > 0) + udelay(delay_us); + } while (max_retries--); + + return reg; +} + +static bool dcn32_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out) +{ + /* Wait for response register to be ready */ + dcn32_smu_wait_for_response(clk_mgr, 10, 200000); + + /* Clear response register */ + REG_WRITE(DAL_RESP_REG, 0); + + /* Set the parameter register for the SMU message */ + REG_WRITE(DAL_ARG_REG, param_in); + + /* Trigger the message transaction by writing the message ID */ + REG_WRITE(DAL_MSG_REG, msg_id); + + /* Wait for response */ + if (dcn32_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) { + if (param_out) + *param_out = REG_READ(DAL_ARG_REG); + + return true; + } + + return false; +} + +void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable) +{ + smu_print("FCLK P-state support value is : %d\n", enable); + + dcn32_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_SetFclkSwitchAllow, enable ? FCLK_PSTATE_SUPPORTED : FCLK_PSTATE_NOTSUPPORTED, NULL); +} + +void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) +{ + smu_print("SMU Transfer WM table DRAM 2 SMU\n"); + + dcn32_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL); +} + +void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways) +{ + smu_print("Numways for SubVP : %d\n", num_ways); + + dcn32_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetCabForUclkPstate, num_ways, NULL); +} + diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h new file mode 100644 index 000000000000..11b25de1527f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h @@ -0,0 +1,49 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DCN32_CLK_MGR_SMU_MSG_H_ +#define __DCN32_CLK_MGR_SMU_MSG_H_ + +#include "core_types.h" +#include "dcn30/dcn30_clk_mgr_smu_msg.h" + +#define FCLK_PSTATE_NOTSUPPORTED 0x00 +#define FCLK_PSTATE_SUPPORTED 0x01 + +/* TODO Remove this MSG ID define after it becomes available in dalsmc */ +#define DALSMC_MSG_SetFclkSwitchAllow 0x11 +#define DALSMC_MSG_SetCabForUclkPstate 0x12 +#define DALSMC_Result_OK 0x1 + +void +dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, + bool enable); + +void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); + +void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways); + + +#endif /* __DCN32_CLK_MGR_SMU_MSG_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h new file mode 100644 index 000000000000..deeb85047e7b --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h @@ -0,0 +1,108 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#ifndef SMU13_DRIVER_IF_DCN32_H +#define SMU13_DRIVER_IF_DCN32_H + +// *** IMPORTANT *** +// PMFW TEAM: Always increment the interface version on any change to this file +#define SMU13_DRIVER_IF_VERSION 0x18 + +//Only Clks that have DPM descriptors are listed here +typedef enum { + PPCLK_GFXCLK = 0, + PPCLK_SOCCLK, + PPCLK_UCLK, + PPCLK_FCLK, + PPCLK_DCLK_0, + PPCLK_VCLK_0, + PPCLK_DCLK_1, + PPCLK_VCLK_1, + PPCLK_DISPCLK, + PPCLK_DPPCLK, + PPCLK_DPREFCLK, + PPCLK_DCFCLK, + PPCLK_DTBCLK, + PPCLK_COUNT, +} PPCLK_e; + +typedef enum { + UCLK_DIV_BY_1 = 0, + UCLK_DIV_BY_2, + UCLK_DIV_BY_4, + UCLK_DIV_BY_8, +} UCLK_DIV_e; + +typedef struct { + uint8_t WmSetting; + uint8_t Flags; + uint8_t Padding[2]; + +} WatermarkRowGeneric_t; + +#define NUM_WM_RANGES 4 + +typedef enum { + WATERMARKS_CLOCK_RANGE = 0, + WATERMARKS_DUMMY_PSTATE, + WATERMARKS_MALL, + WATERMARKS_COUNT, +} WATERMARKS_FLAGS_e; + +typedef struct { + // Watermarks + WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; +} Watermarks_t; + +typedef struct { + Watermarks_t Watermarks; + uint32_t Spare[16]; + + uint32_t MmHubPadding[8]; // SMU internal use +} WatermarksExternal_t; + +// These defines are used with the following messages: +// SMC_MSG_TransferTableDram2Smu +// SMC_MSG_TransferTableSmu2Dram + +// Table transfer status +#define TABLE_TRANSFER_OK 0x0 +#define TABLE_TRANSFER_FAILED 0xFF +#define TABLE_TRANSFER_PENDING 0xAB + +// Table types +#define TABLE_PMFW_PPTABLE 0 +#define TABLE_COMBO_PPTABLE 1 +#define TABLE_WATERMARKS 2 +#define TABLE_AVFS_PSM_DEBUG 3 +#define TABLE_PMSTATUSLOG 4 +#define TABLE_SMU_METRICS 5 +#define TABLE_DRIVER_SMU_CONFIG 6 +#define TABLE_ACTIVITY_MONITOR_COEFF 7 +#define TABLE_OVERDRIVE 8 +#define TABLE_I2C_COMMANDS 9 +#define TABLE_DRIVER_INFO 10 +#define TABLE_COUNT 11 + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index bea77172bd14..1ec81426498f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -3975,6 +3975,9 @@ static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_ return true; } +bool FORCE_RATE = false; +uint32_t FORCE_LANE_COUNT = 0; + void decide_link_settings(struct dc_stream_state *stream, struct dc_link_settings *link_setting) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 11b02a98cf0f..52d6da5ea9a7 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -418,12 +418,15 @@ struct dc_clocks { enum dcn_zstate_support_state zstate_support; bool dtbclk_en; int ref_dtbclk_khz; + int dtbclk_khz; + bool fclk_p_state_change_support; enum dcn_pwr_state pwr_state; /* * Elements below are not compared for the purposes of * optimization required */ bool prev_p_state_change_support; + bool fclk_prev_p_state_change_support; enum dtm_pstate dtm_level; int max_supported_dppclk_khz; int max_supported_dispclk_khz; diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c new file mode 100644 index 000000000000..a8fb4ab8ced1 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c @@ -0,0 +1,2325 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + + +#include "dm_services.h" +#include "dc.h" + +#include "dcn32/dcn32_init.h" + +#include "resource.h" +#include "include/irq_service_interface.h" +#include "dcn32/dcn32_resource.h" +#include "dcn321_resource.h" + +#include "dcn20/dcn20_resource.h" +#include "dcn30/dcn30_resource.h" + +#include "dcn10/dcn10_ipp.h" +#include "dcn30/dcn30_hubbub.h" +#include "dcn31/dcn31_hubbub.h" +#include "dcn32/dcn32_hubbub.h" +#include "dcn32/dcn32_mpc.h" +#include "dcn32/dcn32_hubp.h" +#include "irq/dcn32/irq_service_dcn32.h" +#include "dcn32/dcn32_dpp.h" +#include "dcn32/dcn32_optc.h" +#include "dcn20/dcn20_hwseq.h" +#include "dcn30/dcn30_hwseq.h" +#include "dce110/dce110_hw_sequencer.h" +#include "dcn30/dcn30_opp.h" +#include "dcn20/dcn20_dsc.h" +#include "dcn30/dcn30_vpg.h" +#include "dcn30/dcn30_afmt.h" +#include "dcn30/dcn30_dio_stream_encoder.h" +#include "dcn32/dcn32_dio_stream_encoder.h" +#include "dcn31/dcn31_hpo_dp_stream_encoder.h" +#include "dcn31/dcn31_hpo_dp_link_encoder.h" +#include "dcn32/dcn32_hpo_dp_link_encoder.h" +#include "dc_link_dp.h" +#include "dcn31/dcn31_apg.h" +#include "dcn31/dcn31_dio_link_encoder.h" +#include "dcn32/dcn32_dio_link_encoder.h" +#include "dce/dce_clock_source.h" +#include "dce/dce_audio.h" +#include "dce/dce_hwseq.h" +#include "clk_mgr.h" +#include "virtual/virtual_stream_encoder.h" +#include "dml/display_mode_vba.h" +#include "dcn32/dcn32_dccg.h" +#include "dcn10/dcn10_resource.h" +#include "dc_link_ddc.h" +#include "dcn31/dcn31_panel_cntl.h" + +#include "dcn30/dcn30_dwb.h" +#include "dcn32/dcn32_mmhubbub.h" + +#include "dcn/dcn_3_2_1_offset.h" +#include "dcn/dcn_3_2_1_sh_mask.h" +#include "nbio/nbio_4_3_0_offset.h" + +#include "reg_helper.h" +#include "dce/dmub_abm.h" +#include "dce/dmub_psr.h" +#include "dce/dce_aux.h" +#include "dce/dce_i2c.h" + +#include "dml/dcn30/display_mode_vba_30.h" +#include "vm_helper.h" +#include "dcn20/dcn20_vmid.h" + +#define DCN_BASE__INST0_SEG1 0x000000C0 +#define DCN_BASE__INST0_SEG2 0x000034C0 +#define DCN_BASE__INST0_SEG3 0x00009000 +#define NBIO_BASE__INST0_SEG1 0x00000014 + +#define MAX_INSTANCE 8 +#define MAX_SEGMENT 6 + + +struct IP_BASE_INSTANCE +{ + unsigned int segment[MAX_SEGMENT]; +}; + +struct IP_BASE +{ + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; +}; + +static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; + +#define DC_LOGGER_INIT(logger) +#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16))) +#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) + +#define DCN3_2_DEFAULT_DET_SIZE 256 + +struct _vcs_dpi_ip_params_st dcn3_21_ip = { + .gpuvm_enable = 1, + .gpuvm_max_page_table_levels = 1, + .hostvm_enable = 0, + .rob_buffer_size_kbytes = 128, + .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE, + .config_return_buffer_size_in_kbytes = 1280, + .compressed_buffer_segment_size_in_kbytes = 64, + .meta_fifo_size_in_kentries = 22, + .zero_size_buffer_entries = 512, + .compbuf_reserved_space_64b = 256, + .compbuf_reserved_space_zs = 64, + .dpp_output_buffer_pixels = 2560, + .opp_output_buffer_lines = 1, + .pixel_chunk_size_kbytes = 8, + .alpha_pixel_chunk_size_kbytes = 4, // not appearing in spreadsheet, match c code from hw team + .min_pixel_chunk_size_bytes = 1024, + .dcc_meta_buffer_size_bytes = 6272, + .meta_chunk_size_kbytes = 2, + .min_meta_chunk_size_bytes = 256, + .writeback_chunk_size_kbytes = 8, + .ptoi_supported = false, + .num_dsc = 4, + .maximum_dsc_bits_per_component = 12, + .maximum_pixels_per_line_per_dsc_unit = 6016, + .dsc422_native_support = true, + .is_line_buffer_bpp_fixed = true, + .line_buffer_fixed_bpp = 57, + .line_buffer_size_bits = 1171920, //DPP doc, DCN3_2_DisplayMode_73.xlsm still shows as 986880 bits with 48 bpp + .max_line_buffer_lines = 32, + .writeback_interface_buffer_size_kbytes = 90, + .max_num_dpp = 4, + .max_num_otg = 4, + .max_num_hdmi_frl_outputs = 1, + .max_num_wb = 1, + .max_dchub_pscl_bw_pix_per_clk = 4, + .max_pscl_lb_bw_pix_per_clk = 2, + .max_lb_vscl_bw_pix_per_clk = 4, + .max_vscl_hscl_bw_pix_per_clk = 4, + .max_hscl_ratio = 6, + .max_vscl_ratio = 6, + .max_hscl_taps = 8, + .max_vscl_taps = 8, + .dpte_buffer_size_in_pte_reqs_luma = 64, + .dpte_buffer_size_in_pte_reqs_chroma = 34, + .dispclk_ramp_margin_percent = 1, + .max_inter_dcn_tile_repeaters = 8, + .cursor_buffer_size = 16, + .cursor_chunk_size = 2, + .writeback_line_buffer_buffer_size = 0, + .writeback_min_hscl_ratio = 1, + .writeback_min_vscl_ratio = 1, + .writeback_max_hscl_ratio = 1, + .writeback_max_vscl_ratio = 1, + .writeback_max_hscl_taps = 1, + .writeback_max_vscl_taps = 1, + .dppclk_delay_subtotal = 47, + .dppclk_delay_scl = 50, + .dppclk_delay_scl_lb_only = 16, + .dppclk_delay_cnvc_formatter = 28, + .dppclk_delay_cnvc_cursor = 6, + .dispclk_delay_subtotal = 125, + .dynamic_metadata_vm_enabled = false, + .odm_combine_4to1_supported = false, + .dcc_supported = true, + .max_num_dp2p0_outputs = 2, + .max_num_dp2p0_streams = 4, +}; + +struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = { + .clock_limits = { + { + .state = 0, + .dcfclk_mhz = 1564.0, + .fabricclk_mhz = 400.0, + .dispclk_mhz = 2150.0, + .dppclk_mhz = 2150.0, + .phyclk_mhz = 810.0, + .phyclk_d18_mhz = 667.0, + .phyclk_d32_mhz = 625.0, + .socclk_mhz = 1200.0, + .dscclk_mhz = 716.667, + .dram_speed_mts = 1600.0, + .dtbclk_mhz = 1564.0, + }, + }, + .num_states = 1, + .sr_exit_time_us = 5.20, + .sr_enter_plus_exit_time_us = 9.60, + .sr_exit_z8_time_us = 285.0, + .sr_enter_plus_exit_z8_time_us = 320, + .writeback_latency_us = 12.0, + .round_trip_ping_latency_dcfclk_cycles = 263, + .urgent_latency_pixel_data_only_us = 4.0, + .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, + .urgent_latency_vm_data_only_us = 4.0, + .fclk_change_latency_us = 20, + .usr_retraining_latency_us = 2, + .smn_latency_us = 2, + .mall_allocated_for_dcn_mbytes = 64, + .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, + .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, + .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, + .pct_ideal_sdp_bw_after_urgent = 100.0, + .pct_ideal_fabric_bw_after_urgent = 67.0, + .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0, + .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented + .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented + .pct_ideal_dram_bw_after_urgent_strobe = 67.0, + .max_avg_sdp_bw_use_normal_percent = 80.0, + .max_avg_fabric_bw_use_normal_percent = 60.0, + .max_avg_dram_bw_use_normal_strobe_percent = 50.0, + .max_avg_dram_bw_use_normal_percent = 15.0, + .num_chans = 8, + .dram_channel_width_bytes = 2, + .fabric_datapath_to_dcn_data_return_bytes = 64, + .return_bus_width_bytes = 64, + .downspread_percent = 0.38, + .dcn_downspread_percent = 0.5, + .dram_clock_change_latency_us = 400, + .dispclk_dppclk_vco_speed_mhz = 4300.0, + .do_urgent_latency_adjustment = true, + .urgent_latency_adjustment_fabric_clock_component_us = 1.0, + .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, +}; + +enum dcn321_clk_src_array_id { + DCN321_CLK_SRC_PLL0, + DCN321_CLK_SRC_PLL1, + DCN321_CLK_SRC_PLL2, + DCN321_CLK_SRC_PLL3, + DCN321_CLK_SRC_PLL4, + DCN321_CLK_SRC_TOTAL +}; + +/* begin ********************* + * macros to expend register list macro defined in HW object header file + */ + +/* DCN */ +/* TODO awful hack. fixup dcn20_dwb.h */ +#undef BASE_INNER +#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg + +#define BASE(seg) BASE_INNER(seg) + +#define SR(reg_name)\ + .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ + reg ## reg_name + +#define SRI(reg_name, block, id)\ + .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name + +#define SRI2(reg_name, block, id)\ + .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ + reg ## reg_name + +#define SRIR(var_name, reg_name, block, id)\ + .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name + +#define SRII(reg_name, block, id)\ + .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name + +#define SRII_MPC_RMU(reg_name, block, id)\ + .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name + +#define SRII_DWB(reg_name, temp_name, block, id)\ + .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## temp_name + +#define DCCG_SRII(reg_name, block, id)\ + .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name + +#define VUPDATE_SRII(reg_name, block, id)\ + .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ + reg ## reg_name ## _ ## block ## id + +/* NBIO */ +#define NBIO_BASE_INNER(seg) \ + NBIO_BASE__INST0_SEG ## seg + +#define NBIO_BASE(seg) \ + NBIO_BASE_INNER(seg) + +#define NBIO_SR(reg_name)\ + .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ + regBIF_BX0_ ## reg_name + +#define CTX ctx +#define REG(reg_name) \ + (DCN_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) + +static const struct bios_registers bios_regs = { + NBIO_SR(BIOS_SCRATCH_3), + NBIO_SR(BIOS_SCRATCH_6) +}; + +#define clk_src_regs(index, pllid)\ +[index] = {\ + CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ +} + +static const struct dce110_clk_src_regs clk_src_regs[] = { + clk_src_regs(0, A), + clk_src_regs(1, B), + clk_src_regs(2, C), + clk_src_regs(3, D) +}; + +static const struct dce110_clk_src_shift cs_shift = { + CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) +}; + +static const struct dce110_clk_src_mask cs_mask = { + CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) +}; + +#define abm_regs(id)\ +[id] = {\ + ABM_DCN32_REG_LIST(id)\ +} + +static const struct dce_abm_registers abm_regs[] = { + abm_regs(0), + abm_regs(1), + abm_regs(2), + abm_regs(3), +}; + +static const struct dce_abm_shift abm_shift = { + ABM_MASK_SH_LIST_DCN32(__SHIFT) +}; + +static const struct dce_abm_mask abm_mask = { + ABM_MASK_SH_LIST_DCN32(_MASK) +}; + +#define audio_regs(id)\ +[id] = {\ + AUD_COMMON_REG_LIST(id)\ +} + +static const struct dce_audio_registers audio_regs[] = { + audio_regs(0), + audio_regs(1), + audio_regs(2), + audio_regs(3), + audio_regs(4) +}; + +#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ + SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ + SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ + AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) + +static const struct dce_audio_shift audio_shift = { + DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) +}; + +static const struct dce_audio_mask audio_mask = { + DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) +}; + +#define vpg_regs(id)\ +[id] = {\ + VPG_DCN3_REG_LIST(id)\ +} + +static const struct dcn30_vpg_registers vpg_regs[] = { + vpg_regs(0), + vpg_regs(1), + vpg_regs(2), + vpg_regs(3), + vpg_regs(4), + vpg_regs(5), + vpg_regs(6), + vpg_regs(7), + vpg_regs(8), + vpg_regs(9), +}; + +static const struct dcn30_vpg_shift vpg_shift = { + DCN3_VPG_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn30_vpg_mask vpg_mask = { + DCN3_VPG_MASK_SH_LIST(_MASK) +}; + +#define afmt_regs(id)\ +[id] = {\ + AFMT_DCN3_REG_LIST(id)\ +} + +static const struct dcn30_afmt_registers afmt_regs[] = { + afmt_regs(0), + afmt_regs(1), + afmt_regs(2), + afmt_regs(3), + afmt_regs(4), + afmt_regs(5) +}; + +static const struct dcn30_afmt_shift afmt_shift = { + DCN3_AFMT_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn30_afmt_mask afmt_mask = { + DCN3_AFMT_MASK_SH_LIST(_MASK) +}; + +#define apg_regs(id)\ +[id] = {\ + APG_DCN31_REG_LIST(id)\ +} + +static const struct dcn31_apg_registers apg_regs[] = { + apg_regs(0), + apg_regs(1), + apg_regs(2), + apg_regs(3) +}; + +static const struct dcn31_apg_shift apg_shift = { + DCN31_APG_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn31_apg_mask apg_mask = { + DCN31_APG_MASK_SH_LIST(_MASK) +}; + +#define stream_enc_regs(id)\ +[id] = {\ + SE_DCN32_REG_LIST(id)\ +} + +static const struct dcn10_stream_enc_registers stream_enc_regs[] = { + stream_enc_regs(0), + stream_enc_regs(1), + stream_enc_regs(2), + stream_enc_regs(3), + stream_enc_regs(4) +}; + +static const struct dcn10_stream_encoder_shift se_shift = { + SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) +}; + +static const struct dcn10_stream_encoder_mask se_mask = { + SE_COMMON_MASK_SH_LIST_DCN32(_MASK) +}; + + +#define aux_regs(id)\ +[id] = {\ + DCN2_AUX_REG_LIST(id)\ +} + +static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { + aux_regs(0), + aux_regs(1), + aux_regs(2), + aux_regs(3), + aux_regs(4) +}; + +#define hpd_regs(id)\ +[id] = {\ + HPD_REG_LIST(id)\ +} + +static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { + hpd_regs(0), + hpd_regs(1), + hpd_regs(2), + hpd_regs(3), + hpd_regs(4) +}; + +#define link_regs(id, phyid)\ +[id] = {\ + LE_DCN31_REG_LIST(id), \ + UNIPHY_DCN2_REG_LIST(phyid), \ + /*DPCS_DCN31_REG_LIST(id),*/ \ +} + +static const struct dcn10_link_enc_registers link_enc_regs[] = { + link_regs(0, A), + link_regs(1, B), + link_regs(2, C), + link_regs(3, D), + link_regs(4, E) +}; + +static const struct dcn10_link_enc_shift le_shift = { + LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ +// DPCS_DCN31_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn10_link_enc_mask le_mask = { + LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ +// DPCS_DCN31_MASK_SH_LIST(_MASK) +}; + +#define hpo_dp_stream_encoder_reg_list(id)\ +[id] = {\ + DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ +} + +static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { + hpo_dp_stream_encoder_reg_list(0), + hpo_dp_stream_encoder_reg_list(1), + hpo_dp_stream_encoder_reg_list(2), + hpo_dp_stream_encoder_reg_list(3), +}; + +static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { + DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { + DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) +}; + + +#define hpo_dp_link_encoder_reg_list(id)\ +[id] = {\ + DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ + /*DCN3_1_RDPCSTX_REG_LIST(0),*/\ + /*DCN3_1_RDPCSTX_REG_LIST(1),*/\ + /*DCN3_1_RDPCSTX_REG_LIST(2),*/\ + /*DCN3_1_RDPCSTX_REG_LIST(3),*/\ + /*DCN3_1_RDPCSTX_REG_LIST(4)*/\ +} + +static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { + hpo_dp_link_encoder_reg_list(0), + hpo_dp_link_encoder_reg_list(1), +}; + +static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { + DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { + DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) +}; + +#define dpp_regs(id)\ +[id] = {\ + DPP_REG_LIST_DCN30_COMMON(id),\ +} + +static const struct dcn3_dpp_registers dpp_regs[] = { + dpp_regs(0), + dpp_regs(1), + dpp_regs(2), + dpp_regs(3) +}; + +static const struct dcn3_dpp_shift tf_shift = { + DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) +}; + +static const struct dcn3_dpp_mask tf_mask = { + DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) +}; + + +#define opp_regs(id)\ +[id] = {\ + OPP_REG_LIST_DCN30(id),\ +} + +static const struct dcn20_opp_registers opp_regs[] = { + opp_regs(0), + opp_regs(1), + opp_regs(2), + opp_regs(3) +}; + +static const struct dcn20_opp_shift opp_shift = { + OPP_MASK_SH_LIST_DCN20(__SHIFT) +}; + +static const struct dcn20_opp_mask opp_mask = { + OPP_MASK_SH_LIST_DCN20(_MASK) +}; + +#define aux_engine_regs(id)\ +[id] = {\ + AUX_COMMON_REG_LIST0(id), \ + .AUXN_IMPCAL = 0, \ + .AUXP_IMPCAL = 0, \ + .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ +} + +static const struct dce110_aux_registers aux_engine_regs[] = { + aux_engine_regs(0), + aux_engine_regs(1), + aux_engine_regs(2), + aux_engine_regs(3), + aux_engine_regs(4) +}; + +static const struct dce110_aux_registers_shift aux_shift = { + DCN_AUX_MASK_SH_LIST(__SHIFT) +}; + +static const struct dce110_aux_registers_mask aux_mask = { + DCN_AUX_MASK_SH_LIST(_MASK) +}; + + +#define dwbc_regs_dcn3(id)\ +[id] = {\ + DWBC_COMMON_REG_LIST_DCN30(id),\ +} + +static const struct dcn30_dwbc_registers dwbc30_regs[] = { + dwbc_regs_dcn3(0), +}; + +static const struct dcn30_dwbc_shift dwbc30_shift = { + DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) +}; + +static const struct dcn30_dwbc_mask dwbc30_mask = { + DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) +}; + +#define mcif_wb_regs_dcn3(id)\ +[id] = {\ + MCIF_WB_COMMON_REG_LIST_DCN32(id),\ +} + +static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { + mcif_wb_regs_dcn3(0) +}; + +static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { + MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) +}; + +static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { + MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) +}; + +#define dsc_regsDCN20(id)\ +[id] = {\ + DSC_REG_LIST_DCN20(id)\ +} + +static const struct dcn20_dsc_registers dsc_regs[] = { + dsc_regsDCN20(0), + dsc_regsDCN20(1), + dsc_regsDCN20(2), + dsc_regsDCN20(3) +}; + +static const struct dcn20_dsc_shift dsc_shift = { + DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) +}; + +static const struct dcn20_dsc_mask dsc_mask = { + DSC_REG_LIST_SH_MASK_DCN20(_MASK) +}; + +static const struct dcn30_mpc_registers mpc_regs = { + MPC_REG_LIST_DCN3_0(0), + MPC_REG_LIST_DCN3_0(1), + MPC_REG_LIST_DCN3_0(2), + MPC_REG_LIST_DCN3_0(3), + MPC_OUT_MUX_REG_LIST_DCN3_0(0), + MPC_OUT_MUX_REG_LIST_DCN3_0(1), + MPC_OUT_MUX_REG_LIST_DCN3_0(2), + MPC_OUT_MUX_REG_LIST_DCN3_0(3), + MPC_MCM_REG_LIST_DCN32(0), + MPC_MCM_REG_LIST_DCN32(1), + MPC_MCM_REG_LIST_DCN32(2), + MPC_MCM_REG_LIST_DCN32(3), + MPC_DWB_MUX_REG_LIST_DCN3_0(0), +}; + +static const struct dcn30_mpc_shift mpc_shift = { + MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) +}; + +static const struct dcn30_mpc_mask mpc_mask = { + MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) +}; + +#define optc_regs(id)\ +[id] = {OPTC_COMMON_REG_LIST_DCN3_2(id)} + +static const struct dcn_optc_registers optc_regs[] = { + optc_regs(0), + optc_regs(1), + optc_regs(2), + optc_regs(3) +}; + +static const struct dcn_optc_shift optc_shift = { + OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) +}; + +static const struct dcn_optc_mask optc_mask = { + OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) +}; + +#define hubp_regs(id)\ +[id] = {\ + HUBP_REG_LIST_DCN32(id)\ +} + +static const struct dcn_hubp2_registers hubp_regs[] = { + hubp_regs(0), + hubp_regs(1), + hubp_regs(2), + hubp_regs(3) +}; + + +static const struct dcn_hubp2_shift hubp_shift = { + HUBP_MASK_SH_LIST_DCN32(__SHIFT) +}; + +static const struct dcn_hubp2_mask hubp_mask = { + HUBP_MASK_SH_LIST_DCN32(_MASK) +}; +static const struct dcn_hubbub_registers hubbub_reg = { + HUBBUB_REG_LIST_DCN32(0) +}; + +static const struct dcn_hubbub_shift hubbub_shift = { + HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) +}; + +static const struct dcn_hubbub_mask hubbub_mask = { + HUBBUB_MASK_SH_LIST_DCN32(_MASK) +}; + +static const struct dccg_registers dccg_regs = { + DCCG_REG_LIST_DCN32() +}; + +static const struct dccg_shift dccg_shift = { + DCCG_MASK_SH_LIST_DCN32(__SHIFT) +}; + +static const struct dccg_mask dccg_mask = { + DCCG_MASK_SH_LIST_DCN32(_MASK) +}; + + +#define SRII2(reg_name_pre, reg_name_post, id)\ + .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ + ## id ## _ ## reg_name_post ## _BASE_IDX) + \ + reg ## reg_name_pre ## id ## _ ## reg_name_post + + +#define HWSEQ_DCN32_REG_LIST()\ + SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ + SR(DIO_MEM_PWR_CTRL), \ + SR(ODM_MEM_PWR_CTRL3), \ + SR(MMHUBBUB_MEM_PWR_CNTL), \ + SR(DCCG_GATE_DISABLE_CNTL), \ + SR(DCCG_GATE_DISABLE_CNTL2), \ + SR(DCFCLK_CNTL),\ + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ + SRII(PIXEL_RATE_CNTL, OTG, 0), \ + SRII(PIXEL_RATE_CNTL, OTG, 1),\ + SRII(PIXEL_RATE_CNTL, OTG, 2),\ + SRII(PIXEL_RATE_CNTL, OTG, 3),\ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ + SR(MICROSECOND_TIME_BASE_DIV), \ + SR(MILLISECOND_TIME_BASE_DIV), \ + SR(DISPCLK_FREQ_CHANGE_CNTL), \ + SR(RBBMIF_TIMEOUT_DIS), \ + SR(RBBMIF_TIMEOUT_DIS_2), \ + SR(DCHUBBUB_CRC_CTRL), \ + SR(DPP_TOP0_DPP_CRC_CTRL), \ + SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ + SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ + SR(MPC_CRC_CTRL), \ + SR(MPC_CRC_RESULT_GB), \ + SR(MPC_CRC_RESULT_C), \ + SR(MPC_CRC_RESULT_AR), \ + SR(DOMAIN0_PG_CONFIG), \ + SR(DOMAIN1_PG_CONFIG), \ + SR(DOMAIN2_PG_CONFIG), \ + SR(DOMAIN3_PG_CONFIG), \ + SR(DOMAIN16_PG_CONFIG), \ + SR(DOMAIN17_PG_CONFIG), \ + SR(DOMAIN18_PG_CONFIG), \ + SR(DOMAIN19_PG_CONFIG), \ + SR(DOMAIN0_PG_STATUS), \ + SR(DOMAIN1_PG_STATUS), \ + SR(DOMAIN2_PG_STATUS), \ + SR(DOMAIN3_PG_STATUS), \ + SR(DOMAIN16_PG_STATUS), \ + SR(DOMAIN17_PG_STATUS), \ + SR(DOMAIN18_PG_STATUS), \ + SR(DOMAIN19_PG_STATUS), \ + SR(D1VGA_CONTROL), \ + SR(D2VGA_CONTROL), \ + SR(D3VGA_CONTROL), \ + SR(D4VGA_CONTROL), \ + SR(D5VGA_CONTROL), \ + SR(D6VGA_CONTROL), \ + SR(DC_IP_REQUEST_CNTL), \ + SR(AZALIA_AUDIO_DTO), \ + SR(AZALIA_CONTROLLER_CLOCK_GATING) + +static const struct dce_hwseq_registers hwseq_reg = { + HWSEQ_DCN32_REG_LIST() +}; + +#define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ + HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ + HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ + HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ + HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ + HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ + HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ + HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ + HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) + +static const struct dce_hwseq_shift hwseq_shift = { + HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) +}; + +static const struct dce_hwseq_mask hwseq_mask = { + HWSEQ_DCN32_MASK_SH_LIST(_MASK) +}; +#define vmid_regs(id)\ +[id] = {\ + DCN20_VMID_REG_LIST(id)\ +} + +static const struct dcn_vmid_registers vmid_regs[] = { + vmid_regs(0), + vmid_regs(1), + vmid_regs(2), + vmid_regs(3), + vmid_regs(4), + vmid_regs(5), + vmid_regs(6), + vmid_regs(7), + vmid_regs(8), + vmid_regs(9), + vmid_regs(10), + vmid_regs(11), + vmid_regs(12), + vmid_regs(13), + vmid_regs(14), + vmid_regs(15) +}; + +static const struct dcn20_vmid_shift vmid_shifts = { + DCN20_VMID_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn20_vmid_mask vmid_masks = { + DCN20_VMID_MASK_SH_LIST(_MASK) +}; + +static const struct resource_caps res_cap_dcn321 = { + .num_timing_generator = 4, + .num_opp = 4, + .num_video_plane = 4, + .num_audio = 5, + .num_stream_encoder = 5, + .num_hpo_dp_stream_encoder = 4, + .num_hpo_dp_link_encoder = 2, + .num_pll = 5, + .num_dwb = 1, + .num_ddc = 5, + .num_vmid = 16, + .num_mpc_3dlut = 4, + .num_dsc = 4, +}; + +static const struct dc_plane_cap plane_cap = { + .type = DC_PLANE_TYPE_DCN_UNIVERSAL, + .blends_with_above = true, + .blends_with_below = true, + .per_pixel_alpha = true, + + .pixel_format_support = { + .argb8888 = true, + .nv12 = true, + .fp16 = true, + .p010 = true, + .ayuv = false, + }, + + .max_upscale_factor = { + .argb8888 = 16000, + .nv12 = 16000, + .fp16 = 16000 + }, + + // 6:1 downscaling ratio: 1000/6 = 166.666 + .max_downscale_factor = { + .argb8888 = 167, + .nv12 = 167, + .fp16 = 167 + }, + 64, + 64 +}; + +static const struct dc_debug_options debug_defaults_drv = { + .disable_dmcu = true, + .force_abm_enable = false, + .timing_trace = false, + .clock_trace = true, + .disable_pplib_clock_request = false, + .pipe_split_policy = MPC_SPLIT_DYNAMIC, + .force_single_disp_pipe_split = false, + .disable_dcc = DCC_ENABLE, + .vsr_support = true, + .performance_trace = false, + .max_downscale_src_width = 7680,/*upto 8K*/ + .disable_pplib_wm_range = false, + .scl_reset_length10 = true, + .sanity_checks = false, + .underflow_assert_delay_us = 0xFFFFFFFF, + .dwb_fi_phase = -1, // -1 = disable, + .dmub_command_table = true, + .enable_mem_low_power = { + .bits = { + .vga = false, + .i2c = false, + .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled + .dscl = false, + .cm = false, + .mpc = false, + .optc = false, + } + }, + .use_max_lb = true, + .force_disable_subvp = true +}; + +static const struct dc_debug_options debug_defaults_diags = { + .disable_dmcu = true, + .force_abm_enable = false, + .timing_trace = true, + .clock_trace = true, + .disable_dpp_power_gate = true, + .disable_hubp_power_gate = true, + .disable_dsc_power_gate = true, + .disable_clock_gate = true, + .disable_pplib_clock_request = true, + .disable_pplib_wm_range = true, + .disable_stutter = false, + .scl_reset_length10 = true, + .dwb_fi_phase = -1, // -1 = disable + .dmub_command_table = true, + .enable_tri_buf = true, + .use_max_lb = true, + .force_disable_subvp = true +}; + + +static struct dce_aux *dcn321_aux_engine_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct aux_engine_dce110 *aux_engine = + kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); + + if (!aux_engine) + return NULL; + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, + &aux_engine_regs[inst], + &aux_mask, + &aux_shift, + ctx->dc->caps.extended_aux_timeout_support); + + return &aux_engine->base; +} +#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } + +static const struct dce_i2c_registers i2c_hw_regs[] = { + i2c_inst_regs(1), + i2c_inst_regs(2), + i2c_inst_regs(3), + i2c_inst_regs(4), + i2c_inst_regs(5), +}; + +static const struct dce_i2c_shift i2c_shifts = { + I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) +}; + +static const struct dce_i2c_mask i2c_masks = { + I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) +}; + +static struct dce_i2c_hw *dcn321_i2c_hw_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dce_i2c_hw *dce_i2c_hw = + kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); + + if (!dce_i2c_hw) + return NULL; + + dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, + &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); + + return dce_i2c_hw; +} + +static struct clock_source *dcn321_clock_source_create( + struct dc_context *ctx, + struct dc_bios *bios, + enum clock_source_id id, + const struct dce110_clk_src_regs *regs, + bool dp_clk_src) +{ + struct dce110_clk_src *clk_src = + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); + + if (!clk_src) + return NULL; + + if (dcn3_clk_src_construct(clk_src, ctx, bios, id, + regs, &cs_shift, &cs_mask)) { + clk_src->base.dp_clk_src = dp_clk_src; + return &clk_src->base; + } + + BREAK_TO_DEBUGGER(); + return NULL; +} + +static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx) +{ + int i; + + struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), + GFP_KERNEL); + + if (!hubbub2) + return NULL; + + hubbub32_construct(hubbub2, ctx, + &hubbub_reg, + &hubbub_shift, + &hubbub_mask, + ctx->dc->dml.ip.det_buffer_size_kbytes, + ctx->dc->dml.ip.pixel_chunk_size_kbytes, + ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); + + + for (i = 0; i < res_cap_dcn321.num_vmid; i++) { + struct dcn20_vmid *vmid = &hubbub2->vmid[i]; + + vmid->ctx = ctx; + + vmid->regs = &vmid_regs[i]; + vmid->shifts = &vmid_shifts; + vmid->masks = &vmid_masks; + } + + return &hubbub2->base; +} + +static struct hubp *dcn321_hubp_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn20_hubp *hubp2 = + kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); + + if (!hubp2) + return NULL; + + if (hubp32_construct(hubp2, ctx, inst, + &hubp_regs[inst], &hubp_shift, &hubp_mask)) + return &hubp2->base; + + BREAK_TO_DEBUGGER(); + kfree(hubp2); + return NULL; +} + +static void dcn321_dpp_destroy(struct dpp **dpp) +{ + kfree(TO_DCN30_DPP(*dpp)); + *dpp = NULL; +} + +static struct dpp *dcn321_dpp_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn3_dpp *dpp3 = + kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); + + if (!dpp3) + return NULL; + + if (dpp32_construct(dpp3, ctx, inst, + &dpp_regs[inst], &tf_shift, &tf_mask)) + return &dpp3->base; + + BREAK_TO_DEBUGGER(); + kfree(dpp3); + return NULL; +} + +static struct mpc *dcn321_mpc_create( + struct dc_context *ctx, + int num_mpcc, + int num_rmu) +{ + struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), + GFP_KERNEL); + + if (!mpc30) + return NULL; + + dcn32_mpc_construct(mpc30, ctx, + &mpc_regs, + &mpc_shift, + &mpc_mask, + num_mpcc, + num_rmu); + + return &mpc30->base; +} + +static struct output_pixel_processor *dcn321_opp_create( + struct dc_context *ctx, uint32_t inst) +{ + struct dcn20_opp *opp2 = + kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); + + if (!opp2) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dcn20_opp_construct(opp2, ctx, inst, + &opp_regs[inst], &opp_shift, &opp_mask); + return &opp2->base; +} + + +static struct timing_generator *dcn321_timing_generator_create( + struct dc_context *ctx, + uint32_t instance) +{ + struct optc *tgn10 = + kzalloc(sizeof(struct optc), GFP_KERNEL); + + if (!tgn10) + return NULL; + + tgn10->base.inst = instance; + tgn10->base.ctx = ctx; + + tgn10->tg_regs = &optc_regs[instance]; + tgn10->tg_shift = &optc_shift; + tgn10->tg_mask = &optc_mask; + + dcn32_timing_generator_init(tgn10); + + return &tgn10->base; +} + +static const struct encoder_feature_support link_enc_feature = { + .max_hdmi_deep_color = COLOR_DEPTH_121212, + .max_hdmi_pixel_clock = 600000, + .hdmi_ycbcr420_supported = true, + .dp_ycbcr420_supported = true, + .fec_supported = true, + .flags.bits.IS_HBR2_CAPABLE = true, + .flags.bits.IS_HBR3_CAPABLE = true, + .flags.bits.IS_TPS3_CAPABLE = true, + .flags.bits.IS_TPS4_CAPABLE = true +}; + +static struct link_encoder *dcn321_link_encoder_create( + const struct encoder_init_data *enc_init_data) +{ + struct dcn20_link_encoder *enc20 = + kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); + + if (!enc20) + return NULL; + + dcn32_link_encoder_construct(enc20, + enc_init_data, + &link_enc_feature, + &link_enc_regs[enc_init_data->transmitter], + &link_enc_aux_regs[enc_init_data->channel - 1], + &link_enc_hpd_regs[enc_init_data->hpd_source], + &le_shift, + &le_mask); + + return &enc20->enc10.base; +} + +static void read_dce_straps( + struct dc_context *ctx, + struct resource_straps *straps) +{ + generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), + FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); + +} + +static struct audio *dcn321_create_audio( + struct dc_context *ctx, unsigned int inst) +{ + return dce_audio_create(ctx, inst, + &audio_regs[inst], &audio_shift, &audio_mask); +} + +static struct vpg *dcn321_vpg_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); + + if (!vpg3) + return NULL; + + vpg3_construct(vpg3, ctx, inst, + &vpg_regs[inst], + &vpg_shift, + &vpg_mask); + + return &vpg3->base; +} + +static struct afmt *dcn321_afmt_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); + + if (!afmt3) + return NULL; + + afmt3_construct(afmt3, ctx, inst, + &afmt_regs[inst], + &afmt_shift, + &afmt_mask); + + return &afmt3->base; +} + +static struct apg *dcn321_apg_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); + + if (!apg31) + return NULL; + + apg31_construct(apg31, ctx, inst, + &apg_regs[inst], + &apg_shift, + &apg_mask); + + return &apg31->base; +} + +static struct stream_encoder *dcn321_stream_encoder_create( + enum engine_id eng_id, + struct dc_context *ctx) +{ + struct dcn10_stream_encoder *enc1; + struct vpg *vpg; + struct afmt *afmt; + int vpg_inst; + int afmt_inst; + + /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ + if (eng_id <= ENGINE_ID_DIGF) { + vpg_inst = eng_id; + afmt_inst = eng_id; + } else + return NULL; + + enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); + vpg = dcn321_vpg_create(ctx, vpg_inst); + afmt = dcn321_afmt_create(ctx, afmt_inst); + + if (!enc1 || !vpg || !afmt) { + kfree(enc1); + kfree(vpg); + kfree(afmt); + return NULL; + } + + dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, + eng_id, vpg, afmt, + &stream_enc_regs[eng_id], + &se_shift, &se_mask); + + return &enc1->base; +} + +static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create( + enum engine_id eng_id, + struct dc_context *ctx) +{ + struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; + struct vpg *vpg; + struct apg *apg; + uint32_t hpo_dp_inst; + uint32_t vpg_inst; + uint32_t apg_inst; + + ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); + hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; + + /* Mapping of VPG register blocks to HPO DP block instance: + * VPG[6] -> HPO_DP[0] + * VPG[7] -> HPO_DP[1] + * VPG[8] -> HPO_DP[2] + * VPG[9] -> HPO_DP[3] + */ + vpg_inst = hpo_dp_inst + 6; + + /* Mapping of APG register blocks to HPO DP block instance: + * APG[0] -> HPO_DP[0] + * APG[1] -> HPO_DP[1] + * APG[2] -> HPO_DP[2] + * APG[3] -> HPO_DP[3] + */ + apg_inst = hpo_dp_inst; + + /* allocate HPO stream encoder and create VPG sub-block */ + hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); + vpg = dcn321_vpg_create(ctx, vpg_inst); + apg = dcn321_apg_create(ctx, apg_inst); + + if (!hpo_dp_enc31 || !vpg || !apg) { + kfree(hpo_dp_enc31); + kfree(vpg); + kfree(apg); + return NULL; + } + + dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, + hpo_dp_inst, eng_id, vpg, apg, + &hpo_dp_stream_enc_regs[hpo_dp_inst], + &hpo_dp_se_shift, &hpo_dp_se_mask); + + return &hpo_dp_enc31->base; +} + +static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create( + uint8_t inst, + struct dc_context *ctx) +{ + struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; + + /* allocate HPO link encoder */ + hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); + + hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, + &hpo_dp_link_enc_regs[inst], + &hpo_dp_le_shift, &hpo_dp_le_mask); + + return &hpo_dp_enc31->base; +} + +static struct dce_hwseq *dcn321_hwseq_create( + struct dc_context *ctx) +{ + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); + + if (hws) { + hws->ctx = ctx; + hws->regs = &hwseq_reg; + hws->shifts = &hwseq_shift; + hws->masks = &hwseq_mask; + } + return hws; +} +static const struct resource_create_funcs res_create_funcs = { + .read_dce_straps = read_dce_straps, + .create_audio = dcn321_create_audio, + .create_stream_encoder = dcn321_stream_encoder_create, + .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, + .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, + .create_hwseq = dcn321_hwseq_create, +}; + +static const struct resource_create_funcs res_create_maximus_funcs = { + .read_dce_straps = NULL, + .create_audio = NULL, + .create_stream_encoder = NULL, + .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, + .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, + .create_hwseq = dcn321_hwseq_create, +}; + +static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) +{ + unsigned int i; + + for (i = 0; i < pool->base.stream_enc_count; i++) { + if (pool->base.stream_enc[i] != NULL) { + if (pool->base.stream_enc[i]->vpg != NULL) { + kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); + pool->base.stream_enc[i]->vpg = NULL; + } + if (pool->base.stream_enc[i]->afmt != NULL) { + kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); + pool->base.stream_enc[i]->afmt = NULL; + } + kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); + pool->base.stream_enc[i] = NULL; + } + } + + for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { + if (pool->base.hpo_dp_stream_enc[i] != NULL) { + if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { + kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); + pool->base.hpo_dp_stream_enc[i]->vpg = NULL; + } + if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { + kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); + pool->base.hpo_dp_stream_enc[i]->apg = NULL; + } + kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); + pool->base.hpo_dp_stream_enc[i] = NULL; + } + } + + for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { + if (pool->base.hpo_dp_link_enc[i] != NULL) { + kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); + pool->base.hpo_dp_link_enc[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + if (pool->base.dscs[i] != NULL) + dcn20_dsc_destroy(&pool->base.dscs[i]); + } + + if (pool->base.mpc != NULL) { + kfree(TO_DCN20_MPC(pool->base.mpc)); + pool->base.mpc = NULL; + } + if (pool->base.hubbub != NULL) { + kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); + pool->base.hubbub = NULL; + } + for (i = 0; i < pool->base.pipe_count; i++) { + if (pool->base.dpps[i] != NULL) + dcn321_dpp_destroy(&pool->base.dpps[i]); + + if (pool->base.ipps[i] != NULL) + pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); + + if (pool->base.hubps[i] != NULL) { + kfree(TO_DCN20_HUBP(pool->base.hubps[i])); + pool->base.hubps[i] = NULL; + } + + if (pool->base.irqs != NULL) { + dal_irq_service_destroy(&pool->base.irqs); + } + } + + for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + if (pool->base.engines[i] != NULL) + dce110_engine_destroy(&pool->base.engines[i]); + if (pool->base.hw_i2cs[i] != NULL) { + kfree(pool->base.hw_i2cs[i]); + pool->base.hw_i2cs[i] = NULL; + } + if (pool->base.sw_i2cs[i] != NULL) { + kfree(pool->base.sw_i2cs[i]); + pool->base.sw_i2cs[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_opp; i++) { + if (pool->base.opps[i] != NULL) + pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); + } + + for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + if (pool->base.timing_generators[i] != NULL) { + kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); + pool->base.timing_generators[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + if (pool->base.dwbc[i] != NULL) { + kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); + pool->base.dwbc[i] = NULL; + } + if (pool->base.mcif_wb[i] != NULL) { + kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); + pool->base.mcif_wb[i] = NULL; + } + } + + for (i = 0; i < pool->base.audio_count; i++) { + if (pool->base.audios[i]) + dce_aud_destroy(&pool->base.audios[i]); + } + + for (i = 0; i < pool->base.clk_src_count; i++) { + if (pool->base.clock_sources[i] != NULL) { + dcn20_clock_source_destroy(&pool->base.clock_sources[i]); + pool->base.clock_sources[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + if (pool->base.mpc_lut[i] != NULL) { + dc_3dlut_func_release(pool->base.mpc_lut[i]); + pool->base.mpc_lut[i] = NULL; + } + if (pool->base.mpc_shaper[i] != NULL) { + dc_transfer_func_release(pool->base.mpc_shaper[i]); + pool->base.mpc_shaper[i] = NULL; + } + } + + if (pool->base.dp_clock_source != NULL) { + dcn20_clock_source_destroy(&pool->base.dp_clock_source); + pool->base.dp_clock_source = NULL; + } + + for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + if (pool->base.multiple_abms[i] != NULL) + dce_abm_destroy(&pool->base.multiple_abms[i]); + } + + if (pool->base.psr != NULL) + dmub_psr_destroy(&pool->base.psr); + + if (pool->base.dccg != NULL) + dcn_dccg_destroy(&pool->base.dccg); + + if (pool->base.oem_device != NULL) + dal_ddc_service_destroy(&pool->base.oem_device); +} + + +static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) +{ + int i; + uint32_t dwb_count = pool->res_cap->num_dwb; + + for (i = 0; i < dwb_count; i++) { + struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), + GFP_KERNEL); + + if (!dwbc30) { + dm_error("DC: failed to create dwbc30!\n"); + return false; + } + + dcn30_dwbc_construct(dwbc30, ctx, + &dwbc30_regs[i], + &dwbc30_shift, + &dwbc30_mask, + i); + + pool->dwbc[i] = &dwbc30->base; + } + return true; +} + +static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) +{ + int i; + uint32_t dwb_count = pool->res_cap->num_dwb; + + for (i = 0; i < dwb_count; i++) { + struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), + GFP_KERNEL); + + if (!mcif_wb30) { + dm_error("DC: failed to create mcif_wb30!\n"); + return false; + } + + dcn32_mmhubbub_construct(mcif_wb30, ctx, + &mcif_wb30_regs[i], + &mcif_wb30_shift, + &mcif_wb30_mask, + i); + + pool->mcif_wb[i] = &mcif_wb30->base; + } + return true; +} + +static struct display_stream_compressor *dcn321_dsc_create( + struct dc_context *ctx, uint32_t inst) +{ + struct dcn20_dsc *dsc = + kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); + + if (!dsc) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); + return &dsc->base; +} + +static void dcn321_destroy_resource_pool(struct resource_pool **pool) +{ + struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool); + + dcn321_resource_destruct(dcn321_pool); + kfree(dcn321_pool); + *pool = NULL; +} + +static struct dc_cap_funcs cap_funcs = { + .get_dcc_compression_cap = dcn20_get_dcc_compression_cap +}; + + +static void dcn321_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, + unsigned int *optimal_dcfclk, + unsigned int *optimal_fclk) +{ + double bw_from_dram, bw_from_dram1, bw_from_dram2; + + bw_from_dram1 = uclk_mts * dcn3_21_soc.num_chans * + dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_dram_bw_use_normal_percent / 100); + bw_from_dram2 = uclk_mts * dcn3_21_soc.num_chans * + dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100); + + bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; + + if (optimal_fclk) + *optimal_fclk = bw_from_dram / + (dcn3_21_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100)); + + if (optimal_dcfclk) + *optimal_dcfclk = bw_from_dram / + (dcn3_21_soc.return_bus_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100)); +} + +/* dcn321_update_bw_bounding_box + * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet + * with actual values as per dGPU SKU: + * -with passed few options from dc->config + * -with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might need to get it from PM FW) + * -with passed latency values (passed in ns units) in dc-> bb override for debugging purposes + * -with passed latencies from VBIOS (in 100_ns units) if available for certain dGPU SKU + * -with number of DRAM channels from VBIOS (which differ for certain dGPU SKU of the same ASIC) + * -clocks levels with passed clk_table entries from Clk Mgr as reported by PM FW for different + * clocks (which might differ for certain dGPU SKU of the same ASIC) + */ +static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) +{ + if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + /* Overrides from dc->config options */ + dcn3_21_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk; + + /* Override from passed dc->bb_overrides if available*/ + if ((int)(dcn3_21_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns + && dc->bb_overrides.sr_exit_time_ns) { + dcn3_21_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; + } + + if ((int)(dcn3_21_soc.sr_enter_plus_exit_time_us * 1000) + != dc->bb_overrides.sr_enter_plus_exit_time_ns + && dc->bb_overrides.sr_enter_plus_exit_time_ns) { + dcn3_21_soc.sr_enter_plus_exit_time_us = + dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; + } + + if ((int)(dcn3_21_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns + && dc->bb_overrides.urgent_latency_ns) { + dcn3_21_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; + } + + if ((int)(dcn3_21_soc.dram_clock_change_latency_us * 1000) + != dc->bb_overrides.dram_clock_change_latency_ns + && dc->bb_overrides.dram_clock_change_latency_ns) { + dcn3_21_soc.dram_clock_change_latency_us = + dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; + } + + if ((int)(dcn3_21_soc.dummy_pstate_latency_us * 1000) + != dc->bb_overrides.dummy_clock_change_latency_ns + && dc->bb_overrides.dummy_clock_change_latency_ns) { + dcn3_21_soc.dummy_pstate_latency_us = + dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0; + } + + /* Override from VBIOS if VBIOS bb_info available */ + if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { + struct bp_soc_bb_info bb_info = {0}; + + if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { + if (bb_info.dram_clock_change_latency_100ns > 0) + dcn3_21_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; + + if (bb_info.dram_sr_enter_exit_latency_100ns > 0) + dcn3_21_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10; + + if (bb_info.dram_sr_exit_latency_100ns > 0) + dcn3_21_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10; + } + } + + /* Override from VBIOS for num_chan */ + if (dc->ctx->dc_bios->vram_info.num_chans) + dcn3_21_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; + + if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) + dcn3_21_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; + + } + + /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */ + dcn3_21_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; + dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; + + /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */ + if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) { + unsigned int i = 0, j = 0, num_states = 0; + + unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; + unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; + unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; + unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; + + unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564}; + unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; + unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; + + for (i = 0; i < MAX_NUM_DPM_LVL; i++) { + if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) + max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; + if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) + max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; + if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) + max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; + if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) + max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; + } + if (!max_dcfclk_mhz) + max_dcfclk_mhz = dcn3_21_soc.clock_limits[0].dcfclk_mhz; + if (!max_dispclk_mhz) + max_dispclk_mhz = dcn3_21_soc.clock_limits[0].dispclk_mhz; + if (!max_dppclk_mhz) + max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz; + if (!max_phyclk_mhz) + max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz; + + if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { + // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array + dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; + num_dcfclk_sta_targets++; + } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { + // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates + for (i = 0; i < num_dcfclk_sta_targets; i++) { + if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { + dcfclk_sta_targets[i] = max_dcfclk_mhz; + break; + } + } + // Update size of array since we "removed" duplicates + num_dcfclk_sta_targets = i + 1; + } + + num_uclk_states = bw_params->clk_table.num_entries; + + // Calculate optimal dcfclk for each uclk + for (i = 0; i < num_uclk_states; i++) { + dcn321_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, + &optimal_dcfclk_for_uclk[i], NULL); + if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { + optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; + } + } + + // Calculate optimal uclk for each dcfclk sta target + for (i = 0; i < num_dcfclk_sta_targets; i++) { + for (j = 0; j < num_uclk_states; j++) { + if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { + optimal_uclk_for_dcfclk_sta_targets[i] = + bw_params->clk_table.entries[j].memclk_mhz * 16; + break; + } + } + } + + i = 0; + j = 0; + // create the final dcfclk and uclk table + while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { + if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { + dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; + dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; + } else { + if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { + dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; + dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; + } else { + j = num_uclk_states; + } + } + } + + while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { + dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; + dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; + } + + while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && + optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { + dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; + dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; + } + + dcn3_21_soc.num_states = num_states; + for (i = 0; i < dcn3_21_soc.num_states; i++) { + dcn3_21_soc.clock_limits[i].state = i; + dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; + dcn3_21_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; + dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; + + /* Fill all states with max values of all these clocks */ + dcn3_21_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; + dcn3_21_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; + dcn3_21_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; + dcn3_21_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3; + + /* Populate from bw_params for DTBCLK, SOCCLK */ + if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0) + dcn3_21_soc.clock_limits[i].dtbclk_mhz = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz; + else + dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; + + if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) + dcn3_21_soc.clock_limits[i].socclk_mhz = dcn3_21_soc.clock_limits[i-1].socclk_mhz; + else + dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; + + /* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */ + /* PHYCLK_D18, PHYCLK_D32 */ + dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz; + dcn3_21_soc.clock_limits[i].phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz; + } + + /* Re-init DML with updated bb */ + dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); + if (dc->current_state) + dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); + } +} + +static struct resource_funcs dcn321_res_pool_funcs = { + .destroy = dcn321_destroy_resource_pool, + .link_enc_create = dcn321_link_encoder_create, + .link_enc_create_minimal = NULL, + .panel_cntl_create = dcn32_panel_cntl_create, + .validate_bandwidth = dcn32_validate_bandwidth, + .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, + .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, + .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, + .add_stream_to_ctx = dcn30_add_stream_to_ctx, + .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, + .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, + .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, + .set_mcif_arb_params = dcn30_set_mcif_arb_params, + .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, + .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, + .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, + .update_bw_bounding_box = dcn321_update_bw_bounding_box, + .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, + .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, + .add_phantom_pipes = dcn32_add_phantom_pipes, + .remove_phantom_pipes = dcn32_remove_phantom_pipes, +}; + + +static bool dcn321_resource_construct( + uint8_t num_virtual_links, + struct dc *dc, + struct dcn321_resource_pool *pool) +{ + int i, j; + struct dc_context *ctx = dc->ctx; + struct irq_service_init_data init_data; + struct ddc_service_init_data ddc_init_data = {0}; + uint32_t pipe_fuses = 0; + uint32_t num_pipes = 4; + + ctx->dc_bios->regs = &bios_regs; + + pool->base.res_cap = &res_cap_dcn321; + /* max number of pipes for ASIC before checking for pipe fuses */ + num_pipes = pool->base.res_cap->num_timing_generator; + pipe_fuses = REG_READ(CC_DC_PIPE_DIS); + + for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) + if (pipe_fuses & 1 << i) + num_pipes--; + + if (pipe_fuses & 1) + ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! + + if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) + ASSERT(0); //Entire DCN is harvested! + + /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the + * value will be changed, update max_num_dpp and max_num_otg for dml. + */ + dcn3_21_ip.max_num_dpp = num_pipes; + dcn3_21_ip.max_num_otg = num_pipes; + + pool->base.funcs = &dcn321_res_pool_funcs; + + /************************************************* + * Resource + asic cap harcoding * + *************************************************/ + pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; + pool->base.timing_generator_count = num_pipes; + pool->base.pipe_count = num_pipes; + pool->base.mpcc_count = num_pipes; + dc->caps.max_downscale_ratio = 600; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ + dc->caps.max_cursor_size = 256; + dc->caps.min_horizontal_blanking_period = 80; + dc->caps.dmdata_alloc_size = 2048; + dc->caps.mall_size_per_mem_channel = 0; + dc->caps.mall_size_total = 0; + dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; + dc->caps.cache_line_size = 64; + dc->caps.cache_num_ways = 16; + dc->caps.max_cab_allocation_bytes = 33554432; // 32MB = 1024 * 1024 * 32 + dc->caps.subvp_fw_processing_delay_us = 15; + dc->caps.subvp_prefetch_end_to_mall_start_us = 15; + dc->caps.subvp_pstate_allow_width_us = 20; + + dc->caps.max_slave_planes = 1; + dc->caps.max_slave_yuv_planes = 1; + dc->caps.max_slave_rgb_planes = 1; + dc->caps.post_blend_color_processing = true; + dc->caps.force_dp_tps4_for_cp2520 = true; + dc->caps.dp_hpo = true; + dc->caps.edp_dsc_support = true; + dc->caps.extended_aux_timeout_support = true; + dc->caps.dmcub_support = true; + + /* Color pipeline capabilities */ + dc->caps.color.dpp.dcn_arch = 1; + dc->caps.color.dpp.input_lut_shared = 0; + dc->caps.color.dpp.icsc = 1; + dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr + dc->caps.color.dpp.dgam_rom_caps.srgb = 1; + dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; + dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; + dc->caps.color.dpp.dgam_rom_caps.pq = 1; + dc->caps.color.dpp.dgam_rom_caps.hlg = 1; + dc->caps.color.dpp.post_csc = 1; + dc->caps.color.dpp.gamma_corr = 1; + dc->caps.color.dpp.dgam_rom_for_yuv = 0; + + dc->caps.color.dpp.hw_3d_lut = 0; //3DLUT removed from DPP + dc->caps.color.dpp.ogam_ram = 0; //Blnd Gam also removed + // no OGAM ROM on DCN2 and later ASICs + dc->caps.color.dpp.ogam_rom_caps.srgb = 0; + dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; + dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; + dc->caps.color.dpp.ogam_rom_caps.pq = 0; + dc->caps.color.dpp.ogam_rom_caps.hlg = 0; + dc->caps.color.dpp.ocsc = 0; + + dc->caps.color.mpc.gamut_remap = 1; + dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC + dc->caps.color.mpc.ogam_ram = 1; + dc->caps.color.mpc.ogam_rom_caps.srgb = 0; + dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; + dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; + dc->caps.color.mpc.ogam_rom_caps.pq = 0; + dc->caps.color.mpc.ogam_rom_caps.hlg = 0; + dc->caps.color.mpc.ocsc = 1; + + /* read VBIOS LTTPR caps */ + { + if (ctx->dc_bios->funcs->get_lttpr_caps) { + enum bp_result bp_query_result; + uint8_t is_vbios_lttpr_enable = 0; + + bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); + dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; + } + + /* interop bit is implicit */ + { + dc->caps.vbios_lttpr_aware = true; + } + } + + if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) + dc->debug = debug_defaults_drv; + else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { + dc->debug = debug_defaults_diags; + } else + dc->debug = debug_defaults_diags; + // Init the vm_helper + if (dc->vm_helper) + vm_helper_init(dc->vm_helper, 16); + + /************************************************* + * Create resources * + *************************************************/ + + /* Clock Sources for Pixel Clock*/ + pool->base.clock_sources[DCN321_CLK_SRC_PLL0] = + dcn321_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL0, + &clk_src_regs[0], false); + pool->base.clock_sources[DCN321_CLK_SRC_PLL1] = + dcn321_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL1, + &clk_src_regs[1], false); + pool->base.clock_sources[DCN321_CLK_SRC_PLL2] = + dcn321_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL2, + &clk_src_regs[2], false); + pool->base.clock_sources[DCN321_CLK_SRC_PLL3] = + dcn321_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL3, + &clk_src_regs[3], false); + pool->base.clock_sources[DCN321_CLK_SRC_PLL4] = + dcn321_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL4, + &clk_src_regs[4], false); + + pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL; + + /* todo: not reuse phy_pll registers */ + pool->base.dp_clock_source = + dcn321_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_ID_DP_DTO, + &clk_src_regs[0], true); + + for (i = 0; i < pool->base.clk_src_count; i++) { + if (pool->base.clock_sources[i] == NULL) { + dm_error("DC: failed to create clock sources!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + } + + /* DCCG */ + pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); + if (pool->base.dccg == NULL) { + dm_error("DC: failed to create dccg!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + + /* DML */ + if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) + dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); + + /* IRQ Service */ + init_data.ctx = dc->ctx; + pool->base.irqs = dal_irq_service_dcn32_create(&init_data); + if (!pool->base.irqs) + goto create_fail; + + /* HUBBUB */ + pool->base.hubbub = dcn321_hubbub_create(ctx); + if (pool->base.hubbub == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create hubbub!\n"); + goto create_fail; + } + + /* HUBPs, DPPs, OPPs, TGs, ABMs */ + for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { + + /* if pipe is disabled, skip instance of HW pipe, + * i.e, skip ASIC register instance + */ + if (pipe_fuses & 1 << i) + continue; + + pool->base.hubps[j] = dcn321_hubp_create(ctx, i); + if (pool->base.hubps[j] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create hubps!\n"); + goto create_fail; + } + + pool->base.dpps[j] = dcn321_dpp_create(ctx, i); + if (pool->base.dpps[j] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create dpps!\n"); + goto create_fail; + } + + pool->base.opps[j] = dcn321_opp_create(ctx, i); + if (pool->base.opps[j] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create output pixel processor!\n"); + goto create_fail; + } + + pool->base.timing_generators[j] = dcn321_timing_generator_create( + ctx, i); + if (pool->base.timing_generators[j] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create tg!\n"); + goto create_fail; + } + + pool->base.multiple_abms[j] = dmub_abm_create(ctx, + &abm_regs[i], + &abm_shift, + &abm_mask); + if (pool->base.multiple_abms[j] == NULL) { + dm_error("DC: failed to create abm for pipe %d!\n", i); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + + /* index for resource pool arrays for next valid pipe */ + j++; + } + + /* PSR */ + pool->base.psr = dmub_psr_create(ctx); + if (pool->base.psr == NULL) { + dm_error("DC: failed to create psr obj!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + + /* MPCCs */ + pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); + if (pool->base.mpc == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create mpc!\n"); + goto create_fail; + } + + /* DSCs */ + for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + pool->base.dscs[i] = dcn321_dsc_create(ctx, i); + if (pool->base.dscs[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create display stream compressor %d!\n", i); + goto create_fail; + } + } + + /* DWB */ + if (!dcn321_dwbc_create(ctx, &pool->base)) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create dwbc!\n"); + goto create_fail; + } + + /* MMHUBBUB */ + if (!dcn321_mmhubbub_create(ctx, &pool->base)) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create mcif_wb!\n"); + goto create_fail; + } + + /* AUX and I2C */ + for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + pool->base.engines[i] = dcn321_aux_engine_create(ctx, i); + if (pool->base.engines[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC:failed to create aux engine!!\n"); + goto create_fail; + } + pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i); + if (pool->base.hw_i2cs[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC:failed to create hw i2c!!\n"); + goto create_fail; + } + pool->base.sw_i2cs[i] = NULL; + } + + /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ + if (!resource_construct(num_virtual_links, dc, &pool->base, + (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? + &res_create_funcs : &res_create_maximus_funcs))) + goto create_fail; + + /* HW Sequencer init functions and Plane caps */ + dcn32_hw_sequencer_init_functions(dc); + + dc->caps.max_planes = pool->base.pipe_count; + + for (i = 0; i < dc->caps.max_planes; ++i) + dc->caps.planes[i] = plane_cap; + + dc->cap_funcs = cap_funcs; + + if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { + ddc_init_data.ctx = dc->ctx; + ddc_init_data.link = NULL; + ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; + ddc_init_data.id.enum_id = 0; + ddc_init_data.id.type = OBJECT_TYPE_GENERIC; + pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); + } else { + pool->base.oem_device = NULL; + } + + return true; + +create_fail: + + dcn321_resource_destruct(pool); + + return false; +} + +struct resource_pool *dcn321_create_resource_pool( + const struct dc_init_data *init_data, + struct dc *dc) +{ + struct dcn321_resource_pool *pool = + kzalloc(sizeof(struct dcn321_resource_pool), GFP_KERNEL); + + if (!pool) + return NULL; + + if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool)) + return &pool->base; + + BREAK_TO_DEBUGGER(); + kfree(pool); + return NULL; +} diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index b5570aa8e39d..4dd461e6c14b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -125,6 +125,7 @@ struct nv_wm_range_entry { double pstate_latency_us; double sr_exit_time_us; double sr_enter_plus_exit_time_us; + double fclk_change_latency_us; } dml_input; }; @@ -142,6 +143,7 @@ struct clk_state_registers_and_bypass { uint32_t dprefclk; uint32_t dispclk; uint32_t dppclk; + uint32_t dtbclk; uint32_t dppclk_bypass; uint32_t dcfclk_bypass; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h index 1391c20f1852..68c2ed434d2c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h @@ -112,9 +112,10 @@ enum dentist_divider_range { CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \ CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0) -// TODO: #define CLK_REG_LIST_DCN3() \ - SR(DENTIST_DISPCLK_CNTL) + CLK_COMMON_REG_LIST_DCN_BASE(), \ + CLK_SRI(CLK0_CLK_PLL_REQ, CLK02, 0), \ + CLK_SRI(CLK0_CLK2_DFS_CNTL, CLK02, 0) #define CLK_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -155,6 +156,34 @@ enum dentist_divider_range { CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh),\ CLK_SF(CLK4_0_CLK4_CLK_PLL_REQ, FbMult_int, mask_sh) +#define CLK_REG_LIST_DCN32() \ + SR(DENTIST_DISPCLK_CNTL), \ + CLK_SR_DCN32(CLK1_CLK_PLL_REQ), \ + CLK_SR_DCN32(CLK1_CLK0_DFS_CNTL), \ + CLK_SR_DCN32(CLK1_CLK1_DFS_CNTL), \ + CLK_SR_DCN32(CLK1_CLK2_DFS_CNTL), \ + CLK_SR_DCN32(CLK1_CLK3_DFS_CNTL), \ + CLK_SR_DCN32(CLK1_CLK4_DFS_CNTL) + +#define CLK_COMMON_MASK_SH_LIST_DCN32(mask_sh) \ + CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\ + CLK_SF(CLK1_CLK_PLL_REQ, FbMult_int, mask_sh),\ + CLK_SF(CLK1_CLK_PLL_REQ, FbMult_frac, mask_sh) + +#define CLK_REG_LIST_DCN321() \ + SR(DENTIST_DISPCLK_CNTL), \ + CLK_SR_DCN321(CLK0_CLK_PLL_REQ, CLK01, 0), \ + CLK_SR_DCN321(CLK0_CLK0_DFS_CNTL, CLK01, 0), \ + CLK_SR_DCN321(CLK0_CLK1_DFS_CNTL, CLK01, 0), \ + CLK_SR_DCN321(CLK0_CLK2_DFS_CNTL, CLK01, 0), \ + CLK_SR_DCN321(CLK0_CLK3_DFS_CNTL, CLK01, 0), \ + CLK_SR_DCN321(CLK0_CLK4_DFS_CNTL, CLK01, 0) + +#define CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh) \ + CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\ + CLK_SF(CLK0_CLK_PLL_REQ, FbMult_int, mask_sh),\ + CLK_SF(CLK0_CLK_PLL_REQ, FbMult_frac, mask_sh) + #define CLK_REG_FIELD_LIST(type) \ type DPREFCLK_SRC_SEL; \ type DENTIST_DPREFCLK_WDIVIDER; \ @@ -199,6 +228,18 @@ struct clk_mgr_registers { uint32_t CLK0_CLK2_DFS_CNTL; uint32_t CLK0_CLK_PLL_REQ; + uint32_t CLK1_CLK_PLL_REQ; + uint32_t CLK1_CLK0_DFS_CNTL; + uint32_t CLK1_CLK1_DFS_CNTL; + uint32_t CLK1_CLK2_DFS_CNTL; + uint32_t CLK1_CLK3_DFS_CNTL; + uint32_t CLK1_CLK4_DFS_CNTL; + + uint32_t CLK0_CLK0_DFS_CNTL; + uint32_t CLK0_CLK1_DFS_CNTL; + uint32_t CLK0_CLK3_DFS_CNTL; + uint32_t CLK0_CLK4_DFS_CNTL; + uint32_t MP1_SMN_C2PMSG_67; uint32_t MP1_SMN_C2PMSG_83; uint32_t MP1_SMN_C2PMSG_91; -- cgit v1.2.3 From 235c67634230b0f9ad8c0185272fed36c892b1c4 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Wed, 23 Feb 2022 17:46:31 -0500 Subject: drm/amd/display: add DCN32/321 specific files for Display Core Add core DC support for DCN 3.2.x. v2: squash in fixup (Alex) Signed-off-by: Aurabindo Pillai Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/Makefile | 37 + drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 299 ++ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h | 155 + .../amd/display/dc/dcn32/dcn32_dio_link_encoder.c | 283 ++ .../amd/display/dc/dcn32/dcn32_dio_link_encoder.h | 42 + .../display/dc/dcn32/dcn32_dio_stream_encoder.c | 427 +++ .../display/dc/dcn32/dcn32_dio_stream_encoder.h | 254 ++ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c | 164 + drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h | 38 + .../display/dc/dcn32/dcn32_hpo_dp_link_encoder.c | 90 + .../display/dc/dcn32/dcn32_hpo_dp_link_encoder.h | 63 + .../gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c | 964 +++++ .../gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h | 172 + drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c | 148 + drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h | 69 + drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 891 +++++ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h | 64 + drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 155 + drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.h | 33 + .../gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c | 239 ++ .../gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h | 225 ++ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c | 810 ++++ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h | 213 ++ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c | 236 ++ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h | 253 ++ .../gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 3976 ++++++++++++++++++++ .../gpu/drm/amd/display/dc/dcn32/dcn32_resource.h | 88 + drivers/gpu/drm/amd/display/dc/dcn321/Makefile | 34 + .../drm/amd/display/dc/dcn321/dcn321_resource.c | 32 +- .../drm/amd/display/dc/dcn321/dcn321_resource.h | 42 + 30 files changed, 10478 insertions(+), 18 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/Makefile create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.c create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.h create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.h create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h create mode 100644 drivers/gpu/drm/amd/display/dc/dcn321/Makefile create mode 100644 drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.h diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/Makefile b/drivers/gpu/drm/amd/display/dc/dcn32/Makefile new file mode 100644 index 000000000000..6e0328060255 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/Makefile @@ -0,0 +1,37 @@ +# +# (c) Copyright 2022 Advanced Micro Devices, Inc. All the rights reserved +# +# All rights reserved. This notice is intended as a precaution against +# inadvertent publication and does not imply publication or any waiver +# of confidentiality. The year included in the foregoing notice is the +# year of creation of the work. +# +# Authors: AMD +# +# Makefile for dcn32. + +DCN32 = dcn32_resource.o dcn32_hubbub.o dcn32_hwseq.o dcn32_init.o \ + dcn32_dccg.o dcn32_optc.o dcn32_mmhubbub.o dcn32_hubp.o dcn32_dpp.o \ + dcn32_dio_stream_encoder.o dcn32_dio_link_encoder.o dcn32_hpo_dp_link_encoder.o \ + dcn32_mpc.o + +CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o := -mhard-float -msse + +ifdef CONFIG_CC_IS_GCC +ifeq ($(call cc-ifversion, -lt, 0701, y), y) +IS_OLD_GCC = 1 +endif +endif + +ifdef IS_OLD_GCC +# Stack alignment mismatch, proceed with caution. +# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 +# (8B stack alignment). +CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o += -mpreferred-stack-boundary=4 +else +CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o += -msse2 +endif + +AMD_DAL_DCN32 = $(addprefix $(AMDDALPATH)/dc/dcn32/,$(DCN32)) + +AMD_DISPLAY_FILES += $(AMD_DAL_DCN32) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c new file mode 100644 index 000000000000..12633561be3f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c @@ -0,0 +1,299 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "reg_helper.h" +#include "core_types.h" +#include "dcn32_dccg.h" + +#define TO_DCN_DCCG(dccg)\ + container_of(dccg, struct dcn_dccg, base) + +#define REG(reg) \ + (dccg_dcn->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name + +#define CTX \ + dccg_dcn->base.ctx +#define DC_LOGGER \ + dccg->ctx->logger + +enum pixel_rate_div { + PIXEL_RATE_DIV_BY_1 = 0, + PIXEL_RATE_DIV_BY_2 = 1, + PIXEL_RATE_DIV_BY_4 = 3 +}; + +static void dccg32_set_pixel_rate_div( + struct dccg *dccg, + uint32_t otg_inst, + enum pixel_rate_div k1, + enum pixel_rate_div k2) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + switch (otg_inst) { + case 0: + REG_UPDATE_2(OTG_PIXEL_RATE_DIV, + OTG0_PIXEL_RATE_DIVK1, k1, + OTG0_PIXEL_RATE_DIVK2, k2); + break; + case 1: + REG_UPDATE_2(OTG_PIXEL_RATE_DIV, + OTG1_PIXEL_RATE_DIVK1, k1, + OTG1_PIXEL_RATE_DIVK2, k2); + break; + case 2: + REG_UPDATE_2(OTG_PIXEL_RATE_DIV, + OTG2_PIXEL_RATE_DIVK1, k1, + OTG2_PIXEL_RATE_DIVK2, k2); + break; + case 3: + REG_UPDATE_2(OTG_PIXEL_RATE_DIV, + OTG3_PIXEL_RATE_DIVK1, k1, + OTG3_PIXEL_RATE_DIVK2, k2); + break; + default: + BREAK_TO_DEBUGGER(); + return; + } +} + +static void dccg32_set_dtbclk_p_src( + struct dccg *dccg, + enum streamclk_source src, + uint32_t otg_inst) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + uint32_t p_src_sel = 0; /* selects dprefclk */ + if (src == DTBCLK0) + p_src_sel = 2; /* selects dtbclk0 */ + + switch (otg_inst) { + case 0: + if (src == REFCLK) + REG_UPDATE(DTBCLK_P_CNTL, + DTBCLK_P0_EN, 0); + else + REG_UPDATE_2(DTBCLK_P_CNTL, + DTBCLK_P0_SRC_SEL, p_src_sel, + DTBCLK_P0_EN, 1); + break; + case 1: + if (src == REFCLK) + REG_UPDATE(DTBCLK_P_CNTL, + DTBCLK_P1_EN, 0); + else + REG_UPDATE_2(DTBCLK_P_CNTL, + DTBCLK_P1_SRC_SEL, p_src_sel, + DTBCLK_P1_EN, 1); + break; + case 2: + if (src == REFCLK) + REG_UPDATE(DTBCLK_P_CNTL, + DTBCLK_P2_EN, 0); + else + REG_UPDATE_2(DTBCLK_P_CNTL, + DTBCLK_P2_SRC_SEL, p_src_sel, + DTBCLK_P2_EN, 1); + break; + case 3: + if (src == REFCLK) + REG_UPDATE(DTBCLK_P_CNTL, + DTBCLK_P3_EN, 0); + else + REG_UPDATE_2(DTBCLK_P_CNTL, + DTBCLK_P3_SRC_SEL, p_src_sel, + DTBCLK_P3_EN, 1); + break; + default: + BREAK_TO_DEBUGGER(); + return; + } + +} + +/* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */ +void dccg32_set_dtbclk_dto( + struct dccg *dccg, + int otg_inst, + int pixclk_khz, + int num_odm_segments, + const struct dc_crtc_timing *timing) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + /* DTO Output Rate / Pixel Rate = 1/4 */ + int req_dtbclk_khz = pixclk_khz / 4; + + if (dccg->ref_dtbclk_khz && req_dtbclk_khz) { + uint32_t modulo, phase; + + // phase / modulo = dtbclk / dtbclk ref + modulo = 0xffffffff; + phase = (((unsigned long long)modulo * req_dtbclk_khz) + dccg->ref_dtbclk_khz - 1) / dccg->ref_dtbclk_khz; + + REG_WRITE(DTBCLK_DTO_MODULO[otg_inst], modulo); + REG_WRITE(DTBCLK_DTO_PHASE[otg_inst], phase); + + REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], + DTBCLK_DTO_ENABLE[otg_inst], 1); + + REG_WAIT(OTG_PIXEL_RATE_CNTL[otg_inst], + DTBCLKDTO_ENABLE_STATUS[otg_inst], 1, + 1, 100); + + /* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */ + dccg32_set_pixel_rate_div(dccg, otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1); + + /* The recommended programming sequence to enable DTBCLK DTO to generate + * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should + * be set only after DTO is enabled + */ + REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], + PIPE_DTO_SRC_SEL[otg_inst], 2); + + dccg->dtbclk_khz[otg_inst] = req_dtbclk_khz; + } else { + REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], + DTBCLK_DTO_ENABLE[otg_inst], 0, + PIPE_DTO_SRC_SEL[otg_inst], 1); + + REG_WRITE(DTBCLK_DTO_MODULO[otg_inst], 0); + REG_WRITE(DTBCLK_DTO_PHASE[otg_inst], 0); + + dccg->dtbclk_khz[otg_inst] = 0; + } +} + +static void dccg32_get_dccg_ref_freq(struct dccg *dccg, + unsigned int xtalin_freq_inKhz, + unsigned int *dccg_ref_freq_inKhz) +{ + /* + * Assume refclk is sourced from xtalin + * expect 100MHz + */ + *dccg_ref_freq_inKhz = xtalin_freq_inKhz; + return; +} + +void dccg32_set_dpstreamclk( + struct dccg *dccg, + enum streamclk_source src, + int otg_inst) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + /* set the dtbclk_p source */ + dccg32_set_dtbclk_p_src(dccg, src, otg_inst); + + /* enabled to select one of the DTBCLKs for pipe */ + switch (otg_inst) + { + case 0: + REG_UPDATE_2(DPSTREAMCLK_CNTL, + DPSTREAMCLK0_EN, + (src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, 0); + break; + case 1: + REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, + (src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, 1); + break; + case 2: + REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, + (src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, 2); + break; + case 3: + REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, + (src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, 3); + break; + default: + BREAK_TO_DEBUGGER(); + return; + } +} + +void dccg32_otg_add_pixel(struct dccg *dccg, + uint32_t otg_inst) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], + OTG_ADD_PIXEL[otg_inst], 1); +} + +void dccg32_otg_drop_pixel(struct dccg *dccg, + uint32_t otg_inst) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], + OTG_DROP_PIXEL[otg_inst], 1); +} + +static const struct dccg_funcs dccg32_funcs = { + .update_dpp_dto = dccg2_update_dpp_dto, + .get_dccg_ref_freq = dccg32_get_dccg_ref_freq, + .dccg_init = dccg31_init, + .set_dpstreamclk = dccg32_set_dpstreamclk, + .enable_symclk32_se = dccg31_enable_symclk32_se, + .disable_symclk32_se = dccg31_disable_symclk32_se, + .enable_symclk32_le = dccg31_enable_symclk32_le, + .disable_symclk32_le = dccg31_disable_symclk32_le, + .set_physymclk = dccg31_set_physymclk, + .set_dtbclk_dto = dccg32_set_dtbclk_dto, + .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, + .set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto, + .otg_add_pixel = dccg32_otg_add_pixel, + .otg_drop_pixel = dccg32_otg_drop_pixel, +}; + +struct dccg *dccg32_create( + struct dc_context *ctx, + const struct dccg_registers *regs, + const struct dccg_shift *dccg_shift, + const struct dccg_mask *dccg_mask) +{ + struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL); + struct dccg *base; + + if (dccg_dcn == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + base = &dccg_dcn->base; + base->ctx = ctx; + base->funcs = &dccg32_funcs; + + dccg_dcn->regs = regs; + dccg_dcn->dccg_shift = dccg_shift; + dccg_dcn->dccg_mask = dccg_mask; + + return &dccg_dcn->base; +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h new file mode 100644 index 000000000000..0e54c0a105a1 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h @@ -0,0 +1,155 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DCN32_DCCG_H__ +#define __DCN32_DCCG_H__ + +#include "dcn31/dcn31_dccg.h" + +#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\ + .field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix + + +#define DCCG_REG_LIST_DCN32() \ + SR(DPPCLK_DTO_CTRL),\ + DCCG_SRII(DTO_PARAM, DPPCLK, 0),\ + DCCG_SRII(DTO_PARAM, DPPCLK, 1),\ + DCCG_SRII(DTO_PARAM, DPPCLK, 2),\ + DCCG_SRII(DTO_PARAM, DPPCLK, 3),\ + DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),\ + SR(PHYASYMCLK_CLOCK_CNTL),\ + SR(PHYBSYMCLK_CLOCK_CNTL),\ + SR(PHYCSYMCLK_CLOCK_CNTL),\ + SR(PHYDSYMCLK_CLOCK_CNTL),\ + SR(PHYESYMCLK_CLOCK_CNTL),\ + SR(DPSTREAMCLK_CNTL),\ + SR(SYMCLK32_SE_CNTL),\ + SR(SYMCLK32_LE_CNTL),\ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\ + DCCG_SRII(MODULO, DTBCLK_DTO, 0),\ + DCCG_SRII(MODULO, DTBCLK_DTO, 1),\ + DCCG_SRII(MODULO, DTBCLK_DTO, 2),\ + DCCG_SRII(MODULO, DTBCLK_DTO, 3),\ + DCCG_SRII(PHASE, DTBCLK_DTO, 0),\ + DCCG_SRII(PHASE, DTBCLK_DTO, 1),\ + DCCG_SRII(PHASE, DTBCLK_DTO, 2),\ + DCCG_SRII(PHASE, DTBCLK_DTO, 3),\ + SR(DCCG_AUDIO_DTBCLK_DTO_MODULO),\ + SR(DCCG_AUDIO_DTBCLK_DTO_PHASE),\ + SR(OTG_PIXEL_RATE_DIV),\ + SR(DTBCLK_P_CNTL),\ + SR(DCCG_AUDIO_DTO_SOURCE) + + +#define DCCG_MASK_SH_LIST_DCN32(mask_sh) \ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\ + DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\ + DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\ + DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\ + DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\ + DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\ + DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\ + DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\ + DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\ + DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\ + DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\ + DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_EN, mask_sh),\ + DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_SRC_SEL, mask_sh),\ + DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_EN, mask_sh),\ + DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_SRC_SEL, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_SRC_SEL, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_SRC_SEL, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_SRC_SEL, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_SRC_SEL, mask_sh),\ + DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_EN, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_PIXEL_RATE_DIVK1, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_PIXEL_RATE_DIVK2, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_PIXEL_RATE_DIVK1, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_PIXEL_RATE_DIVK2, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_PIXEL_RATE_DIVK1, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_PIXEL_RATE_DIVK2, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK1, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK2, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK2, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_SRC_SEL, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_SRC_SEL, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_EN, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_SRC_SEL, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\ + DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh) + + +struct dccg *dccg32_create( + struct dc_context *ctx, + const struct dccg_registers *regs, + const struct dccg_shift *dccg_shift, + const struct dccg_mask *dccg_mask); + +#endif //__DCN32_DCCG_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c new file mode 100644 index 000000000000..7170a9aa82a4 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c @@ -0,0 +1,283 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + + +#include "reg_helper.h" + +#include "core_types.h" +#include "link_encoder.h" +#include "dcn31/dcn31_dio_link_encoder.h" +#include "dcn32_dio_link_encoder.h" +#include "stream_encoder.h" +#include "i2caux_interface.h" +#include "dc_bios_types.h" + +#include "gpio_service_interface.h" + +#ifndef MIN +#define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) +#endif + +#define CTX \ + enc10->base.ctx +#define DC_LOGGER \ + enc10->base.ctx->logger + +#define REG(reg)\ + (enc10->link_regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + enc10->link_shift->field_name, enc10->link_mask->field_name + +#define AUX_REG(reg)\ + (enc10->aux_regs->reg) + +#define AUX_REG_READ(reg_name) \ + dm_read_reg(CTX, AUX_REG(reg_name)) + +#define AUX_REG_WRITE(reg_name, val) \ + dm_write_reg(CTX, AUX_REG(reg_name), val) + + +void enc32_hw_init(struct link_encoder *enc) +{ + struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); + +/* + 00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2 + 01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4 + 02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8 + 03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16 + 04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32 + 05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64 + 06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128 + 07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256 +*/ + +/* + AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0, + AUX_RX_START_WINDOW = 1 [6:4] + AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8] + AUX_RX_HALF_SYM_DETECT_LEN = 1 [13:12] default is 1 + AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1 + AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0 default is 0 + AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1 default is 1 + AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1 default is 1 + AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3 + AUX_RX_DETECTION_THRESHOLD [30:28] = 1 +*/ + AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110); + + AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a); + + //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32; + // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk + // 27MHz -> 0xd + // 100MHz -> 0x32 + // 48MHz -> 0x18 + + // Set TMDS_CTL0 to 1. This is a legacy setting. + REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1); + + dcn10_aux_initialize(enc10); +} + + +void dcn32_link_encoder_enable_dp_output( + struct link_encoder *enc, + const struct dc_link_settings *link_settings, + enum clock_source_id clock_source) +{ + if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { + dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source); + return; + } +} + +bool dcn32_link_encoder_is_in_alt_mode(struct link_encoder *enc) +{ + struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); + uint32_t dp_alt_mode_disable = 0; + bool is_usb_c_alt_mode = false; + + if (enc->features.flags.bits.DP_IS_USB_C) { + /* if value == 1 alt mode is disabled, otherwise it is enabled */ + //REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable); + is_usb_c_alt_mode = (dp_alt_mode_disable == 0); + } + + return is_usb_c_alt_mode; +} + +void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc, + struct dc_link_settings *link_settings) +{ + struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); + uint32_t is_in_usb_c_dp4_mode = 0; + + dcn10_link_encoder_get_max_link_cap(enc, link_settings); + + /* in usb c dp2 mode, max lane count is 2 */ + if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) { +// REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode); + if (!is_in_usb_c_dp4_mode) + link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); + } + +} + +static const struct link_encoder_funcs dcn32_link_enc_funcs = { + .read_state = link_enc2_read_state, + .validate_output_with_stream = + dcn30_link_encoder_validate_output_with_stream, + .hw_init = enc32_hw_init, + .setup = dcn10_link_encoder_setup, + .enable_tmds_output = dcn10_link_encoder_enable_tmds_output, + .enable_dp_output = dcn32_link_encoder_enable_dp_output, + .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output, + .disable_output = dcn10_link_encoder_disable_output, + .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings, + .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern, + .update_mst_stream_allocation_table = + dcn10_link_encoder_update_mst_stream_allocation_table, + .psr_program_dp_dphy_fast_training = + dcn10_psr_program_dp_dphy_fast_training, + .psr_program_secondary_packet = dcn10_psr_program_secondary_packet, + .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe, + .enable_hpd = dcn10_link_encoder_enable_hpd, + .disable_hpd = dcn10_link_encoder_disable_hpd, + .is_dig_enabled = dcn10_is_dig_enabled, + .destroy = dcn10_link_encoder_destroy, + .fec_set_enable = enc2_fec_set_enable, + .fec_set_ready = enc2_fec_set_ready, + .fec_is_active = enc2_fec_is_active, + .get_dig_frontend = dcn10_get_dig_frontend, + .get_dig_mode = dcn10_get_dig_mode, + .is_in_alt_mode = dcn32_link_encoder_is_in_alt_mode, + .get_max_link_cap = dcn32_link_encoder_get_max_link_cap, + .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux, +}; + +void dcn32_link_encoder_construct( + struct dcn20_link_encoder *enc20, + const struct encoder_init_data *init_data, + const struct encoder_feature_support *enc_features, + const struct dcn10_link_enc_registers *link_regs, + const struct dcn10_link_enc_aux_registers *aux_regs, + const struct dcn10_link_enc_hpd_registers *hpd_regs, + const struct dcn10_link_enc_shift *link_shift, + const struct dcn10_link_enc_mask *link_mask) +{ + struct bp_connector_speed_cap_info bp_cap_info = {0}; + const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; + enum bp_result result = BP_RESULT_OK; + struct dcn10_link_encoder *enc10 = &enc20->enc10; + + enc10->base.funcs = &dcn32_link_enc_funcs; + enc10->base.ctx = init_data->ctx; + enc10->base.id = init_data->encoder; + + enc10->base.hpd_source = init_data->hpd_source; + enc10->base.connector = init_data->connector; + + enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; + + enc10->base.features = *enc_features; + + enc10->base.transmitter = init_data->transmitter; + + /* set the flag to indicate whether driver poll the I2C data pin + * while doing the DP sink detect + */ + +/* if (dal_adapter_service_is_feature_supported(as, + FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) + enc10->base.features.flags.bits. + DP_SINK_DETECT_POLL_DATA_PIN = true;*/ + + enc10->base.output_signals = + SIGNAL_TYPE_DVI_SINGLE_LINK | + SIGNAL_TYPE_DVI_DUAL_LINK | + SIGNAL_TYPE_LVDS | + SIGNAL_TYPE_DISPLAY_PORT | + SIGNAL_TYPE_DISPLAY_PORT_MST | + SIGNAL_TYPE_EDP | + SIGNAL_TYPE_HDMI_TYPE_A; + + enc10->link_regs = link_regs; + enc10->aux_regs = aux_regs; + enc10->hpd_regs = hpd_regs; + enc10->link_shift = link_shift; + enc10->link_mask = link_mask; + + switch (enc10->base.transmitter) { + case TRANSMITTER_UNIPHY_A: + enc10->base.preferred_engine = ENGINE_ID_DIGA; + break; + case TRANSMITTER_UNIPHY_B: + enc10->base.preferred_engine = ENGINE_ID_DIGB; + break; + case TRANSMITTER_UNIPHY_C: + enc10->base.preferred_engine = ENGINE_ID_DIGC; + break; + case TRANSMITTER_UNIPHY_D: + enc10->base.preferred_engine = ENGINE_ID_DIGD; + break; + case TRANSMITTER_UNIPHY_E: + enc10->base.preferred_engine = ENGINE_ID_DIGE; + break; + default: + ASSERT_CRITICAL(false); + enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; + } + + /* default to one to mirror Windows behavior */ + enc10->base.features.flags.bits.HDMI_6GB_EN = 1; + + if (bp_funcs->get_connector_speed_cap_info) + result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios, + enc10->base.connector, &bp_cap_info); + + /* Override features with DCE-specific values */ + if (result == BP_RESULT_OK) { + enc10->base.features.flags.bits.IS_HBR2_CAPABLE = + bp_cap_info.DP_HBR2_EN; + enc10->base.features.flags.bits.IS_HBR3_CAPABLE = + bp_cap_info.DP_HBR3_EN; + enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; + enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1; + enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN; + enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN; + enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN; + } else { + DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", + __func__, + result); + } + if (enc10->base.ctx->dc->debug.hdmi20_disable) { + enc10->base.features.flags.bits.HDMI_6GB_EN = 0; + } +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h new file mode 100644 index 000000000000..e880b76d5f25 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h @@ -0,0 +1,42 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_LINK_ENCODER__DCN32_H__ +#define __DC_LINK_ENCODER__DCN32_H__ + +#include "dcn30/dcn30_dio_link_encoder.h" + +void dcn32_link_encoder_construct( + struct dcn20_link_encoder *enc20, + const struct encoder_init_data *init_data, + const struct encoder_feature_support *enc_features, + const struct dcn10_link_enc_registers *link_regs, + const struct dcn10_link_enc_aux_registers *aux_regs, + const struct dcn10_link_enc_hpd_registers *hpd_regs, + const struct dcn10_link_enc_shift *link_shift, + const struct dcn10_link_enc_mask *link_mask); + + +#endif /* __DC_LINK_ENCODER__DCN32_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c new file mode 100644 index 000000000000..62532da94913 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c @@ -0,0 +1,427 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + + +#include "dc_bios_types.h" +#include "dcn30/dcn30_dio_stream_encoder.h" +#include "dcn32_dio_stream_encoder.h" +#include "reg_helper.h" +#include "hw_shared.h" +#include "inc/link_dpcd.h" +#include "dpcd_defs.h" + +#define DC_LOGGER \ + enc1->base.ctx->logger + +#define REG(reg)\ + (enc1->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + enc1->se_shift->field_name, enc1->se_mask->field_name + +#define VBI_LINE_0 0 +#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 + +#define CTX \ + enc1->base.ctx + + + +static void enc32_dp_set_odm_combine( + struct stream_encoder *enc, + bool odm_combine) +{ + //struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + //TODO: REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine); +} + +/* setup stream encoder in dvi mode */ +void enc32_stream_encoder_dvi_set_stream_attribute( + struct stream_encoder *enc, + struct dc_crtc_timing *crtc_timing, + bool is_dual_link) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { + struct bp_encoder_control cntl = {0}; + + cntl.action = ENCODER_CONTROL_SETUP; + cntl.engine_id = enc1->base.id; + cntl.signal = is_dual_link ? + SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; + cntl.enable_dp_audio = false; + cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; + cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; + + if (enc1->base.bp->funcs->encoder_control( + enc1->base.bp, &cntl) != BP_RESULT_OK) + return; + + } else { + + //Set pattern for clock channel, default vlue 0x63 does not work + REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); + + //DIG_BE_TMDS_DVI_MODE : TMDS-DVI mode is already set in link_encoder_setup + + //DIG_SOURCE_SELECT is already set in dig_connect_to_otg + + /* DIG_START is removed from the register spec */ + } + + ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); + ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); + enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); +} + +/* setup stream encoder in hdmi mode */ +static void enc32_stream_encoder_hdmi_set_stream_attribute( + struct stream_encoder *enc, + struct dc_crtc_timing *crtc_timing, + int actual_pix_clk_khz, + bool enable_audio) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { + struct bp_encoder_control cntl = {0}; + + cntl.action = ENCODER_CONTROL_SETUP; + cntl.engine_id = enc1->base.id; + cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; + cntl.enable_dp_audio = enable_audio; + cntl.pixel_clock = actual_pix_clk_khz; + cntl.lanes_number = LANE_COUNT_FOUR; + + if (enc1->base.bp->funcs->encoder_control( + enc1->base.bp, &cntl) != BP_RESULT_OK) + return; + + } else { + + //Set pattern for clock channel, default vlue 0x63 does not work + REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); + + //DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup + + //DIG_SOURCE_SELECT is already set in dig_connect_to_otg + + /* DIG_START is removed from the register spec */ + } + + /* Configure pixel encoding */ + enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); + + /* setup HDMI engine */ + REG_UPDATE_6(HDMI_CONTROL, + HDMI_PACKET_GEN_VERSION, 1, + HDMI_KEEPOUT_MODE, 1, + HDMI_DEEP_COLOR_ENABLE, 0, + HDMI_DATA_SCRAMBLE_EN, 0, + HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1, + HDMI_CLOCK_CHANNEL_RATE, 0); + + /* Configure color depth */ + switch (crtc_timing->display_color_depth) { + case COLOR_DEPTH_888: + REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); + break; + case COLOR_DEPTH_101010: + if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 1, + HDMI_DEEP_COLOR_ENABLE, 0); + } else { + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 1, + HDMI_DEEP_COLOR_ENABLE, 1); + } + break; + case COLOR_DEPTH_121212: + if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 2, + HDMI_DEEP_COLOR_ENABLE, 0); + } else { + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 2, + HDMI_DEEP_COLOR_ENABLE, 1); + } + break; + case COLOR_DEPTH_161616: + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 3, + HDMI_DEEP_COLOR_ENABLE, 1); + break; + default: + break; + } + + if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { + /* enable HDMI data scrambler + * HDMI_CLOCK_CHANNEL_RATE_MORE_340M + * Clock channel frequency is 1/4 of character rate. + */ + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DATA_SCRAMBLE_EN, 1, + HDMI_CLOCK_CHANNEL_RATE, 1); + } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { + + /* TODO: New feature for DCE11, still need to implement */ + + /* enable HDMI data scrambler + * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE + * Clock channel frequency is the same + * as character rate + */ + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DATA_SCRAMBLE_EN, 1, + HDMI_CLOCK_CHANNEL_RATE, 0); + } + + + /* Enable transmission of General Control packet on every frame */ + REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, + HDMI_GC_CONT, 1, + HDMI_GC_SEND, 1, + HDMI_NULL_SEND, 1); + + /* Disable Audio Content Protection packet transmission */ + REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0); + + /* following belongs to audio */ + /* Enable Audio InfoFrame packet transmission. */ + REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); + + /* update double-buffered AUDIO_INFO registers immediately */ + ASSERT(enc->afmt); + enc->afmt->funcs->audio_info_immediate_update(enc->afmt); + + /* Select line number on which to send Audio InfoFrame packets */ + REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, + VBI_LINE_0 + 2); + + /* set HDMI GC AVMUTE */ + REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); +} + + + +static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing) +{ + bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; + + two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 + && !timing->dsc_cfg.ycbcr422_simple); + return two_pix; +} + +static void enc32_stream_encoder_dp_unblank( + struct dc_link *link, + struct stream_encoder *enc, + const struct encoder_unblank_param *param) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { + uint32_t n_vid = 0x8000; + uint32_t m_vid; + uint32_t n_multiply = 0; + uint64_t m_vid_l = n_vid; + + /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ + if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1) { + /*this logic should be the same in get_pixel_clock_parameters() */ + n_multiply = 1; + } + /* M / N = Fstream / Flink + * m_vid / n_vid = pixel rate / link rate + */ + + m_vid_l *= param->timing.pix_clk_100hz / 10; + m_vid_l = div_u64(m_vid_l, + param->link_settings.link_rate + * LINK_RATE_REF_FREQ_IN_KHZ); + + m_vid = (uint32_t) m_vid_l; + + /* enable auto measurement */ + + REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); + + /* auto measurement need 1 full 0x8000 symbol cycle to kick in, + * therefore program initial value for Mvid and Nvid + */ + + REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); + + REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); + + REG_UPDATE_2(DP_VID_TIMING, + DP_VID_M_N_GEN_EN, 1, + DP_VID_N_MUL, n_multiply); + } + + /* make sure stream is disabled before resetting steer fifo */ + REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false); + REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); + + /* DIG_START is removed from the register spec */ + + /* switch DP encoder to CRTC data, but reset it the fifo first. It may happen + * that it overflows during mode transition, and sometimes doesn't recover. + */ + REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1); + udelay(10); + + REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); + + /* wait 100us for DIG/DP logic to prime + * (i.e. a few video lines) + */ + udelay(100); + + /* the hardware would start sending video at the start of the next DP + * frame (i.e. rising edge of the vblank). + * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this + * register has no effect on enable transition! HW always guarantees + * VID_STREAM enable at start of next frame, and this is not + * programmable + */ + + REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); + + dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); +} + +/* Set DSC-related configuration. + * dsc_mode: 0 disables DSC, other values enable DSC in specified format + * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32 + * dsc_slice_width: DP_DSC_SLICE_WIDTH removed in DCN32 + */ +static void enc32_dp_set_dsc_config(struct stream_encoder *enc, + enum optc_dsc_mode dsc_mode, + uint32_t dsc_bytes_per_pixel, + uint32_t dsc_slice_width) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode); +} + +/* this function read dsc related register fields to be logged later in dcn10_log_hw_state + * into a dcn_dsc_state struct. + */ +static void enc32_read_state(struct stream_encoder *enc, struct enc_state *s) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + //if dsc is enabled, continue to read + REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); + if (s->dsc_mode) { + REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num); + + REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); + REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); + + REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable); + REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); + } +} + + +static const struct stream_encoder_funcs dcn32_str_enc_funcs = { + .dp_set_odm_combine = + enc32_dp_set_odm_combine, + .dp_set_stream_attribute = + enc2_stream_encoder_dp_set_stream_attribute, + .hdmi_set_stream_attribute = + enc32_stream_encoder_hdmi_set_stream_attribute, + .dvi_set_stream_attribute = + enc32_stream_encoder_dvi_set_stream_attribute, + .set_throttled_vcp_size = + enc1_stream_encoder_set_throttled_vcp_size, + .update_hdmi_info_packets = + enc3_stream_encoder_update_hdmi_info_packets, + .stop_hdmi_info_packets = + enc3_stream_encoder_stop_hdmi_info_packets, + .update_dp_info_packets = + enc3_stream_encoder_update_dp_info_packets, + .stop_dp_info_packets = + enc1_stream_encoder_stop_dp_info_packets, + .reset_fifo = + enc1_stream_encoder_reset_fifo, + .dp_blank = + enc1_stream_encoder_dp_blank, + .dp_unblank = + enc32_stream_encoder_dp_unblank, + .audio_mute_control = enc3_audio_mute_control, + + .dp_audio_setup = enc3_se_dp_audio_setup, + .dp_audio_enable = enc3_se_dp_audio_enable, + .dp_audio_disable = enc1_se_dp_audio_disable, + + .hdmi_audio_setup = enc3_se_hdmi_audio_setup, + .hdmi_audio_disable = enc1_se_hdmi_audio_disable, + .setup_stereo_sync = enc1_setup_stereo_sync, + .set_avmute = enc1_stream_encoder_set_avmute, + .dig_connect_to_otg = enc1_dig_connect_to_otg, + .dig_source_otg = enc1_dig_source_otg, + + .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, + + .enc_read_state = enc32_read_state, + .dp_set_dsc_config = enc32_dp_set_dsc_config, + .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, + .set_dynamic_metadata = enc2_set_dynamic_metadata, + .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, +}; + +void dcn32_dio_stream_encoder_construct( + struct dcn10_stream_encoder *enc1, + struct dc_context *ctx, + struct dc_bios *bp, + enum engine_id eng_id, + struct vpg *vpg, + struct afmt *afmt, + const struct dcn10_stream_enc_registers *regs, + const struct dcn10_stream_encoder_shift *se_shift, + const struct dcn10_stream_encoder_mask *se_mask) +{ + enc1->base.funcs = &dcn32_str_enc_funcs; + enc1->base.ctx = ctx; + enc1->base.id = eng_id; + enc1->base.bp = bp; + enc1->base.vpg = vpg; + enc1->base.afmt = afmt; + enc1->regs = regs; + enc1->se_shift = se_shift; + enc1->se_mask = se_mask; + enc1->base.stream_enc_inst = vpg->inst; +} + diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h new file mode 100644 index 000000000000..7241080b1553 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h @@ -0,0 +1,254 @@ +/* + * Copyright 2021 - Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_DIO_STREAM_ENCODER_DCN32_H__ +#define __DC_DIO_STREAM_ENCODER_DCN32_H__ + +#include "dcn30/dcn30_vpg.h" +#include "dcn30/dcn30_afmt.h" +#include "stream_encoder.h" +#include "dcn20/dcn20_stream_encoder.h" + +#define SE_DCN32_REG_LIST(id)\ + SRI(AFMT_CNTL, DIG, id), \ + SRI(DIG_FE_CNTL, DIG, id), \ + SRI(HDMI_CONTROL, DIG, id), \ + SRI(HDMI_DB_CONTROL, DIG, id), \ + SRI(HDMI_GC, DIG, id), \ + SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \ + SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \ + SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \ + SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \ + SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \ + SRI(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \ + SRI(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \ + SRI(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \ + SRI(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \ + SRI(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \ + SRI(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \ + SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \ + SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \ + SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \ + SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\ + SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\ + SRI(HDMI_ACR_32_0, DIG, id),\ + SRI(HDMI_ACR_32_1, DIG, id),\ + SRI(HDMI_ACR_44_0, DIG, id),\ + SRI(HDMI_ACR_44_1, DIG, id),\ + SRI(HDMI_ACR_48_0, DIG, id),\ + SRI(HDMI_ACR_48_1, DIG, id),\ + SRI(DP_DB_CNTL, DP, id), \ + SRI(DP_MSA_MISC, DP, id), \ + SRI(DP_MSA_VBID_MISC, DP, id), \ + SRI(DP_MSA_COLORIMETRY, DP, id), \ + SRI(DP_MSA_TIMING_PARAM1, DP, id), \ + SRI(DP_MSA_TIMING_PARAM2, DP, id), \ + SRI(DP_MSA_TIMING_PARAM3, DP, id), \ + SRI(DP_MSA_TIMING_PARAM4, DP, id), \ + SRI(DP_MSE_RATE_CNTL, DP, id), \ + SRI(DP_MSE_RATE_UPDATE, DP, id), \ + SRI(DP_PIXEL_FORMAT, DP, id), \ + SRI(DP_SEC_CNTL, DP, id), \ + SRI(DP_SEC_CNTL2, DP, id), \ + SRI(DP_SEC_CNTL6, DP, id), \ + SRI(DP_STEER_FIFO, DP, id), \ + SRI(DP_VID_M, DP, id), \ + SRI(DP_VID_N, DP, id), \ + SRI(DP_VID_STREAM_CNTL, DP, id), \ + SRI(DP_VID_TIMING, DP, id), \ + SRI(DP_SEC_AUD_N, DP, id), \ + SRI(DP_SEC_TIMESTAMP, DP, id), \ + SRI(DP_DSC_CNTL, DP, id), \ + SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \ + SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ + SRI(DP_SEC_FRAMING4, DP, id), \ + SRI(DP_GSP11_CNTL, DP, id), \ + SRI(DME_CONTROL, DME, id),\ + SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \ + SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ + SRI(DIG_FE_CNTL, DIG, id), \ + SRI(DIG_CLOCK_PATTERN, DIG, id) + + +#define SE_COMMON_MASK_SH_LIST_DCN32_BASE(mask_sh)\ + SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\ + SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_NO_EXTRA_NULL_PACKET_FILLED, mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\ + SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\ + SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\ + SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL4, DP_SEC_GSP4_LINE_NUM, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, mask_sh),\ + SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\ + SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ + SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\ + SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\ + SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\ + SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\ + SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\ + SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\ + SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\ + SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\ + SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP11_PPS, mask_sh),\ + SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, mask_sh),\ + SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, mask_sh),\ + SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\ + SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\ + SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\ + SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh), \ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC8_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC8_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC9_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC9_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC10_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC10_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC11_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC11_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC12_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC12_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC13_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC13_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC14_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC14_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC0_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC1_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC2_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC3_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC4_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC5_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC6_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC7_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL7, HDMI_GENERIC8_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL7, HDMI_GENERIC9_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL8, HDMI_GENERIC10_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL8, HDMI_GENERIC11_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL9, HDMI_GENERIC12_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL9, HDMI_GENERIC13_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL10, HDMI_GENERIC14_LINE, mask_sh),\ + SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\ + SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, mask_sh),\ + SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, mask_sh),\ + SE_SF(DME0_DME_CONTROL, METADATA_ENGINE_EN, mask_sh),\ + SE_SF(DME0_DME_CONTROL, METADATA_HUBP_REQUESTOR_ID, mask_sh),\ + SE_SF(DME0_DME_CONTROL, METADATA_STREAM_TYPE, mask_sh),\ + SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE_REFERENCE, mask_sh),\ + SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_ENABLE, mask_sh),\ + SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE_REFERENCE, mask_sh),\ + SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, DOLBY_VISION_EN, mask_sh),\ + SE_SF(DP0_DP_SEC_FRAMING4, DP_SST_SDP_SPLITTING, mask_sh),\ + SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh) + +#define SE_COMMON_MASK_SH_LIST_DCN32(mask_sh)\ + SE_COMMON_MASK_SH_LIST_DCN32_BASE(mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh) + +void dcn32_dio_stream_encoder_construct( + struct dcn10_stream_encoder *enc1, + struct dc_context *ctx, + struct dc_bios *bp, + enum engine_id eng_id, + struct vpg *vpg, + struct afmt *afmt, + const struct dcn10_stream_enc_registers *regs, + const struct dcn10_stream_encoder_shift *se_shift, + const struct dcn10_stream_encoder_mask *se_mask); + +#endif /* __DC_DIO_STREAM_ENCODER_DCN32_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c new file mode 100644 index 000000000000..f349cbe2a0f0 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c @@ -0,0 +1,164 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" +#include "core_types.h" +#include "reg_helper.h" +#include "dcn32_dpp.h" +#include "basics/conversion.h" +#include "dcn30/dcn30_cm_common.h" + +/* Compute the maximum number of lines that we can fit in the line buffer */ +void dscl32_calc_lb_num_partitions( + const struct scaler_data *scl_data, + enum lb_memory_config lb_config, + int *num_part_y, + int *num_part_c) +{ + int memory_line_size_y, memory_line_size_c, memory_line_size_a, + lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a; + + int line_size = scl_data->viewport.width < scl_data->recout.width ? + scl_data->viewport.width : scl_data->recout.width; + int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? + scl_data->viewport_c.width : scl_data->recout.width; + + if (line_size == 0) + line_size = 1; + + if (line_size_c == 0) + line_size_c = 1; + + memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */ + memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */ + memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */ + + if (lb_config == LB_MEMORY_CONFIG_1) { + lb_memory_size = 970; + lb_memory_size_c = 970; + lb_memory_size_a = 970; + } else if (lb_config == LB_MEMORY_CONFIG_2) { + lb_memory_size = 1290; + lb_memory_size_c = 1290; + lb_memory_size_a = 1290; + } else if (lb_config == LB_MEMORY_CONFIG_3) { + if (scl_data->viewport.width == scl_data->h_active && + scl_data->viewport.height == scl_data->v_active) { + /* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */ + /* use increased LB size for calculation only if Scaler not enabled */ + lb_memory_size = 970 + 1290 + 1170 + 1170 + 1170; + lb_memory_size_c = 970 + 1290; + lb_memory_size_a = 970 + 1290 + 1170; + } else { + /* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */ + lb_memory_size = 970 + 1290 + 484 + 484 + 484; + lb_memory_size_c = 970 + 1290; + lb_memory_size_a = 970 + 1290 + 484; + } + } else { + if (scl_data->viewport.width == scl_data->h_active && + scl_data->viewport.height == scl_data->v_active) { + /* use increased LB size for calculation only if Scaler not enabled */ + lb_memory_size = 970 + 1290 + 1170; + lb_memory_size_c = 970 + 1290 + 1170; + lb_memory_size_a = 970 + 1290 + 1170; + } else { + lb_memory_size = 970 + 1290 + 484; + lb_memory_size_c = 970 + 1290 + 484; + lb_memory_size_a = 970 + 1290 + 484; + } + } + *num_part_y = lb_memory_size / memory_line_size_y; + *num_part_c = lb_memory_size_c / memory_line_size_c; + num_partitions_a = lb_memory_size_a / memory_line_size_a; + + if (scl_data->lb_params.alpha_en + && (num_partitions_a < *num_part_y)) + *num_part_y = num_partitions_a; + + if (*num_part_y > 32) + *num_part_y = 32; + if (*num_part_c > 32) + *num_part_c = 32; +} + +static struct dpp_funcs dcn32_dpp_funcs = { + .dpp_program_gamcor_lut = dpp3_program_gamcor_lut, + .dpp_read_state = dpp30_read_state, + .dpp_reset = dpp_reset, + .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale, + .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps, + .dpp_set_gamut_remap = dpp3_cm_set_gamut_remap, + .dpp_set_csc_adjustment = NULL, + .dpp_set_csc_default = NULL, + .dpp_program_regamma_pwl = NULL, + .dpp_set_pre_degam = dpp3_set_pre_degam, + .dpp_program_input_lut = NULL, + .dpp_full_bypass = dpp1_full_bypass, + .dpp_setup = dpp3_cnv_setup, + .dpp_program_degamma_pwl = NULL, + .dpp_program_cm_dealpha = dpp3_program_cm_dealpha, + .dpp_program_cm_bias = dpp3_program_cm_bias, + + .dpp_program_blnd_lut = NULL, // BLNDGAM is removed completely in DCN3.2 DPP + .dpp_program_shaper_lut = NULL, // CM SHAPER block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND) + .dpp_program_3dlut = NULL, // CM 3DLUT block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND) + + .dpp_program_bias_and_scale = NULL, + .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer, + .set_cursor_attributes = dpp3_set_cursor_attributes, + .set_cursor_position = dpp1_set_cursor_position, + .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, + .dpp_dppclk_control = dpp1_dppclk_control, + .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier, +}; + + +static struct dpp_caps dcn32_dpp_cap = { + .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT, + .max_lb_partitions = 31, + .dscl_calc_lb_num_partitions = dscl32_calc_lb_num_partitions, +}; + +bool dpp32_construct( + struct dcn3_dpp *dpp, + struct dc_context *ctx, + uint32_t inst, + const struct dcn3_dpp_registers *tf_regs, + const struct dcn3_dpp_shift *tf_shift, + const struct dcn3_dpp_mask *tf_mask) +{ + dpp->base.ctx = ctx; + + dpp->base.inst = inst; + dpp->base.funcs = &dcn32_dpp_funcs; + dpp->base.caps = &dcn32_dpp_cap; + + dpp->tf_regs = tf_regs; + dpp->tf_shift = tf_shift; + dpp->tf_mask = tf_mask; + + return true; +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h new file mode 100644 index 000000000000..572958d287eb --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h @@ -0,0 +1,38 @@ +/* Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DCN32_DPP_H__ +#define __DCN32_DPP_H__ + +#include "dcn20/dcn20_dpp.h" +#include "dcn30/dcn30_dpp.h" + +bool dpp32_construct(struct dcn3_dpp *dpp3, + struct dc_context *ctx, + uint32_t inst, + const struct dcn3_dpp_registers *tf_regs, + const struct dcn3_dpp_shift *tf_shift, + const struct dcn3_dpp_mask *tf_mask); + +#endif /* __DCN32_DPP_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.c new file mode 100644 index 000000000000..4dbad8d4b4fc --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.c @@ -0,0 +1,90 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "dc_bios_types.h" +#include "dcn31/dcn31_hpo_dp_link_encoder.h" +#include "dcn32_hpo_dp_link_encoder.h" +#include "reg_helper.h" +#include "dc_link.h" +#include "stream_encoder.h" + +#define DC_LOGGER \ + enc3->base.ctx->logger + +#define REG(reg)\ + (enc3->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + enc3->hpo_le_shift->field_name, enc3->hpo_le_mask->field_name + +#define CTX \ + enc3->base.ctx + +static bool dcn32_hpo_dp_link_enc_is_in_alt_mode( + struct hpo_dp_link_encoder *enc) +{ + struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc); + uint32_t dp_alt_mode_disable = 0; + + ASSERT((enc->transmitter >= TRANSMITTER_UNIPHY_A) && (enc->transmitter <= TRANSMITTER_UNIPHY_E)); + + /* if value == 1 alt mode is disabled, otherwise it is enabled */ + REG_GET(RDPCSTX_PHY_CNTL6[enc->transmitter], RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable); + return (dp_alt_mode_disable == 0); +} + + + +static struct hpo_dp_link_encoder_funcs dcn32_hpo_dp_link_encoder_funcs = { + .enable_link_phy = dcn31_hpo_dp_link_enc_enable_dp_output, + .disable_link_phy = dcn31_hpo_dp_link_enc_disable_output, + .link_enable = dcn31_hpo_dp_link_enc_enable, + .link_disable = dcn31_hpo_dp_link_enc_disable, + .set_link_test_pattern = dcn31_hpo_dp_link_enc_set_link_test_pattern, + .update_stream_allocation_table = dcn31_hpo_dp_link_enc_update_stream_allocation_table, + .set_throttled_vcp_size = dcn31_hpo_dp_link_enc_set_throttled_vcp_size, + .is_in_alt_mode = dcn32_hpo_dp_link_enc_is_in_alt_mode, + .read_state = dcn31_hpo_dp_link_enc_read_state, + .set_ffe = dcn31_hpo_dp_link_enc_set_ffe, +}; + +void hpo_dp_link_encoder32_construct(struct dcn31_hpo_dp_link_encoder *enc31, + struct dc_context *ctx, + uint32_t inst, + const struct dcn31_hpo_dp_link_encoder_registers *hpo_le_regs, + const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift, + const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask) +{ + enc31->base.ctx = ctx; + + enc31->base.inst = inst; + enc31->base.funcs = &dcn32_hpo_dp_link_encoder_funcs; + enc31->base.hpd_source = HPD_SOURCEID_UNKNOWN; + enc31->base.transmitter = TRANSMITTER_UNKNOWN; + + enc31->regs = hpo_le_regs; + enc31->hpo_le_shift = hpo_le_shift; + enc31->hpo_le_mask = hpo_le_mask; +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.h new file mode 100644 index 000000000000..9db1323e1933 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.h @@ -0,0 +1,63 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_DCN32_HPO_DP_LINK_ENCODER_H__ +#define __DAL_DCN32_HPO_DP_LINK_ENCODER_H__ + +#include "link_encoder.h" + +#define DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(mask_sh)\ + SE_SF(DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC_CLOCK_EN, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_RESET, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_ENABLE, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, PRECODER_ENABLE, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, MODE, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, NUM_LANES, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS, STATUS, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS, SAT_UPDATE_PENDING, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS, RATE_UPDATE_PENDING, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0, TP_CUSTOM, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT0, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT1, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT2, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT3, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL0, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL1, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL2, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL3, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_STREAM_SOURCE, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_SLOT_COUNT, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_X, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_Y, mask_sh),\ + SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE, SAT_UPDATE, mask_sh) + +void hpo_dp_link_encoder32_construct(struct dcn31_hpo_dp_link_encoder *enc31, + struct dc_context *ctx, + uint32_t inst, + const struct dcn31_hpo_dp_link_encoder_registers *hpo_le_regs, + const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift, + const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask); + +#endif // __DAL_DCN32_HPO_DP_LINK_ENCODER_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c new file mode 100644 index 000000000000..27813374f2bb --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c @@ -0,0 +1,964 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + + +#include "dcn30/dcn30_hubbub.h" +#include "dcn32_hubbub.h" +#include "dm_services.h" +#include "reg_helper.h" + + +#define CTX \ + hubbub2->base.ctx +#define DC_LOGGER \ + hubbub2->base.ctx->logger +#define REG(reg)\ + hubbub2->regs->reg + +#undef FN +#define FN(reg_name, field_name) \ + hubbub2->shifts->field_name, hubbub2->masks->field_name + +#define DCN32_CRB_SEGMENT_SIZE_KB 64 + +static void dcn32_init_crb(struct hubbub *hubbub) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + + REG_GET(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, + &hubbub2->det0_size); + + REG_GET(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, + &hubbub2->det1_size); + + REG_GET(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, + &hubbub2->det2_size); + + REG_GET(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, + &hubbub2->det3_size); + + REG_GET(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, + &hubbub2->compbuf_size_segments); + + REG_SET_2(COMPBUF_RESERVED_SPACE, 0, + COMPBUF_RESERVED_SPACE_64B, hubbub2->pixel_chunk_size / 32, + COMPBUF_RESERVED_SPACE_ZS, hubbub2->pixel_chunk_size / 128); + REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x17F); +} + +static void dcn32_program_det_size(struct hubbub *hubbub, int hubp_inst, unsigned int det_buffer_size_in_kbyte) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + + unsigned int det_size_segments = (det_buffer_size_in_kbyte + DCN32_CRB_SEGMENT_SIZE_KB - 1) / DCN32_CRB_SEGMENT_SIZE_KB; + + switch (hubp_inst) { + case 0: + REG_UPDATE(DCHUBBUB_DET0_CTRL, + DET0_SIZE, det_size_segments); + hubbub2->det0_size = det_size_segments; + break; + case 1: + REG_UPDATE(DCHUBBUB_DET1_CTRL, + DET1_SIZE, det_size_segments); + hubbub2->det1_size = det_size_segments; + break; + case 2: + REG_UPDATE(DCHUBBUB_DET2_CTRL, + DET2_SIZE, det_size_segments); + hubbub2->det2_size = det_size_segments; + break; + case 3: + REG_UPDATE(DCHUBBUB_DET3_CTRL, + DET3_SIZE, det_size_segments); + hubbub2->det3_size = det_size_segments; + break; + default: + break; + } + /* Should never be hit, if it is we have an erroneous hw config*/ + ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size + + hubbub2->det3_size + hubbub2->compbuf_size_segments <= hubbub2->crb_size_segs); +} + +static void dcn32_program_compbuf_size(struct hubbub *hubbub, unsigned int compbuf_size_kb, bool safe_to_increase) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + unsigned int compbuf_size_segments = (compbuf_size_kb + DCN32_CRB_SEGMENT_SIZE_KB - 1) / DCN32_CRB_SEGMENT_SIZE_KB; + + if (safe_to_increase || compbuf_size_segments <= hubbub2->compbuf_size_segments) { + if (compbuf_size_segments > hubbub2->compbuf_size_segments) { + REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100); + REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1, 100); + REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1, 100); + REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1, 100); + } + /* Should never be hit, if it is we have an erroneous hw config*/ + ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size + + hubbub2->det3_size + compbuf_size_segments <= hubbub2->crb_size_segs); + REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_segments); + REG_WAIT(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, compbuf_size_segments, 1, 100); + hubbub2->compbuf_size_segments = compbuf_size_segments; + } +} + +static uint32_t convert_and_clamp( + uint32_t wm_ns, + uint32_t refclk_mhz, + uint32_t clamp_value) +{ + uint32_t ret_val = 0; + ret_val = wm_ns * refclk_mhz; + + ret_val /= 1000; + + if (ret_val > clamp_value) + ret_val = clamp_value; + + return ret_val; +} + +static bool hubbub32_program_urgent_watermarks( + struct hubbub *hubbub, + struct dcn_watermark_set *watermarks, + unsigned int refclk_mhz, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + uint32_t prog_wm_value; + bool wm_pending = false; + + /* Repeat for water mark set A, B, C and D. */ + /* clock state A */ + if (safe_to_lower || watermarks->a.urgent_ns > hubbub2->watermarks.a.urgent_ns) { + hubbub2->watermarks.a.urgent_ns = watermarks->a.urgent_ns; + prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns, + refclk_mhz, 0x3fff); + REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value); + + DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.urgent_ns, prog_wm_value); + } else if (watermarks->a.urgent_ns < hubbub2->watermarks.a.urgent_ns) + wm_pending = true; + + /* determine the transfer time for a quantity of data for a particular requestor.*/ + if (safe_to_lower || watermarks->a.frac_urg_bw_flip + > hubbub2->watermarks.a.frac_urg_bw_flip) { + hubbub2->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip; + + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, + DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks->a.frac_urg_bw_flip); + } else if (watermarks->a.frac_urg_bw_flip + < hubbub2->watermarks.a.frac_urg_bw_flip) + wm_pending = true; + + if (safe_to_lower || watermarks->a.frac_urg_bw_nom + > hubbub2->watermarks.a.frac_urg_bw_nom) { + hubbub2->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom; + + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, + DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, watermarks->a.frac_urg_bw_nom); + } else if (watermarks->a.frac_urg_bw_nom + < hubbub2->watermarks.a.frac_urg_bw_nom) + wm_pending = true; + + if (safe_to_lower || watermarks->a.urgent_latency_ns > hubbub2->watermarks.a.urgent_latency_ns) { + hubbub2->watermarks.a.urgent_latency_ns = watermarks->a.urgent_latency_ns; + prog_wm_value = convert_and_clamp(watermarks->a.urgent_latency_ns, + refclk_mhz, 0x3fff); + REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0, + DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, prog_wm_value); + } else if (watermarks->a.urgent_latency_ns < hubbub2->watermarks.a.urgent_latency_ns) + wm_pending = true; + + /* clock state B */ + if (safe_to_lower || watermarks->b.urgent_ns > hubbub2->watermarks.b.urgent_ns) { + hubbub2->watermarks.b.urgent_ns = watermarks->b.urgent_ns; + prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns, + refclk_mhz, 0x3fff); + REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value); + + DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.urgent_ns, prog_wm_value); + } else if (watermarks->b.urgent_ns < hubbub2->watermarks.b.urgent_ns) + wm_pending = true; + + /* determine the transfer time for a quantity of data for a particular requestor.*/ + if (safe_to_lower || watermarks->b.frac_urg_bw_flip + > hubbub2->watermarks.b.frac_urg_bw_flip) { + hubbub2->watermarks.b.frac_urg_bw_flip = watermarks->b.frac_urg_bw_flip; + + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0, + DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, watermarks->b.frac_urg_bw_flip); + } else if (watermarks->b.frac_urg_bw_flip + < hubbub2->watermarks.b.frac_urg_bw_flip) + wm_pending = true; + + if (safe_to_lower || watermarks->b.frac_urg_bw_nom + > hubbub2->watermarks.b.frac_urg_bw_nom) { + hubbub2->watermarks.b.frac_urg_bw_nom = watermarks->b.frac_urg_bw_nom; + + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0, + DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, watermarks->b.frac_urg_bw_nom); + } else if (watermarks->b.frac_urg_bw_nom + < hubbub2->watermarks.b.frac_urg_bw_nom) + wm_pending = true; + + if (safe_to_lower || watermarks->b.urgent_latency_ns > hubbub2->watermarks.b.urgent_latency_ns) { + hubbub2->watermarks.b.urgent_latency_ns = watermarks->b.urgent_latency_ns; + prog_wm_value = convert_and_clamp(watermarks->b.urgent_latency_ns, + refclk_mhz, 0x3fff); + REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0, + DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, prog_wm_value); + } else if (watermarks->b.urgent_latency_ns < hubbub2->watermarks.b.urgent_latency_ns) + wm_pending = true; + + /* clock state C */ + if (safe_to_lower || watermarks->c.urgent_ns > hubbub2->watermarks.c.urgent_ns) { + hubbub2->watermarks.c.urgent_ns = watermarks->c.urgent_ns; + prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns, + refclk_mhz, 0x3fff); + REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value); + + DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.urgent_ns, prog_wm_value); + } else if (watermarks->c.urgent_ns < hubbub2->watermarks.c.urgent_ns) + wm_pending = true; + + /* determine the transfer time for a quantity of data for a particular requestor.*/ + if (safe_to_lower || watermarks->c.frac_urg_bw_flip + > hubbub2->watermarks.c.frac_urg_bw_flip) { + hubbub2->watermarks.c.frac_urg_bw_flip = watermarks->c.frac_urg_bw_flip; + + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0, + DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, watermarks->c.frac_urg_bw_flip); + } else if (watermarks->c.frac_urg_bw_flip + < hubbub2->watermarks.c.frac_urg_bw_flip) + wm_pending = true; + + if (safe_to_lower || watermarks->c.frac_urg_bw_nom + > hubbub2->watermarks.c.frac_urg_bw_nom) { + hubbub2->watermarks.c.frac_urg_bw_nom = watermarks->c.frac_urg_bw_nom; + + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0, + DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, watermarks->c.frac_urg_bw_nom); + } else if (watermarks->c.frac_urg_bw_nom + < hubbub2->watermarks.c.frac_urg_bw_nom) + wm_pending = true; + + if (safe_to_lower || watermarks->c.urgent_latency_ns > hubbub2->watermarks.c.urgent_latency_ns) { + hubbub2->watermarks.c.urgent_latency_ns = watermarks->c.urgent_latency_ns; + prog_wm_value = convert_and_clamp(watermarks->c.urgent_latency_ns, + refclk_mhz, 0x3fff); + REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, 0, + DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, prog_wm_value); + } else if (watermarks->c.urgent_latency_ns < hubbub2->watermarks.c.urgent_latency_ns) + wm_pending = true; + + /* clock state D */ + if (safe_to_lower || watermarks->d.urgent_ns > hubbub2->watermarks.d.urgent_ns) { + hubbub2->watermarks.d.urgent_ns = watermarks->d.urgent_ns; + prog_wm_value = convert_and_clamp(watermarks->d.urgent_ns, + refclk_mhz, 0x3fff); + REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value); + + DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.urgent_ns, prog_wm_value); + } else if (watermarks->d.urgent_ns < hubbub2->watermarks.d.urgent_ns) + wm_pending = true; + + /* determine the transfer time for a quantity of data for a particular requestor.*/ + if (safe_to_lower || watermarks->d.frac_urg_bw_flip + > hubbub2->watermarks.d.frac_urg_bw_flip) { + hubbub2->watermarks.d.frac_urg_bw_flip = watermarks->d.frac_urg_bw_flip; + + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0, + DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, watermarks->d.frac_urg_bw_flip); + } else if (watermarks->d.frac_urg_bw_flip + < hubbub2->watermarks.d.frac_urg_bw_flip) + wm_pending = true; + + if (safe_to_lower || watermarks->d.frac_urg_bw_nom + > hubbub2->watermarks.d.frac_urg_bw_nom) { + hubbub2->watermarks.d.frac_urg_bw_nom = watermarks->d.frac_urg_bw_nom; + + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0, + DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, watermarks->d.frac_urg_bw_nom); + } else if (watermarks->d.frac_urg_bw_nom + < hubbub2->watermarks.d.frac_urg_bw_nom) + wm_pending = true; + + if (safe_to_lower || watermarks->d.urgent_latency_ns > hubbub2->watermarks.d.urgent_latency_ns) { + hubbub2->watermarks.d.urgent_latency_ns = watermarks->d.urgent_latency_ns; + prog_wm_value = convert_and_clamp(watermarks->d.urgent_latency_ns, + refclk_mhz, 0x3fff); + REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, 0, + DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, prog_wm_value); + } else if (watermarks->d.urgent_latency_ns < hubbub2->watermarks.d.urgent_latency_ns) + wm_pending = true; + + return wm_pending; +} + +static bool hubbub32_program_stutter_watermarks( + struct hubbub *hubbub, + struct dcn_watermark_set *watermarks, + unsigned int refclk_mhz, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + uint32_t prog_wm_value; + bool wm_pending = false; + + /* clock state A */ + if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns + > hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) { + hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = + watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns; + prog_wm_value = convert_and_clamp( + watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0xffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + } else if (watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns + < hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) + wm_pending = true; + + if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_ns + > hubbub2->watermarks.a.cstate_pstate.cstate_exit_ns) { + hubbub2->watermarks.a.cstate_pstate.cstate_exit_ns = + watermarks->a.cstate_pstate.cstate_exit_ns; + prog_wm_value = convert_and_clamp( + watermarks->a.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0xffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value); + } else if (watermarks->a.cstate_pstate.cstate_exit_ns + < hubbub2->watermarks.a.cstate_pstate.cstate_exit_ns) + wm_pending = true; + + /* clock state B */ + if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns + > hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) { + hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = + watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns; + prog_wm_value = convert_and_clamp( + watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0xffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + } else if (watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns + < hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) + wm_pending = true; + + if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_ns + > hubbub2->watermarks.b.cstate_pstate.cstate_exit_ns) { + hubbub2->watermarks.b.cstate_pstate.cstate_exit_ns = + watermarks->b.cstate_pstate.cstate_exit_ns; + prog_wm_value = convert_and_clamp( + watermarks->b.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0xffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value); + } else if (watermarks->b.cstate_pstate.cstate_exit_ns + < hubbub2->watermarks.b.cstate_pstate.cstate_exit_ns) + wm_pending = true; + + /* clock state C */ + if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns + > hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) { + hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = + watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns; + prog_wm_value = convert_and_clamp( + watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0xffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + } else if (watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns + < hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) + wm_pending = true; + + if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_ns + > hubbub2->watermarks.c.cstate_pstate.cstate_exit_ns) { + hubbub2->watermarks.c.cstate_pstate.cstate_exit_ns = + watermarks->c.cstate_pstate.cstate_exit_ns; + prog_wm_value = convert_and_clamp( + watermarks->c.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0xffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value); + } else if (watermarks->c.cstate_pstate.cstate_exit_ns + < hubbub2->watermarks.c.cstate_pstate.cstate_exit_ns) + wm_pending = true; + + /* clock state D */ + if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns + > hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) { + hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = + watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns; + prog_wm_value = convert_and_clamp( + watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0xffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + } else if (watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns + < hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) + wm_pending = true; + + if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_ns + > hubbub2->watermarks.d.cstate_pstate.cstate_exit_ns) { + hubbub2->watermarks.d.cstate_pstate.cstate_exit_ns = + watermarks->d.cstate_pstate.cstate_exit_ns; + prog_wm_value = convert_and_clamp( + watermarks->d.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0xffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value); + } else if (watermarks->d.cstate_pstate.cstate_exit_ns + < hubbub2->watermarks.d.cstate_pstate.cstate_exit_ns) + wm_pending = true; + + return wm_pending; +} + + +static bool hubbub32_program_pstate_watermarks( + struct hubbub *hubbub, + struct dcn_watermark_set *watermarks, + unsigned int refclk_mhz, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + uint32_t prog_wm_value; + + bool wm_pending = false; + + /* Section for UCLK_PSTATE_CHANGE_WATERMARKS */ + /* clock state A */ + if (safe_to_lower || watermarks->a.cstate_pstate.pstate_change_ns + > hubbub2->watermarks.a.cstate_pstate.pstate_change_ns) { + hubbub2->watermarks.a.cstate_pstate.pstate_change_ns = + watermarks->a.cstate_pstate.pstate_change_ns; + prog_wm_value = convert_and_clamp( + watermarks->a.cstate_pstate.pstate_change_ns, + refclk_mhz, 0xffff); + REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, 0, + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value); + } else if (watermarks->a.cstate_pstate.pstate_change_ns + < hubbub2->watermarks.a.cstate_pstate.pstate_change_ns) + wm_pending = true; + + /* clock state B */ + if (safe_to_lower || watermarks->b.cstate_pstate.pstate_change_ns + > hubbub2->watermarks.b.cstate_pstate.pstate_change_ns) { + hubbub2->watermarks.b.cstate_pstate.pstate_change_ns = + watermarks->b.cstate_pstate.pstate_change_ns; + prog_wm_value = convert_and_clamp( + watermarks->b.cstate_pstate.pstate_change_ns, + refclk_mhz, 0xffff); + REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, 0, + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value); + } else if (watermarks->b.cstate_pstate.pstate_change_ns + < hubbub2->watermarks.b.cstate_pstate.pstate_change_ns) + wm_pending = true; + + /* clock state C */ + if (safe_to_lower || watermarks->c.cstate_pstate.pstate_change_ns + > hubbub2->watermarks.c.cstate_pstate.pstate_change_ns) { + hubbub2->watermarks.c.cstate_pstate.pstate_change_ns = + watermarks->c.cstate_pstate.pstate_change_ns; + prog_wm_value = convert_and_clamp( + watermarks->c.cstate_pstate.pstate_change_ns, + refclk_mhz, 0xffff); + REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, 0, + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value); + } else if (watermarks->c.cstate_pstate.pstate_change_ns + < hubbub2->watermarks.c.cstate_pstate.pstate_change_ns) + wm_pending = true; + + /* clock state D */ + if (safe_to_lower || watermarks->d.cstate_pstate.pstate_change_ns + > hubbub2->watermarks.d.cstate_pstate.pstate_change_ns) { + hubbub2->watermarks.d.cstate_pstate.pstate_change_ns = + watermarks->d.cstate_pstate.pstate_change_ns; + prog_wm_value = convert_and_clamp( + watermarks->d.cstate_pstate.pstate_change_ns, + refclk_mhz, 0xffff); + REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, 0, + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value); + } else if (watermarks->d.cstate_pstate.pstate_change_ns + < hubbub2->watermarks.d.cstate_pstate.pstate_change_ns) + wm_pending = true; + + /* Section for FCLK_PSTATE_CHANGE_WATERMARKS */ + /* clock state A */ + if (safe_to_lower || watermarks->a.cstate_pstate.fclk_pstate_change_ns + > hubbub2->watermarks.a.cstate_pstate.fclk_pstate_change_ns) { + hubbub2->watermarks.a.cstate_pstate.fclk_pstate_change_ns = + watermarks->a.cstate_pstate.fclk_pstate_change_ns; + prog_wm_value = convert_and_clamp( + watermarks->a.cstate_pstate.fclk_pstate_change_ns, + refclk_mhz, 0xffff); + REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, 0, + DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("FCLK_CHANGE_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->a.cstate_pstate.fclk_pstate_change_ns, prog_wm_value); + } else if (watermarks->a.cstate_pstate.fclk_pstate_change_ns + < hubbub2->watermarks.a.cstate_pstate.fclk_pstate_change_ns) + wm_pending = true; + + /* clock state B */ + if (safe_to_lower || watermarks->b.cstate_pstate.fclk_pstate_change_ns + > hubbub2->watermarks.b.cstate_pstate.fclk_pstate_change_ns) { + hubbub2->watermarks.b.cstate_pstate.fclk_pstate_change_ns = + watermarks->b.cstate_pstate.fclk_pstate_change_ns; + prog_wm_value = convert_and_clamp( + watermarks->b.cstate_pstate.fclk_pstate_change_ns, + refclk_mhz, 0xffff); + REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, 0, + DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("FCLK_CHANGE_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->b.cstate_pstate.fclk_pstate_change_ns, prog_wm_value); + } else if (watermarks->b.cstate_pstate.fclk_pstate_change_ns + < hubbub2->watermarks.b.cstate_pstate.fclk_pstate_change_ns) + wm_pending = true; + + /* clock state C */ + if (safe_to_lower || watermarks->c.cstate_pstate.fclk_pstate_change_ns + > hubbub2->watermarks.c.cstate_pstate.fclk_pstate_change_ns) { + hubbub2->watermarks.c.cstate_pstate.fclk_pstate_change_ns = + watermarks->c.cstate_pstate.fclk_pstate_change_ns; + prog_wm_value = convert_and_clamp( + watermarks->c.cstate_pstate.fclk_pstate_change_ns, + refclk_mhz, 0xffff); + REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, 0, + DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("FCLK_CHANGE_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->c.cstate_pstate.fclk_pstate_change_ns, prog_wm_value); + } else if (watermarks->c.cstate_pstate.fclk_pstate_change_ns + < hubbub2->watermarks.c.cstate_pstate.fclk_pstate_change_ns) + wm_pending = true; + + /* clock state D */ + if (safe_to_lower || watermarks->d.cstate_pstate.fclk_pstate_change_ns + > hubbub2->watermarks.d.cstate_pstate.fclk_pstate_change_ns) { + hubbub2->watermarks.d.cstate_pstate.fclk_pstate_change_ns = + watermarks->d.cstate_pstate.fclk_pstate_change_ns; + prog_wm_value = convert_and_clamp( + watermarks->d.cstate_pstate.fclk_pstate_change_ns, + refclk_mhz, 0xffff); + REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, 0, + DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("FCLK_CHANGE_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->d.cstate_pstate.fclk_pstate_change_ns, prog_wm_value); + } else if (watermarks->d.cstate_pstate.fclk_pstate_change_ns + < hubbub2->watermarks.d.cstate_pstate.fclk_pstate_change_ns) + wm_pending = true; + + return wm_pending; +} + + +static bool hubbub32_program_usr_watermarks( + struct hubbub *hubbub, + struct dcn_watermark_set *watermarks, + unsigned int refclk_mhz, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + uint32_t prog_wm_value; + + bool wm_pending = false; + + /* clock state A */ + if (safe_to_lower || watermarks->a.usr_retraining_ns + > hubbub2->watermarks.a.usr_retraining_ns) { + hubbub2->watermarks.a.usr_retraining_ns = watermarks->a.usr_retraining_ns; + prog_wm_value = convert_and_clamp( + watermarks->a.usr_retraining_ns, + refclk_mhz, 0x3fff); + REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, 0, + DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("USR_RETRAINING_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->a.usr_retraining_ns, prog_wm_value); + } else if (watermarks->a.usr_retraining_ns + < hubbub2->watermarks.a.usr_retraining_ns) + wm_pending = true; + + /* clock state B */ + if (safe_to_lower || watermarks->b.usr_retraining_ns + > hubbub2->watermarks.b.usr_retraining_ns) { + hubbub2->watermarks.b.usr_retraining_ns = watermarks->b.usr_retraining_ns; + prog_wm_value = convert_and_clamp( + watermarks->b.usr_retraining_ns, + refclk_mhz, 0x3fff); + REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, 0, + DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("USR_RETRAINING_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->b.usr_retraining_ns, prog_wm_value); + } else if (watermarks->b.usr_retraining_ns + < hubbub2->watermarks.b.usr_retraining_ns) + wm_pending = true; + + /* clock state C */ + if (safe_to_lower || watermarks->c.usr_retraining_ns + > hubbub2->watermarks.c.usr_retraining_ns) { + hubbub2->watermarks.c.usr_retraining_ns = + watermarks->c.usr_retraining_ns; + prog_wm_value = convert_and_clamp( + watermarks->c.usr_retraining_ns, + refclk_mhz, 0x3fff); + REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, 0, + DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("USR_RETRAINING_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->c.usr_retraining_ns, prog_wm_value); + } else if (watermarks->c.usr_retraining_ns + < hubbub2->watermarks.c.usr_retraining_ns) + wm_pending = true; + + /* clock state D */ + if (safe_to_lower || watermarks->d.usr_retraining_ns + > hubbub2->watermarks.d.usr_retraining_ns) { + hubbub2->watermarks.d.usr_retraining_ns = + watermarks->d.usr_retraining_ns; + prog_wm_value = convert_and_clamp( + watermarks->d.usr_retraining_ns, + refclk_mhz, 0x3fff); + REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, 0, + DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("USR_RETRAINING_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->d.usr_retraining_ns, prog_wm_value); + } else if (watermarks->d.usr_retraining_ns + < hubbub2->watermarks.d.usr_retraining_ns) + wm_pending = true; + + return wm_pending; +} + +void hubbub32_force_usr_retraining_allow(struct hubbub *hubbub, bool allow) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + + /* + * DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE = 1 means enabling forcing value + * DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE = 1 or 0, means value to be forced when force enable + */ + + REG_UPDATE_2(DCHUBBUB_ARB_USR_RETRAINING_CNTL, + DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE, allow, + DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE, allow); +} + +static bool hubbub32_program_watermarks( + struct hubbub *hubbub, + struct dcn_watermark_set *watermarks, + unsigned int refclk_mhz, + bool safe_to_lower) +{ + bool wm_pending = false; + + if (hubbub32_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) + wm_pending = true; + + if (hubbub32_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) + wm_pending = true; + + if (hubbub32_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) + wm_pending = true; + + if (hubbub32_program_usr_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) + wm_pending = true; + + /* + * The DCHub arbiter has a mechanism to dynamically rate limit the DCHub request stream to the fabric. + * If the memory controller is fully utilized and the DCHub requestors are + * well ahead of their amortized schedule, then it is safe to prevent the next winner + * from being committed and sent to the fabric. + * The utilization of the memory controller is approximated by ensuring that + * the number of outstanding requests is greater than a threshold specified + * by the ARB_MIN_REQ_OUTSTANDING. To determine that the DCHub requestors are well ahead of the amortized schedule, + * the slack of the next winner is compared with the ARB_SAT_LEVEL in DLG RefClk cycles. + * + * TODO: Revisit request limit after figure out right number. request limit for RM isn't decided yet, set maximum value (0x1FF) + * to turn off it for now. + */ + /*REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, + DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz); + REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, + DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);*/ + + hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); + + hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow); + + return wm_pending; +} + +/* Copy values from WM set A to all other sets */ +void hubbub32_init_watermarks(struct hubbub *hubbub) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + uint32_t reg; + + reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); + REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg); + REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg); + REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg); + + reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A); + REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg); + REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg); + REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg); + + reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A); + REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg); + REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg); + REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg); + + reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A); + REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg); + REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg); + REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg); + + reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg); + + reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg); + + reg = REG_READ(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A); + REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, reg); + REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, reg); + REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, reg); + + reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A); + REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, reg); + REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, reg); + REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, reg); + + reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A); + REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, reg); + REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, reg); + REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, reg); +} + +void hubbub32_wm_read_state(struct hubbub *hubbub, + struct dcn_hubbub_wm *wm) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + struct dcn_hubbub_wm_set *s; + + memset(wm, 0, sizeof(struct dcn_hubbub_wm)); + + s = &wm->sets[0]; + s->wm_set = 0; + REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, &s->data_urgent); + + REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, &s->sr_enter); + + REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, &s->sr_exit); + + REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, &s->dram_clk_chanage); + + REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, + DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, &s->usr_retrain); + + REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, + DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, &s->fclk_pstate_change); + + s = &wm->sets[1]; + s->wm_set = 1; + REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, &s->data_urgent); + + REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, &s->sr_enter); + + REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, &s->sr_exit); + + REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, &s->dram_clk_chanage); + + REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, + DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, &s->usr_retrain); + + REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, + DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, &s->fclk_pstate_change); + + s = &wm->sets[2]; + s->wm_set = 2; + REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, &s->data_urgent); + + REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, &s->sr_enter); + + REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, &s->sr_exit); + + REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, &s->dram_clk_chanage); + + REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, + DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, &s->usr_retrain); + + REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, + DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, &s->fclk_pstate_change); + + s = &wm->sets[3]; + s->wm_set = 3; + REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, &s->data_urgent); + + REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, &s->sr_enter); + + REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, &s->sr_exit); + + REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, &s->dram_clk_chanage); + + REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, + DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, &s->usr_retrain); + + REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, + DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, &s->fclk_pstate_change); +} + +void hubbub32_force_wm_propagate_to_pipes(struct hubbub *hubbub) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + uint32_t refclk_mhz = hubbub->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; + uint32_t prog_wm_value = convert_and_clamp(hubbub2->watermarks.a.urgent_ns, + refclk_mhz, 0x3fff); + + REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value); +} + +static const struct hubbub_funcs hubbub32_funcs = { + .update_dchub = hubbub2_update_dchub, + .init_dchub_sys_ctx = hubbub3_init_dchub_sys_ctx, + .init_vm_ctx = hubbub2_init_vm_ctx, + .dcc_support_swizzle = hubbub3_dcc_support_swizzle, + .dcc_support_pixel_format = hubbub2_dcc_support_pixel_format, + .get_dcc_compression_cap = hubbub3_get_dcc_compression_cap, + .wm_read_state = hubbub32_wm_read_state, + .get_dchub_ref_freq = hubbub2_get_dchub_ref_freq, + .program_watermarks = hubbub32_program_watermarks, + .allow_self_refresh_control = hubbub1_allow_self_refresh_control, + .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled, + .force_wm_propagate_to_pipes = hubbub32_force_wm_propagate_to_pipes, + .force_pstate_change_control = hubbub3_force_pstate_change_control, + .init_watermarks = hubbub32_init_watermarks, + .program_det_size = dcn32_program_det_size, + .program_compbuf_size = dcn32_program_compbuf_size, + .init_crb = dcn32_init_crb, + .hubbub_read_state = hubbub2_read_state, + .force_usr_retraining_allow = hubbub32_force_usr_retraining_allow, +}; + +void hubbub32_construct(struct dcn20_hubbub *hubbub2, + struct dc_context *ctx, + const struct dcn_hubbub_registers *hubbub_regs, + const struct dcn_hubbub_shift *hubbub_shift, + const struct dcn_hubbub_mask *hubbub_mask, + int det_size_kb, + int pixel_chunk_size_kb, + int config_return_buffer_size_kb) +{ + hubbub2->base.ctx = ctx; + hubbub2->base.funcs = &hubbub32_funcs; + hubbub2->regs = hubbub_regs; + hubbub2->shifts = hubbub_shift; + hubbub2->masks = hubbub_mask; + + hubbub2->debug_test_index_pstate = 0xB; + hubbub2->detile_buf_size = det_size_kb * 1024; + hubbub2->pixel_chunk_size = pixel_chunk_size_kb * 1024; + hubbub2->crb_size_segs = config_return_buffer_size_kb / DCN32_CRB_SEGMENT_SIZE_KB; +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h new file mode 100644 index 000000000000..8d3ea8ee5b3b --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h @@ -0,0 +1,172 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_HUBBUB_DCN32_H__ +#define __DC_HUBBUB_DCN32_H__ + +#include "dcn21/dcn21_hubbub.h" + +#define HUBBUB_REG_LIST_DCN32(id)\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ + SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ + SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ + SR(DCHUBBUB_ARB_SAT_LEVEL),\ + SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ + SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ + SR(DCHUBBUB_SOFT_RESET),\ + SR(DCHUBBUB_CRC_CTRL), \ + SR(DCN_VM_FB_LOCATION_BASE),\ + SR(DCN_VM_FB_LOCATION_TOP),\ + SR(DCN_VM_FB_OFFSET),\ + SR(DCN_VM_AGP_BOT),\ + SR(DCN_VM_AGP_TOP),\ + SR(DCN_VM_AGP_BASE),\ + HUBBUB_SR_WATERMARK_REG_LIST(), \ + SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\ + SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\ + SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\ + SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\ + SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\ + SR(DCHUBBUB_DET0_CTRL),\ + SR(DCHUBBUB_DET1_CTRL),\ + SR(DCHUBBUB_DET2_CTRL),\ + SR(DCHUBBUB_DET3_CTRL),\ + SR(DCHUBBUB_COMPBUF_CTRL),\ + SR(COMPBUF_RESERVED_SPACE),\ + SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL),\ + SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A),\ + SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B),\ + SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C),\ + SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D),\ + SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A),\ + SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B),\ + SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C),\ + SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D),\ + SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A),\ + SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B),\ + SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C),\ + SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D),\ + SR(DCN_VM_FAULT_ADDR_MSB),\ + SR(DCN_VM_FAULT_ADDR_LSB),\ + SR(DCN_VM_FAULT_CNTL),\ + SR(DCN_VM_FAULT_STATUS) + +#define HUBBUB_MASK_SH_LIST_DCN32(mask_sh)\ + HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_SOFT_RESET, DCHUBBUB_GLOBAL_SOFT_RESET, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, mask_sh), \ + HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \ + HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ + HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \ + HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \ + HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \ + HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \ + HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \ + HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET3_CTRL, DET3_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_64B, mask_sh),\ + HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_ZS, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_ADDR_MSB, DCN_VM_FAULT_ADDR_MSB, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_ADDR_LSB, DCN_VM_FAULT_ADDR_LSB, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_CLEAR, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_INTERRUPT_ENABLE, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_RANGE_FAULT_DISABLE, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_PRQ_FAULT_DISABLE, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh) + + +void hubbub32_construct(struct dcn20_hubbub *hubbub2, + struct dc_context *ctx, + const struct dcn_hubbub_registers *hubbub_regs, + const struct dcn_hubbub_shift *hubbub_shift, + const struct dcn_hubbub_mask *hubbub_mask, + int det_size_kb, + int pixel_chunk_size_kb, + int config_return_buffer_size_kb); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c new file mode 100644 index 000000000000..0a7d64306481 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c @@ -0,0 +1,148 @@ +/* + * Copyright 2012-20 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" +#include "dce_calcs.h" +#include "reg_helper.h" +#include "basics/conversion.h" +#include "dcn32_hubp.h" + +#define REG(reg)\ + hubp2->hubp_regs->reg + +#define CTX \ + hubp2->base.ctx + +#undef FN +#define FN(reg_name, field_name) \ + hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name + +void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + REG_UPDATE_2(UCLK_PSTATE_FORCE, + DATA_UCLK_PSTATE_FORCE_EN, pstate_disallow, + DATA_UCLK_PSTATE_FORCE_VALUE, 0); +} + +void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + // Also cache cursor in MALL if using MALL for SS + REG_UPDATE_2(DCHUBP_MALL_CONFIG, USE_MALL_SEL, mall_sel, + USE_MALL_FOR_CURSOR, mall_sel == 2 ? 1 : 0); +} + +void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + REG_UPDATE(DCHUBP_VMPG_CONFIG, FORCE_ONE_ROW_FOR_FRAME, enable); + + /* Programming guide suggests CURSOR_REQ_MODE = 1 for SubVP: + * For Pstate change using the MALL with sub-viewport buffering, + * the cursor does not use the MALL (USE_MALL_FOR_CURSOR is ignored) + * and sub-viewport positioning by Display FW has to avoid the cursor + * requests to DRAM (set CURSOR_REQ_MODE = 1 to minimize this exclusion). + * + * CURSOR_REQ_MODE = 1 begins fetching cursor data at the beginning of display prefetch. + * Setting this should allow the sub-viewport position to always avoid the cursor because + * we do not allow the sub-viewport region to overlap with display prefetch (i.e. during blank). + */ + REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, enable); +} + +void hubp32_phantom_hubp_post_enable(struct hubp *hubp) +{ + uint32_t reg_val; + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, 1); + reg_val = REG_READ(DCHUBP_CNTL); + if (reg_val) { + /* init sequence workaround: in case HUBP is + * power gated, this wait would timeout. + * + * we just wrote reg_val to non-0, if it stay 0 + * it means HUBP is gated + */ + REG_WAIT(DCHUBP_CNTL, + HUBP_NO_OUTSTANDING_REQ, 1, + 1, 200); + } +} + +static struct hubp_funcs dcn32_hubp_funcs = { + .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, + .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, + .hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr, + .hubp_program_surface_config = hubp3_program_surface_config, + .hubp_is_flip_pending = hubp2_is_flip_pending, + .hubp_setup = hubp3_setup, + .hubp_setup_interdependent = hubp2_setup_interdependent, + .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings, + .set_blank = hubp2_set_blank, + .dcc_control = hubp3_dcc_control, + .mem_program_viewport = min_set_viewport, + .set_cursor_attributes = hubp2_cursor_set_attributes, + .set_cursor_position = hubp2_cursor_set_position, + .hubp_clk_cntl = hubp2_clk_cntl, + .hubp_vtg_sel = hubp2_vtg_sel, + .dmdata_set_attributes = hubp3_dmdata_set_attributes, + .dmdata_load = hubp2_dmdata_load, + .dmdata_status_done = hubp2_dmdata_status_done, + .hubp_read_state = hubp3_read_state, + .hubp_clear_underflow = hubp2_clear_underflow, + .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, + .hubp_init = hubp3_init, + .set_unbounded_requesting = hubp31_set_unbounded_requesting, + .hubp_soft_reset = hubp31_soft_reset, + .hubp_in_blank = hubp1_in_blank, + .hubp_update_force_pstate_disallow = hubp32_update_force_pstate_disallow, + .phantom_hubp_post_enable = hubp32_phantom_hubp_post_enable, + .hubp_update_mall_sel = hubp32_update_mall_sel, + .hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering, + .hubp_set_flip_int = hubp1_set_flip_int +}; + +bool hubp32_construct( + struct dcn20_hubp *hubp2, + struct dc_context *ctx, + uint32_t inst, + const struct dcn_hubp2_registers *hubp_regs, + const struct dcn_hubp2_shift *hubp_shift, + const struct dcn_hubp2_mask *hubp_mask) +{ + hubp2->base.funcs = &dcn32_hubp_funcs; + hubp2->base.ctx = ctx; + hubp2->hubp_regs = hubp_regs; + hubp2->hubp_shift = hubp_shift; + hubp2->hubp_mask = hubp_mask; + hubp2->base.inst = inst; + hubp2->base.opp_id = OPP_ID_INVALID; + hubp2->base.mpcc_id = 0xf; + + return true; +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h new file mode 100644 index 000000000000..00b4211389c2 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h @@ -0,0 +1,69 @@ +/* + * Copyright 2012-20 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_HUBP_DCN32_H__ +#define __DC_HUBP_DCN32_H__ + +#include "dcn20/dcn20_hubp.h" +#include "dcn21/dcn21_hubp.h" +#include "dcn30/dcn30_hubp.h" +#include "dcn31/dcn31_hubp.h" + +#define HUBP_REG_LIST_DCN32(id)\ + HUBP_REG_LIST_DCN30(id),\ + SRI(DCHUBP_MALL_CONFIG, HUBP, id),\ + SRI(DCHUBP_VMPG_CONFIG, HUBP, id),\ + SRI(UCLK_PSTATE_FORCE, HUBPREQ, id) + +#define HUBP_MASK_SH_LIST_DCN32(mask_sh)\ + HUBP_MASK_SH_LIST_DCN31(mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, USE_MALL_SEL, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, VMPG_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, PTE_BUFFER_MODE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, BIGK_FRAGMENT_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, FORCE_ONE_ROW_FOR_FRAME, mask_sh),\ + HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, DATA_UCLK_PSTATE_FORCE_EN, mask_sh),\ + HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, DATA_UCLK_PSTATE_FORCE_VALUE, mask_sh),\ + HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, CURSOR_UCLK_PSTATE_FORCE_EN, mask_sh),\ + HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, CURSOR_UCLK_PSTATE_FORCE_VALUE, mask_sh) + +void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow); + +void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel); + +void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable); + +void hubp32_phantom_hubp_post_enable(struct hubp *hubp); + +bool hubp32_construct( + struct dcn20_hubp *hubp2, + struct dc_context *ctx, + uint32_t inst, + const struct dcn_hubp2_registers *hubp_regs, + const struct dcn_hubp2_shift *hubp_shift, + const struct dcn_hubp2_mask *hubp_mask); + +#endif /* __DC_HUBP_DCN32_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c new file mode 100644 index 000000000000..d0a222f1a09c --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c @@ -0,0 +1,891 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + + +#include "dm_services.h" +#include "dm_helpers.h" +#include "core_types.h" +#include "resource.h" +#include "dccg.h" +#include "dce/dce_hwseq.h" +#include "dcn30/dcn30_cm_common.h" +#include "reg_helper.h" +#include "abm.h" +#include "hubp.h" +#include "dchubbub.h" +#include "timing_generator.h" +#include "opp.h" +#include "ipp.h" +#include "mpc.h" +#include "mcif_wb.h" +#include "dc_dmub_srv.h" +#include "link_hwss.h" +#include "dpcd_defs.h" +#include "dcn32_hwseq.h" +#include "clk_mgr.h" +#include "dsc.h" +#include "dcn20/dcn20_optc.h" + +#define DC_LOGGER_INIT(logger) + +#define CTX \ + hws->ctx +#define REG(reg)\ + hws->regs->reg +#define DC_LOGGER \ + dc->ctx->logger + + +#undef FN +#define FN(reg_name, field_name) \ + hws->shifts->field_name, hws->masks->field_name + +void dcn32_dsc_pg_control( + struct dce_hwseq *hws, + unsigned int dsc_inst, + bool power_on) +{ + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + uint32_t org_ip_request_cntl = 0; + + if (hws->ctx->dc->debug.disable_dsc_power_gate) + return; + + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + + switch (dsc_inst) { + case 0: /* DSC0 */ + REG_UPDATE(DOMAIN16_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN16_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 1: /* DSC1 */ + REG_UPDATE(DOMAIN17_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN17_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 2: /* DSC2 */ + REG_UPDATE(DOMAIN18_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN18_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 3: /* DSC3 */ + REG_UPDATE(DOMAIN19_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN19_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); +} + + +void dcn32_enable_power_gating_plane( + struct dce_hwseq *hws, + bool enable) +{ + bool force_on = true; /* disable power gating */ + + if (enable) + force_on = false; + + /* DCHUBP0/1/2/3 */ + REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); + REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); + REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); + REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); + + /* DCS0/1/2/3 */ + REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); + REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); + REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); + REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); +} + +void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) +{ + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + + if (hws->ctx->dc->debug.disable_hubp_power_gate) + return; + + if (REG(DOMAIN0_PG_CONFIG) == 0) + return; + + switch (hubp_inst) { + case 0: + REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + break; + case 1: + REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + break; + case 2: + REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + break; + case 3: + REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } +} + +static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) +{ + int i; + + /* First, check no-memory-request case */ + for (i = 0; i < dc->current_state->stream_count; i++) { + if (dc->current_state->stream_status[i].plane_count) + /* Fail eligibility on a visible stream */ + break; + } + + if (i == dc->current_state->stream_count) + return true; + + return false; +} + +/* This function takes in the start address and surface size to be cached in CAB + * and calculates the total number of cache lines required to store the surface. + * The number of cache lines used for each surface is calculated independently of + * one another. For example, if there is a primary surface(1), meta surface(2), and + * cursor(3), this function should be called 3 times to calculate the number of cache + * lines used for each of those surfaces. + */ +static uint32_t dcn32_cache_lines_for_surface(struct dc *dc, uint32_t surface_size, uint64_t start_address) +{ + uint32_t lines_used = 1; + uint32_t num_cached_bytes = 0; + uint32_t remaining_size = 0; + uint32_t cache_line_size = dc->caps.cache_line_size; + + /* 1. Calculate surface size minus the number of bytes stored + * in the first cache line (all bytes in first cache line might + * not be fully used). + */ + num_cached_bytes = cache_line_size - (start_address % cache_line_size); + remaining_size = surface_size - num_cached_bytes; + + /* 2. Calculate number of cache lines that will be fully used with + * the remaining number of bytes to be stored. + */ + lines_used += (remaining_size / cache_line_size); + + /* 3. Check if we need an extra line due to the remaining size not being + * a multiple of CACHE_LINE_SIZE. + */ + if (remaining_size % cache_line_size > 0) + lines_used++; + + return lines_used; +} + +/* This function loops through every surface that needs to be cached in CAB for SS, + * and calculates the total number of ways required to store all surfaces (primary, + * meta, cursor). + */ +static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) +{ + uint8_t i, j; + struct dc_stream_state *stream = NULL; + struct dc_plane_state *plane = NULL; + uint32_t surface_size = 0; + uint32_t cursor_size = 0; + uint32_t cache_lines_used = 0; + uint32_t total_lines = 0; + uint32_t lines_per_way = 0; + uint32_t num_ways = 0; + + for (i = 0; i < ctx->stream_count; i++) { + stream = ctx->streams[i]; + + // Don't include PSR surface in the total surface size for CAB allocation + if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) + continue; + + if (ctx->stream_status[i].plane_count == 0) + continue; + + // For each stream, loop through each plane to calculate the number of cache + // lines required to store the surface in CAB + for (j = 0; j < ctx->stream_status[i].plane_count; j++) { + plane = ctx->stream_status[i].plane_states[j]; + + // Calculate total surface size + surface_size = plane->plane_size.surface_pitch * + plane->plane_size.surface_size.height * + (plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4); + + // Convert surface size + starting address to number of cache lines required + // (alignment accounted for) + cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size, + plane->address.grph.addr.quad_part); + + if (plane->address.grph.meta_addr.quad_part) { + // Meta surface + cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size, + plane->address.grph.meta_addr.quad_part); + } + } + + // Include cursor size for CAB allocation + if (stream->cursor_position.enable && plane->address.grph.cursor_cache_addr.quad_part) { + cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size; + switch (stream->cursor_attributes.color_format) { + case CURSOR_MODE_MONO: + cursor_size /= 2; + break; + case CURSOR_MODE_COLOR_1BIT_AND: + case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: + case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: + cursor_size *= 4; + break; + + case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: + case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: + cursor_size *= 8; + break; + } + cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size, + plane->address.grph.cursor_cache_addr.quad_part); + } + } + + // Convert number of cache lines required to number of ways + total_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size; + lines_per_way = total_lines / dc->caps.cache_num_ways; + num_ways = cache_lines_used / lines_per_way; + + if (cache_lines_used % lines_per_way > 0) + num_ways++; + + return num_ways; +} + +bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable) +{ + union dmub_rb_cmd cmd; + uint8_t ways; + + if (!dc->ctx->dmub_srv) + return false; + + if (enable) { + if (dc->current_state) { + + /* 1. Check no memory request case for CAB. + * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message + */ + if (dcn32_check_no_memory_request_for_cab(dc)) { + /* Enable no-memory-requests case */ + memset(&cmd, 0, sizeof(cmd)); + cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; + cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ; + cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); + + dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); + dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); + + return true; + } + + /* 2. Check if all surfaces can fit in CAB. + * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message + * and configure HUBP's to fetch from MALL + */ + ways = dcn32_calculate_cab_allocation(dc, dc->current_state); + if (ways <= dc->caps.cache_num_ways) { + memset(&cmd, 0, sizeof(cmd)); + cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; + cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB; + cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); + cmd.cab.cab_alloc_ways = ways; + + dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); + dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); + + return true; + } + + } + return false; + } + + /* Disable CAB */ + memset(&cmd, 0, sizeof(cmd)); + cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; + cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION; + cmd.cab.header.payload_bytes = + sizeof(cmd.cab) - sizeof(cmd.cab.header); + + dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); + dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); + dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); + + return false; +} + +/* Send DMCUB message with SubVP pipe info + * - For each pipe in context, populate payload with required SubVP information + * if the pipe is using SubVP for MCLK switch + * - This function must be called while the DMUB HW lock is acquired by driver + */ +void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context) +{ +/* + int i; + bool enable_subvp = false; + + if (!dc->ctx || !dc->ctx->dmub_srv) + return; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream && + pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) { + // There is at least 1 SubVP pipe, so enable SubVP + enable_subvp = true; + break; + } + } + dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp); +*/ +} + +static bool dcn32_set_mpc_shaper_3dlut( + struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) +{ + struct dpp *dpp_base = pipe_ctx->plane_res.dpp; + int mpcc_id = pipe_ctx->plane_res.hubp->inst; + struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; + bool result = false; + + const struct pwl_params *shaper_lut = NULL; + //get the shaper lut params + if (stream->func_shaper) { + if (stream->func_shaper->type == TF_TYPE_HWPWL) + shaper_lut = &stream->func_shaper->pwl; + else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { + cm_helper_translate_curve_to_hw_format( + stream->func_shaper, + &dpp_base->shaper_params, true); + shaper_lut = &dpp_base->shaper_params; + } + } + + if (stream->lut3d_func && + stream->lut3d_func->state.bits.initialized == 1) { + + result = mpc->funcs->program_3dlut(mpc, + &stream->lut3d_func->lut_3d, + mpcc_id); + + result = mpc->funcs->program_shaper(mpc, + shaper_lut, + mpcc_id); + } + + return result; +} +bool dcn32_set_output_transfer_func(struct dc *dc, + struct pipe_ctx *pipe_ctx, + const struct dc_stream_state *stream) +{ + int mpcc_id = pipe_ctx->plane_res.hubp->inst; + struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; + struct pwl_params *params = NULL; + bool ret = false; + + /* program OGAM or 3DLUT only for the top pipe*/ + if (pipe_ctx->top_pipe == NULL) { + /*program shaper and 3dlut in MPC*/ + ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream); + if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) { + if (stream->out_transfer_func->type == TF_TYPE_HWPWL) + params = &stream->out_transfer_func->pwl; + else if (pipe_ctx->stream->out_transfer_func->type == + TF_TYPE_DISTRIBUTED_POINTS && + cm3_helper_translate_curve_to_hw_format( + stream->out_transfer_func, + &mpc->blender_params, false)) + params = &mpc->blender_params; + /* there are no ROM LUTs in OUTGAM */ + if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) + BREAK_TO_DEBUGGER(); + } + } + + mpc->funcs->set_output_gamma(mpc, mpcc_id, params); + return ret; +} + +/* Program P-State force value according to if pipe is using SubVP or not: + * 1. Reset P-State force on all pipes first + * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB) + */ +void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context) +{ + int i; + int num_subvp = 0; + /* Unforce p-state for each pipe + */ + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct hubp *hubp = pipe->plane_res.hubp; + + if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) + hubp->funcs->hubp_update_force_pstate_disallow(hubp, false); + if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN) + num_subvp++; + } + + if (num_subvp == 0) + return; + + /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false. + */ + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + + if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { + struct hubp *hubp = pipe->plane_res.hubp; + + if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) + hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); + } + } +} + +/* Update MALL_SEL register based on if pipe / plane + * is a phantom pipe, main pipe, and if using MALL + * for SS. + */ +void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context) +{ + int i; + unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context); + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct hubp *hubp = pipe->plane_res.hubp; + + if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) { + if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { + hubp->funcs->hubp_update_mall_sel(hubp, 1); + } else { + hubp->funcs->hubp_update_mall_sel(hubp, + num_ways <= dc->caps.cache_num_ways && + pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED ? 2 : 0); + } + } + } +} + +/* Program the sub-viewport pipe configuration after the main / phantom pipes + * have been programmed in hardware. + * 1. Update force P-State for all the main pipes (disallow P-state) + * 2. Update MALL_SEL register + * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes + */ +void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context) +{ + int i; + struct dce_hwseq *hws = dc->hwseq; + // Update force P-state for each pipe accordingly + if (hws && hws->funcs.subvp_update_force_pstate) + hws->funcs.subvp_update_force_pstate(dc, context); + + // Update MALL_SEL register for each pipe + if (hws && hws->funcs.update_mall_sel) + hws->funcs.update_mall_sel(dc, context); + + // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct hubp *hubp = pipe->plane_res.hubp; + + if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) { + if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) { + hubp->funcs->hubp_prepare_subvp_buffering(hubp, true); + } else { + hubp->funcs->hubp_prepare_subvp_buffering(hubp, false); + } + } + } +} + +void dcn32_init_hw(struct dc *dc) +{ + struct abm **abms = dc->res_pool->multiple_abms; + struct dce_hwseq *hws = dc->hwseq; + struct dc_bios *dcb = dc->ctx->dc_bios; + struct resource_pool *res_pool = dc->res_pool; + int i; + int edp_num; + uint32_t backlight = MAX_BACKLIGHT_LEVEL; + + dc->debug.disable_idle_power_optimizations = true; + if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) + dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); + + // Initialize the dccg + if (res_pool->dccg->funcs->dccg_init) + res_pool->dccg->funcs->dccg_init(res_pool->dccg); + + if (!dcb->funcs->is_accelerated_mode(dcb)) { + hws->funcs.bios_golden_init(dc); + hws->funcs.disable_vga(dc->hwseq); + } + + // Set default OPTC memory power states + if (dc->debug.enable_mem_low_power.bits.optc) { + // Shutdown when unassigned and light sleep in VBLANK + REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); + } + + if (dc->debug.enable_mem_low_power.bits.vga) { + // Power down VGA memory + REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); + } + + if (dc->ctx->dc_bios->fw_info_valid) { + res_pool->ref_clocks.xtalin_clock_inKhz = + dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; + + if (res_pool->dccg && res_pool->hubbub) { + (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, + dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, + &res_pool->ref_clocks.dccg_ref_clock_inKhz); + + (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, + res_pool->ref_clocks.dccg_ref_clock_inKhz, + &res_pool->ref_clocks.dchub_ref_clock_inKhz); + } else { + // Not all ASICs have DCCG sw component + res_pool->ref_clocks.dccg_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + res_pool->ref_clocks.dchub_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + } + } else + ASSERT_CRITICAL(false); + + for (i = 0; i < dc->link_count; i++) { + /* Power up AND update implementation according to the + * required signal (which may be different from the + * default signal on connector). + */ + struct dc_link *link = dc->links[i]; + + link->link_enc->funcs->hw_init(link->link_enc); + + /* Check for enabled DIG to identify enabled display */ + if (link->link_enc->funcs->is_dig_enabled && + link->link_enc->funcs->is_dig_enabled(link->link_enc)) + link->link_status.link_active = true; + } + + /* Power gate DSCs */ + for (i = 0; i < res_pool->res_cap->num_dsc; i++) + if (hws->funcs.dsc_pg_control != NULL) + hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); + + /* we want to turn off all dp displays before doing detection */ + dc_link_blank_all_dp_displays(dc); + + /* If taking control over from VBIOS, we may want to optimize our first + * mode set, so we need to skip powering down pipes until we know which + * pipes we want to use. + * Otherwise, if taking control is not possible, we need to power + * everything down. + */ + if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) { + hws->funcs.init_pipes(dc, dc->current_state); + if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) + dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, + !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); + } + + /* In headless boot cases, DIG may be turned + * on which causes HW/SW discrepancies. + * To avoid this, power down hardware on boot + * if DIG is turned on and seamless boot not enabled + */ + if (dc->config.power_down_display_on_boot) { + struct dc_link *edp_links[MAX_NUM_EDP]; + struct dc_link *edp_link; + + get_edp_links(dc, edp_links, &edp_num); + if (edp_num) { + for (i = 0; i < edp_num; i++) { + edp_link = edp_links[i]; + if (edp_link->link_enc->funcs->is_dig_enabled && + edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && + dc->hwss.edp_backlight_control && + dc->hwss.power_down && + dc->hwss.edp_power_control) { + dc->hwss.edp_backlight_control(edp_link, false); + dc->hwss.power_down(dc); + dc->hwss.edp_power_control(edp_link, false); + } + } + } else { + for (i = 0; i < dc->link_count; i++) { + struct dc_link *link = dc->links[i]; + + if (link->link_enc->funcs->is_dig_enabled && + link->link_enc->funcs->is_dig_enabled(link->link_enc) && + dc->hwss.power_down) { + dc->hwss.power_down(dc); + break; + } + + } + } + } + + for (i = 0; i < res_pool->audio_count; i++) { + struct audio *audio = res_pool->audios[i]; + + audio->funcs->hw_init(audio); + } + + for (i = 0; i < dc->link_count; i++) { + struct dc_link *link = dc->links[i]; + + if (link->panel_cntl) + backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (abms[i] != NULL && abms[i]->funcs != NULL) + abms[i]->funcs->abm_init(abms[i], backlight); + } + + /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ + REG_WRITE(DIO_MEM_PWR_CTRL, 0); + + if (!dc->debug.disable_clock_gate) { + /* enable all DCN clock gating */ + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); + + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + + REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); + } + if (hws->funcs.enable_power_gating_plane) + hws->funcs.enable_power_gating_plane(dc->hwseq, true); + + if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) + dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); + + if (dc->clk_mgr->funcs->notify_wm_ranges) + dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); + + if (dc->clk_mgr->funcs->set_hard_max_memclk) + dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); + + if (dc->res_pool->hubbub->funcs->force_pstate_change_control) + dc->res_pool->hubbub->funcs->force_pstate_change_control( + dc->res_pool->hubbub, false, false); + + if (dc->res_pool->hubbub->funcs->init_crb) + dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); + + // Get DMCUB capabilities + if (dc->ctx->dmub_srv) { + dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub); + dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; + } +} + +static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, + int opp_cnt) +{ + bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); + int flow_ctrl_cnt; + + if (opp_cnt >= 2) + hblank_halved = true; + + flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - + stream->timing.h_border_left - + stream->timing.h_border_right; + + if (hblank_halved) + flow_ctrl_cnt /= 2; + + /* ODM combine 4:1 case */ + if (opp_cnt == 4) + flow_ctrl_cnt /= 2; + + return flow_ctrl_cnt; +} + +static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) +{ + struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; + struct dc_stream_state *stream = pipe_ctx->stream; + struct pipe_ctx *odm_pipe; + int opp_cnt = 1; + + ASSERT(dsc); + for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) + opp_cnt++; + + if (enable) { + struct dsc_config dsc_cfg; + struct dsc_optc_config dsc_optc_cfg; + enum optc_dsc_mode optc_dsc_mode; + + /* Enable DSC hw block */ + dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; + dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; + dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; + dsc_cfg.color_depth = stream->timing.display_color_depth; + dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; + dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; + ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); + dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; + + dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); + dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); + for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { + struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; + + ASSERT(odm_dsc); + odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); + odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); + } + dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; + dsc_cfg.pic_width *= opp_cnt; + + optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; + + /* Enable DSC in OPTC */ + DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); + pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, + optc_dsc_mode, + dsc_optc_cfg.bytes_per_pixel, + dsc_optc_cfg.slice_width); + } else { + /* disable DSC in OPTC */ + pipe_ctx->stream_res.tg->funcs->set_dsc_config( + pipe_ctx->stream_res.tg, + OPTC_DSC_DISABLED, 0, 0); + + /* disable DSC block */ + dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); + for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { + ASSERT(odm_pipe->stream_res.dsc); + odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); + } + } +} + +void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) +{ + struct pipe_ctx *odm_pipe; + int opp_cnt = 1; + int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; + bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing)); + struct mpc_dwb_flow_control flow_control; + struct mpc *mpc = dc->res_pool->mpc; + int i; + + for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { + opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; + opp_cnt++; + } + + if (opp_cnt > 1) + pipe_ctx->stream_res.tg->funcs->set_odm_combine( + pipe_ctx->stream_res.tg, + opp_inst, opp_cnt, + &pipe_ctx->stream->timing); + else + pipe_ctx->stream_res.tg->funcs->set_odm_bypass( + pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); + + rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; + flow_control.flow_ctrl_mode = 0; + flow_control.flow_ctrl_cnt0 = 0x80; + flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt); + if (mpc->funcs->set_out_rate_control) { + for (i = 0; i < opp_cnt; ++i) { + mpc->funcs->set_out_rate_control( + mpc, opp_inst[i], + true, + rate_control_2x_pclk, + &flow_control); + } + } + + for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { + odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( + odm_pipe->stream_res.opp, + true); + } + + // Don't program pixel clock after link is already enabled +/* if (false == pipe_ctx->clock_source->funcs->program_pix_clk( + pipe_ctx->clock_source, + &pipe_ctx->stream_res.pix_clk_params, + &pipe_ctx->pll_settings)) { + BREAK_TO_DEBUGGER(); + }*/ + + if (pipe_ctx->stream_res.dsc) + update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); +} + diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h new file mode 100644 index 000000000000..737a7fac5cf9 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h @@ -0,0 +1,64 @@ +/* +* Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_HWSS_DCN32_H__ +#define __DC_HWSS_DCN32_H__ + +#include "hw_sequencer_private.h" + +struct dc; + +void dcn32_dsc_pg_control( + struct dce_hwseq *hws, + unsigned int dsc_inst, + bool power_on); + +void dcn32_enable_power_gating_plane( + struct dce_hwseq *hws, + bool enable); + +void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on); + +bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable); + +void dcn32_cab_for_ss_control(struct dc *dc, bool enable); + +void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context); + +bool dcn32_set_output_transfer_func(struct dc *dc, + struct pipe_ctx *pipe_ctx, + const struct dc_stream_state *stream); + +void dcn32_init_hw(struct dc *dc); + +void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context); + +void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context); + +void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context); + +void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); + +#endif /* __DC_HWSS_DCN32_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c new file mode 100644 index 000000000000..d1e3db1bc488 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c @@ -0,0 +1,155 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dce110/dce110_hw_sequencer.h" +#include "dcn10/dcn10_hw_sequencer.h" +#include "dcn20/dcn20_hwseq.h" +#include "dcn21/dcn21_hwseq.h" +#include "dcn30/dcn30_hwseq.h" +#include "dcn31/dcn31_hwseq.h" +#include "dcn32_hwseq.h" + +static const struct hw_sequencer_funcs dcn32_funcs = { + .program_gamut_remap = dcn10_program_gamut_remap, + .init_hw = dcn32_init_hw, + .apply_ctx_to_hw = dce110_apply_ctx_to_hw, + .apply_ctx_for_surface = NULL, + .program_front_end_for_ctx = dcn20_program_front_end_for_ctx, + .wait_for_pending_cleared = dcn10_wait_for_pending_cleared, + .post_unlock_program_front_end = dcn20_post_unlock_program_front_end, + .update_plane_addr = dcn20_update_plane_addr, + .update_dchub = dcn10_update_dchub, + .update_pending_status = dcn10_update_pending_status, + .program_output_csc = dcn20_program_output_csc, + .enable_accelerated_mode = dce110_enable_accelerated_mode, + .enable_timing_synchronization = dcn10_enable_timing_synchronization, + .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset, + .update_info_frame = dcn31_update_info_frame, + .send_immediate_sdp_message = dcn10_send_immediate_sdp_message, + .enable_stream = dcn20_enable_stream, + .disable_stream = dce110_disable_stream, + .unblank_stream = dcn20_unblank_stream, + .blank_stream = dce110_blank_stream, + .enable_audio_stream = dce110_enable_audio_stream, + .disable_audio_stream = dce110_disable_audio_stream, + .disable_plane = dcn20_disable_plane, + .pipe_control_lock = dcn20_pipe_control_lock, + .interdependent_update_lock = dcn10_lock_all_pipes, + .cursor_lock = dcn10_cursor_lock, + .prepare_bandwidth = dcn20_prepare_bandwidth, + .optimize_bandwidth = dcn20_optimize_bandwidth, + .update_bandwidth = dcn20_update_bandwidth, + .set_drr = dcn10_set_drr, + .get_position = dcn10_get_position, + .set_static_screen_control = dcn10_set_static_screen_control, + .setup_stereo = dcn10_setup_stereo, + .set_avmute = dcn30_set_avmute, + .log_hw_state = dcn10_log_hw_state, + .get_hw_state = dcn10_get_hw_state, + .clear_status_bits = dcn10_clear_status_bits, + .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, + .edp_backlight_control = dce110_edp_backlight_control, + .edp_power_control = dce110_edp_power_control, + .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, + .edp_wait_for_T12 = dce110_edp_wait_for_T12, + .set_cursor_position = dcn10_set_cursor_position, + .set_cursor_attribute = dcn10_set_cursor_attribute, + .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level, + .setup_periodic_interrupt = dcn10_setup_periodic_interrupt, + .set_clock = dcn10_set_clock, + .get_clock = dcn10_get_clock, + .program_triplebuffer = dcn20_program_triple_buffer, + .enable_writeback = dcn30_enable_writeback, + .disable_writeback = dcn30_disable_writeback, + .update_writeback = dcn30_update_writeback, + .mmhubbub_warmup = dcn30_mmhubbub_warmup, + .dmdata_status_done = dcn20_dmdata_status_done, + .program_dmdata_engine = dcn30_program_dmdata_engine, + .set_dmdata_attributes = dcn20_set_dmdata_attributes, + .init_sys_ctx = dcn20_init_sys_ctx, + .init_vm_ctx = dcn20_init_vm_ctx, + .set_flip_control_gsl = dcn20_set_flip_control_gsl, + .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, + .calc_vupdate_position = dcn10_calc_vupdate_position, + .apply_idle_power_optimizations = dcn32_apply_idle_power_optimizations, + .does_plane_fit_in_mall = dcn30_does_plane_fit_in_mall, + .set_backlight_level = dcn21_set_backlight_level, + .set_abm_immediate_disable = dcn21_set_abm_immediate_disable, + .hardware_release = dcn30_hardware_release, + .set_pipe = dcn21_set_pipe, + .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, + .get_dcc_en_bits = dcn10_get_dcc_en_bits, + .commit_subvp_config = dcn32_commit_subvp_config, + .update_visual_confirm_color = dcn20_update_visual_confirm_color, +}; + +static const struct hwseq_private_funcs dcn32_private_funcs = { + .init_pipes = dcn10_init_pipes, + .update_plane_addr = dcn20_update_plane_addr, + .plane_atomic_disconnect = dcn10_plane_atomic_disconnect, + .update_mpcc = dcn20_update_mpcc, + .set_input_transfer_func = dcn30_set_input_transfer_func, + .set_output_transfer_func = dcn32_set_output_transfer_func, + .power_down = dce110_power_down, + .enable_display_power_gating = dcn10_dummy_display_power_gating, + .blank_pixel_data = dcn20_blank_pixel_data, + .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap, + .enable_stream_timing = dcn20_enable_stream_timing, + .edp_backlight_control = dce110_edp_backlight_control, + .disable_stream_gating = dcn20_disable_stream_gating, + .enable_stream_gating = dcn20_enable_stream_gating, + .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt, + .did_underflow_occur = dcn10_did_underflow_occur, + .init_blank = dcn20_init_blank, + .disable_vga = dcn20_disable_vga, + .bios_golden_init = dcn10_bios_golden_init, + .plane_atomic_disable = dcn20_plane_atomic_disable, + .plane_atomic_power_down = dcn10_plane_atomic_power_down, + .enable_power_gating_plane = dcn32_enable_power_gating_plane, + .hubp_pg_control = dcn32_hubp_pg_control, + .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, + .update_odm = dcn32_update_odm, + .dsc_pg_control = dcn32_dsc_pg_control, + .set_hdr_multiplier = dcn10_set_hdr_multiplier, + .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, + .wait_for_blank_complete = dcn20_wait_for_blank_complete, + .dccg_init = dcn20_dccg_init, + .set_blend_lut = dcn30_set_blend_lut, + .set_shaper_3dlut = dcn20_set_shaper_3dlut, + .program_mall_pipe_config = dcn32_program_mall_pipe_config, + .subvp_update_force_pstate = dcn32_subvp_update_force_pstate, + .update_mall_sel = dcn32_update_mall_sel, +}; + +void dcn32_hw_sequencer_init_functions(struct dc *dc) +{ + dc->hwss = dcn32_funcs; + dc->hwseq->funcs = dcn32_private_funcs; + + if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + dc->hwss.init_hw = dcn20_fpga_init_hw; + dc->hwseq->funcs.init_pipes = NULL; + } +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.h new file mode 100644 index 000000000000..89a591eb2c23 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.h @@ -0,0 +1,33 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_DCN32_INIT_H__ +#define __DC_DCN32_INIT_H__ + +struct dc; + +void dcn32_hw_sequencer_init_functions(struct dc *dc); + +#endif /* __DC_DCN32_INIT_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c new file mode 100644 index 000000000000..adf93cc8359c --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c @@ -0,0 +1,239 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + + +#include "reg_helper.h" +#include "resource.h" +#include "mcif_wb.h" +#include "dcn32_mmhubbub.h" + + +#define REG(reg)\ + mcif_wb30->mcif_wb_regs->reg + +#define CTX \ + mcif_wb30->base.ctx + +#undef FN +#define FN(reg_name, field_name) \ + mcif_wb30->mcif_wb_shift->field_name, mcif_wb30->mcif_wb_mask->field_name + +#define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8 +#define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40 + +/* wbif programming guide: + * 1. set up wbif parameter: + * unsigned long long luma_address[4]; //4 frame buffer + * unsigned long long chroma_address[4]; + * unsigned int luma_pitch; + * unsigned int chroma_pitch; + * unsigned int warmup_pitch=0x10; //256B align, the page size is 4KB when it is 0x10 + * unsigned int slice_lines; //slice size + * unsigned int time_per_pixel; // time per pixel, in ns + * unsigned int arbitration_slice; // 0: 2048 bytes 1: 4096 bytes 2: 8192 Bytes + * unsigned int max_scaled_time; // used for QOS generation + * unsigned int swlock=0x0; + * unsigned int cli_watermark[4]; //4 group urgent watermark + * unsigned int pstate_watermark[4]; //4 group pstate watermark + * unsigned int sw_int_en; // Software interrupt enable, frame end and overflow + * unsigned int sw_slice_int_en; // slice end interrupt enable + * unsigned int sw_overrun_int_en; // overrun error interrupt enable + * unsigned int vce_int_en; // VCE interrupt enable, frame end and overflow + * unsigned int vce_slice_int_en; // VCE slice end interrupt enable, frame end and overflow + * + * 2. configure wbif register + * a. call mmhubbub_config_wbif() + * + * 3. Enable wbif + * call set_wbif_bufmgr_enable(); + * + * 4. wbif_dump_status(), option, for debug purpose + * the bufmgr status can show the progress of write back, can be used for debug purpose + */ + +static void mmhubbub32_warmup_mcif(struct mcif_wb *mcif_wb, + struct mcif_warmup_params *params) +{ + struct dcn30_mmhubbub *mcif_wb30 = TO_DCN30_MMHUBBUB(mcif_wb); + union large_integer start_address_shift = {.quad_part = params->start_address.quad_part >> 5}; + + /* Set base address and region size for warmup */ + REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, 0, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, start_address_shift.high_part); + REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_LOW, 0, MMHUBBUB_WARMUP_BASE_ADDR_LOW, start_address_shift.low_part); + REG_SET(MMHUBBUB_WARMUP_ADDR_REGION, 0, MMHUBBUB_WARMUP_ADDR_REGION, params->region_size >> 5); +// REG_SET(MMHUBBUB_WARMUP_P_VMID, 0, MMHUBBUB_WARMUP_P_VMID, params->p_vmid); + + /* Set address increment and enable warmup */ + REG_SET_3(MMHUBBUB_WARMUP_CONTROL_STATUS, 0, MMHUBBUB_WARMUP_EN, true, + MMHUBBUB_WARMUP_SW_INT_EN, true, + MMHUBBUB_WARMUP_INC_ADDR, params->address_increment >> 5); + + /* Wait for an interrupt to signal warmup is completed */ + REG_WAIT(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_STATUS, 1, 20, 100); + + /* Acknowledge interrupt */ + REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, 1); + + /* Disable warmup */ + REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false); +} + +void mmhubbub32_config_mcif_buf(struct mcif_wb *mcif_wb, + struct mcif_buf_params *params, + unsigned int dest_height) +{ + struct dcn30_mmhubbub *mcif_wb30 = TO_DCN30_MMHUBBUB(mcif_wb); + + /* buffer address for packing mode or Luma in planar mode */ + REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); + REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[0])); + + /* buffer address for Chroma in planar mode (unused in packing mode) */ + REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); + REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[0])); + + /* buffer address for packing mode or Luma in planar mode */ + REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); + REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[1])); + + /* buffer address for Chroma in planar mode (unused in packing mode) */ + REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1])); + REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[1])); + + /* buffer address for packing mode or Luma in planar mode */ + REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, MCIF_ADDR(params->luma_address[2])); + REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[2])); + + /* buffer address for Chroma in planar mode (unused in packing mode) */ + REG_UPDATE(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, MCIF_ADDR(params->chroma_address[2])); + REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[2])); + + /* buffer address for packing mode or Luma in planar mode */ + REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, MCIF_ADDR(params->luma_address[3])); + REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[3])); + + /* buffer address for Chroma in planar mode (unused in packing mode) */ + REG_UPDATE(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, MCIF_ADDR(params->chroma_address[3])); + REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[3])); + + /* setup luma & chroma size + * should be enough to contain a whole frame Luma data, + * the programmed value is frame buffer size [27:8], 256-byte aligned + */ + REG_UPDATE(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, (params->luma_pitch>>8) * dest_height); + REG_UPDATE(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, (params->chroma_pitch>>8) * dest_height); + + /* enable address fence */ + REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, 1); + + /* setup pitch, the programmed value is [15:8], 256B align */ + REG_UPDATE_2(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, params->luma_pitch >> 8, + MCIF_WB_BUF_CHROMA_PITCH, params->chroma_pitch >> 8); +} + +static void mmhubbub32_config_mcif_arb(struct mcif_wb *mcif_wb, + struct mcif_arb_params *params) +{ + struct dcn30_mmhubbub *mcif_wb30 = TO_DCN30_MMHUBBUB(mcif_wb); + + /* Programmed by the video driver based on the CRTC timing (for DWB) */ + REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, params->time_per_pixel); + + /* Programming dwb watermark */ + /* Watermark to generate urgent in MCIF_WB_CLI, value is determined by MCIF_WB_CLI_WATERMARK_MASK. */ + /* Program in ns. A formula will be provided in the pseudo code to calculate the value. */ + REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x0); + /* urgent_watermarkA */ + REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[0]); + REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x1); + /* urgent_watermarkB */ + REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[1]); + REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x2); + /* urgent_watermarkC */ + REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[2]); + REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x3); + /* urgent_watermarkD */ + REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[3]); + + /* Programming nb pstate watermark */ + /* nbp_state_change_watermarkA */ + REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x0); + REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, + NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[0]); + /* nbp_state_change_watermarkB */ + REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x1); + REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, + NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[1]); + /* nbp_state_change_watermarkC */ + REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x2); + REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, + NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[2]); + /* nbp_state_change_watermarkD */ + REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x3); + REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, + NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[3]); + + /* dram_speed_change_duration - register removed */ + //REG_UPDATE(MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI, + // MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI, params->dram_speed_change_duration); + + /* max_scaled_time */ + REG_UPDATE(MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, params->max_scaled_time); + + /* slice_lines */ + REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1); + + /* Set arbitration unit for Luma/Chroma */ + /* arb_unit=2 should be chosen for more efficiency */ + /* Arbitration size, 0: 2048 bytes 1: 4096 bytes 2: 8192 Bytes */ + REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, params->arbitration_slice); +} + +const struct mcif_wb_funcs dcn32_mmhubbub_funcs = { + .warmup_mcif = mmhubbub32_warmup_mcif, + .enable_mcif = mmhubbub2_enable_mcif, + .disable_mcif = mmhubbub2_disable_mcif, + .config_mcif_buf = mmhubbub32_config_mcif_buf, + .config_mcif_arb = mmhubbub32_config_mcif_arb, + .config_mcif_irq = mmhubbub2_config_mcif_irq, + .dump_frame = mcifwb2_dump_frame, +}; + +void dcn32_mmhubbub_construct(struct dcn30_mmhubbub *mcif_wb30, + struct dc_context *ctx, + const struct dcn30_mmhubbub_registers *mcif_wb_regs, + const struct dcn30_mmhubbub_shift *mcif_wb_shift, + const struct dcn30_mmhubbub_mask *mcif_wb_mask, + int inst) +{ + mcif_wb30->base.ctx = ctx; + + mcif_wb30->base.inst = inst; + mcif_wb30->base.funcs = &dcn32_mmhubbub_funcs; + + mcif_wb30->mcif_wb_regs = mcif_wb_regs; + mcif_wb30->mcif_wb_shift = mcif_wb_shift; + mcif_wb30->mcif_wb_mask = mcif_wb_mask; +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h new file mode 100644 index 000000000000..22355051f5f7 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h @@ -0,0 +1,225 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_MCIF_WB_DCN32_H__ +#define __DC_MCIF_WB_DCN32_H__ + +#include "dcn20/dcn20_mmhubbub.h" +#include "dcn30/dcn30_mmhubbub.h" + +#define MCIF_WB_COMMON_REG_LIST_DCN32(inst) \ + SRI2(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\ + SRI2(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\ + SRI2(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\ + SRI2(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB, inst),\ + SRI2(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\ + SRI2(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MMHUBBUB, inst),\ + SRI2(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\ + SRI2(MCIF_WB_WATERMARK, MMHUBBUB, inst),\ + SRI2(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\ + SRI2(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\ + SRI2(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\ + SRI2(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\ + SRI2(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\ + SRI2(MMHUBBUB_MEM_PWR_CNTL, MMHUBBUB, inst),\ + SRI2(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB, inst),\ + SRI2(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB, inst),\ + SRI2(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB, inst),\ + SRI2(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB, inst) + + +#define MCIF_WB_COMMON_MASK_SH_LIST_DCN32(mask_sh) \ + SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\ + SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\ + SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\ + SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\ + SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\ + SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\ + SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\ + SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\ + SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\ + SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\ + SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_BUF, mask_sh),\ + SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_BUFTAG, mask_sh),\ + SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_LINE_L, mask_sh),\ + SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_NEXT_BUF, mask_sh),\ + SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\ + SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\ + SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_ACTIVE, mask_sh),\ + SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SW_LOCKED, mask_sh),\ + SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_VCE_LOCKED, mask_sh),\ + SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_OVERFLOW, mask_sh),\ + SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_DISABLE, mask_sh),\ + SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\ + SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_BUFTAG, mask_sh),\ + SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_NXT_BUF, mask_sh),\ + SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_CUR_LINE_L, mask_sh),\ + SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_NEW_CONTENT, mask_sh),\ + SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_COLOR_DEPTH, mask_sh),\ + SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ_BLACK_PIXEL, mask_sh),\ + SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\ + SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_Y_OVERRUN, mask_sh),\ + SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_C_OVERRUN, mask_sh),\ + SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_ACTIVE, mask_sh),\ + SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SW_LOCKED, mask_sh),\ + SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_VCE_LOCKED, mask_sh),\ + SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_OVERFLOW, mask_sh),\ + SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_DISABLE, mask_sh),\ + SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\ + SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_BUFTAG, mask_sh),\ + SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_NXT_BUF, mask_sh),\ + SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_CUR_LINE_L, mask_sh),\ + SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_NEW_CONTENT, mask_sh),\ + SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_COLOR_DEPTH, mask_sh),\ + SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ_BLACK_PIXEL, mask_sh),\ + SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\ + SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_Y_OVERRUN, mask_sh),\ + SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_C_OVERRUN, mask_sh),\ + SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_ACTIVE, mask_sh),\ + SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SW_LOCKED, mask_sh),\ + SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_VCE_LOCKED, mask_sh),\ + SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_OVERFLOW, mask_sh),\ + SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_DISABLE, mask_sh),\ + SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\ + SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_BUFTAG, mask_sh),\ + SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_NXT_BUF, mask_sh),\ + SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_CUR_LINE_L, mask_sh),\ + SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_NEW_CONTENT, mask_sh),\ + SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_COLOR_DEPTH, mask_sh),\ + SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ_BLACK_PIXEL, mask_sh),\ + SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\ + SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_Y_OVERRUN, mask_sh),\ + SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_C_OVERRUN, mask_sh),\ + SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_ACTIVE, mask_sh),\ + SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SW_LOCKED, mask_sh),\ + SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_VCE_LOCKED, mask_sh),\ + SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_OVERFLOW, mask_sh),\ + SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_DISABLE, mask_sh),\ + SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\ + SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_BUFTAG, mask_sh),\ + SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_NXT_BUF, mask_sh),\ + SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_CUR_LINE_L, mask_sh),\ + SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_NEW_CONTENT, mask_sh),\ + SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_COLOR_DEPTH, mask_sh),\ + SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ_BLACK_PIXEL, mask_sh),\ + SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\ + SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_Y_OVERRUN, mask_sh),\ + SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_C_OVERRUN, mask_sh),\ + SF(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\ + SF(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\ + SF(MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\ + SF(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB_TEST_DEBUG_INDEX, mask_sh),\ + SF(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB_TEST_DEBUG_DATA, mask_sh),\ + SF(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\ + SF(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\ + SF(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\ + SF(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\ + SF(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\ + SF(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\ + SF(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\ + SF(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\ + SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\ + SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\ + SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\ + SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\ + SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\ + SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\ + SF(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\ + SF(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ + SF(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\ + SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\ + SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\ + SF(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB_CLI_CLOCK_GATER_OVERRIDE, mask_sh),\ + SF(MCIF_WB_SELF_REFRESH_CONTROL, PERFRAME_SELF_REFRESH, mask_sh),\ + SF(MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, mask_sh),\ + SF(MCIF_WB_SECURITY_LEVEL, MCIF_WB_SECURITY_LEVEL, mask_sh),\ + SF(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\ + SF(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh),\ + SF(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, mask_sh),\ + SF(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, mask_sh),\ + SF(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, mask_sh),\ + SF(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, mask_sh),\ + SF(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, mask_sh),\ + SF(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, mask_sh),\ + SF(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, mask_sh),\ + SF(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, mask_sh),\ + SF(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_WIDTH, mask_sh),\ + SF(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_HEIGHT, mask_sh),\ + SF(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_WIDTH, mask_sh),\ + SF(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_HEIGHT, mask_sh),\ + SF(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_WIDTH, mask_sh),\ + SF(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_HEIGHT, mask_sh),\ + SF(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_WIDTH, mask_sh),\ + SF(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_HEIGHT, mask_sh),\ + SF(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB_WARMUP_ADDR_REGION, mask_sh),\ + SF(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, mask_sh),\ + SF(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB_WARMUP_BASE_ADDR_LOW, mask_sh),\ + SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, mask_sh),\ + SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_EN, mask_sh),\ + SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_STATUS, mask_sh),\ + SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, mask_sh),\ + SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_INC_ADDR, mask_sh) + + +void dcn32_mmhubbub_construct(struct dcn30_mmhubbub *mcif_wb30, + struct dc_context *ctx, + const struct dcn30_mmhubbub_registers *mcif_wb_regs, + const struct dcn30_mmhubbub_shift *mcif_wb_shift, + const struct dcn30_mmhubbub_mask *mcif_wb_mask, + int inst); + +#endif //__DC_MCIF_WB_DCN32_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c new file mode 100644 index 000000000000..a308f33d3d0d --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c @@ -0,0 +1,810 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "reg_helper.h" +#include "dcn30/dcn30_mpc.h" +#include "dcn30/dcn30_cm_common.h" +#include "dcn30/dcn30_mpc.h" +#include "basics/conversion.h" +#include "dcn10/dcn10_cm_common.h" +#include "dc.h" + +#define REG(reg)\ + mpc30->mpc_regs->reg + +#define CTX \ + mpc30->base.ctx + +#undef FN +#define FN(reg_name, field_name) \ + mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name + + +static void mpc32_mpc_init(struct mpc *mpc) +{ + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); + int mpcc_id; + + mpc1_mpc_init(mpc); + + if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) { + if (mpc30->mpc_mask->MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE) { + for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) { + REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, 3); + REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, 3); + REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, 3); + } + } + if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) { + for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) + REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_LOW_PWR_MODE, 3); + } + } +} + + +static enum dc_lut_mode mpc32_get_shaper_current(struct mpc *mpc, uint32_t mpcc_id) +{ + enum dc_lut_mode mode; + uint32_t state_mode; + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); + + REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], + MPCC_MCM_SHAPER_MODE_CURRENT, &state_mode); + + switch (state_mode) { + case 0: + mode = LUT_BYPASS; + break; + case 1: + mode = LUT_RAM_A; + break; + case 2: + mode = LUT_RAM_B; + break; + default: + mode = LUT_BYPASS; + break; + } + return mode; +} + + +static void mpc32_configure_shaper_lut( + struct mpc *mpc, + bool is_ram_a, + uint32_t mpcc_id) +{ + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); + + REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], + MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, 7); + REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], + MPCC_MCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); + REG_SET(MPCC_MCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_INDEX, 0); +} + + +static void mpc32_program_shaper_luta_settings( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t mpcc_id) +{ + const struct gamma_curve *curve; + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); + + REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_B[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); + REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_G[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); + REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_R[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); + + REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_B[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); + REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_G[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y); + REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_R[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y); + + curve = params->arr_curve_points; + REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_18_19[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_20_21[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_22_23[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_24_25[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_26_27[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_28_29[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_30_31[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_32_33[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); +} + + +static void mpc32_program_shaper_lutb_settings( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t mpcc_id) +{ + const struct gamma_curve *curve; + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); + + REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); + REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); + REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); + + REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); + REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_G[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y); + REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_R[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x, + MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y); + + curve = params->arr_curve_points; + REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_0_1[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_2_3[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_4_5[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_6_7[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_8_9[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_10_11[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_12_13[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_14_15[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_16_17[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_18_19[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_20_21[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_22_23[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_24_25[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_26_27[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_28_29[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_30_31[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_32_33[mpcc_id], 0, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); +} + + +static void mpc32_program_shaper_lut( + struct mpc *mpc, + const struct pwl_result_data *rgb, + uint32_t num, + uint32_t mpcc_id) +{ + uint32_t i, red, green, blue; + uint32_t red_delta, green_delta, blue_delta; + uint32_t red_value, green_value, blue_value; + + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); + + for (i = 0 ; i < num; i++) { + + red = rgb[i].red_reg; + green = rgb[i].green_reg; + blue = rgb[i].blue_reg; + + red_delta = rgb[i].delta_red_reg; + green_delta = rgb[i].delta_green_reg; + blue_delta = rgb[i].delta_blue_reg; + + red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff); + green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff); + blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff); + + REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, red_value); + REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, green_value); + REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, blue_value); + } + +} + + +static void mpc32_power_on_shaper_3dlut( + struct mpc *mpc, + uint32_t mpcc_id, + bool power_on) +{ + uint32_t power_status_shaper = 2; + uint32_t power_status_3dlut = 2; + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); + int max_retries = 10; + + REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, + MPCC_MCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1:0); + /* wait for memory to fully power up */ + if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) { + REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries); + REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries); + } + + /*read status is not mandatory, it is just for debugging*/ + REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, &power_status_shaper); + REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut); + + if (power_status_shaper != 0 && power_on == true) + BREAK_TO_DEBUGGER(); + + if (power_status_3dlut != 0 && power_on == true) + BREAK_TO_DEBUGGER(); +} + + +bool mpc32_program_shaper( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t mpcc_id) +{ + enum dc_lut_mode current_mode; + enum dc_lut_mode next_mode; + + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); + + if (params == NULL) { + REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, 0); + return false; + } + + if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) + mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true); + + current_mode = mpc32_get_shaper_current(mpc, mpcc_id); + + if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A) + next_mode = LUT_RAM_B; + else + next_mode = LUT_RAM_A; + + mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A ? true:false, mpcc_id); + + if (next_mode == LUT_RAM_A) + mpc32_program_shaper_luta_settings(mpc, params, mpcc_id); + else + mpc32_program_shaper_lutb_settings(mpc, params, mpcc_id); + + mpc32_program_shaper_lut( + mpc, params->rgb_resulted, params->hw_points_num, mpcc_id); + + REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2); + mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false); + + return true; +} + + +static enum dc_lut_mode get3dlut_config( + struct mpc *mpc, + bool *is_17x17x17, + bool *is_12bits_color_channel, + int mpcc_id) +{ + uint32_t i_mode, i_enable_10bits, lut_size; + enum dc_lut_mode mode; + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); + + REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], + MPCC_MCM_3DLUT_MODE_CURRENT, &i_mode); + + REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPCC_MCM_3DLUT_30BIT_EN, &i_enable_10bits); + + switch (i_mode) { + case 0: + mode = LUT_BYPASS; + break; + case 1: + mode = LUT_RAM_A; + break; + case 2: + mode = LUT_RAM_B; + break; + default: + mode = LUT_BYPASS; + break; + } + if (i_enable_10bits > 0) + *is_12bits_color_channel = false; + else + *is_12bits_color_channel = true; + + REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &lut_size); + + if (lut_size == 0) + *is_17x17x17 = true; + else + *is_17x17x17 = false; + + return mode; +} + + +static void mpc32_select_3dlut_ram( + struct mpc *mpc, + enum dc_lut_mode mode, + bool is_color_channel_12bits, + uint32_t mpcc_id) +{ + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); + + REG_UPDATE_2(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPCC_MCM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1, + MPCC_MCM_3DLUT_30BIT_EN, is_color_channel_12bits == true ? 0:1); +} + + +static void mpc32_select_3dlut_ram_mask( + struct mpc *mpc, + uint32_t ram_selection_mask, + uint32_t mpcc_id) +{ + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); + + REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_WRITE_EN_MASK, + ram_selection_mask); + REG_SET(MPCC_MCM_3DLUT_INDEX[mpcc_id], 0, MPCC_MCM_3DLUT_INDEX, 0); +} + + +static void mpc32_set3dlut_ram12( + struct mpc *mpc, + const struct dc_rgb *lut, + uint32_t entries, + uint32_t mpcc_id) +{ + uint32_t i, red, green, blue, red1, green1, blue1; + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); + + for (i = 0 ; i < entries; i += 2) { + red = lut[i].red<<4; + green = lut[i].green<<4; + blue = lut[i].blue<<4; + red1 = lut[i+1].red<<4; + green1 = lut[i+1].green<<4; + blue1 = lut[i+1].blue<<4; + + REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0, + MPCC_MCM_3DLUT_DATA0, red, + MPCC_MCM_3DLUT_DATA1, red1); + + REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0, + MPCC_MCM_3DLUT_DATA0, green, + MPCC_MCM_3DLUT_DATA1, green1); + + REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0, + MPCC_MCM_3DLUT_DATA0, blue, + MPCC_MCM_3DLUT_DATA1, blue1); + } +} + + +static void mpc32_set3dlut_ram10( + struct mpc *mpc, + const struct dc_rgb *lut, + uint32_t entries, + uint32_t mpcc_id) +{ + uint32_t i, red, green, blue, value; + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); + + for (i = 0; i < entries; i++) { + red = lut[i].red; + green = lut[i].green; + blue = lut[i].blue; + //should we shift red 22bit and green 12? + value = (red<<20) | (green<<10) | blue; + + REG_SET(MPCC_MCM_3DLUT_DATA_30BIT[mpcc_id], 0, MPCC_MCM_3DLUT_DATA_30BIT, value); + } + +} + + +static void mpc32_set_3dlut_mode( + struct mpc *mpc, + enum dc_lut_mode mode, + bool is_color_channel_12bits, + bool is_lut_size17x17x17, + uint32_t mpcc_id) +{ + uint32_t lut_mode; + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); + + if (mode == LUT_BYPASS) + lut_mode = 0; + else if (mode == LUT_RAM_A) + lut_mode = 1; + else + lut_mode = 2; + + REG_UPDATE_2(MPCC_MCM_3DLUT_MODE[mpcc_id], + MPCC_MCM_3DLUT_MODE, lut_mode, + MPCC_MCM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1); +} + + +bool mpc32_program_3dlut( + struct mpc *mpc, + const struct tetrahedral_params *params, + int mpcc_id) +{ + enum dc_lut_mode mode; + bool is_17x17x17; + bool is_12bits_color_channel; + const struct dc_rgb *lut0; + const struct dc_rgb *lut1; + const struct dc_rgb *lut2; + const struct dc_rgb *lut3; + int lut_size0; + int lut_size; + + if (params == NULL) { + mpc32_set_3dlut_mode(mpc, LUT_BYPASS, false, false, mpcc_id); + return false; + } + mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true); + + mode = get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, mpcc_id); + + if (mode == LUT_BYPASS || mode == LUT_RAM_B) + mode = LUT_RAM_A; + else + mode = LUT_RAM_B; + + is_17x17x17 = !params->use_tetrahedral_9; + is_12bits_color_channel = params->use_12bits; + if (is_17x17x17) { + lut0 = params->tetrahedral_17.lut0; + lut1 = params->tetrahedral_17.lut1; + lut2 = params->tetrahedral_17.lut2; + lut3 = params->tetrahedral_17.lut3; + lut_size0 = sizeof(params->tetrahedral_17.lut0)/ + sizeof(params->tetrahedral_17.lut0[0]); + lut_size = sizeof(params->tetrahedral_17.lut1)/ + sizeof(params->tetrahedral_17.lut1[0]); + } else { + lut0 = params->tetrahedral_9.lut0; + lut1 = params->tetrahedral_9.lut1; + lut2 = params->tetrahedral_9.lut2; + lut3 = params->tetrahedral_9.lut3; + lut_size0 = sizeof(params->tetrahedral_9.lut0)/ + sizeof(params->tetrahedral_9.lut0[0]); + lut_size = sizeof(params->tetrahedral_9.lut1)/ + sizeof(params->tetrahedral_9.lut1[0]); + } + + mpc32_select_3dlut_ram(mpc, mode, + is_12bits_color_channel, mpcc_id); + mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id); + if (is_12bits_color_channel) + mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id); + else + mpc32_set3dlut_ram10(mpc, lut0, lut_size0, mpcc_id); + + mpc32_select_3dlut_ram_mask(mpc, 0x2, mpcc_id); + if (is_12bits_color_channel) + mpc32_set3dlut_ram12(mpc, lut1, lut_size, mpcc_id); + else + mpc32_set3dlut_ram10(mpc, lut1, lut_size, mpcc_id); + + mpc32_select_3dlut_ram_mask(mpc, 0x4, mpcc_id); + if (is_12bits_color_channel) + mpc32_set3dlut_ram12(mpc, lut2, lut_size, mpcc_id); + else + mpc32_set3dlut_ram10(mpc, lut2, lut_size, mpcc_id); + + mpc32_select_3dlut_ram_mask(mpc, 0x8, mpcc_id); + if (is_12bits_color_channel) + mpc32_set3dlut_ram12(mpc, lut3, lut_size, mpcc_id); + else + mpc32_set3dlut_ram10(mpc, lut3, lut_size, mpcc_id); + + mpc32_set_3dlut_mode(mpc, mode, is_12bits_color_channel, + is_17x17x17, mpcc_id); + + if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) + mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false); + + return true; +} + +const struct mpc_funcs dcn32_mpc_funcs = { + .read_mpcc_state = mpc1_read_mpcc_state, + .insert_plane = mpc1_insert_plane, + .remove_mpcc = mpc1_remove_mpcc, + .mpc_init = mpc32_mpc_init, + .mpc_init_single_inst = mpc1_mpc_init_single_inst, + .update_blending = mpc2_update_blending, + .cursor_lock = mpc1_cursor_lock, + .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp, + .wait_for_idle = mpc2_assert_idle_mpcc, + .assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect, + .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw, + .set_denorm = mpc3_set_denorm, + .set_denorm_clamp = mpc3_set_denorm_clamp, + .set_output_csc = mpc3_set_output_csc, + .set_ocsc_default = mpc3_set_ocsc_default, + .set_output_gamma = mpc3_set_output_gamma, + .insert_plane_to_secondary = NULL, + .remove_mpcc_from_secondary = NULL, + .set_dwb_mux = mpc3_set_dwb_mux, + .disable_dwb_mux = mpc3_disable_dwb_mux, + .is_dwb_idle = mpc3_is_dwb_idle, + .set_out_rate_control = mpc3_set_out_rate_control, + .set_gamut_remap = mpc3_set_gamut_remap, + .program_shaper = mpc32_program_shaper, + .program_3dlut = mpc32_program_3dlut, + .acquire_rmu = NULL, + .release_rmu = NULL, + .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut, + .get_mpc_out_mux = mpc1_get_mpc_out_mux, + .set_bg_color = mpc1_set_bg_color, +}; + + +void dcn32_mpc_construct(struct dcn30_mpc *mpc30, + struct dc_context *ctx, + const struct dcn30_mpc_registers *mpc_regs, + const struct dcn30_mpc_shift *mpc_shift, + const struct dcn30_mpc_mask *mpc_mask, + int num_mpcc, + int num_rmu) +{ + int i; + + mpc30->base.ctx = ctx; + + mpc30->base.funcs = &dcn32_mpc_funcs; + + mpc30->mpc_regs = mpc_regs; + mpc30->mpc_shift = mpc_shift; + mpc30->mpc_mask = mpc_mask; + + mpc30->mpcc_in_use_mask = 0; + mpc30->num_mpcc = num_mpcc; + mpc30->num_rmu = num_rmu; + + for (i = 0; i < MAX_MPCC; i++) + mpc3_init_mpcc(&mpc30->base.mpcc_array[i], i); +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h new file mode 100644 index 000000000000..d4be3c89ec7b --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h @@ -0,0 +1,213 @@ +/* Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_MPCC_DCN32_H__ +#define __DC_MPCC_DCN32_H__ + +#include "dcn20/dcn20_mpc.h" +#include "dcn30/dcn30_mpc.h" + +#define MPC_MCM_REG_LIST_DCN32(inst) \ + SRII(MPCC_MCM_SHAPER_CONTROL, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_G, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_R, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_G, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_R, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_REGION_2_3, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_REGION_4_5, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_REGION_6_7, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_REGION_8_9, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_REGION_10_11, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_REGION_12_13, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_REGION_14_15, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_REGION_16_17, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_REGION_18_19, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_REGION_20_21, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_REGION_22_23, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_REGION_24_25, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_REGION_26_27, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_REGION_28_29, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_REGION_30_31, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMA_REGION_32_33, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_B, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_G, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_R, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_B, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_G, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_R, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_REGION_0_1, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_REGION_2_3, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_REGION_4_5, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_REGION_6_7, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_REGION_8_9, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_REGION_10_11, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_REGION_12_13, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_REGION_14_15, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_REGION_16_17, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_REGION_18_19, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_REGION_20_21, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_REGION_22_23, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_REGION_24_25, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_REGION_26_27, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_REGION_28_29, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_REGION_30_31, MPCC_MCM, inst),\ + SRII(MPCC_MCM_SHAPER_RAMB_REGION_32_33, MPCC_MCM, inst), \ + SRII(MPCC_MCM_3DLUT_MODE, MPCC_MCM, inst),\ + SRII(MPCC_MCM_3DLUT_INDEX, MPCC_MCM, inst),\ + SRII(MPCC_MCM_3DLUT_DATA, MPCC_MCM, inst),\ + SRII(MPCC_MCM_3DLUT_DATA_30BIT, MPCC_MCM, inst),\ + SRII(MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM, inst),\ + SRII(MPCC_MCM_3DLUT_OUT_NORM_FACTOR, MPCC_MCM, inst),\ + SRII(MPCC_MCM_3DLUT_OUT_OFFSET_R, MPCC_MCM, inst),\ + SRII(MPCC_MCM_3DLUT_OUT_OFFSET_G, MPCC_MCM, inst),\ + SRII(MPCC_MCM_3DLUT_OUT_OFFSET_B, MPCC_MCM, inst),\ + SRII(MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM, inst) + + +#define MPC_COMMON_MASK_SH_LIST_DCN32(mask_sh) \ + MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\ + SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\ + SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\ + SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\ + SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\ + SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\ + SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\ + SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\ + SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\ + SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\ + SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\ + SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\ + SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\ + SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\ + SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\ + SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\ + SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\ + SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\ + SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\ + SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\ + SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\ + SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\ + SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\ + SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\ + SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\ + SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\ + SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\ + SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\ + SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\ + SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\ + SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\ + SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_MODE, MPCC_MCM_3DLUT_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_MODE, MPCC_MCM_3DLUT_SIZE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_MODE, MPCC_MCM_3DLUT_MODE_CURRENT, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_WRITE_EN_MASK, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_RAM_SEL, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_30BIT_EN, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_READ_SEL, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_INDEX, MPCC_MCM_3DLUT_INDEX, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_DATA, MPCC_MCM_3DLUT_DATA0, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_DATA, MPCC_MCM_3DLUT_DATA1, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT, MPCC_MCM_3DLUT_DATA_30BIT, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL, MPCC_MCM_SHAPER_LUT_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL, MPCC_MCM_SHAPER_MODE_CURRENT, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM_SHAPER_OFFSET_R, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM_SHAPER_OFFSET_G, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM_SHAPER_OFFSET_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM_SHAPER_SCALE_R, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM_SHAPER_SCALE_G, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM_SHAPER_SCALE_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM_SHAPER_LUT_INDEX, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM_SHAPER_LUT_DATA, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM_SHAPER_LUT_WRITE_SEL, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_PWR_FORCE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_PWR_DIS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_PWR_FORCE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_PWR_DIS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_PWR_FORCE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_PWR_DIS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_PWR_STATE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_PWR_STATE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_PWR_STATE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL, MPCC_MCM_SHAPER_MODE_CURRENT, mask_sh),\ + SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh) + + +void dcn32_mpc_construct(struct dcn30_mpc *mpc30, + struct dc_context *ctx, + const struct dcn30_mpc_registers *mpc_regs, + const struct dcn30_mpc_shift *mpc_shift, + const struct dcn30_mpc_mask *mpc_mask, + int num_mpcc, + int num_rmu); + +#endif //__DC_MPCC_DCN32_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c new file mode 100644 index 000000000000..f1ed25e972f2 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c @@ -0,0 +1,236 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dcn32_optc.h" + +#include "dcn30/dcn30_optc.h" +#include "reg_helper.h" +#include "dc.h" +#include "dcn_calc_math.h" + +#define REG(reg)\ + optc1->tg_regs->reg + +#define CTX \ + optc1->base.ctx + +#undef FN +#define FN(reg_name, field_name) \ + optc1->tg_shift->field_name, optc1->tg_mask->field_name + +static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, + struct dc_crtc_timing *timing) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + uint32_t memory_mask = 0; + int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right; + int mpcc_hactive = h_active / opp_cnt; + /* Each memory instance is 2048x(32x2) bits to support half line of 4096 */ + int odm_mem_count = (h_active + 2047) / 2048; + + /* + * display <= 4k : 2 memories + 2 pipes + * 4k < display <= 8k : 4 memories + 2 pipes + * 8k < display <= 12k : 6 memories + 4 pipes + */ + if (opp_cnt == 4) { + if (odm_mem_count <= 2) + memory_mask = 0x3; + else if (odm_mem_count <= 4) + memory_mask = 0xf; + else + memory_mask = 0x3f; + } else { + if (odm_mem_count <= 2) + memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); + else if (odm_mem_count <= 4) + memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); + else + memory_mask = 0x77; + } + + REG_SET(OPTC_MEMORY_CONFIG, 0, + OPTC_MEM_SEL, memory_mask); + + if (opp_cnt == 2) { + REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, + OPTC_NUM_OF_INPUT_SEGMENT, 1, + OPTC_SEG0_SRC_SEL, opp_id[0], + OPTC_SEG1_SRC_SEL, opp_id[1]); + } else if (opp_cnt == 4) { + REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, + OPTC_NUM_OF_INPUT_SEGMENT, 3, + OPTC_SEG0_SRC_SEL, opp_id[0], + OPTC_SEG1_SRC_SEL, opp_id[1], + OPTC_SEG2_SRC_SEL, opp_id[2], + OPTC_SEG3_SRC_SEL, opp_id[3]); + } + + REG_UPDATE(OPTC_WIDTH_CONTROL, + OPTC_SEGMENT_WIDTH, mpcc_hactive); + + REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); + optc1->opp_count = opp_cnt; +} + +/** + * Enable CRTC + * Enable CRTC - call ASIC Control Object to enable Timing generator. + */ +static bool optc32_enable_crtc(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + /* opp instance for OTG, 1 to 1 mapping and odm will adjust */ + REG_UPDATE(OPTC_DATA_SOURCE_SELECT, + OPTC_SEG0_SRC_SEL, optc->inst); + + /* VTG enable first is for HW workaround */ + REG_UPDATE(CONTROL, + VTG0_ENABLE, 1); + + REG_SEQ_START(); + + /* Enable CRTC */ + REG_UPDATE_2(OTG_CONTROL, + OTG_DISABLE_POINT_CNTL, 2, + OTG_MASTER_EN, 1); + + REG_SEQ_SUBMIT(); + REG_SEQ_WAIT_DONE(); + + return true; +} + +/* disable_crtc */ +static bool optc32_disable_crtc(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + /* disable otg request until end of the first line + * in the vertical blank region + */ + REG_UPDATE(OTG_CONTROL, + OTG_MASTER_EN, 0); + + REG_UPDATE(CONTROL, + VTG0_ENABLE, 0); + + /* CRTC disabled, so disable clock. */ + REG_WAIT(OTG_CLOCK_CONTROL, + OTG_BUSY, 0, + 1, 100000); + + return true; +} + +void optc32_phantom_crtc_post_enable(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + /* Disable immediately. */ + REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0); + + /* CRTC disabled, so disable clock. */ + REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); +} + + +static struct timing_generator_funcs dcn32_tg_funcs = { + .validate_timing = optc1_validate_timing, + .program_timing = optc1_program_timing, + .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, + .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, + .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, + .program_global_sync = optc1_program_global_sync, + .enable_crtc = optc32_enable_crtc, + .disable_crtc = optc32_disable_crtc, + .phantom_crtc_post_enable = optc32_phantom_crtc_post_enable, + /* used by enable_timing_synchronization. Not need for FPGA */ + .is_counter_moving = optc1_is_counter_moving, + .get_position = optc1_get_position, + .get_frame_count = optc1_get_vblank_counter, + .get_scanoutpos = optc1_get_crtc_scanoutpos, + .get_otg_active_size = optc1_get_otg_active_size, + .set_early_control = optc1_set_early_control, + /* used by enable_timing_synchronization. Not need for FPGA */ + .wait_for_state = optc1_wait_for_state, + .set_blank_color = optc3_program_blank_color, + .did_triggered_reset_occur = optc1_did_triggered_reset_occur, + .triplebuffer_lock = optc3_triplebuffer_lock, + .triplebuffer_unlock = optc2_triplebuffer_unlock, + .enable_reset_trigger = optc1_enable_reset_trigger, + .enable_crtc_reset = optc1_enable_crtc_reset, + .disable_reset_trigger = optc1_disable_reset_trigger, + .lock = optc3_lock, + .unlock = optc1_unlock, + .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable, + .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable, + .enable_optc_clock = optc1_enable_optc_clock, + .set_vrr_m_const = optc3_set_vrr_m_const, + .set_drr = optc1_set_drr, + .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal, + .set_vtotal_min_max = optc1_set_vtotal_min_max, + .set_static_screen_control = optc1_set_static_screen_control, + .program_stereo = optc1_program_stereo, + .is_stereo_left_eye = optc1_is_stereo_left_eye, + .tg_init = optc3_tg_init, + .is_tg_enabled = optc1_is_tg_enabled, + .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, + .clear_optc_underflow = optc1_clear_optc_underflow, + .setup_global_swap_lock = NULL, + .get_crc = optc1_get_crc, + .configure_crc = optc1_configure_crc, + .set_dsc_config = optc3_set_dsc_config, + .get_dsc_status = optc2_get_dsc_status, + .set_dwb_source = NULL, + .set_odm_bypass = optc3_set_odm_bypass, + .set_odm_combine = optc32_set_odm_combine, + .get_optc_source = optc2_get_optc_source, + .set_out_mux = optc3_set_out_mux, + .set_drr_trigger_window = optc3_set_drr_trigger_window, + .set_vtotal_change_limit = optc3_set_vtotal_change_limit, + .set_gsl = optc2_set_gsl, + .set_gsl_source_select = optc2_set_gsl_source_select, + .set_vtg_params = optc1_set_vtg_params, + .program_manual_trigger = optc2_program_manual_trigger, + .setup_manual_trigger = optc2_setup_manual_trigger, + .get_hw_timing = optc1_get_hw_timing, +}; + +void dcn32_timing_generator_init(struct optc *optc1) +{ + optc1->base.funcs = &dcn32_tg_funcs; + + optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; + optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; + + optc1->min_h_blank = 32; + optc1->min_v_blank = 3; + optc1->min_v_blank_interlace = 5; + optc1->min_h_sync_width = 4; + optc1->min_v_sync_width = 1; +} + diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h new file mode 100644 index 000000000000..e07b317ed3f4 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h @@ -0,0 +1,253 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_OPTC_DCN32_H__ +#define __DC_OPTC_DCN32_H__ + +#include "dcn10/dcn10_optc.h" + +#define OPTC_COMMON_REG_LIST_DCN3_2(inst) \ + SRI(OTG_VSTARTUP_PARAM, OTG, inst),\ + SRI(OTG_VUPDATE_PARAM, OTG, inst),\ + SRI(OTG_VREADY_PARAM, OTG, inst),\ + SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\ + SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\ + SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\ + SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\ + SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\ + SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\ + SRI(OTG_H_TOTAL, OTG, inst),\ + SRI(OTG_H_BLANK_START_END, OTG, inst),\ + SRI(OTG_H_SYNC_A, OTG, inst),\ + SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\ + SRI(OTG_H_TIMING_CNTL, OTG, inst),\ + SRI(OTG_V_TOTAL, OTG, inst),\ + SRI(OTG_V_BLANK_START_END, OTG, inst),\ + SRI(OTG_V_SYNC_A, OTG, inst),\ + SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\ + SRI(OTG_CONTROL, OTG, inst),\ + SRI(OTG_STEREO_CONTROL, OTG, inst),\ + SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\ + SRI(OTG_STEREO_STATUS, OTG, inst),\ + SRI(OTG_V_TOTAL_MAX, OTG, inst),\ + SRI(OTG_V_TOTAL_MIN, OTG, inst),\ + SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\ + SRI(OTG_TRIGA_CNTL, OTG, inst),\ + SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\ + SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\ + SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\ + SRI(OTG_STATUS, OTG, inst),\ + SRI(OTG_STATUS_POSITION, OTG, inst),\ + SRI(OTG_NOM_VERT_POSITION, OTG, inst),\ + SRI(OTG_M_CONST_DTO0, OTG, inst),\ + SRI(OTG_M_CONST_DTO1, OTG, inst),\ + SRI(OTG_CLOCK_CONTROL, OTG, inst),\ + SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\ + SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\ + SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\ + SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\ + SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\ + SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\ + SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\ + SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\ + SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\ + SRI(CONTROL, VTG, inst),\ + SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\ + SRI(OTG_GSL_CONTROL, OTG, inst),\ + SRI(OTG_CRC_CNTL, OTG, inst),\ + SRI(OTG_CRC0_DATA_RG, OTG, inst),\ + SRI(OTG_CRC0_DATA_B, OTG, inst),\ + SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\ + SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\ + SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\ + SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\ + SR(GSL_SOURCE_SELECT),\ + SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\ + SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\ + SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\ + SRI(OTG_GSL_WINDOW_X, OTG, inst),\ + SRI(OTG_GSL_WINDOW_Y, OTG, inst),\ + SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\ + SRI(OTG_DSC_START_POSITION, OTG, inst),\ + SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\ + SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\ + SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\ + SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\ + SRI(OPTC_WIDTH_CONTROL, ODM, inst),\ + SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ + SRI(OTG_DRR_CONTROL, OTG, inst) + +#define OPTC_COMMON_MASK_SH_LIST_DCN3_2(mask_sh)\ + SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ + SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\ + SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\ + SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\ + SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\ + SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\ + SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\ + SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\ + SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\ + SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\ + SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\ + SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\ + SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\ + SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\ + SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\ + SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\ + SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\ + SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\ + SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ + SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\ + SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\ + SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\ + SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\ + SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\ + SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\ + SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\ + SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\ + SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\ + SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\ + SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\ + SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\ + SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\ + SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\ + SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\ + SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\ + SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\ + SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\ + SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\ + SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\ + SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\ + SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\ + SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ + SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ + SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ + SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ + SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ + SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ + SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ + SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\ + SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\ + SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ + SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\ + SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\ + SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\ + SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\ + SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ + SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ + SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\ + SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\ + SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \ + SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\ + SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\ + SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \ + SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \ + SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \ + SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \ + SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \ + SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\ + SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\ + SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\ + SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\ + SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\ + SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\ + SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\ + SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\ + SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\ + SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ + SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ + SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) + +void dcn32_timing_generator_init(struct optc *optc1); + +#endif /* __DC_OPTC_DCN32_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c new file mode 100644 index 000000000000..17a287bc89ce --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c @@ -0,0 +1,3976 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" +#include "dc.h" + +#include "dcn32_init.h" + +#include "resource.h" +#include "include/irq_service_interface.h" +#include "dcn32_resource.h" + +#include "dcn20/dcn20_resource.h" +#include "dcn30/dcn30_resource.h" + +#include "dcn10/dcn10_ipp.h" +#include "dcn30/dcn30_hubbub.h" +#include "dcn31/dcn31_hubbub.h" +#include "dcn32/dcn32_hubbub.h" +#include "dcn32/dcn32_mpc.h" +#include "dcn32_hubp.h" +#include "irq/dcn32/irq_service_dcn32.h" +#include "dcn32/dcn32_dpp.h" +#include "dcn32/dcn32_optc.h" +#include "dcn20/dcn20_hwseq.h" +#include "dcn30/dcn30_hwseq.h" +#include "dce110/dce110_hw_sequencer.h" +#include "dcn30/dcn30_opp.h" +#include "dcn20/dcn20_dsc.h" +#include "dcn30/dcn30_vpg.h" +#include "dcn30/dcn30_afmt.h" +#include "dcn30/dcn30_dio_stream_encoder.h" +#include "dcn32/dcn32_dio_stream_encoder.h" +#include "dcn31/dcn31_hpo_dp_stream_encoder.h" +#include "dcn31/dcn31_hpo_dp_link_encoder.h" +#include "dcn32/dcn32_hpo_dp_link_encoder.h" +#include "dc_link_dp.h" +#include "dcn31/dcn31_apg.h" +#include "dcn31/dcn31_dio_link_encoder.h" +#include "dcn32/dcn32_dio_link_encoder.h" +#include "dce/dce_clock_source.h" +#include "dce/dce_audio.h" +#include "dce/dce_hwseq.h" +#include "clk_mgr.h" +#include "virtual/virtual_stream_encoder.h" +#include "dml/display_mode_vba.h" +#include "dcn32/dcn32_dccg.h" +#include "dcn10/dcn10_resource.h" +#include "dc_link_ddc.h" +#include "dcn31/dcn31_panel_cntl.h" + +#include "dcn30/dcn30_dwb.h" +#include "dcn32/dcn32_mmhubbub.h" + +#include "dcn/dcn_3_2_0_offset.h" +#include "dcn/dcn_3_2_0_sh_mask.h" +#include "dcn/nbio_4_3_0_offset.h" + +#include "reg_helper.h" +#include "dce/dmub_abm.h" +#include "dce/dmub_psr.h" +#include "dce/dce_aux.h" +#include "dce/dce_i2c.h" + +#include "dml/dcn30/display_mode_vba_30.h" +#include "vm_helper.h" +#include "dcn20/dcn20_vmid.h" + +#define DCN_BASE__INST0_SEG1 0x000000C0 +#define DCN_BASE__INST0_SEG2 0x000034C0 +#define DCN_BASE__INST0_SEG3 0x00009000 +#define NBIO_BASE__INST0_SEG1 0x00000014 + +#define MAX_INSTANCE 6 +#define MAX_SEGMENT 6 + +struct IP_BASE_INSTANCE { + unsigned int segment[MAX_SEGMENT]; +}; + +struct IP_BASE { + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; +}; + +static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; + +#define DC_LOGGER_INIT(logger) + +#define DCN3_2_DEFAULT_DET_SIZE 256 +#define DCN3_2_MAX_DET_SIZE 1152 +#define DCN3_2_MIN_DET_SIZE 128 +#define DCN3_2_MIN_COMPBUF_SIZE_KB 128 + +struct _vcs_dpi_ip_params_st dcn3_2_ip = { + .gpuvm_enable = 1, + .gpuvm_max_page_table_levels = 1, + .hostvm_enable = 0, + .rob_buffer_size_kbytes = 128, + .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE, + .config_return_buffer_size_in_kbytes = 1280, + .compressed_buffer_segment_size_in_kbytes = 64, + .meta_fifo_size_in_kentries = 22, + .zero_size_buffer_entries = 512, + .compbuf_reserved_space_64b = 256, + .compbuf_reserved_space_zs = 64, + .dpp_output_buffer_pixels = 2560, + .opp_output_buffer_lines = 1, + .pixel_chunk_size_kbytes = 8, + .alpha_pixel_chunk_size_kbytes = 4, // not appearing in spreadsheet, match c code from hw team + .min_pixel_chunk_size_bytes = 1024, + .dcc_meta_buffer_size_bytes = 6272, + .meta_chunk_size_kbytes = 2, + .min_meta_chunk_size_bytes = 256, + .writeback_chunk_size_kbytes = 8, + .ptoi_supported = false, + .num_dsc = 4, + .maximum_dsc_bits_per_component = 12, + .maximum_pixels_per_line_per_dsc_unit = 6016, + .dsc422_native_support = true, + .is_line_buffer_bpp_fixed = true, + .line_buffer_fixed_bpp = 57, + .line_buffer_size_bits = 1171920, //DPP doc, DCN3_2_DisplayMode_73.xlsm still shows as 986880 bits with 48 bpp + .max_line_buffer_lines = 32, + .writeback_interface_buffer_size_kbytes = 90, + .max_num_dpp = 4, + .max_num_otg = 4, + .max_num_hdmi_frl_outputs = 1, + .max_num_wb = 1, + .max_dchub_pscl_bw_pix_per_clk = 4, + .max_pscl_lb_bw_pix_per_clk = 2, + .max_lb_vscl_bw_pix_per_clk = 4, + .max_vscl_hscl_bw_pix_per_clk = 4, + .max_hscl_ratio = 6, + .max_vscl_ratio = 6, + .max_hscl_taps = 8, + .max_vscl_taps = 8, + .dpte_buffer_size_in_pte_reqs_luma = 64, + .dpte_buffer_size_in_pte_reqs_chroma = 34, + .dispclk_ramp_margin_percent = 1, + .max_inter_dcn_tile_repeaters = 8, + .cursor_buffer_size = 16, + .cursor_chunk_size = 2, + .writeback_line_buffer_buffer_size = 0, + .writeback_min_hscl_ratio = 1, + .writeback_min_vscl_ratio = 1, + .writeback_max_hscl_ratio = 1, + .writeback_max_vscl_ratio = 1, + .writeback_max_hscl_taps = 1, + .writeback_max_vscl_taps = 1, + .dppclk_delay_subtotal = 47, + .dppclk_delay_scl = 50, + .dppclk_delay_scl_lb_only = 16, + .dppclk_delay_cnvc_formatter = 28, + .dppclk_delay_cnvc_cursor = 6, + .dispclk_delay_subtotal = 125, + .dynamic_metadata_vm_enabled = false, + .odm_combine_4to1_supported = false, + .dcc_supported = true, + .max_num_dp2p0_outputs = 2, + .max_num_dp2p0_streams = 4, +}; + +struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = { + .clock_limits = { + { + .state = 0, + .dcfclk_mhz = 1564.0, + .fabricclk_mhz = 400.0, + .dispclk_mhz = 2150.0, + .dppclk_mhz = 2150.0, + .phyclk_mhz = 810.0, + .phyclk_d18_mhz = 667.0, + .phyclk_d32_mhz = 625.0, + .socclk_mhz = 1200.0, + .dscclk_mhz = 716.667, + .dram_speed_mts = 1600.0, + .dtbclk_mhz = 1564.0, + }, + }, + .num_states = 1, + .sr_exit_time_us = 5.20, + .sr_enter_plus_exit_time_us = 9.60, + .sr_exit_z8_time_us = 285.0, + .sr_enter_plus_exit_z8_time_us = 320, + .writeback_latency_us = 12.0, + .round_trip_ping_latency_dcfclk_cycles = 263, + .urgent_latency_pixel_data_only_us = 4.0, + .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, + .urgent_latency_vm_data_only_us = 4.0, + .fclk_change_latency_us = 20, + .usr_retraining_latency_us = 2, + .smn_latency_us = 2, + .mall_allocated_for_dcn_mbytes = 64, + .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, + .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, + .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, + .pct_ideal_sdp_bw_after_urgent = 100.0, + .pct_ideal_fabric_bw_after_urgent = 67.0, + .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0, + .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented + .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented + .pct_ideal_dram_bw_after_urgent_strobe = 67.0, + .max_avg_sdp_bw_use_normal_percent = 80.0, + .max_avg_fabric_bw_use_normal_percent = 60.0, + .max_avg_dram_bw_use_normal_strobe_percent = 50.0, + .max_avg_dram_bw_use_normal_percent = 15.0, + .num_chans = 8, + .dram_channel_width_bytes = 2, + .fabric_datapath_to_dcn_data_return_bytes = 64, + .return_bus_width_bytes = 64, + .downspread_percent = 0.38, + .dcn_downspread_percent = 0.5, + .dram_clock_change_latency_us = 400, + .dispclk_dppclk_vco_speed_mhz = 4300.0, + .do_urgent_latency_adjustment = true, + .urgent_latency_adjustment_fabric_clock_component_us = 1.0, + .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, +}; + +enum dcn32_clk_src_array_id { + DCN32_CLK_SRC_PLL0, + DCN32_CLK_SRC_PLL1, + DCN32_CLK_SRC_PLL2, + DCN32_CLK_SRC_PLL3, + DCN32_CLK_SRC_PLL4, + DCN32_CLK_SRC_TOTAL +}; + +/* begin ********************* + * macros to expend register list macro defined in HW object header file + */ + +/* DCN */ +/* TODO awful hack. fixup dcn20_dwb.h */ +#undef BASE_INNER +#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg + +#define BASE(seg) BASE_INNER(seg) + +#define SR(reg_name)\ + .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ + reg ## reg_name + +#define SRI(reg_name, block, id)\ + .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name + +#define SRI2(reg_name, block, id)\ + .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ + reg ## reg_name + +#define SRIR(var_name, reg_name, block, id)\ + .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name + +#define SRII(reg_name, block, id)\ + .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name + +#define SRII_MPC_RMU(reg_name, block, id)\ + .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name + +#define SRII_DWB(reg_name, temp_name, block, id)\ + .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## temp_name + +#define DCCG_SRII(reg_name, block, id)\ + .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name + +#define VUPDATE_SRII(reg_name, block, id)\ + .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ + reg ## reg_name ## _ ## block ## id + +/* NBIO */ +#define NBIO_BASE_INNER(seg) \ + NBIO_BASE__INST0_SEG ## seg + +#define NBIO_BASE(seg) \ + NBIO_BASE_INNER(seg) + +#define NBIO_SR(reg_name)\ + .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ + regBIF_BX0_ ## reg_name + +#define CTX ctx +#define REG(reg_name) \ + (DCN_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) + +static const struct bios_registers bios_regs = { + NBIO_SR(BIOS_SCRATCH_3), + NBIO_SR(BIOS_SCRATCH_6) +}; + +#define clk_src_regs(index, pllid)\ +[index] = {\ + CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ +} + +static const struct dce110_clk_src_regs clk_src_regs[] = { + clk_src_regs(0, A), + clk_src_regs(1, B), + clk_src_regs(2, C), + clk_src_regs(3, D) +}; + +static const struct dce110_clk_src_shift cs_shift = { + CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) +}; + +static const struct dce110_clk_src_mask cs_mask = { + CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) +}; + +#define abm_regs(id)\ +[id] = {\ + ABM_DCN32_REG_LIST(id)\ +} + +static const struct dce_abm_registers abm_regs[] = { + abm_regs(0), + abm_regs(1), + abm_regs(2), + abm_regs(3), +}; + +static const struct dce_abm_shift abm_shift = { + ABM_MASK_SH_LIST_DCN32(__SHIFT) +}; + +static const struct dce_abm_mask abm_mask = { + ABM_MASK_SH_LIST_DCN32(_MASK) +}; + +#define audio_regs(id)\ +[id] = {\ + AUD_COMMON_REG_LIST(id)\ +} + +static const struct dce_audio_registers audio_regs[] = { + audio_regs(0), + audio_regs(1), + audio_regs(2), + audio_regs(3), + audio_regs(4) +}; + +#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ + SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ + SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ + AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) + +static const struct dce_audio_shift audio_shift = { + DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) +}; + +static const struct dce_audio_mask audio_mask = { + DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) +}; + +#define vpg_regs(id)\ +[id] = {\ + VPG_DCN3_REG_LIST(id)\ +} + +static const struct dcn30_vpg_registers vpg_regs[] = { + vpg_regs(0), + vpg_regs(1), + vpg_regs(2), + vpg_regs(3), + vpg_regs(4), + vpg_regs(5), + vpg_regs(6), + vpg_regs(7), + vpg_regs(8), + vpg_regs(9), +}; + +static const struct dcn30_vpg_shift vpg_shift = { + DCN3_VPG_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn30_vpg_mask vpg_mask = { + DCN3_VPG_MASK_SH_LIST(_MASK) +}; + +#define afmt_regs(id)\ +[id] = {\ + AFMT_DCN3_REG_LIST(id)\ +} + +static const struct dcn30_afmt_registers afmt_regs[] = { + afmt_regs(0), + afmt_regs(1), + afmt_regs(2), + afmt_regs(3), + afmt_regs(4), + afmt_regs(5) +}; + +static const struct dcn30_afmt_shift afmt_shift = { + DCN3_AFMT_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn30_afmt_mask afmt_mask = { + DCN3_AFMT_MASK_SH_LIST(_MASK) +}; + +#define apg_regs(id)\ +[id] = {\ + APG_DCN31_REG_LIST(id)\ +} + +static const struct dcn31_apg_registers apg_regs[] = { + apg_regs(0), + apg_regs(1), + apg_regs(2), + apg_regs(3) +}; + +static const struct dcn31_apg_shift apg_shift = { + DCN31_APG_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn31_apg_mask apg_mask = { + DCN31_APG_MASK_SH_LIST(_MASK) +}; + +#define stream_enc_regs(id)\ +[id] = {\ + SE_DCN32_REG_LIST(id)\ +} + +static const struct dcn10_stream_enc_registers stream_enc_regs[] = { + stream_enc_regs(0), + stream_enc_regs(1), + stream_enc_regs(2), + stream_enc_regs(3), + stream_enc_regs(4) +}; + +static const struct dcn10_stream_encoder_shift se_shift = { + SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) +}; + +static const struct dcn10_stream_encoder_mask se_mask = { + SE_COMMON_MASK_SH_LIST_DCN32(_MASK) +}; + + +#define aux_regs(id)\ +[id] = {\ + DCN2_AUX_REG_LIST(id)\ +} + +static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { + aux_regs(0), + aux_regs(1), + aux_regs(2), + aux_regs(3), + aux_regs(4) +}; + +#define hpd_regs(id)\ +[id] = {\ + HPD_REG_LIST(id)\ +} + +static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { + hpd_regs(0), + hpd_regs(1), + hpd_regs(2), + hpd_regs(3), + hpd_regs(4) +}; + +#define link_regs(id, phyid)\ +[id] = {\ + LE_DCN31_REG_LIST(id), \ + UNIPHY_DCN2_REG_LIST(phyid), \ + /*DPCS_DCN31_REG_LIST(id),*/ \ +} + +static const struct dcn10_link_enc_registers link_enc_regs[] = { + link_regs(0, A), + link_regs(1, B), + link_regs(2, C), + link_regs(3, D), + link_regs(4, E) +}; + +static const struct dcn10_link_enc_shift le_shift = { + LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ + //DPCS_DCN31_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn10_link_enc_mask le_mask = { + LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ + + //DPCS_DCN31_MASK_SH_LIST(_MASK) +}; + +#define hpo_dp_stream_encoder_reg_list(id)\ +[id] = {\ + DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ +} + +static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { + hpo_dp_stream_encoder_reg_list(0), + hpo_dp_stream_encoder_reg_list(1), + hpo_dp_stream_encoder_reg_list(2), + hpo_dp_stream_encoder_reg_list(3), +}; + +static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { + DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { + DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) +}; + + +#define hpo_dp_link_encoder_reg_list(id)\ +[id] = {\ + DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ + /*DCN3_1_RDPCSTX_REG_LIST(0),*/\ + /*DCN3_1_RDPCSTX_REG_LIST(1),*/\ + /*DCN3_1_RDPCSTX_REG_LIST(2),*/\ + /*DCN3_1_RDPCSTX_REG_LIST(3),*/\ + /*DCN3_1_RDPCSTX_REG_LIST(4)*/\ +} + +static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { + hpo_dp_link_encoder_reg_list(0), + hpo_dp_link_encoder_reg_list(1), +}; + +static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { + DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { + DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) +}; + +#define dpp_regs(id)\ +[id] = {\ + DPP_REG_LIST_DCN30_COMMON(id),\ +} + +static const struct dcn3_dpp_registers dpp_regs[] = { + dpp_regs(0), + dpp_regs(1), + dpp_regs(2), + dpp_regs(3) +}; + +static const struct dcn3_dpp_shift tf_shift = { + DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) +}; + +static const struct dcn3_dpp_mask tf_mask = { + DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) +}; + + +#define opp_regs(id)\ +[id] = {\ + OPP_REG_LIST_DCN30(id),\ +} + +static const struct dcn20_opp_registers opp_regs[] = { + opp_regs(0), + opp_regs(1), + opp_regs(2), + opp_regs(3) +}; + +static const struct dcn20_opp_shift opp_shift = { + OPP_MASK_SH_LIST_DCN20(__SHIFT) +}; + +static const struct dcn20_opp_mask opp_mask = { + OPP_MASK_SH_LIST_DCN20(_MASK) +}; + +#define aux_engine_regs(id)\ +[id] = {\ + AUX_COMMON_REG_LIST0(id), \ + .AUXN_IMPCAL = 0, \ + .AUXP_IMPCAL = 0, \ + .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ +} + +static const struct dce110_aux_registers aux_engine_regs[] = { + aux_engine_regs(0), + aux_engine_regs(1), + aux_engine_regs(2), + aux_engine_regs(3), + aux_engine_regs(4) +}; + +static const struct dce110_aux_registers_shift aux_shift = { + DCN_AUX_MASK_SH_LIST(__SHIFT) +}; + +static const struct dce110_aux_registers_mask aux_mask = { + DCN_AUX_MASK_SH_LIST(_MASK) +}; + + +#define dwbc_regs_dcn3(id)\ +[id] = {\ + DWBC_COMMON_REG_LIST_DCN30(id),\ +} + +static const struct dcn30_dwbc_registers dwbc30_regs[] = { + dwbc_regs_dcn3(0), +}; + +static const struct dcn30_dwbc_shift dwbc30_shift = { + DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) +}; + +static const struct dcn30_dwbc_mask dwbc30_mask = { + DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) +}; + +#define mcif_wb_regs_dcn3(id)\ +[id] = {\ + MCIF_WB_COMMON_REG_LIST_DCN32(id),\ +} + +static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { + mcif_wb_regs_dcn3(0) +}; + +static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { + MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) +}; + +static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { + MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) +}; + +#define dsc_regsDCN20(id)\ +[id] = {\ + DSC_REG_LIST_DCN20(id)\ +} + +static const struct dcn20_dsc_registers dsc_regs[] = { + dsc_regsDCN20(0), + dsc_regsDCN20(1), + dsc_regsDCN20(2), + dsc_regsDCN20(3) +}; + +static const struct dcn20_dsc_shift dsc_shift = { + DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) +}; + +static const struct dcn20_dsc_mask dsc_mask = { + DSC_REG_LIST_SH_MASK_DCN20(_MASK) +}; + +static const struct dcn30_mpc_registers mpc_regs = { + MPC_REG_LIST_DCN3_0(0), + MPC_REG_LIST_DCN3_0(1), + MPC_REG_LIST_DCN3_0(2), + MPC_REG_LIST_DCN3_0(3), + MPC_OUT_MUX_REG_LIST_DCN3_0(0), + MPC_OUT_MUX_REG_LIST_DCN3_0(1), + MPC_OUT_MUX_REG_LIST_DCN3_0(2), + MPC_OUT_MUX_REG_LIST_DCN3_0(3), + MPC_MCM_REG_LIST_DCN32(0), + MPC_MCM_REG_LIST_DCN32(1), + MPC_MCM_REG_LIST_DCN32(2), + MPC_MCM_REG_LIST_DCN32(3), + MPC_DWB_MUX_REG_LIST_DCN3_0(0), +}; + +static const struct dcn30_mpc_shift mpc_shift = { + MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) +}; + +static const struct dcn30_mpc_mask mpc_mask = { + MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) +}; + +#define optc_regs(id)\ +[id] = {OPTC_COMMON_REG_LIST_DCN3_2(id)} + +//#ifdef DIAGS_BUILD +//static struct dcn_optc_registers optc_regs[] = { +//#else +static const struct dcn_optc_registers optc_regs[] = { +//#endif + optc_regs(0), + optc_regs(1), + optc_regs(2), + optc_regs(3) +}; + +static const struct dcn_optc_shift optc_shift = { + OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) +}; + +static const struct dcn_optc_mask optc_mask = { + OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) +}; + +#define hubp_regs(id)\ +[id] = {\ + HUBP_REG_LIST_DCN32(id)\ +} + +static const struct dcn_hubp2_registers hubp_regs[] = { + hubp_regs(0), + hubp_regs(1), + hubp_regs(2), + hubp_regs(3) +}; + + +static const struct dcn_hubp2_shift hubp_shift = { + HUBP_MASK_SH_LIST_DCN32(__SHIFT) +}; + +static const struct dcn_hubp2_mask hubp_mask = { + HUBP_MASK_SH_LIST_DCN32(_MASK) +}; +static const struct dcn_hubbub_registers hubbub_reg = { + HUBBUB_REG_LIST_DCN32(0) +}; + +static const struct dcn_hubbub_shift hubbub_shift = { + HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) +}; + +static const struct dcn_hubbub_mask hubbub_mask = { + HUBBUB_MASK_SH_LIST_DCN32(_MASK) +}; + +static const struct dccg_registers dccg_regs = { + DCCG_REG_LIST_DCN32() +}; + +static const struct dccg_shift dccg_shift = { + DCCG_MASK_SH_LIST_DCN32(__SHIFT) +}; + +static const struct dccg_mask dccg_mask = { + DCCG_MASK_SH_LIST_DCN32(_MASK) +}; + + +#define SRII2(reg_name_pre, reg_name_post, id)\ + .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ + ## id ## _ ## reg_name_post ## _BASE_IDX) + \ + reg ## reg_name_pre ## id ## _ ## reg_name_post + + +#define HWSEQ_DCN32_REG_LIST()\ + SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ + SR(DIO_MEM_PWR_CTRL), \ + SR(ODM_MEM_PWR_CTRL3), \ + SR(MMHUBBUB_MEM_PWR_CNTL), \ + SR(DCCG_GATE_DISABLE_CNTL), \ + SR(DCCG_GATE_DISABLE_CNTL2), \ + SR(DCFCLK_CNTL),\ + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ + SRII(PIXEL_RATE_CNTL, OTG, 0), \ + SRII(PIXEL_RATE_CNTL, OTG, 1),\ + SRII(PIXEL_RATE_CNTL, OTG, 2),\ + SRII(PIXEL_RATE_CNTL, OTG, 3),\ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ + SR(MICROSECOND_TIME_BASE_DIV), \ + SR(MILLISECOND_TIME_BASE_DIV), \ + SR(DISPCLK_FREQ_CHANGE_CNTL), \ + SR(RBBMIF_TIMEOUT_DIS), \ + SR(RBBMIF_TIMEOUT_DIS_2), \ + SR(DCHUBBUB_CRC_CTRL), \ + SR(DPP_TOP0_DPP_CRC_CTRL), \ + SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ + SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ + SR(MPC_CRC_CTRL), \ + SR(MPC_CRC_RESULT_GB), \ + SR(MPC_CRC_RESULT_C), \ + SR(MPC_CRC_RESULT_AR), \ + SR(DOMAIN0_PG_CONFIG), \ + SR(DOMAIN1_PG_CONFIG), \ + SR(DOMAIN2_PG_CONFIG), \ + SR(DOMAIN3_PG_CONFIG), \ + SR(DOMAIN16_PG_CONFIG), \ + SR(DOMAIN17_PG_CONFIG), \ + SR(DOMAIN18_PG_CONFIG), \ + SR(DOMAIN19_PG_CONFIG), \ + SR(DOMAIN0_PG_STATUS), \ + SR(DOMAIN1_PG_STATUS), \ + SR(DOMAIN2_PG_STATUS), \ + SR(DOMAIN3_PG_STATUS), \ + SR(DOMAIN16_PG_STATUS), \ + SR(DOMAIN17_PG_STATUS), \ + SR(DOMAIN18_PG_STATUS), \ + SR(DOMAIN19_PG_STATUS), \ + SR(D1VGA_CONTROL), \ + SR(D2VGA_CONTROL), \ + SR(D3VGA_CONTROL), \ + SR(D4VGA_CONTROL), \ + SR(D5VGA_CONTROL), \ + SR(D6VGA_CONTROL), \ + SR(DC_IP_REQUEST_CNTL), \ + SR(AZALIA_AUDIO_DTO), \ + SR(AZALIA_CONTROLLER_CLOCK_GATING) + +static const struct dce_hwseq_registers hwseq_reg = { + HWSEQ_DCN32_REG_LIST() +}; + +#define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ + HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ + HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ + HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ + HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ + HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ + HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ + HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ + HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) + +static const struct dce_hwseq_shift hwseq_shift = { + HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) +}; + +static const struct dce_hwseq_mask hwseq_mask = { + HWSEQ_DCN32_MASK_SH_LIST(_MASK) +}; +#define vmid_regs(id)\ +[id] = {\ + DCN20_VMID_REG_LIST(id)\ +} + +static const struct dcn_vmid_registers vmid_regs[] = { + vmid_regs(0), + vmid_regs(1), + vmid_regs(2), + vmid_regs(3), + vmid_regs(4), + vmid_regs(5), + vmid_regs(6), + vmid_regs(7), + vmid_regs(8), + vmid_regs(9), + vmid_regs(10), + vmid_regs(11), + vmid_regs(12), + vmid_regs(13), + vmid_regs(14), + vmid_regs(15) +}; + +static const struct dcn20_vmid_shift vmid_shifts = { + DCN20_VMID_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn20_vmid_mask vmid_masks = { + DCN20_VMID_MASK_SH_LIST(_MASK) +}; + +static const struct resource_caps res_cap_dcn32 = { + .num_timing_generator = 4, + .num_opp = 4, + .num_video_plane = 4, + .num_audio = 5, + .num_stream_encoder = 5, + .num_hpo_dp_stream_encoder = 4, + .num_hpo_dp_link_encoder = 2, + .num_pll = 5, + .num_dwb = 1, + .num_ddc = 5, + .num_vmid = 16, + .num_mpc_3dlut = 4, + .num_dsc = 4, +}; + +static const struct dc_plane_cap plane_cap = { + .type = DC_PLANE_TYPE_DCN_UNIVERSAL, + .blends_with_above = true, + .blends_with_below = true, + .per_pixel_alpha = true, + + .pixel_format_support = { + .argb8888 = true, + .nv12 = true, + .fp16 = true, + .p010 = true, + .ayuv = false, + }, + + .max_upscale_factor = { + .argb8888 = 16000, + .nv12 = 16000, + .fp16 = 16000 + }, + + // 6:1 downscaling ratio: 1000/6 = 166.666 + .max_downscale_factor = { + .argb8888 = 167, + .nv12 = 167, + .fp16 = 167 + }, + 64, + 64 +}; + +static const struct dc_debug_options debug_defaults_drv = { + .disable_dmcu = true, + .force_abm_enable = false, + .timing_trace = false, + .clock_trace = true, + .disable_pplib_clock_request = false, + .pipe_split_policy = MPC_SPLIT_DYNAMIC, + .force_single_disp_pipe_split = false, + .disable_dcc = DCC_ENABLE, + .vsr_support = true, + .performance_trace = false, + .max_downscale_src_width = 7680,/*upto 8K*/ + .disable_pplib_wm_range = false, + .scl_reset_length10 = true, + .sanity_checks = false, + .underflow_assert_delay_us = 0xFFFFFFFF, + .dwb_fi_phase = -1, // -1 = disable, + .dmub_command_table = true, + .enable_mem_low_power = { + .bits = { + .vga = false, + .i2c = false, + .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled + .dscl = false, + .cm = false, + .mpc = false, + .optc = false, + } + }, + .use_max_lb = true, + .force_disable_subvp = true +}; + +static const struct dc_debug_options debug_defaults_diags = { + .disable_dmcu = true, + .force_abm_enable = false, + .timing_trace = true, + .clock_trace = true, + .disable_dpp_power_gate = true, + .disable_hubp_power_gate = true, + .disable_dsc_power_gate = true, + .disable_clock_gate = true, + .disable_pplib_clock_request = true, + .disable_pplib_wm_range = true, + .disable_stutter = false, + .scl_reset_length10 = true, + .dwb_fi_phase = -1, // -1 = disable + .dmub_command_table = true, + .enable_tri_buf = true, + .use_max_lb = true, + .force_disable_subvp = true +}; + +static struct dce_aux *dcn32_aux_engine_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct aux_engine_dce110 *aux_engine = + kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); + + if (!aux_engine) + return NULL; + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, + &aux_engine_regs[inst], + &aux_mask, + &aux_shift, + ctx->dc->caps.extended_aux_timeout_support); + + return &aux_engine->base; +} +#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } + +static const struct dce_i2c_registers i2c_hw_regs[] = { + i2c_inst_regs(1), + i2c_inst_regs(2), + i2c_inst_regs(3), + i2c_inst_regs(4), + i2c_inst_regs(5), +}; + +static const struct dce_i2c_shift i2c_shifts = { + I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) +}; + +static const struct dce_i2c_mask i2c_masks = { + I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) +}; + +static struct dce_i2c_hw *dcn32_i2c_hw_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dce_i2c_hw *dce_i2c_hw = + kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); + + if (!dce_i2c_hw) + return NULL; + + dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, + &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); + + return dce_i2c_hw; +} + +static struct clock_source *dcn32_clock_source_create( + struct dc_context *ctx, + struct dc_bios *bios, + enum clock_source_id id, + const struct dce110_clk_src_regs *regs, + bool dp_clk_src) +{ + struct dce110_clk_src *clk_src = + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); + + if (!clk_src) + return NULL; + + if (dcn3_clk_src_construct(clk_src, ctx, bios, id, + regs, &cs_shift, &cs_mask)) { + clk_src->base.dp_clk_src = dp_clk_src; + return &clk_src->base; + } + + BREAK_TO_DEBUGGER(); + return NULL; +} + +static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx) +{ + int i; + + struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), + GFP_KERNEL); + + if (!hubbub2) + return NULL; + + hubbub32_construct(hubbub2, ctx, + &hubbub_reg, + &hubbub_shift, + &hubbub_mask, + ctx->dc->dml.ip.det_buffer_size_kbytes, + ctx->dc->dml.ip.pixel_chunk_size_kbytes, + ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); + + + for (i = 0; i < res_cap_dcn32.num_vmid; i++) { + struct dcn20_vmid *vmid = &hubbub2->vmid[i]; + + vmid->ctx = ctx; + + vmid->regs = &vmid_regs[i]; + vmid->shifts = &vmid_shifts; + vmid->masks = &vmid_masks; + } + + return &hubbub2->base; +} + +static struct hubp *dcn32_hubp_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn20_hubp *hubp2 = + kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); + + if (!hubp2) + return NULL; + + if (hubp32_construct(hubp2, ctx, inst, + &hubp_regs[inst], &hubp_shift, &hubp_mask)) + return &hubp2->base; + + BREAK_TO_DEBUGGER(); + kfree(hubp2); + return NULL; +} + +static void dcn32_dpp_destroy(struct dpp **dpp) +{ + kfree(TO_DCN30_DPP(*dpp)); + *dpp = NULL; +} + +static struct dpp *dcn32_dpp_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn3_dpp *dpp3 = + kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); + + if (!dpp3) + return NULL; + + if (dpp32_construct(dpp3, ctx, inst, + &dpp_regs[inst], &tf_shift, &tf_mask)) + return &dpp3->base; + + BREAK_TO_DEBUGGER(); + kfree(dpp3); + return NULL; +} + +static struct mpc *dcn32_mpc_create( + struct dc_context *ctx, + int num_mpcc, + int num_rmu) +{ + struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), + GFP_KERNEL); + + if (!mpc30) + return NULL; + + dcn32_mpc_construct(mpc30, ctx, + &mpc_regs, + &mpc_shift, + &mpc_mask, + num_mpcc, + num_rmu); + + return &mpc30->base; +} + +static struct output_pixel_processor *dcn32_opp_create( + struct dc_context *ctx, uint32_t inst) +{ + struct dcn20_opp *opp2 = + kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); + + if (!opp2) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dcn20_opp_construct(opp2, ctx, inst, + &opp_regs[inst], &opp_shift, &opp_mask); + return &opp2->base; +} + + +static struct timing_generator *dcn32_timing_generator_create( + struct dc_context *ctx, + uint32_t instance) +{ + struct optc *tgn10 = + kzalloc(sizeof(struct optc), GFP_KERNEL); + + if (!tgn10) + return NULL; + + tgn10->base.inst = instance; + tgn10->base.ctx = ctx; + + tgn10->tg_regs = &optc_regs[instance]; + tgn10->tg_shift = &optc_shift; + tgn10->tg_mask = &optc_mask; + + dcn32_timing_generator_init(tgn10); + + return &tgn10->base; +} + +static const struct encoder_feature_support link_enc_feature = { + .max_hdmi_deep_color = COLOR_DEPTH_121212, + .max_hdmi_pixel_clock = 600000, + .hdmi_ycbcr420_supported = true, + .dp_ycbcr420_supported = true, + .fec_supported = true, + .flags.bits.IS_HBR2_CAPABLE = true, + .flags.bits.IS_HBR3_CAPABLE = true, + .flags.bits.IS_TPS3_CAPABLE = true, + .flags.bits.IS_TPS4_CAPABLE = true +}; + +static struct link_encoder *dcn32_link_encoder_create( + const struct encoder_init_data *enc_init_data) +{ + struct dcn20_link_encoder *enc20 = + kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); + + if (!enc20) + return NULL; + + dcn32_link_encoder_construct(enc20, + enc_init_data, + &link_enc_feature, + &link_enc_regs[enc_init_data->transmitter], + &link_enc_aux_regs[enc_init_data->channel - 1], + &link_enc_hpd_regs[enc_init_data->hpd_source], + &le_shift, + &le_mask); + + return &enc20->enc10.base; +} + +struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data) +{ + struct dcn31_panel_cntl *panel_cntl = + kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); + + if (!panel_cntl) + return NULL; + + dcn31_panel_cntl_construct(panel_cntl, init_data); + + return &panel_cntl->base; +} + +static void read_dce_straps( + struct dc_context *ctx, + struct resource_straps *straps) +{ + generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), + FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); + +} + +static struct audio *dcn32_create_audio( + struct dc_context *ctx, unsigned int inst) +{ + return dce_audio_create(ctx, inst, + &audio_regs[inst], &audio_shift, &audio_mask); +} + +static struct vpg *dcn32_vpg_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); + + if (!vpg3) + return NULL; + + vpg3_construct(vpg3, ctx, inst, + &vpg_regs[inst], + &vpg_shift, + &vpg_mask); + + return &vpg3->base; +} + +static struct afmt *dcn32_afmt_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); + + if (!afmt3) + return NULL; + + afmt3_construct(afmt3, ctx, inst, + &afmt_regs[inst], + &afmt_shift, + &afmt_mask); + + return &afmt3->base; +} + +static struct apg *dcn31_apg_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); + + if (!apg31) + return NULL; + + apg31_construct(apg31, ctx, inst, + &apg_regs[inst], + &apg_shift, + &apg_mask); + + return &apg31->base; +} + +static struct stream_encoder *dcn32_stream_encoder_create( + enum engine_id eng_id, + struct dc_context *ctx) +{ + struct dcn10_stream_encoder *enc1; + struct vpg *vpg; + struct afmt *afmt; + int vpg_inst; + int afmt_inst; + + /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ + if (eng_id <= ENGINE_ID_DIGF) { + vpg_inst = eng_id; + afmt_inst = eng_id; + } else + return NULL; + + enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); + vpg = dcn32_vpg_create(ctx, vpg_inst); + afmt = dcn32_afmt_create(ctx, afmt_inst); + + if (!enc1 || !vpg || !afmt) { + kfree(enc1); + kfree(vpg); + kfree(afmt); + return NULL; + } + + dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, + eng_id, vpg, afmt, + &stream_enc_regs[eng_id], + &se_shift, &se_mask); + + return &enc1->base; +} + +static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create( + enum engine_id eng_id, + struct dc_context *ctx) +{ + struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; + struct vpg *vpg; + struct apg *apg; + uint32_t hpo_dp_inst; + uint32_t vpg_inst; + uint32_t apg_inst; + + ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); + hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; + + /* Mapping of VPG register blocks to HPO DP block instance: + * VPG[6] -> HPO_DP[0] + * VPG[7] -> HPO_DP[1] + * VPG[8] -> HPO_DP[2] + * VPG[9] -> HPO_DP[3] + */ + vpg_inst = hpo_dp_inst + 6; + + /* Mapping of APG register blocks to HPO DP block instance: + * APG[0] -> HPO_DP[0] + * APG[1] -> HPO_DP[1] + * APG[2] -> HPO_DP[2] + * APG[3] -> HPO_DP[3] + */ + apg_inst = hpo_dp_inst; + + /* allocate HPO stream encoder and create VPG sub-block */ + hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); + vpg = dcn32_vpg_create(ctx, vpg_inst); + apg = dcn31_apg_create(ctx, apg_inst); + + if (!hpo_dp_enc31 || !vpg || !apg) { + kfree(hpo_dp_enc31); + kfree(vpg); + kfree(apg); + return NULL; + } + + dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, + hpo_dp_inst, eng_id, vpg, apg, + &hpo_dp_stream_enc_regs[hpo_dp_inst], + &hpo_dp_se_shift, &hpo_dp_se_mask); + + return &hpo_dp_enc31->base; +} + +static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create( + uint8_t inst, + struct dc_context *ctx) +{ + struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; + + /* allocate HPO link encoder */ + hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); + + hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, + &hpo_dp_link_enc_regs[inst], + &hpo_dp_le_shift, &hpo_dp_le_mask); + + return &hpo_dp_enc31->base; +} + +static struct dce_hwseq *dcn32_hwseq_create( + struct dc_context *ctx) +{ + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); + + if (hws) { + hws->ctx = ctx; + hws->regs = &hwseq_reg; + hws->shifts = &hwseq_shift; + hws->masks = &hwseq_mask; + } + return hws; +} +static const struct resource_create_funcs res_create_funcs = { + .read_dce_straps = read_dce_straps, + .create_audio = dcn32_create_audio, + .create_stream_encoder = dcn32_stream_encoder_create, + .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, + .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, + .create_hwseq = dcn32_hwseq_create, +}; + +static const struct resource_create_funcs res_create_maximus_funcs = { + .read_dce_straps = NULL, + .create_audio = NULL, + .create_stream_encoder = NULL, + .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, + .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, + .create_hwseq = dcn32_hwseq_create, +}; + +static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) +{ + unsigned int i; + + for (i = 0; i < pool->base.stream_enc_count; i++) { + if (pool->base.stream_enc[i] != NULL) { + if (pool->base.stream_enc[i]->vpg != NULL) { + kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); + pool->base.stream_enc[i]->vpg = NULL; + } + if (pool->base.stream_enc[i]->afmt != NULL) { + kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); + pool->base.stream_enc[i]->afmt = NULL; + } + kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); + pool->base.stream_enc[i] = NULL; + } + } + + for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { + if (pool->base.hpo_dp_stream_enc[i] != NULL) { + if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { + kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); + pool->base.hpo_dp_stream_enc[i]->vpg = NULL; + } + if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { + kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); + pool->base.hpo_dp_stream_enc[i]->apg = NULL; + } + kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); + pool->base.hpo_dp_stream_enc[i] = NULL; + } + } + + for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { + if (pool->base.hpo_dp_link_enc[i] != NULL) { + kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); + pool->base.hpo_dp_link_enc[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + if (pool->base.dscs[i] != NULL) + dcn20_dsc_destroy(&pool->base.dscs[i]); + } + + if (pool->base.mpc != NULL) { + kfree(TO_DCN20_MPC(pool->base.mpc)); + pool->base.mpc = NULL; + } + if (pool->base.hubbub != NULL) { + kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); + pool->base.hubbub = NULL; + } + for (i = 0; i < pool->base.pipe_count; i++) { + if (pool->base.dpps[i] != NULL) + dcn32_dpp_destroy(&pool->base.dpps[i]); + + if (pool->base.ipps[i] != NULL) + pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); + + if (pool->base.hubps[i] != NULL) { + kfree(TO_DCN20_HUBP(pool->base.hubps[i])); + pool->base.hubps[i] = NULL; + } + + if (pool->base.irqs != NULL) { + dal_irq_service_destroy(&pool->base.irqs); + } + } + + for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + if (pool->base.engines[i] != NULL) + dce110_engine_destroy(&pool->base.engines[i]); + if (pool->base.hw_i2cs[i] != NULL) { + kfree(pool->base.hw_i2cs[i]); + pool->base.hw_i2cs[i] = NULL; + } + if (pool->base.sw_i2cs[i] != NULL) { + kfree(pool->base.sw_i2cs[i]); + pool->base.sw_i2cs[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_opp; i++) { + if (pool->base.opps[i] != NULL) + pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); + } + + for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + if (pool->base.timing_generators[i] != NULL) { + kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); + pool->base.timing_generators[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + if (pool->base.dwbc[i] != NULL) { + kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); + pool->base.dwbc[i] = NULL; + } + if (pool->base.mcif_wb[i] != NULL) { + kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); + pool->base.mcif_wb[i] = NULL; + } + } + + for (i = 0; i < pool->base.audio_count; i++) { + if (pool->base.audios[i]) + dce_aud_destroy(&pool->base.audios[i]); + } + + for (i = 0; i < pool->base.clk_src_count; i++) { + if (pool->base.clock_sources[i] != NULL) { + dcn20_clock_source_destroy(&pool->base.clock_sources[i]); + pool->base.clock_sources[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + if (pool->base.mpc_lut[i] != NULL) { + dc_3dlut_func_release(pool->base.mpc_lut[i]); + pool->base.mpc_lut[i] = NULL; + } + if (pool->base.mpc_shaper[i] != NULL) { + dc_transfer_func_release(pool->base.mpc_shaper[i]); + pool->base.mpc_shaper[i] = NULL; + } + } + + if (pool->base.dp_clock_source != NULL) { + dcn20_clock_source_destroy(&pool->base.dp_clock_source); + pool->base.dp_clock_source = NULL; + } + + for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + if (pool->base.multiple_abms[i] != NULL) + dce_abm_destroy(&pool->base.multiple_abms[i]); + } + + if (pool->base.psr != NULL) + dmub_psr_destroy(&pool->base.psr); + + if (pool->base.dccg != NULL) + dcn_dccg_destroy(&pool->base.dccg); + + if (pool->base.oem_device != NULL) + dal_ddc_service_destroy(&pool->base.oem_device); +} + + +static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) +{ + int i; + uint32_t dwb_count = pool->res_cap->num_dwb; + + for (i = 0; i < dwb_count; i++) { + struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), + GFP_KERNEL); + + if (!dwbc30) { + dm_error("DC: failed to create dwbc30!\n"); + return false; + } + + dcn30_dwbc_construct(dwbc30, ctx, + &dwbc30_regs[i], + &dwbc30_shift, + &dwbc30_mask, + i); + + pool->dwbc[i] = &dwbc30->base; + } + return true; +} + +static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) +{ + int i; + uint32_t dwb_count = pool->res_cap->num_dwb; + + for (i = 0; i < dwb_count; i++) { + struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), + GFP_KERNEL); + + if (!mcif_wb30) { + dm_error("DC: failed to create mcif_wb30!\n"); + return false; + } + + dcn32_mmhubbub_construct(mcif_wb30, ctx, + &mcif_wb30_regs[i], + &mcif_wb30_shift, + &mcif_wb30_mask, + i); + + pool->mcif_wb[i] = &mcif_wb30->base; + } + return true; +} + +static struct display_stream_compressor *dcn32_dsc_create( + struct dc_context *ctx, uint32_t inst) +{ + struct dcn20_dsc *dsc = + kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); + + if (!dsc) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); + return &dsc->base; +} + +static void dcn32_destroy_resource_pool(struct resource_pool **pool) +{ + struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool); + + dcn32_resource_destruct(dcn32_pool); + kfree(dcn32_pool); + *pool = NULL; +} + +bool dcn32_acquire_post_bldn_3dlut( + struct resource_context *res_ctx, + const struct resource_pool *pool, + int mpcc_id, + struct dc_3dlut **lut, + struct dc_transfer_func **shaper) +{ + bool ret = false; + union dc_3dlut_state *state; + + ASSERT(*lut == NULL && *shaper == NULL); + *lut = NULL; + *shaper = NULL; + + if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { + *lut = pool->mpc_lut[mpcc_id]; + *shaper = pool->mpc_shaper[mpcc_id]; + state = &pool->mpc_lut[mpcc_id]->state; + res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; + ret = true; + } + return ret; +} + +bool dcn32_release_post_bldn_3dlut( + struct resource_context *res_ctx, + const struct resource_pool *pool, + struct dc_3dlut **lut, + struct dc_transfer_func **shaper) +{ + int i; + bool ret = false; + + for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { + if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) { + res_ctx->is_mpc_3dlut_acquired[i] = false; + pool->mpc_lut[i]->state.raw = 0; + *lut = NULL; + *shaper = NULL; + ret = true; + break; + } + } + return ret; +} + +/** + ******************************************************************************************** + * dcn32_get_num_free_pipes: Calculate number of free pipes + * + * This function assumes that a "used" pipe is a pipe that has + * both a stream and a plane assigned to it. + * + * @param [in] dc: current dc state + * @param [in] context: new dc state + * + * @return: Number of free pipes available in the context + * + ******************************************************************************************** + */ +static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context) +{ + unsigned int i; + unsigned int free_pipes = 0; + unsigned int num_pipes = 0; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + + if (pipe->stream && pipe->plane_state && !pipe->top_pipe) { + while (pipe) { + num_pipes++; + pipe = pipe->bottom_pipe; + } + } + } + + free_pipes = dc->res_pool->pipe_count - num_pipes; + return free_pipes; +} + +/** + ******************************************************************************************** + * dcn32_assign_subvp_pipe: Function to decide which pipe will use Sub-VP. + * + * We enter this function if we are Sub-VP capable (i.e. enough pipes available) + * and regular P-State switching (i.e. VACTIVE/VBLANK) is not supported, or if + * we are forcing SubVP P-State switching on the current config. + * + * The number of pipes used for the chosen surface must be less than or equal to the + * number of free pipes available. + * + * In general we choose surfaces that have ActiveDRAMClockChangeLatencyMargin <= 0 first, + * then among those surfaces we choose the one with the smallest VBLANK time. We only consider + * surfaces with ActiveDRAMClockChangeLatencyMargin > 0 if we are forcing a Sub-VP config. + * + * @param [in] dc: current dc state + * @param [in] context: new dc state + * @param [out] index: dc pipe index for the pipe chosen to have phantom pipes assigned + * + * @return: True if a valid pipe assignment was found for Sub-VP. Otherwise false. + * + ******************************************************************************************** + */ + +static bool dcn32_assign_subvp_pipe(struct dc *dc, + struct dc_state *context, + unsigned int *index) +{ + unsigned int i, pipe_idx; + unsigned int min_vblank_us = INT_MAX; + struct vba_vars_st *vba = &context->bw_ctx.dml.vba; + bool valid_assignment_found = false; + unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context); + + for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + unsigned int num_pipes = 0; + + if (!pipe->stream) + continue; + + if (pipe->plane_state && !pipe->top_pipe && + pipe->stream->mall_stream_config.type == SUBVP_NONE) { + while (pipe) { + num_pipes++; + pipe = pipe->bottom_pipe; + } + + pipe = &context->res_ctx.pipe_ctx[i]; + if (num_pipes <= free_pipes) { + struct dc_stream_state *stream = pipe->stream; + unsigned int vblank_us = ((stream->timing.v_total - stream->timing.v_addressable) * + stream->timing.h_total / + (double)(stream->timing.pix_clk_100hz * 100)) * 1000000; + if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] <= 0 && + vblank_us < min_vblank_us) { + *index = i; + min_vblank_us = vblank_us; + valid_assignment_found = true; + } else if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 && + dc->debug.force_subvp_mclk_switch && !valid_assignment_found) { + // Handle case for forcing Sub-VP config. In this case we can assign + // phantom pipes to a surface that has active margin > 0. + *index = i; + valid_assignment_found = true; + } + } + } + pipe_idx++; + } + return valid_assignment_found; +} + +/** + * *************************************************************************************** + * dcn32_enough_pipes_for_subvp: Function to check if there are "enough" pipes for SubVP. + * + * This function returns true if there are enough free pipes + * to create the required phantom pipes for any given stream + * (that does not already have phantom pipe assigned). + * + * e.g. For a 2 stream config where the first stream uses one + * pipe and the second stream uses 2 pipes (i.e. pipe split), + * this function will return true because there is 1 remaining + * pipe which can be used as the phantom pipe for the non pipe + * split pipe. + * + * @param [in] dc: current dc state + * @param [in] context: new dc state + * + * @return: True if there are enough free pipes to assign phantom pipes to at least one + * stream that does not already have phantom pipes assigned. Otherwise false. + * + * *************************************************************************************** + */ +static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context) +{ + unsigned int i, split_cnt, free_pipes; + unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1 + bool subvp_possible = false; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + + // Find the minimum pipe split count for non SubVP pipes + if (pipe->stream && pipe->plane_state && !pipe->top_pipe && + pipe->stream->mall_stream_config.type == SUBVP_NONE) { + split_cnt = 0; + while (pipe) { + split_cnt++; + pipe = pipe->bottom_pipe; + } + + if (split_cnt < min_pipe_split) + min_pipe_split = split_cnt; + } + } + + free_pipes = dcn32_get_num_free_pipes(dc, context); + + // SubVP only possible if at least one pipe is being used (i.e. free_pipes + // should not equal to the pipe_count) + if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count) + subvp_possible = true; + + return subvp_possible; +} + +static void dcn32_enable_phantom_plane(struct dc *dc, + struct dc_state *context, + struct dc_stream_state *phantom_stream, + unsigned int dc_pipe_idx) +{ + struct dc_plane_state *phantom_plane = NULL; + struct dc_plane_state *prev_phantom_plane = NULL; + struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; + + while (curr_pipe) { + if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state) + phantom_plane = prev_phantom_plane; + else + phantom_plane = dc_create_plane_state(dc); + + memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address)); + memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality, + sizeof(phantom_plane->scaling_quality)); + memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect)); + memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect)); + memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect)); + memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size, + sizeof(phantom_plane->plane_size)); + memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info, + sizeof(phantom_plane->tiling_info)); + memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc)); + phantom_plane->format = curr_pipe->plane_state->format; + phantom_plane->rotation = curr_pipe->plane_state->rotation; + phantom_plane->visible = curr_pipe->plane_state->visible; + + /* Shadow pipe has small viewport. */ + phantom_plane->clip_rect.y = 0; + phantom_plane->clip_rect.height = phantom_stream->timing.v_addressable; + + dc_add_plane_to_context(dc, phantom_stream, phantom_plane, context); + + curr_pipe = curr_pipe->bottom_pipe; + prev_phantom_plane = phantom_plane; + } +} + +/** + * *************************************************************************************** + * dcn32_set_phantom_stream_timing: Set timing params for the phantom stream + * + * Set timing params of the phantom stream based on calculated output from DML. + * This function first gets the DML pipe index using the DC pipe index, then + * calls into DML (get_subviewport_lines_needed_in_mall) to get the number of + * lines required for SubVP MCLK switching and assigns to the phantom stream + * accordingly. + * + * - The number of SubVP lines calculated in DML does not take into account + * FW processing delays and required pstate allow width, so we must include + * that separately. + * + * - Set phantom backporch = vstartup of main pipe + * + * @param [in] dc: current dc state + * @param [in] context: new dc state + * @param [in] ref_pipe: Main pipe for the phantom stream + * @param [in] pipes: DML pipe params + * @param [in] pipe_cnt: number of DML pipes + * @param [in] dc_pipe_idx: DC pipe index for the main pipe (i.e. ref_pipe) + * + * @return: void + * + * *************************************************************************************** + */ +static void dcn32_set_phantom_stream_timing(struct dc *dc, + struct dc_state *context, + struct pipe_ctx *ref_pipe, + struct dc_stream_state *phantom_stream, + display_e2e_pipe_params_st *pipes, + unsigned int pipe_cnt, + unsigned int dc_pipe_idx) +{ + unsigned int i, pipe_idx; + struct pipe_ctx *pipe; + uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines; + unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel; + unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; + unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel]; + + // Find DML pipe index (pipe_idx) using dc_pipe_idx + for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { + pipe = &context->res_ctx.pipe_ctx[i]; + + if (!pipe->stream) + continue; + + if (i == dc_pipe_idx) + break; + + pipe_idx++; + } + + // Calculate lines required for pstate allow width and FW processing delays + pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us + + dc->caps.subvp_pstate_allow_width_us) / 1000000) * + (ref_pipe->stream->timing.pix_clk_100hz * 100) / + (double)ref_pipe->stream->timing.h_total; + + // Update clks_cfg for calling into recalculate + pipes[0].clks_cfg.voltage = vlevel; + pipes[0].clks_cfg.dcfclk_mhz = dcfclk; + pipes[0].clks_cfg.socclk_mhz = socclk; + + // DML calculation for MALL region doesn't take into account FW delay + // and required pstate allow width for multi-display cases + phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) + + pstate_width_fw_delay_lines; + + // For backporch of phantom pipe, use vstartup of the main pipe + phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + + phantom_stream->dst.y = 0; + phantom_stream->dst.height = phantom_vactive; + phantom_stream->src.y = 0; + phantom_stream->src.height = phantom_vactive; + + phantom_stream->timing.v_addressable = phantom_vactive; + phantom_stream->timing.v_front_porch = 1; + phantom_stream->timing.v_total = phantom_stream->timing.v_addressable + + phantom_stream->timing.v_front_porch + + phantom_stream->timing.v_sync_width + + phantom_bp; +} + +static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc, + struct dc_state *context, + display_e2e_pipe_params_st *pipes, + unsigned int pipe_cnt, + unsigned int dc_pipe_idx) +{ + struct dc_stream_state *phantom_stream = NULL; + struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; + + phantom_stream = dc_create_stream_for_sink(ref_pipe->stream->sink); + phantom_stream->signal = SIGNAL_TYPE_VIRTUAL; + phantom_stream->dpms_off = true; + phantom_stream->mall_stream_config.type = SUBVP_PHANTOM; + phantom_stream->mall_stream_config.paired_stream = ref_pipe->stream; + ref_pipe->stream->mall_stream_config.type = SUBVP_MAIN; + ref_pipe->stream->mall_stream_config.paired_stream = phantom_stream; + + /* stream has limited viewport and small timing */ + memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing)); + memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src)); + memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst)); + dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx); + + dc_add_stream_to_ctx(dc, context, phantom_stream); + return phantom_stream; +} + +void dcn32_remove_phantom_pipes(struct dc *dc, struct dc_state *context) +{ + int i; + bool removed_pipe = false; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + // build scaling params for phantom pipes + if (pipe->plane_state && pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { + dc_rem_all_planes_for_stream(dc, pipe->stream, context); + dc_remove_stream_from_ctx(dc, context, pipe->stream); + removed_pipe = true; + } + + // Clear all phantom stream info + if (pipe->stream) { + pipe->stream->mall_stream_config.type = SUBVP_NONE; + pipe->stream->mall_stream_config.paired_stream = NULL; + } + } + if (removed_pipe) + dc->hwss.apply_ctx_to_hw(dc, context); +} + +/* TODO: Input to this function should indicate which pipe indexes (or streams) + * require a phantom pipe / stream + */ +void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context, + display_e2e_pipe_params_st *pipes, + unsigned int pipe_cnt, + unsigned int index) +{ + struct dc_stream_state *phantom_stream = NULL; + unsigned int i; + + // The index of the DC pipe passed into this function is guarenteed to + // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't + // already have phantom pipe assigned, etc.) by previous checks. + phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index); + dcn32_enable_phantom_plane(dc, context, phantom_stream, index); + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + + // Build scaling params for phantom pipes which were newly added. + // We determine which phantom pipes were added by comparing with + // the phantom stream. + if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream && + pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { + pipe->stream->use_dynamic_meta = false; + pipe->plane_state->flip_immediate = false; + if (!resource_build_scaling_params(pipe)) { + // Log / remove phantom pipes since failed to build scaling params + } + } + } +} + +static bool dcn32_split_stream_for_mpc_or_odm( + const struct dc *dc, + struct resource_context *res_ctx, + struct pipe_ctx *pri_pipe, + struct pipe_ctx *sec_pipe, + bool odm) +{ + int pipe_idx = sec_pipe->pipe_idx; + const struct resource_pool *pool = dc->res_pool; + + if (pri_pipe->plane_state) { + /* ODM + window MPO, where MPO window is on left half only */ + if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <= + pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) + return true; + + /* ODM + window MPO, where MPO window is on right half only */ + if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.width/2) + return true; + } + + *sec_pipe = *pri_pipe; + + sec_pipe->pipe_idx = pipe_idx; + sec_pipe->plane_res.mi = pool->mis[pipe_idx]; + sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; + sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; + sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; + sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; + sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; + sec_pipe->stream_res.dsc = NULL; + if (odm) { + if (pri_pipe->next_odm_pipe) { + ASSERT(pri_pipe->next_odm_pipe != sec_pipe); + sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe; + sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe; + } + if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) { + pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe; + sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe; + } + if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) { + pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe; + sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe; + } + pri_pipe->next_odm_pipe = sec_pipe; + sec_pipe->prev_odm_pipe = pri_pipe; + ASSERT(sec_pipe->top_pipe == NULL); + + if (!sec_pipe->top_pipe) + sec_pipe->stream_res.opp = pool->opps[pipe_idx]; + else + sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; + if (sec_pipe->stream->timing.flags.DSC == 1) { + dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); + ASSERT(sec_pipe->stream_res.dsc); + if (sec_pipe->stream_res.dsc == NULL) + return false; + } + } else { + if (pri_pipe->bottom_pipe) { + ASSERT(pri_pipe->bottom_pipe != sec_pipe); + sec_pipe->bottom_pipe = pri_pipe->bottom_pipe; + sec_pipe->bottom_pipe->top_pipe = sec_pipe; + } + pri_pipe->bottom_pipe = sec_pipe; + sec_pipe->top_pipe = pri_pipe; + + ASSERT(pri_pipe->plane_state); + } + + return true; +} + +static struct pipe_ctx *dcn32_find_split_pipe( + struct dc *dc, + struct dc_state *context, + int old_index) +{ + struct pipe_ctx *pipe = NULL; + int i; + + if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) { + pipe = &context->res_ctx.pipe_ctx[old_index]; + pipe->pipe_idx = old_index; + } + + if (!pipe) + for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { + if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL + && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) { + if (context->res_ctx.pipe_ctx[i].stream == NULL) { + pipe = &context->res_ctx.pipe_ctx[i]; + pipe->pipe_idx = i; + break; + } + } + } + + /* + * May need to fix pipes getting tossed from 1 opp to another on flip + * Add for debugging transient underflow during topology updates: + * ASSERT(pipe); + */ + if (!pipe) + for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { + if (context->res_ctx.pipe_ctx[i].stream == NULL) { + pipe = &context->res_ctx.pipe_ctx[i]; + pipe->pipe_idx = i; + break; + } + } + + return pipe; +} + + +/** + * *************************************************************************************** + * subvp_subvp_schedulable: Determine if SubVP + SubVP config is schedulable + * + * High level algorithm: + * 1. Find longest microschedule length (in us) between the two SubVP pipes + * 2. Check if the worst case overlap (VBLANK in middle of ACTIVE) for both + * pipes still allows for the maximum microschedule to fit in the active + * region for both pipes. + * + * @param [in] dc: current dc state + * @param [in] context: new dc state + * + * @return: bool - True if the SubVP + SubVP config is schedulable, false otherwise + * + * *************************************************************************************** + */ +static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context) +{ + struct pipe_ctx *subvp_pipes[2]; + struct dc_stream_state *phantom = NULL; + uint32_t microschedule_lines = 0; + uint32_t index = 0; + uint32_t i; + uint32_t max_microschedule_us = 0; + int32_t vactive1_us, vactive2_us, vblank1_us, vblank2_us; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + uint32_t time_us = 0; + + /* Loop to calculate the maximum microschedule time between the two SubVP pipes, + * and also to store the two main SubVP pipe pointers in subvp_pipes[2]. + */ + if (pipe->stream && pipe->plane_state && !pipe->top_pipe && + pipe->stream->mall_stream_config.type == SUBVP_MAIN) { + phantom = pipe->stream->mall_stream_config.paired_stream; + microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) + + phantom->timing.v_addressable; + + // Round up when calculating microschedule time + time_us = ((microschedule_lines * phantom->timing.h_total + + phantom->timing.pix_clk_100hz * 100 - 1) / + (double)(phantom->timing.pix_clk_100hz * 100)) * 1000000 + + dc->caps.subvp_prefetch_end_to_mall_start_us + + dc->caps.subvp_fw_processing_delay_us; + if (time_us > max_microschedule_us) + max_microschedule_us = time_us; + + subvp_pipes[index] = pipe; + index++; + + // Maximum 2 SubVP pipes + if (index == 2) + break; + } + } + vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) / + (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; + vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) / + (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; + vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) * + subvp_pipes[0]->stream->timing.h_total) / + (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; + vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) * + subvp_pipes[1]->stream->timing.h_total) / + (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; + + if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us && + (vactive2_us - vblank1_us) / 2 > max_microschedule_us) + return true; + + return false; +} + +/** + * *************************************************************************************** + * subvp_drr_schedulable: Determine if SubVP + DRR config is schedulable + * + * High level algorithm: + * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe + * 2. Determine the frame time for the DRR display when adding required margin for MCLK switching + * (the margin is equal to the MALL region + DRR margin (500us)) + * 3.If (SubVP Active - Prefetch > Stretched DRR frame + max(MALL region, Stretched DRR frame)) + * then report the configuration as supported + * + * @param [in] dc: current dc state + * @param [in] context: new dc state + * @param [in] drr_pipe: DRR pipe_ctx for the SubVP + DRR config + * + * @return: bool - True if the SubVP + DRR config is schedulable, false otherwise + * + * *************************************************************************************** + */ +static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struct pipe_ctx *drr_pipe) +{ + bool schedulable = false; + uint32_t i; + struct pipe_ctx *pipe = NULL; + struct dc_crtc_timing *main_timing = NULL; + struct dc_crtc_timing *phantom_timing = NULL; + struct dc_crtc_timing *drr_timing = NULL; + int16_t prefetch_us = 0; + int16_t mall_region_us = 0; + int16_t drr_frame_us = 0; // nominal frame time + int16_t subvp_active_us = 0; + int16_t stretched_drr_us = 0; + int16_t drr_stretched_vblank_us = 0; + int16_t max_vblank_mallregion = 0; + + // Find SubVP pipe + for (i = 0; i < dc->res_pool->pipe_count; i++) { + pipe = &context->res_ctx.pipe_ctx[i]; + + // We check for master pipe, but it shouldn't matter since we only need + // the pipe for timing info (stream should be same for any pipe splits) + if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe) + continue; + + // Find the SubVP pipe + if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) + break; + } + + main_timing = &pipe->stream->timing; + phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing; + drr_timing = &drr_pipe->stream->timing; + prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / + (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + + dc->caps.subvp_prefetch_end_to_mall_start_us; + subvp_active_us = main_timing->v_addressable * main_timing->h_total / + (double)(main_timing->pix_clk_100hz * 100) * 1000000; + drr_frame_us = drr_timing->v_total * drr_timing->h_total / + (double)(drr_timing->pix_clk_100hz * 100) * 1000000; + // P-State allow width and FW delays already included phantom_timing->v_addressable + mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / + (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; + stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; + drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total / + (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us); + max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us; + + /* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the + * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis + * for VBLANK: (VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time, + * and the max of (VBLANK blanking time, MALL region)). + */ + if (stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 && + subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion > 0) + schedulable = true; + + return schedulable; +} + +/** + * *************************************************************************************** + * subvp_vblank_schedulable: Determine if SubVP + VBLANK config is schedulable + * + * High level algorithm: + * 1. Get timing for SubVP pipe, phantom pipe, and VBLANK pipe + * 2. If (SubVP Active - Prefetch > Vblank Frame Time + max(MALL region, Vblank blanking time)) + * then report the configuration as supported + * 3. If the VBLANK display is DRR, then take the DRR static schedulability path + * + * @param [in] dc: current dc state + * @param [in] context: new dc state + * + * @return: bool - True if the SubVP + VBLANK/DRR config is schedulable, false otherwise + * + * *************************************************************************************** + */ +static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context) +{ + struct pipe_ctx *pipe = NULL; + struct pipe_ctx *subvp_pipe = NULL; + bool found = false; + bool schedulable = false; + uint32_t i = 0; + uint8_t vblank_index = 0; + int16_t prefetch_us = 0; + int16_t mall_region_us = 0; + int16_t vblank_frame_us = 0; + int16_t subvp_active_us = 0; + int16_t vblank_blank_us = 0; + int16_t max_vblank_mallregion = 0; + struct dc_crtc_timing *main_timing = NULL; + struct dc_crtc_timing *phantom_timing = NULL; + struct dc_crtc_timing *vblank_timing = NULL; + + /* For SubVP + VBLANK/DRR cases, we assume there can only be + * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK + * is supported, it is either a single VBLANK case or two VBLANK + * displays which are synchronized (in which case they have identical + * timings). + */ + for (i = 0; i < dc->res_pool->pipe_count; i++) { + pipe = &context->res_ctx.pipe_ctx[i]; + + // We check for master pipe, but it shouldn't matter since we only need + // the pipe for timing info (stream should be same for any pipe splits) + if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe) + continue; + + if (!found && pipe->stream->mall_stream_config.type == SUBVP_NONE) { + // Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe). + vblank_index = i; + found = true; + } + + if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN) + subvp_pipe = pipe; + } + // Use ignore_msa_timing_param flag to identify as DRR + if (found && pipe->stream->ignore_msa_timing_param) { + // SUBVP + DRR case + schedulable = subvp_drr_schedulable(dc, context, &context->res_ctx.pipe_ctx[vblank_index]); + } else if (found) { + main_timing = &subvp_pipe->stream->timing; + phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; + vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing; + // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe + // Also include the prefetch end to mallstart delay time + prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / + (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + + dc->caps.subvp_prefetch_end_to_mall_start_us; + // P-State allow width and FW delays already included phantom_timing->v_addressable + mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / + (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; + vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total / + (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; + vblank_blank_us = (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total / + (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; + subvp_active_us = main_timing->v_addressable * main_timing->h_total / + (double)(main_timing->pix_clk_100hz * 100) * 1000000; + max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us; + + // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time, + // and the max of (VBLANK blanking time, MALL region) + // TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0) + if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0) + schedulable = true; + } + return schedulable; +} + +/** + * ******************************************************************************************** + * subvp_validate_static_schedulability: Check which SubVP case is calculated and handle + * static analysis based on the case. + * + * Three cases: + * 1. SubVP + SubVP + * 2. SubVP + VBLANK (DRR checked internally) + * 3. SubVP + VACTIVE (currently unsupported) + * + * @param [in] dc: current dc state + * @param [in] context: new dc state + * @param [in] vlevel: Voltage level calculated by DML + * + * @return: bool - True if statically schedulable, false otherwise + * + * ******************************************************************************************** + */ +static bool subvp_validate_static_schedulability(struct dc *dc, + struct dc_state *context, + int vlevel) +{ + bool schedulable = true; // true by default for single display case + struct vba_vars_st *vba = &context->bw_ctx.dml.vba; + uint32_t i, pipe_idx; + uint8_t subvp_count = 0; + uint8_t vactive_count = 0; + + for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + + if (!pipe->stream) + continue; + + if (pipe->plane_state && !pipe->top_pipe && + pipe->stream->mall_stream_config.type == SUBVP_MAIN) + subvp_count++; + + // Count how many planes are capable of VACTIVE switching (SubVP + VACTIVE unsupported) + if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0) { + vactive_count++; + } + pipe_idx++; + } + + if (subvp_count == 2) { + // Static schedulability check for SubVP + SubVP case + schedulable = subvp_subvp_schedulable(dc, context); + } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) { + // Static schedulability check for SubVP + VBLANK case. Also handle the case where + // DML outputs SubVP + VBLANK + VACTIVE (DML will report as SubVP + VBLANK) + if (vactive_count > 0) + schedulable = false; + else + schedulable = subvp_vblank_schedulable(dc, context); + } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp) { + // SubVP + VACTIVE currently unsupported + schedulable = false; + } + return schedulable; +} + +static void dcn32_full_validate_bw_helper(struct dc *dc, + struct dc_state *context, + display_e2e_pipe_params_st *pipes, + int *vlevel, + int *split, + bool *merge, + int *pipe_cnt) +{ + struct vba_vars_st *vba = &context->bw_ctx.dml.vba; + unsigned int dc_pipe_idx = 0; + bool found_supported_config = false; + struct pipe_ctx *pipe = NULL; + uint32_t non_subvp_pipes = 0; + bool drr_pipe_found = false; + uint32_t drr_pipe_index = 0; + uint32_t i = 0; + + /* + * DML favors voltage over p-state, but we're more interested in + * supporting p-state over voltage. We can't support p-state in + * prefetch mode > 0 so try capping the prefetch mode to start. + */ + context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = + dm_prefetch_support_uclk_fclk_and_stutter; + *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); + /* This may adjust vlevel and maxMpcComb */ + if (*vlevel < context->bw_ctx.dml.soc.num_states) + *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); + + /* Conditions for setting up phantom pipes for SubVP: + * 1. Not force disable SubVP + * 2. Full update (i.e. !fast_validate) + * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?) + * 4. Display configuration passes validation + * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch) + */ + if (!dc->debug.force_disable_subvp && + (*vlevel == context->bw_ctx.dml.soc.num_states || + vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported || + dc->debug.force_subvp_mclk_switch)) { + + while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) && + dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) { + + dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx); + + *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false); + *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); + + if (*vlevel < context->bw_ctx.dml.soc.num_states && + vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported + && subvp_validate_static_schedulability(dc, context, *vlevel)) { + found_supported_config = true; + } else if (*vlevel < context->bw_ctx.dml.soc.num_states && + vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) { + /* Case where 1 SubVP is added, and DML reports MCLK unsupported. This handles + * the case for SubVP + DRR, where the DRR display does not support MCLK switch + * at it's native refresh rate / timing. + */ + for (i = 0; i < dc->res_pool->pipe_count; i++) { + pipe = &context->res_ctx.pipe_ctx[i]; + if (pipe->stream && pipe->plane_state && !pipe->top_pipe && + pipe->stream->mall_stream_config.type == SUBVP_NONE) { + non_subvp_pipes++; + // Use ignore_msa_timing_param flag to identify as DRR + if (pipe->stream->ignore_msa_timing_param) { + drr_pipe_found = true; + drr_pipe_index = i; + } + } + } + // If there is only 1 remaining non SubVP pipe that is DRR, check static + // schedulability for SubVP + DRR. + if (non_subvp_pipes == 1 && drr_pipe_found) { + found_supported_config = subvp_drr_schedulable(dc, + context, &context->res_ctx.pipe_ctx[drr_pipe_index]); + } + } + } + + // If SubVP pipe config is unsupported (or cannot be used for UCLK switching) + // remove phantom pipes and repopulate dml pipes + if (!found_supported_config) { + dc->res_pool->funcs->remove_phantom_pipes(dc, context); + *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false); + } else { + // only call dcn20_validate_apply_pipe_split_flags if we found a supported config + memset(split, 0, MAX_PIPES * sizeof(int)); + memset(merge, 0, MAX_PIPES * sizeof(bool)); + *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); + + // If found a supported SubVP config, phantom pipes were added to the context. + // Program timing for the phantom pipes. + dc->hwss.apply_ctx_to_hw(dc, context); + } + } +} + +static bool dcn32_internal_validate_bw( + struct dc *dc, + struct dc_state *context, + display_e2e_pipe_params_st *pipes, + int *pipe_cnt_out, + int *vlevel_out, + bool fast_validate) +{ + bool out = false; + bool repopulate_pipes = false; + int split[MAX_PIPES] = { 0 }; + bool merge[MAX_PIPES] = { false }; + bool newly_split[MAX_PIPES] = { false }; + int pipe_cnt, i, pipe_idx, vlevel; + struct vba_vars_st *vba = &context->bw_ctx.dml.vba; + + ASSERT(pipes); + if (!pipes) + return false; + + // For each full update, remove all existing phantom pipes first + dc->res_pool->funcs->remove_phantom_pipes(dc, context); + + dc->res_pool->funcs->update_soc_for_wm_a(dc, context); + + pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); + + if (!pipe_cnt) { + out = true; + goto validate_out; + } + + dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt); + + if (!fast_validate) { + dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt); + } + + if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || + vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) { + /* + * If mode is unsupported or there's still no p-state support then + * fall back to favoring voltage. + * + * We don't actually support prefetch mode 2, so require that we + * at least support prefetch mode 1. + */ + context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = + dm_prefetch_support_stutter; + + vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); + if (vlevel < context->bw_ctx.dml.soc.num_states) { + memset(split, 0, MAX_PIPES * sizeof(int)); + memset(merge, 0, MAX_PIPES * sizeof(bool)); + vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); + } + } + + dml_log_mode_support_params(&context->bw_ctx.dml); + + if (vlevel == context->bw_ctx.dml.soc.num_states) + goto validate_fail; + + for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; + + if (!pipe->stream) + continue; + + /* We only support full screen mpo with ODM */ + if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled + && pipe->plane_state && mpo_pipe + && memcmp(&mpo_pipe->plane_res.scl_data.recout, + &pipe->plane_res.scl_data.recout, + sizeof(struct rect)) != 0) { + ASSERT(mpo_pipe->plane_state != pipe->plane_state); + goto validate_fail; + } + pipe_idx++; + } + + /* merge pipes if necessary */ + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + + /*skip pipes that don't need merging*/ + if (!merge[i]) + continue; + + /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */ + if (pipe->prev_odm_pipe) { + /*split off odm pipe*/ + pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe; + if (pipe->next_odm_pipe) + pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe; + + pipe->bottom_pipe = NULL; + pipe->next_odm_pipe = NULL; + pipe->plane_state = NULL; + pipe->stream = NULL; + pipe->top_pipe = NULL; + pipe->prev_odm_pipe = NULL; + if (pipe->stream_res.dsc) + dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); + memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); + memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); + repopulate_pipes = true; + } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { + struct pipe_ctx *top_pipe = pipe->top_pipe; + struct pipe_ctx *bottom_pipe = pipe->bottom_pipe; + + top_pipe->bottom_pipe = bottom_pipe; + if (bottom_pipe) + bottom_pipe->top_pipe = top_pipe; + + pipe->top_pipe = NULL; + pipe->bottom_pipe = NULL; + pipe->plane_state = NULL; + pipe->stream = NULL; + memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); + memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); + repopulate_pipes = true; + } else + ASSERT(0); /* Should never try to merge master pipe */ + + } + + for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; + struct pipe_ctx *hsplit_pipe = NULL; + bool odm; + int old_index = -1; + + if (!pipe->stream || newly_split[i]) + continue; + + pipe_idx++; + odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled; + + if (!pipe->plane_state && !odm) + continue; + + if (split[i]) { + if (odm) { + if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe) + old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx; + else if (old_pipe->next_odm_pipe) + old_index = old_pipe->next_odm_pipe->pipe_idx; + } else { + if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe && + old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state) + old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx; + else if (old_pipe->bottom_pipe && + old_pipe->bottom_pipe->plane_state == old_pipe->plane_state) + old_index = old_pipe->bottom_pipe->pipe_idx; + } + hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index); + ASSERT(hsplit_pipe); + if (!hsplit_pipe) + goto validate_fail; + + if (!dcn32_split_stream_for_mpc_or_odm( + dc, &context->res_ctx, + pipe, hsplit_pipe, odm)) + goto validate_fail; + + newly_split[hsplit_pipe->pipe_idx] = true; + repopulate_pipes = true; + } + if (split[i] == 4) { + struct pipe_ctx *pipe_4to1; + + if (odm && old_pipe->next_odm_pipe) + old_index = old_pipe->next_odm_pipe->pipe_idx; + else if (!odm && old_pipe->bottom_pipe && + old_pipe->bottom_pipe->plane_state == old_pipe->plane_state) + old_index = old_pipe->bottom_pipe->pipe_idx; + else + old_index = -1; + pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index); + ASSERT(pipe_4to1); + if (!pipe_4to1) + goto validate_fail; + if (!dcn32_split_stream_for_mpc_or_odm( + dc, &context->res_ctx, + pipe, pipe_4to1, odm)) + goto validate_fail; + newly_split[pipe_4to1->pipe_idx] = true; + + if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe + && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe) + old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx; + else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe && + old_pipe->bottom_pipe->bottom_pipe->bottom_pipe && + old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state) + old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx; + else + old_index = -1; + pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index); + ASSERT(pipe_4to1); + if (!pipe_4to1) + goto validate_fail; + if (!dcn32_split_stream_for_mpc_or_odm( + dc, &context->res_ctx, + hsplit_pipe, pipe_4to1, odm)) + goto validate_fail; + newly_split[pipe_4to1->pipe_idx] = true; + } + if (odm) + dcn20_build_mapped_resource(dc, context, pipe->stream); + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + + if (pipe->plane_state) { + if (!resource_build_scaling_params(pipe)) + goto validate_fail; + } + } + + /* Actual dsc count per stream dsc validation*/ + if (!dcn20_validate_dsc(dc, context)) { + vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; + goto validate_fail; + } + + if (repopulate_pipes) + pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); + *vlevel_out = vlevel; + *pipe_cnt_out = pipe_cnt; + + out = true; + goto validate_out; + +validate_fail: + out = false; + +validate_out: + return out; +} + +bool dcn32_validate_bandwidth(struct dc *dc, + struct dc_state *context, + bool fast_validate) +{ + bool out = false; + + BW_VAL_TRACE_SETUP(); + + int vlevel = 0; + int pipe_cnt = 0; + display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); + DC_LOGGER_INIT(dc->ctx->logger); + + BW_VAL_TRACE_COUNT(); + + DC_FP_START(); + out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); + DC_FP_END(); + + if (pipe_cnt == 0) + goto validate_out; + + if (!out) + goto validate_fail; + + BW_VAL_TRACE_END_VOLTAGE_LEVEL(); + + if (fast_validate) { + BW_VAL_TRACE_SKIP(fast); + goto validate_out; + } + + dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); + + BW_VAL_TRACE_END_WATERMARKS(); + + goto validate_out; + +validate_fail: + DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", + dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); + + BW_VAL_TRACE_SKIP(fail); + out = false; + +validate_out: + kfree(pipes); + + BW_VAL_TRACE_FINISH(); + + return out; +} + + +static bool is_dual_plane(enum surface_pixel_format format) +{ + return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; +} + +int dcn32_populate_dml_pipes_from_context( + struct dc *dc, struct dc_state *context, + display_e2e_pipe_params_st *pipes, + bool fast_validate) +{ + int i, pipe_cnt; + struct resource_context *res_ctx = &context->res_ctx; + struct pipe_ctx *pipe; + + dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); + + for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { + struct dc_crtc_timing *timing; + + if (!res_ctx->pipe_ctx[i].stream) + continue; + pipe = &res_ctx->pipe_ctx[i]; + timing = &pipe->stream->timing; + + pipes[pipe_cnt].pipe.src.gpuvm = true; + pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; + pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; + pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; + pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet + pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; + pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19; + + switch (pipe->stream->mall_stream_config.type) { + case SUBVP_MAIN: + pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport; + break; + case SUBVP_PHANTOM: + pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe; + pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_enable; + break; + case SUBVP_NONE: + pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable; + pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; + break; + default: + break; + } + + pipes[pipe_cnt].dout.dsc_input_bpc = 0; + if (pipes[pipe_cnt].dout.dsc_enable) { + switch (timing->display_color_depth) { + case COLOR_DEPTH_888: + pipes[pipe_cnt].dout.dsc_input_bpc = 8; + break; + case COLOR_DEPTH_101010: + pipes[pipe_cnt].dout.dsc_input_bpc = 10; + break; + case COLOR_DEPTH_121212: + pipes[pipe_cnt].dout.dsc_input_bpc = 12; + break; + default: + ASSERT(0); + break; + } + } + pipe_cnt++; + } + context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE; + + if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { + if (!is_dual_plane(pipe->plane_state->format)) { + context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; + pipes[0].pipe.src.unbounded_req_mode = true; + } + } + + return pipe_cnt; +} + +void dcn32_calculate_wm_and_dlg_fp( + struct dc *dc, struct dc_state *context, + display_e2e_pipe_params_st *pipes, + int pipe_cnt, + int vlevel) +{ + int i, pipe_idx, vlevel_temp = 0; + + double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz; + double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; + unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; + bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != + dm_dram_clock_change_unsupported; + + /* Set B: + * For Set B calculations use clocks from clock_limits[2] when available i.e. when SMU is present, + * otherwise use arbitrary low value from spreadsheet for DCFCLK as lower is safer for watermark + * calculations to cover bootup clocks. + * DCFCLK: soc.clock_limits[2] when available + * UCLK: soc.clock_limits[2] when available + */ + if (dcn3_2_soc.num_states > 2) { + vlevel_temp = 2; + dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz; + } else + dcfclk = 615; //DCFCLK Vmin_lv + + pipes[0].clks_cfg.voltage = vlevel_temp; + pipes[0].clks_cfg.dcfclk_mhz = dcfclk; + pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz; + + if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { + context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us; + context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us; + context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; + context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; + } + context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + + /* Set D: + * All clocks min. + * DCFCLK: Min, as reported by PM FW when available + * UCLK : Min, as reported by PM FW when available + * sr_enter_exit/sr_exit should be lower than used for DRAM (TBD after bringup or later, use as decided in Clk Mgr) + */ + + if (dcn3_2_soc.num_states > 2) { + vlevel_temp = 0; + dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; + } else + dcfclk = 615; //DCFCLK Vmin_lv + + pipes[0].clks_cfg.voltage = vlevel_temp; + pipes[0].clks_cfg.dcfclk_mhz = dcfclk; + pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz; + + if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { + context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us; + context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us; + context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us; + context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us; + } + context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + + /* Set C, for Dummy P-State: + * All clocks min. + * DCFCLK: Min, as reported by PM FW, when available + * UCLK : Min, as reported by PM FW, when available + * pstate latency as per UCLK state dummy pstate latency + */ + + if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { + unsigned int min_dram_speed_mts_margin = 160; + + if ((!pstate_en)) + min_dram_speed_mts = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz * 16; + + /* find largest table entry that is lower than dram speed, but lower than DPM0 still uses DPM0 */ + for (i = 3; i > 0; i--) + if (min_dram_speed_mts + min_dram_speed_mts_margin > dc->clk_mgr->bw_params->dummy_pstate_table[i].dram_speed_mts) + break; + + context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us; + context->bw_ctx.dml.soc.dummy_pstate_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us; + context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us; + context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us; + context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; + } + context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + + if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) { + /* The only difference between A and C is p-state latency, if p-state is not supported + * with full p-state latency we want to calculate DLG based on dummy p-state latency, + * Set A p-state watermark set to 0 on DCN32, when p-state unsupported, for now keep as DCN32. + */ + context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c; + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0; + } else { + /* Set A: + * All clocks min. + * DCFCLK: Min, as reported by PM FW, when available + * UCLK: Min, as reported by PM FW, when available + */ + dc->res_pool->funcs->update_soc_for_wm_a(dc, context); + context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + } + + pipes[0].clks_cfg.voltage = vlevel; + pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation; + pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; + + for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { + if (!context->res_ctx.pipe_ctx[i].stream) + continue; + + pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); + pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + + if (dc->config.forced_clocks) { + pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; + pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; + } + if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) + pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; + if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) + pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; + + pipe_idx++; + } + + context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod; + + dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); + + if (!pstate_en) + /* Restore full p-state latency */ + context->bw_ctx.dml.soc.dram_clock_change_latency_us = + dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; +} + +static struct dc_cap_funcs cap_funcs = { + .get_dcc_compression_cap = dcn20_get_dcc_compression_cap +}; + + +static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, + unsigned int *optimal_dcfclk, + unsigned int *optimal_fclk) +{ + double bw_from_dram, bw_from_dram1, bw_from_dram2; + + bw_from_dram1 = uclk_mts * dcn3_2_soc.num_chans * + dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100); + bw_from_dram2 = uclk_mts * dcn3_2_soc.num_chans * + dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100); + + bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; + + if (optimal_fclk) + *optimal_fclk = bw_from_dram / + (dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100)); + + if (optimal_dcfclk) + *optimal_dcfclk = bw_from_dram / + (dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100)); +} + +void dcn32_calculate_wm_and_dlg( + struct dc *dc, struct dc_state *context, + display_e2e_pipe_params_st *pipes, + int pipe_cnt, + int vlevel) +{ + DC_FP_START(); + dcn32_calculate_wm_and_dlg_fp( + dc, context, + pipes, + pipe_cnt, + vlevel); + DC_FP_END(); +} + +static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) +{ + int i; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (!context->res_ctx.pipe_ctx[i].stream) + continue; + if (is_dp_128b_132b_signal(&context->res_ctx.pipe_ctx[i])) + return true; + } + return false; +} + +void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, + int pipe_cnt, int vlevel) +{ + int i, pipe_idx; + bool usr_retraining_support = false; + + /* Writeback MCIF_WB arbitration parameters */ + dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); + + context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; + context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; + context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; + context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; + context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; + context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; + context->bw_ctx.bw.dcn.clk.p_state_change_support = + context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] + != dm_dram_clock_change_unsupported; + + /* + * TODO: needs FAMS + * Pstate change might not be supported by hardware, but it might be + * possible with firmware driven vertical blank stretching. + */ + // context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching; + + context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; + context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); + if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported) + context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false; + else + context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true; + + usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; + ASSERT(usr_retraining_support); + + if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) + context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; + + for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { + if (!context->res_ctx.pipe_ctx[i].stream) + continue; + pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, + pipe_idx); + pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, + pipe_idx); + pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, + pipe_idx); + pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, + pipe_idx); + if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { + // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests + context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0; + context->res_ctx.pipe_ctx[i].unbounded_req = false; + } else { + context->res_ctx.pipe_ctx[i].det_buffer_size_kb = + context->bw_ctx.dml.ip.det_buffer_size_kbytes; + context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode; + } + if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) + context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; + context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; + context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; + pipe_idx++; + } + /*save a original dppclock copy*/ + context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; + context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; + context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz + * 1000; + context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz + * 1000; + + context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes + - context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx; + + for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { + + if (!context->res_ctx.pipe_ctx[i].stream) + continue; + + /* cstate disabled on 201 */ +// if (dc->ctx->dce_version == DCN_VERSION_2_01) +// cstate_en = false; + + + context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml, + &context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes, + pipe_cnt, pipe_idx); + + context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs, + &context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + + pipe_idx++; + } +} + +/* dcn32_update_bw_bounding_box + * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet + * with actual values as per dGPU SKU: + * -with passed few options from dc->config + * -with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might need to get it from PM FW) + * -with passed latency values (passed in ns units) in dc-> bb override for debugging purposes + * -with passed latencies from VBIOS (in 100_ns units) if available for certain dGPU SKU + * -with number of DRAM channels from VBIOS (which differ for certain dGPU SKU of the same ASIC) + * -clocks levels with passed clk_table entries from Clk Mgr as reported by PM FW for different + * clocks (which might differ for certain dGPU SKU of the same ASIC) + */ +static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) +{ + if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + + /* Overrides from dc->config options */ + dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk; + + /* Override from passed dc->bb_overrides if available*/ + if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns + && dc->bb_overrides.sr_exit_time_ns) { + dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; + } + + if ((int)(dcn3_2_soc.sr_enter_plus_exit_time_us * 1000) + != dc->bb_overrides.sr_enter_plus_exit_time_ns + && dc->bb_overrides.sr_enter_plus_exit_time_ns) { + dcn3_2_soc.sr_enter_plus_exit_time_us = + dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; + } + + if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns + && dc->bb_overrides.urgent_latency_ns) { + dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; + } + + if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000) + != dc->bb_overrides.dram_clock_change_latency_ns + && dc->bb_overrides.dram_clock_change_latency_ns) { + dcn3_2_soc.dram_clock_change_latency_us = + dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; + } + + if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000) + != dc->bb_overrides.dummy_clock_change_latency_ns + && dc->bb_overrides.dummy_clock_change_latency_ns) { + dcn3_2_soc.dummy_pstate_latency_us = + dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0; + } + + /* Override from VBIOS if VBIOS bb_info available */ + if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { + struct bp_soc_bb_info bb_info = {0}; + + if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { + if (bb_info.dram_clock_change_latency_100ns > 0) + dcn3_2_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; + + if (bb_info.dram_sr_enter_exit_latency_100ns > 0) + dcn3_2_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10; + + if (bb_info.dram_sr_exit_latency_100ns > 0) + dcn3_2_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10; + } + } + + /* Override from VBIOS for num_chan */ + if (dc->ctx->dc_bios->vram_info.num_chans) + dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; + + if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) + dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; + + } + + /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */ + dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; + dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; + + /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */ + if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) { + unsigned int i = 0, j = 0, num_states = 0; + + unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; + unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; + unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; + unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; + + unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564}; + unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; + unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; + + for (i = 0; i < MAX_NUM_DPM_LVL; i++) { + if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) + max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; + if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) + max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; + if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) + max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; + if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) + max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; + } + if (!max_dcfclk_mhz) + max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz; + if (!max_dispclk_mhz) + max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz; + if (!max_dppclk_mhz) + max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz; + if (!max_phyclk_mhz) + max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz; + + if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { + // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array + dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; + num_dcfclk_sta_targets++; + } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { + // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates + for (i = 0; i < num_dcfclk_sta_targets; i++) { + if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { + dcfclk_sta_targets[i] = max_dcfclk_mhz; + break; + } + } + // Update size of array since we "removed" duplicates + num_dcfclk_sta_targets = i + 1; + } + + num_uclk_states = bw_params->clk_table.num_entries; + + // Calculate optimal dcfclk for each uclk + for (i = 0; i < num_uclk_states; i++) { + dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, + &optimal_dcfclk_for_uclk[i], NULL); + if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { + optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; + } + } + + // Calculate optimal uclk for each dcfclk sta target + for (i = 0; i < num_dcfclk_sta_targets; i++) { + for (j = 0; j < num_uclk_states; j++) { + if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { + optimal_uclk_for_dcfclk_sta_targets[i] = + bw_params->clk_table.entries[j].memclk_mhz * 16; + break; + } + } + } + + i = 0; + j = 0; + // create the final dcfclk and uclk table + while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { + if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { + dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; + dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; + } else { + if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { + dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; + dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; + } else { + j = num_uclk_states; + } + } + } + + while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { + dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; + dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; + } + + while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && + optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { + dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; + dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; + } + + dcn3_2_soc.num_states = num_states; + for (i = 0; i < dcn3_2_soc.num_states; i++) { + dcn3_2_soc.clock_limits[i].state = i; + dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; + dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; + dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; + + /* Fill all states with max values of all these clocks */ + dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; + dcn3_2_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; + dcn3_2_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; + dcn3_2_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3; + + /* Populate from bw_params for DTBCLK, SOCCLK */ + if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0) + dcn3_2_soc.clock_limits[i].dtbclk_mhz = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz; + else + dcn3_2_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; + + if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) + dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz; + else + dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; + + /* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */ + /* PHYCLK_D18, PHYCLK_D32 */ + dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz; + dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz; + } + + /* Re-init DML with updated bb */ + dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); + if (dc->current_state) + dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); + } +} + +static struct resource_funcs dcn32_res_pool_funcs = { + .destroy = dcn32_destroy_resource_pool, + .link_enc_create = dcn32_link_encoder_create, + .link_enc_create_minimal = NULL, + .panel_cntl_create = dcn32_panel_cntl_create, + .validate_bandwidth = dcn32_validate_bandwidth, + .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, + .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, + .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, + .add_stream_to_ctx = dcn30_add_stream_to_ctx, + .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, + .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, + .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, + .set_mcif_arb_params = dcn30_set_mcif_arb_params, + .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, + .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, + .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, + .update_bw_bounding_box = dcn32_update_bw_bounding_box, + .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, + .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, + .add_phantom_pipes = dcn32_add_phantom_pipes, + .remove_phantom_pipes = dcn32_remove_phantom_pipes, +}; + + +static bool dcn32_resource_construct( + uint8_t num_virtual_links, + struct dc *dc, + struct dcn32_resource_pool *pool) +{ + int i, j; + struct dc_context *ctx = dc->ctx; + struct irq_service_init_data init_data; + struct ddc_service_init_data ddc_init_data = {0}; + uint32_t pipe_fuses = 0; + uint32_t num_pipes = 4; + + DC_FP_START(); + + ctx->dc_bios->regs = &bios_regs; + + pool->base.res_cap = &res_cap_dcn32; + /* max number of pipes for ASIC before checking for pipe fuses */ + num_pipes = pool->base.res_cap->num_timing_generator; + pipe_fuses = REG_READ(CC_DC_PIPE_DIS); + + for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) + if (pipe_fuses & 1 << i) + num_pipes--; + + if (pipe_fuses & 1) + ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! + + if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) + ASSERT(0); //Entire DCN is harvested! + + /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the + * value will be changed, update max_num_dpp and max_num_otg for dml. + */ + dcn3_2_ip.max_num_dpp = num_pipes; + dcn3_2_ip.max_num_otg = num_pipes; + + pool->base.funcs = &dcn32_res_pool_funcs; + + /************************************************* + * Resource + asic cap harcoding * + *************************************************/ + pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; + pool->base.timing_generator_count = num_pipes; + pool->base.pipe_count = num_pipes; + pool->base.mpcc_count = num_pipes; + dc->caps.max_downscale_ratio = 600; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ + dc->caps.max_cursor_size = 256; + dc->caps.min_horizontal_blanking_period = 80; + dc->caps.dmdata_alloc_size = 2048; + dc->caps.mall_size_per_mem_channel = 0; + dc->caps.mall_size_total = 0; + dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; + + dc->caps.cache_line_size = 64; + dc->caps.cache_num_ways = 16; + dc->caps.max_cab_allocation_bytes = 67108864; // 64MB = 1024 * 1024 * 64 + dc->caps.subvp_fw_processing_delay_us = 15; + dc->caps.subvp_prefetch_end_to_mall_start_us = 15; + dc->caps.subvp_pstate_allow_width_us = 20; + dc->caps.subvp_vertical_int_margin_us = 30; + + dc->caps.max_slave_planes = 2; + dc->caps.max_slave_yuv_planes = 2; + dc->caps.max_slave_rgb_planes = 2; + dc->caps.post_blend_color_processing = true; + dc->caps.force_dp_tps4_for_cp2520 = true; + dc->caps.dp_hpo = true; + dc->caps.edp_dsc_support = true; + dc->caps.extended_aux_timeout_support = true; + dc->caps.dmcub_support = true; + + /* Color pipeline capabilities */ + dc->caps.color.dpp.dcn_arch = 1; + dc->caps.color.dpp.input_lut_shared = 0; + dc->caps.color.dpp.icsc = 1; + dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr + dc->caps.color.dpp.dgam_rom_caps.srgb = 1; + dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; + dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; + dc->caps.color.dpp.dgam_rom_caps.pq = 1; + dc->caps.color.dpp.dgam_rom_caps.hlg = 1; + dc->caps.color.dpp.post_csc = 1; + dc->caps.color.dpp.gamma_corr = 1; + dc->caps.color.dpp.dgam_rom_for_yuv = 0; + + dc->caps.color.dpp.hw_3d_lut = 1; + dc->caps.color.dpp.ogam_ram = 0; //Blnd Gam also removed + // no OGAM ROM on DCN2 and later ASICs + dc->caps.color.dpp.ogam_rom_caps.srgb = 0; + dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; + dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; + dc->caps.color.dpp.ogam_rom_caps.pq = 0; + dc->caps.color.dpp.ogam_rom_caps.hlg = 0; + dc->caps.color.dpp.ocsc = 0; + + dc->caps.color.mpc.gamut_remap = 1; + dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC + dc->caps.color.mpc.ogam_ram = 1; + dc->caps.color.mpc.ogam_rom_caps.srgb = 0; + dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; + dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; + dc->caps.color.mpc.ogam_rom_caps.pq = 0; + dc->caps.color.mpc.ogam_rom_caps.hlg = 0; + dc->caps.color.mpc.ocsc = 1; + + /* Use pipe context based otg sync logic */ + dc->config.use_pipe_ctx_sync_logic = true; + + /* read VBIOS LTTPR caps */ + { + if (ctx->dc_bios->funcs->get_lttpr_caps) { + enum bp_result bp_query_result; + uint8_t is_vbios_lttpr_enable = 0; + + bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); + dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; + } + + /* interop bit is implicit */ + { + dc->caps.vbios_lttpr_aware = true; + } + } + + if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) + dc->debug = debug_defaults_drv; + else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { + dc->debug = debug_defaults_diags; + } else + dc->debug = debug_defaults_diags; + // Init the vm_helper + if (dc->vm_helper) + vm_helper_init(dc->vm_helper, 16); + + /************************************************* + * Create resources * + *************************************************/ + + /* Clock Sources for Pixel Clock*/ + pool->base.clock_sources[DCN32_CLK_SRC_PLL0] = + dcn32_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL0, + &clk_src_regs[0], false); + pool->base.clock_sources[DCN32_CLK_SRC_PLL1] = + dcn32_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL1, + &clk_src_regs[1], false); + pool->base.clock_sources[DCN32_CLK_SRC_PLL2] = + dcn32_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL2, + &clk_src_regs[2], false); + pool->base.clock_sources[DCN32_CLK_SRC_PLL3] = + dcn32_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL3, + &clk_src_regs[3], false); + pool->base.clock_sources[DCN32_CLK_SRC_PLL4] = + dcn32_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL4, + &clk_src_regs[4], false); + + pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL; + + /* todo: not reuse phy_pll registers */ + pool->base.dp_clock_source = + dcn32_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_ID_DP_DTO, + &clk_src_regs[0], true); + + for (i = 0; i < pool->base.clk_src_count; i++) { + if (pool->base.clock_sources[i] == NULL) { + dm_error("DC: failed to create clock sources!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + } + + /* DCCG */ + pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); + if (pool->base.dccg == NULL) { + dm_error("DC: failed to create dccg!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + + /* DML */ + if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) + dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); + + /* IRQ Service */ + init_data.ctx = dc->ctx; + pool->base.irqs = dal_irq_service_dcn32_create(&init_data); + if (!pool->base.irqs) + goto create_fail; + + /* HUBBUB */ + pool->base.hubbub = dcn32_hubbub_create(ctx); + if (pool->base.hubbub == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create hubbub!\n"); + goto create_fail; + } + + /* HUBPs, DPPs, OPPs, TGs, ABMs */ + for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { + + /* if pipe is disabled, skip instance of HW pipe, + * i.e, skip ASIC register instance + */ + if (pipe_fuses & 1 << i) + continue; + + /* HUBPs */ + pool->base.hubps[j] = dcn32_hubp_create(ctx, i); + if (pool->base.hubps[j] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create hubps!\n"); + goto create_fail; + } + + /* DPPs */ + pool->base.dpps[j] = dcn32_dpp_create(ctx, i); + if (pool->base.dpps[j] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create dpps!\n"); + goto create_fail; + } + + /* OPPs */ + pool->base.opps[j] = dcn32_opp_create(ctx, i); + if (pool->base.opps[j] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create output pixel processor!\n"); + goto create_fail; + } + + /* TGs */ + pool->base.timing_generators[j] = dcn32_timing_generator_create( + ctx, i); + if (pool->base.timing_generators[j] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create tg!\n"); + goto create_fail; + } + + /* ABMs */ + pool->base.multiple_abms[j] = dmub_abm_create(ctx, + &abm_regs[i], + &abm_shift, + &abm_mask); + if (pool->base.multiple_abms[j] == NULL) { + dm_error("DC: failed to create abm for pipe %d!\n", i); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + + /* index for resource pool arrays for next valid pipe */ + j++; + } + + /* PSR */ + pool->base.psr = dmub_psr_create(ctx); + if (pool->base.psr == NULL) { + dm_error("DC: failed to create psr obj!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + + /* MPCCs */ + pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); + if (pool->base.mpc == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create mpc!\n"); + goto create_fail; + } + + /* DSCs */ + for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + pool->base.dscs[i] = dcn32_dsc_create(ctx, i); + if (pool->base.dscs[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create display stream compressor %d!\n", i); + goto create_fail; + } + } + + /* DWB */ + if (!dcn32_dwbc_create(ctx, &pool->base)) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create dwbc!\n"); + goto create_fail; + } + + /* MMHUBBUB */ + if (!dcn32_mmhubbub_create(ctx, &pool->base)) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create mcif_wb!\n"); + goto create_fail; + } + + /* AUX and I2C */ + for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + pool->base.engines[i] = dcn32_aux_engine_create(ctx, i); + if (pool->base.engines[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC:failed to create aux engine!!\n"); + goto create_fail; + } + pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i); + if (pool->base.hw_i2cs[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC:failed to create hw i2c!!\n"); + goto create_fail; + } + pool->base.sw_i2cs[i] = NULL; + } + + /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ + if (!resource_construct(num_virtual_links, dc, &pool->base, + (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? + &res_create_funcs : &res_create_maximus_funcs))) + goto create_fail; + + /* HW Sequencer init functions and Plane caps */ + dcn32_hw_sequencer_init_functions(dc); + + dc->caps.max_planes = pool->base.pipe_count; + + for (i = 0; i < dc->caps.max_planes; ++i) + dc->caps.planes[i] = plane_cap; + + dc->cap_funcs = cap_funcs; + + if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { + ddc_init_data.ctx = dc->ctx; + ddc_init_data.link = NULL; + ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; + ddc_init_data.id.enum_id = 0; + ddc_init_data.id.type = OBJECT_TYPE_GENERIC; + pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); + } else { + pool->base.oem_device = NULL; + } + + DC_FP_END(); + + return true; + +create_fail: + + DC_FP_END(); + + dcn32_resource_destruct(pool); + + return false; +} + +struct resource_pool *dcn32_create_resource_pool( + const struct dc_init_data *init_data, + struct dc *dc) +{ + struct dcn32_resource_pool *pool = + kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL); + + if (!pool) + return NULL; + + if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool)) + return &pool->base; + + BREAK_TO_DEBUGGER(); + kfree(pool); + return NULL; +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h new file mode 100644 index 000000000000..10b58f1c724a --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h @@ -0,0 +1,88 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _DCN32_RESOURCE_H_ +#define _DCN32_RESOURCE_H_ + +#include "core_types.h" + +#define TO_DCN32_RES_POOL(pool)\ + container_of(pool, struct dcn32_resource_pool, base) + +struct dcn32_resource_pool { + struct resource_pool base; +}; + +struct resource_pool *dcn32_create_resource_pool( + const struct dc_init_data *init_data, + struct dc *dc); + +void dcn32_calculate_dlg_params( + struct dc *dc, struct dc_state *context, + display_e2e_pipe_params_st *pipes, + int pipe_cnt, + int vlevel); + +struct panel_cntl *dcn32_panel_cntl_create( + const struct panel_cntl_init_data *init_data); + +bool dcn32_acquire_post_bldn_3dlut( + struct resource_context *res_ctx, + const struct resource_pool *pool, + int mpcc_id, + struct dc_3dlut **lut, + struct dc_transfer_func **shaper); + +bool dcn32_release_post_bldn_3dlut( + struct resource_context *res_ctx, + const struct resource_pool *pool, + struct dc_3dlut **lut, + struct dc_transfer_func **shaper); + +void dcn32_remove_phantom_pipes(struct dc *dc, + struct dc_state *context); + +void dcn32_add_phantom_pipes(struct dc *dc, + struct dc_state *context, + display_e2e_pipe_params_st *pipes, + unsigned int pipe_cnt, + unsigned int index); + +bool dcn32_validate_bandwidth(struct dc *dc, + struct dc_state *context, + bool fast_validate); + +int dcn32_populate_dml_pipes_from_context( + struct dc *dc, struct dc_state *context, + display_e2e_pipe_params_st *pipes, + bool fast_validate); + +void dcn32_calculate_wm_and_dlg( + struct dc *dc, struct dc_state *context, + display_e2e_pipe_params_st *pipes, + int pipe_cnt, + int vlevel); + +#endif /* _DCN32_RESOURCE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/Makefile b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile new file mode 100644 index 000000000000..99515cb3ed31 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile @@ -0,0 +1,34 @@ +# +# (c) Copyright 2020 Advanced Micro Devices, Inc. All the rights reserved +# +# All rights reserved. This notice is intended as a precaution against +# inadvertent publication and does not imply publication or any waiver +# of confidentiality. The year included in the foregoing notice is the +# year of creation of the work. +# +# Authors: AMD +# +# Makefile for dcn321. + +DCN321 = dcn321_resource.o + +CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o := -mhard-float -msse + +ifdef CONFIG_CC_IS_GCC +ifeq ($(call cc-ifversion, -lt, 0701, y), y) +IS_OLD_GCC = 1 +endif +endif + +ifdef IS_OLD_GCC +# Stack alignment mismatch, proceed with caution. +# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 +# (8B stack alignment). +CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o += -mpreferred-stack-boundary=4 +else +CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o += -msse2 +endif + +AMD_DAL_DCN321 = $(addprefix $(AMDDALPATH)/dc/dcn321/,$(DCN321)) + +AMD_DISPLAY_FILES += $(AMD_DAL_DCN321) diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c index a8fb4ab8ced1..6bc477a212b0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: MIT /* * Copyright 2019 Advanced Micro Devices, Inc. * @@ -23,7 +24,6 @@ * */ - #include "dm_services.h" #include "dc.h" @@ -98,28 +98,25 @@ #define MAX_INSTANCE 8 #define MAX_SEGMENT 6 - -struct IP_BASE_INSTANCE -{ - unsigned int segment[MAX_SEGMENT]; +struct IP_BASE_INSTANCE { + unsigned int segment[MAX_SEGMENT]; }; -struct IP_BASE -{ - struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; +struct IP_BASE { + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; }; static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, - { { 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0 } } } }; + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; #define DC_LOGGER_INIT(logger) -#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16))) +#define fixed16_to_double(x) (((double)x) / ((double) (1 << 16))) #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) #define DCN3_2_DEFAULT_DET_SIZE 256 @@ -1534,9 +1531,8 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) pool->base.hubps[i] = NULL; } - if (pool->base.irqs != NULL) { + if (pool->base.irqs != NULL) dal_irq_service_destroy(&pool->base.irqs); - } } for (i = 0; i < pool->base.res_cap->num_ddc; i++) { diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.h b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.h new file mode 100644 index 000000000000..2732085a0e88 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.h @@ -0,0 +1,42 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _DCN321_RESOURCE_H_ +#define _DCN321_RESOURCE_H_ + +#include "core_types.h" + +#define TO_DCN321_RES_POOL(pool)\ + container_of(pool, struct dcn321_resource_pool, base) + +struct dcn321_resource_pool { + struct resource_pool base; +}; + +struct resource_pool *dcn321_create_resource_pool( + const struct dc_init_data *init_data, + struct dc *dc); + +#endif /* _DCN321_RESOURCE_H_ */ -- cgit v1.2.3 From d3dfceb58de5f897640cdd424f6c2538d9514367 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Wed, 23 Feb 2022 17:48:45 -0500 Subject: drm/amd/display: Add dependant changes for DCN32/321 [Why&How] This patch adds necessary changes needed in DC files outside DCN32/321 specific tree v2: squash in updates (Alex) Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/Makefile | 2 + drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 949 ++++++++++++++++----- .../display/dc/bios/bios_parser_types_internal2.h | 1 + .../amd/display/dc/bios/command_table_helper2.c | 2 + drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 14 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 20 +- drivers/gpu/drm/amd/display/dc/dc.h | 19 + drivers/gpu/drm/amd/display/dc/dc_bios_types.h | 5 + drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 1 + drivers/gpu/drm/amd/display/dc/dc_stream.h | 21 + drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 45 + .../gpu/drm/amd/display/dc/dce/dce_clock_source.h | 15 + .../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h | 33 + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 5 - drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 2 + .../amd/display/dc/dcn10/dcn10_stream_encoder.h | 25 + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 34 +- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 25 +- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 32 +- .../display/dc/dcn30/dcn30_dio_stream_encoder.c | 16 +- .../display/dc/dcn30/dcn30_dio_stream_encoder.h | 35 + drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c | 8 +- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h | 16 + drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c | 14 +- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h | 147 ++++ drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h | 9 + drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 28 +- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h | 14 +- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c | 22 +- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h | 6 +- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 45 +- .../display/dc/dcn32/dcn32_dio_stream_encoder.c | 36 +- .../display/dc/dcn32/dcn32_dio_stream_encoder.h | 15 +- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 4 +- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c | 36 +- .../gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +- .../gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 59 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 10 + drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 5 +- drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 3 + drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 7 + drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 2 + .../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 4 + .../drm/amd/display/dc/inc/hw/timing_generator.h | 10 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 + .../drm/amd/display/dc/inc/hw_sequencer_private.h | 5 + drivers/gpu/drm/amd/display/dc/inc/resource.h | 7 + .../drm/amd/display/include/bios_parser_types.h | 10 + 49 files changed, 1521 insertions(+), 308 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index b4eca0236435..4de8e1871711 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -38,6 +38,8 @@ DC_LIBS += dcn303 DC_LIBS += dcn31 DC_LIBS += dcn315 DC_LIBS += dcn316 +DC_LIBS += dcn32 +DC_LIBS += dcn321 endif DC_LIBS += dce120 diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c index 23a3b640f0ee..bbc0a5769e88 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c @@ -165,9 +165,21 @@ static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) unsigned int count = 0; unsigned int i; - for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { - if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) - count++; + switch (bp->object_info_tbl.revision.minor) { + default: + case 4: + for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) + if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) + count++; + + break; + + case 5: + for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) + if (bp->object_info_tbl.v1_5->display_path[i].encoderobjid != 0) + count++; + + break; } return count; } @@ -182,16 +194,34 @@ static struct graphics_object_id bios_parser_get_connector_id( struct object_info_table *tbl = &bp->object_info_tbl; struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4; - if (v1_4->number_of_path > i) { - /* If display_objid is generic object id, the encoderObj - * /extencoderobjId should be 0 - */ - if (v1_4->display_path[i].encoderobjid != 0 && - v1_4->display_path[i].display_objid != 0) - object_id = object_id_from_bios_object_id( + struct display_object_info_table_v1_5 *v1_5 = tbl->v1_5; + + switch (bp->object_info_tbl.revision.minor) { + default: + case 4: + if (v1_4->number_of_path > i) { + /* If display_objid is generic object id, the encoderObj + * /extencoderobjId should be 0 + */ + if (v1_4->display_path[i].encoderobjid != 0 && + v1_4->display_path[i].display_objid != 0) + object_id = object_id_from_bios_object_id( v1_4->display_path[i].display_objid); - } + } + break; + case 5: + if (v1_5->number_of_path > i) { + /* If display_objid is generic object id, the encoderObjId + * should be 0 + */ + if (v1_5->display_path[i].encoderobjid != 0 && + v1_5->display_path[i].display_objid != 0) + object_id = object_id_from_bios_object_id( + v1_5->display_path[i].display_objid); + } + break; + } return object_id; } @@ -201,8 +231,8 @@ static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, { struct bios_parser *bp = BP_FROM_DCB(dcb); unsigned int i; - enum bp_result bp_result = BP_RESULT_BADINPUT; - struct graphics_object_id obj_id = {0}; + enum bp_result bp_result = BP_RESULT_BADINPUT; + struct graphics_object_id obj_id = { 0 }; struct object_info_table *tbl = &bp->object_info_tbl; if (!src_object_id) @@ -217,37 +247,84 @@ static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, * If found in for loop, should break. * DAL2 implementation may be changed too */ - for (i = 0; i < tbl->v1_4->number_of_path; i++) { - obj_id = object_id_from_bios_object_id( - tbl->v1_4->display_path[i].encoderobjid); - if (object_id.type == obj_id.type && - object_id.id == obj_id.id && - object_id.enum_id == - obj_id.enum_id) { - *src_object_id = - object_id_from_bios_object_id(0x1100); - /* break; */ + switch (bp->object_info_tbl.revision.minor) { + default: + case 4: + for (i = 0; i < tbl->v1_4->number_of_path; i++) { + obj_id = object_id_from_bios_object_id( + tbl->v1_4->display_path[i].encoderobjid); + if (object_id.type == obj_id.type && + object_id.id == obj_id.id && + object_id.enum_id == obj_id.enum_id) { + *src_object_id = + object_id_from_bios_object_id( + 0x1100); + /* break; */ + } + } + bp_result = BP_RESULT_OK; + break; + + case 5: + for (i = 0; i < tbl->v1_5->number_of_path; i++) { + obj_id = object_id_from_bios_object_id( + tbl->v1_5->display_path[i].encoderobjid); + if (object_id.type == obj_id.type && + object_id.id == obj_id.id && + object_id.enum_id == obj_id.enum_id) { + *src_object_id = + object_id_from_bios_object_id( + 0x1100); + /* break; */ + } } + bp_result = BP_RESULT_OK; + break; } - bp_result = BP_RESULT_OK; break; case OBJECT_TYPE_CONNECTOR: - for (i = 0; i < tbl->v1_4->number_of_path; i++) { - obj_id = object_id_from_bios_object_id( - tbl->v1_4->display_path[i].display_objid); - - if (object_id.type == obj_id.type && - object_id.id == obj_id.id && - object_id.enum_id == obj_id.enum_id) { - *src_object_id = - object_id_from_bios_object_id( - tbl->v1_4->display_path[i].encoderobjid); - /* break; */ + switch (bp->object_info_tbl.revision.minor) { + default: + case 4: + for (i = 0; i < tbl->v1_4->number_of_path; i++) { + obj_id = object_id_from_bios_object_id( + tbl->v1_4->display_path[i] + .display_objid); + + if (object_id.type == obj_id.type && + object_id.id == obj_id.id && + object_id.enum_id == obj_id.enum_id) { + *src_object_id = + object_id_from_bios_object_id( + tbl->v1_4 + ->display_path[i] + .encoderobjid); + /* break; */ + } } + bp_result = BP_RESULT_OK; + break; } bp_result = BP_RESULT_OK; break; + case 5: + for (i = 0; i < tbl->v1_5->number_of_path; i++) { + obj_id = object_id_from_bios_object_id( + tbl->v1_5->display_path[i].display_objid); + + if (object_id.type == obj_id.type && + object_id.id == obj_id.id && + object_id.enum_id == obj_id.enum_id) { + *src_object_id = object_id_from_bios_object_id( + tbl->v1_5->display_path[i].encoderobjid); + /* break; */ + } + } + bp_result = BP_RESULT_OK; + break; + default: + bp_result = BP_RESULT_OK; break; } @@ -290,12 +367,55 @@ static struct atom_display_object_path_v2 *get_bios_object( } } +/* from graphics_object_id, find display path which includes the object_id */ +static struct atom_display_object_path_v3 *get_bios_object_from_path_v3( + struct bios_parser *bp, + struct graphics_object_id id) +{ + unsigned int i; + struct graphics_object_id obj_id = {0}; + + switch (id.type) { + case OBJECT_TYPE_ENCODER: + for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) { + obj_id = object_id_from_bios_object_id( + bp->object_info_tbl.v1_5->display_path[i].encoderobjid); + if (id.type == obj_id.type && id.id == obj_id.id + && id.enum_id == obj_id.enum_id) + return &bp->object_info_tbl.v1_5->display_path[i]; + } + break; + + case OBJECT_TYPE_CONNECTOR: + case OBJECT_TYPE_GENERIC: + /* Both Generic and Connector Object ID + * will be stored on display_objid + */ + for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) { + obj_id = object_id_from_bios_object_id( + bp->object_info_tbl.v1_5->display_path[i].display_objid); + if (id.type == obj_id.type && id.id == obj_id.id + && id.enum_id == obj_id.enum_id) + return &bp->object_info_tbl.v1_5->display_path[i]; + } + break; + + default: + return NULL; + } + + return NULL; +} + static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, struct graphics_object_id id, struct graphics_object_i2c_info *info) { uint32_t offset; struct atom_display_object_path_v2 *object; + + struct atom_display_object_path_v3 *object_path_v3; + struct atom_common_record_header *header; struct atom_i2c_record *record; struct atom_i2c_record dummy_record = {0}; @@ -313,12 +433,25 @@ static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, return BP_RESULT_NORECORD; } - object = get_bios_object(bp, id); + switch (bp->object_info_tbl.revision.minor) { + case 4: + default: + object = get_bios_object(bp, id); - if (!object) - return BP_RESULT_BADINPUT; + if (!object) + return BP_RESULT_BADINPUT; - offset = object->disp_recordoffset + bp->object_info_tbl_offset; + offset = object->disp_recordoffset + bp->object_info_tbl_offset; + break; + case 5: + object_path_v3 = get_bios_object_from_path_v3(bp, id); + + if (!object_path_v3) + return BP_RESULT_BADINPUT; + + offset = object_path_v3->disp_recordoffset + bp->object_info_tbl_offset; + break; + } for (;;) { header = GET_IMAGE(struct atom_common_record_header, offset); @@ -421,6 +554,41 @@ static enum bp_result get_gpio_i2c_info( return BP_RESULT_OK; } +static struct atom_hpd_int_record *get_hpd_record_for_path_v3( + struct bios_parser *bp, + struct atom_display_object_path_v3 *object) +{ + struct atom_common_record_header *header; + uint32_t offset; + + if (!object) { + BREAK_TO_DEBUGGER(); /* Invalid object */ + return NULL; + } + + offset = object->disp_recordoffset + bp->object_info_tbl_offset; + + for (;;) { + header = GET_IMAGE(struct atom_common_record_header, offset); + + if (!header) + return NULL; + + if (header->record_type == ATOM_RECORD_END_TYPE || + !header->record_size) + break; + + if (header->record_type == ATOM_HPD_INT_RECORD_TYPE + && sizeof(struct atom_hpd_int_record) <= + header->record_size) + return (struct atom_hpd_int_record *) header; + + offset += header->record_size; + } + + return NULL; +} + static enum bp_result bios_parser_get_hpd_info( struct dc_bios *dcb, struct graphics_object_id id, @@ -428,17 +596,32 @@ static enum bp_result bios_parser_get_hpd_info( { struct bios_parser *bp = BP_FROM_DCB(dcb); struct atom_display_object_path_v2 *object; + struct atom_display_object_path_v3 *object_path_v3; struct atom_hpd_int_record *record = NULL; if (!info) return BP_RESULT_BADINPUT; - object = get_bios_object(bp, id); + switch (bp->object_info_tbl.revision.minor) { + case 4: + default: + object = get_bios_object(bp, id); - if (!object) - return BP_RESULT_BADINPUT; + if (!object) + return BP_RESULT_BADINPUT; + + record = get_hpd_record(bp, object); + + break; + case 5: + object_path_v3 = get_bios_object_from_path_v3(bp, id); - record = get_hpd_record(bp, object); + if (!object_path_v3) + return BP_RESULT_BADINPUT; + + record = get_hpd_record_for_path_v3(bp, object_path_v3); + break; + } if (record != NULL) { info->hpd_int_gpio_uid = record->pin_id; @@ -526,25 +709,9 @@ static enum bp_result bios_parser_get_gpio_pin_info( return BP_RESULT_UNSUPPORTED; /* Temporary hard code gpio pin info */ -#if defined(FOR_SIMNOW_BOOT) - { - struct atom_gpio_pin_assignment gpio_pin[8] = { - {0x5db5, 0, 0, 1, 0}, - {0x5db5, 8, 8, 2, 0}, - {0x5db5, 0x10, 0x10, 3, 0}, - {0x5db5, 0x18, 0x14, 4, 0}, - {0x5db5, 0x1A, 0x18, 5, 0}, - {0x5db5, 0x1C, 0x1C, 6, 0}, - }; - - count = 6; - memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin)); - } -#else count = (le16_to_cpu(header->table_header.structuresize) - sizeof(struct atom_common_table_header)) / sizeof(struct atom_gpio_pin_assignment); -#endif for (i = 0; i < count; ++i) { if (header->gpio_pin[i].gpio_id != gpio_id) continue; @@ -633,19 +800,37 @@ static enum bp_result bios_parser_get_device_tag( struct bios_parser *bp = BP_FROM_DCB(dcb); struct atom_display_object_path_v2 *object; + struct atom_display_object_path_v3 *object_path_v3; + + if (!info) return BP_RESULT_BADINPUT; - /* getBiosObject will return MXM object */ - object = get_bios_object(bp, connector_object_id); + switch (bp->object_info_tbl.revision.minor) { + case 4: + default: + /* getBiosObject will return MXM object */ + object = get_bios_object(bp, connector_object_id); - if (!object) { - BREAK_TO_DEBUGGER(); /* Invalid object id */ - return BP_RESULT_BADINPUT; - } + if (!object) { + BREAK_TO_DEBUGGER(); /* Invalid object id */ + return BP_RESULT_BADINPUT; + } - info->acpi_device = 0; /* BIOS no longer provides this */ - info->dev_id = device_type_from_device_id(object->device_tag); + info->acpi_device = 0; /* BIOS no longer provides this */ + info->dev_id = device_type_from_device_id(object->device_tag); + break; + case 5: + object_path_v3 = get_bios_object_from_path_v3(bp, connector_object_id); + + if (!object_path_v3) { + BREAK_TO_DEBUGGER(); /* Invalid object id */ + return BP_RESULT_BADINPUT; + } + info->acpi_device = 0; /* BIOS no longer provides this */ + info->dev_id = device_type_from_device_id(object_path_v3->device_tag); + break; + } return BP_RESULT_OK; } @@ -803,6 +988,71 @@ static enum bp_result get_ss_info_v4_2( return result; } +static enum bp_result get_ss_info_v4_5( + struct bios_parser *bp, + uint32_t id, + uint32_t index, + struct spread_spectrum_info *ss_info) +{ + enum bp_result result = BP_RESULT_OK; + struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; + + if (!ss_info) + return BP_RESULT_BADINPUT; + + if (!DATA_TABLES(dce_info)) + return BP_RESULT_BADBIOSTABLE; + + disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, + DATA_TABLES(dce_info)); + if (!disp_cntl_tbl) + return BP_RESULT_BADBIOSTABLE; + + ss_info->type.STEP_AND_DELAY_INFO = false; + ss_info->spread_percentage_divider = 1000; + /* BIOS no longer uses target clock. Always enable for now */ + ss_info->target_clock_range = 0xffffffff; + + switch (id) { + case AS_SIGNAL_TYPE_DVI: + ss_info->spread_spectrum_percentage = + disp_cntl_tbl->dvi_ss_percentage; + ss_info->spread_spectrum_range = + disp_cntl_tbl->dvi_ss_rate_10hz * 10; + if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) + ss_info->type.CENTER_MODE = true; + break; + case AS_SIGNAL_TYPE_HDMI: + ss_info->spread_spectrum_percentage = + disp_cntl_tbl->hdmi_ss_percentage; + ss_info->spread_spectrum_range = + disp_cntl_tbl->hdmi_ss_rate_10hz * 10; + if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) + ss_info->type.CENTER_MODE = true; + break; + case AS_SIGNAL_TYPE_DISPLAY_PORT: + ss_info->spread_spectrum_percentage = + disp_cntl_tbl->dp_ss_percentage; + ss_info->spread_spectrum_range = + disp_cntl_tbl->dp_ss_rate_10hz * 10; + if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) + ss_info->type.CENTER_MODE = true; + break; + case AS_SIGNAL_TYPE_GPU_PLL: + /* atom_smu_info_v4_0 does not have fields for SS for SMU Display PLL anymore. + * SMU Display PLL supposed to be without spread. + * Better place for it would be in atom_display_controller_info_v4_5 table. + */ + result = BP_RESULT_UNSUPPORTED; + break; + default: + result = BP_RESULT_UNSUPPORTED; + break; + } + + return result; +} + /** * bios_parser_get_spread_spectrum_info * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or @@ -847,6 +1097,9 @@ static enum bp_result bios_parser_get_spread_spectrum_info( case 3: case 4: return get_ss_info_v4_2(bp, signal, index, ss_info); + case 5: + return get_ss_info_v4_5(bp, signal, index, ss_info); + default: ASSERT(0); break; @@ -887,6 +1140,31 @@ static enum bp_result get_soc_bb_info_v4_4( return result; } +static enum bp_result get_soc_bb_info_v4_5( + struct bios_parser *bp, + struct bp_soc_bb_info *soc_bb_info) +{ + enum bp_result result = BP_RESULT_OK; + struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; + + if (!soc_bb_info) + return BP_RESULT_BADINPUT; + + if (!DATA_TABLES(dce_info)) + return BP_RESULT_BADBIOSTABLE; + + disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, + DATA_TABLES(dce_info)); + if (!disp_cntl_tbl) + return BP_RESULT_BADBIOSTABLE; + + soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; + soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; + soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; + + return result; +} + static enum bp_result bios_parser_get_soc_bb_info( struct dc_bios *dcb, struct bp_soc_bb_info *soc_bb_info) @@ -916,6 +1194,9 @@ static enum bp_result bios_parser_get_soc_bb_info( case 4: result = get_soc_bb_info_v4_4(bp, soc_bb_info); break; + case 5: + result = get_soc_bb_info_v4_5(bp, soc_bb_info); + break; default: break; } @@ -1023,6 +1304,30 @@ static enum bp_result get_disp_caps_v4_4( return result; } +static enum bp_result get_disp_caps_v4_5( + struct bios_parser *bp, + uint8_t *dce_caps) +{ + enum bp_result result = BP_RESULT_OK; + struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; + + if (!dce_caps) + return BP_RESULT_BADINPUT; + + if (!DATA_TABLES(dce_info)) + return BP_RESULT_BADBIOSTABLE; + + disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, + DATA_TABLES(dce_info)); + + if (!disp_cntl_tbl) + return BP_RESULT_BADBIOSTABLE; + + *dce_caps = disp_cntl_tbl->display_caps; + + return result; +} + static enum bp_result bios_parser_get_lttpr_interop( struct dc_bios *dcb, uint8_t *dce_caps) @@ -1057,6 +1362,11 @@ static enum bp_result bios_parser_get_lttpr_interop( result = get_disp_caps_v4_4(bp, dce_caps); *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); break; + case 5: + result = get_disp_caps_v4_5(bp, dce_caps); + *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); + break; + default: break; } @@ -1102,6 +1412,10 @@ static enum bp_result bios_parser_get_lttpr_caps( result = get_disp_caps_v4_4(bp, dce_caps); *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); break; + case 5: + result = get_disp_caps_v4_5(bp, dce_caps); + *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); + default: break; } @@ -1218,7 +1532,6 @@ static enum bp_result bios_parser_get_embedded_panel_info( default: break; } - break; default: break; } @@ -1274,8 +1587,17 @@ static bool bios_parser_is_device_id_supported( uint32_t mask = get_support_mask_for_device_id(id); - return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & - mask) != 0; + switch (bp->object_info_tbl.revision.minor) { + case 4: + default: + return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & mask) != 0; + break; + case 5: + return (le16_to_cpu(bp->object_info_tbl.v1_5->supporteddevices) & mask) != 0; + break; + } + + return false; } static uint32_t bios_parser_get_ss_entry_number( @@ -1408,12 +1730,21 @@ static void bios_parser_set_scratch_critical_state( bios_set_scratch_critical_state(dcb, state); } +struct atom_dig_transmitter_info_header_v5_3 { + struct atom_common_table_header table_header; + uint16_t dpphy_hdmi_settings_offset; + uint16_t dpphy_dvi_settings_offset; + uint16_t dpphy_dp_setting_table_offset; + uint16_t uniphy_xbar_settings_v2_table_offset; + uint16_t dpphy_internal_reg_overide_offset; +}; + static enum bp_result bios_parser_get_firmware_info( struct dc_bios *dcb, struct dc_firmware_info *info) { struct bios_parser *bp = BP_FROM_DCB(dcb); - enum bp_result result = BP_RESULT_BADBIOSTABLE; + static enum bp_result result = BP_RESULT_BADBIOSTABLE; struct atom_common_table_header *header; struct atom_data_revision revision; @@ -1590,6 +1921,11 @@ static enum bp_result get_firmware_info_v3_4( struct atom_data_revision revision; struct atom_display_controller_info_v4_1 *dce_info_v4_1 = NULL; struct atom_display_controller_info_v4_4 *dce_info_v4_4 = NULL; + + struct atom_smu_info_v3_5 *smu_info_v3_5 = NULL; + struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL; + struct atom_smu_info_v4_0 *smu_info_v4_0 = NULL; + if (!info) return BP_RESULT_BADINPUT; @@ -1609,6 +1945,22 @@ static enum bp_result get_firmware_info_v3_4( switch (revision.major) { case 4: switch (revision.minor) { + case 5: + dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5, + DATA_TABLES(dce_info)); + + if (!dce_info_v4_5) + return BP_RESULT_BADBIOSTABLE; + + /* 100MHz expected */ + info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10; + info->dp_phy_ref_clk = dce_info_v4_5->dpphy_refclk_10khz * 10; + /* 50MHz expected */ + info->i2c_engine_ref_clk = dce_info_v4_5->i2c_engine_refclk_10khz * 10; + + /* For DCN32/321 Display PLL VCO Frequency from dce_info_v4_5 may not be reliable */ + break; + case 4: dce_info_v4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, DATA_TABLES(dce_info)); @@ -1650,6 +2002,45 @@ static enum bp_result get_firmware_info_v3_4( DATA_TABLES(smu_info)); get_atom_data_table_revision(header, &revision); + switch (revision.major) { + case 3: + switch (revision.minor) { + case 5: + smu_info_v3_5 = GET_IMAGE(struct atom_smu_info_v3_5, + DATA_TABLES(smu_info)); + + if (!smu_info_v3_5) + return BP_RESULT_BADBIOSTABLE; + + info->default_engine_clk = smu_info_v3_5->bootup_dcefclk_10khz * 10; + break; + + default: + break; + } + break; + + case 4: + switch (revision.minor) { + case 0: + smu_info_v4_0 = GET_IMAGE(struct atom_smu_info_v4_0, + DATA_TABLES(smu_info)); + + if (!smu_info_v4_0) + return BP_RESULT_BADBIOSTABLE; + + /* For DCN32/321 bootup DCFCLK from smu_info_v4_0 may not be reliable */ + break; + + default: + break; + } + break; + + default: + break; + } + // We need to convert from 10KHz units into KHz units. info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; @@ -1675,6 +2066,12 @@ static enum bp_result bios_parser_get_encoder_cap_info( if (!info) return BP_RESULT_BADINPUT; +#if defined(CONFIG_DRM_AMD_DC_DCN) + /* encoder cap record not available in v1_5 */ + if (bp->object_info_tbl.revision.minor == 5) + return BP_RESULT_NORECORD; +#endif + object = get_bios_object(bp, object_id); if (!object) @@ -1781,6 +2178,42 @@ static struct atom_disp_connector_caps_record *get_disp_connector_caps_record( return NULL; } +static struct atom_connector_caps_record *get_connector_caps_record( + struct bios_parser *bp, + struct atom_display_object_path_v3 *object) +{ + struct atom_common_record_header *header; + uint32_t offset; + + if (!object) { + BREAK_TO_DEBUGGER(); /* Invalid object */ + return NULL; + } + + offset = object->disp_recordoffset + bp->object_info_tbl_offset; + + for (;;) { + header = GET_IMAGE(struct atom_common_record_header, offset); + + if (!header) + return NULL; + + offset += header->record_size; + + if (header->record_type == ATOM_RECORD_END_TYPE || + !header->record_size) + break; + + if (header->record_type != ATOM_CONNECTOR_CAP_RECORD_TYPE) + continue; + + if (sizeof(struct atom_connector_caps_record) <= header->record_size) + return (struct atom_connector_caps_record *)header; + } + + return NULL; +} + static enum bp_result bios_parser_get_disp_connector_caps_info( struct dc_bios *dcb, struct graphics_object_id object_id, @@ -1788,25 +2221,116 @@ static enum bp_result bios_parser_get_disp_connector_caps_info( { struct bios_parser *bp = BP_FROM_DCB(dcb); struct atom_display_object_path_v2 *object; + + struct atom_display_object_path_v3 *object_path_v3; + struct atom_connector_caps_record *record_path_v3; + struct atom_disp_connector_caps_record *record = NULL; if (!info) return BP_RESULT_BADINPUT; - object = get_bios_object(bp, object_id); + switch (bp->object_info_tbl.revision.minor) { + case 4: + default: + object = get_bios_object(bp, object_id); - if (!object) + if (!object) + return BP_RESULT_BADINPUT; + + record = get_disp_connector_caps_record(bp, object); + if (!record) + return BP_RESULT_NORECORD; + + info->INTERNAL_DISPLAY = + (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) ? 1 : 0; + info->INTERNAL_DISPLAY_BL = + (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) ? 1 : 0; + break; + case 5: + object_path_v3 = get_bios_object_from_path_v3(bp, object_id); + + if (!object_path_v3) + return BP_RESULT_BADINPUT; + + record_path_v3 = get_connector_caps_record(bp, object_path_v3); + if (!record_path_v3) + return BP_RESULT_NORECORD; + + info->INTERNAL_DISPLAY = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) + ? 1 : 0; + info->INTERNAL_DISPLAY_BL = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) + ? 1 : 0; + break; + } + + return BP_RESULT_OK; +} + +static struct atom_connector_speed_record *get_connector_speed_cap_record( + struct bios_parser *bp, + struct atom_display_object_path_v3 *object) +{ + struct atom_common_record_header *header; + uint32_t offset; + + if (!object) { + BREAK_TO_DEBUGGER(); /* Invalid object */ + return NULL; + } + + offset = object->disp_recordoffset + bp->object_info_tbl_offset; + + for (;;) { + header = GET_IMAGE(struct atom_common_record_header, offset); + + if (!header) + return NULL; + + offset += header->record_size; + + if (header->record_type == ATOM_RECORD_END_TYPE || + !header->record_size) + break; + + if (header->record_type != ATOM_CONNECTOR_SPEED_UPTO) + continue; + + if (sizeof(struct atom_connector_speed_record) <= header->record_size) + return (struct atom_connector_speed_record *)header; + } + + return NULL; +} + +static enum bp_result bios_parser_get_connector_speed_cap_info( + struct dc_bios *dcb, + struct graphics_object_id object_id, + struct bp_connector_speed_cap_info *info) +{ + struct bios_parser *bp = BP_FROM_DCB(dcb); + struct atom_display_object_path_v3 *object_path_v3; + //struct atom_connector_speed_record *record = NULL; + struct atom_connector_speed_record *record; + + if (!info) + return BP_RESULT_BADINPUT; + + object_path_v3 = get_bios_object_from_path_v3(bp, object_id); + + if (!object_path_v3) return BP_RESULT_BADINPUT; - record = get_disp_connector_caps_record(bp, object); + record = get_connector_speed_cap_record(bp, object_path_v3); if (!record) return BP_RESULT_NORECORD; - info->INTERNAL_DISPLAY = (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) - ? 1 : 0; - info->INTERNAL_DISPLAY_BL = (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) - ? 1 : 0; - + info->DP_HBR2_EN = (record->connector_max_speed >= 5400) ? 1 : 0; + info->DP_HBR3_EN = (record->connector_max_speed >= 8100) ? 1 : 0; + info->HDMI_6GB_EN = (record->connector_max_speed >= 5940) ? 1 : 0; + info->DP_UHBR10_EN = (record->connector_max_speed >= 10000) ? 1 : 0; + info->DP_UHBR13_5_EN = (record->connector_max_speed >= 13500) ? 1 : 0; + info->DP_UHBR20_EN = (record->connector_max_speed >= 20000) ? 1 : 0; return BP_RESULT_OK; } @@ -1815,7 +2339,7 @@ static enum bp_result get_vram_info_v23( struct dc_vram_info *info) { struct atom_vram_info_header_v2_3 *info_v23; - enum bp_result result = BP_RESULT_OK; + static enum bp_result result = BP_RESULT_OK; info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3, DATA_TABLES(vram_info)); @@ -1834,7 +2358,7 @@ static enum bp_result get_vram_info_v24( struct dc_vram_info *info) { struct atom_vram_info_header_v2_4 *info_v24; - enum bp_result result = BP_RESULT_OK; + static enum bp_result result = BP_RESULT_OK; info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4, DATA_TABLES(vram_info)); @@ -1853,7 +2377,7 @@ static enum bp_result get_vram_info_v25( struct dc_vram_info *info) { struct atom_vram_info_header_v2_5 *info_v25; - enum bp_result result = BP_RESULT_OK; + static enum bp_result result = BP_RESULT_OK; info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5, DATA_TABLES(vram_info)); @@ -1878,7 +2402,7 @@ static enum bp_result get_vram_info_v25( * integrated_info *info - [out] store and output integrated info * * @return - * enum bp_result - BP_RESULT_OK if information is available, + * static enum bp_result - BP_RESULT_OK if information is available, * BP_RESULT_BADBIOSTABLE otherwise. */ static enum bp_result get_integrated_info_v11( @@ -2369,17 +2893,19 @@ static enum bp_result get_integrated_info_v2_2( * integrated_info *info - [out] store and output integrated info * * @return - * enum bp_result - BP_RESULT_OK if information is available, + * static enum bp_result - BP_RESULT_OK if information is available, * BP_RESULT_BADBIOSTABLE otherwise. */ static enum bp_result construct_integrated_info( struct bios_parser *bp, struct integrated_info *info) { - enum bp_result result = BP_RESULT_BADBIOSTABLE; + static enum bp_result result = BP_RESULT_BADBIOSTABLE; struct atom_common_table_header *header; struct atom_data_revision revision; + + struct clock_voltage_caps temp = {0, 0}; uint32_t i; uint32_t j; @@ -2427,8 +2953,10 @@ static enum bp_result construct_integrated_info( info->disp_clk_voltage[j-1].max_supported_clk ) { /* swap j and j - 1*/ - swap(info->disp_clk_voltage[j - 1], - info->disp_clk_voltage[j]); + temp = info->disp_clk_voltage[j-1]; + info->disp_clk_voltage[j-1] = + info->disp_clk_voltage[j]; + info->disp_clk_voltage[j] = temp; } } } @@ -2441,7 +2969,7 @@ static enum bp_result bios_parser_get_vram_info( struct dc_vram_info *info) { struct bios_parser *bp = BP_FROM_DCB(dcb); - enum bp_result result = BP_RESULT_BADBIOSTABLE; + static enum bp_result result = BP_RESULT_BADBIOSTABLE; struct atom_common_table_header *header; struct atom_data_revision revision; @@ -2507,7 +3035,7 @@ static enum bp_result update_slot_layout_info( struct atom_display_object_path_v2 *object; struct atom_bracket_layout_record *record; struct atom_common_record_header *record_header; - enum bp_result result; + static enum bp_result result; struct bios_parser *bp; struct object_info_table *tbl; struct display_object_info_table_v1_4 *v1_4; @@ -2613,6 +3141,104 @@ static enum bp_result update_slot_layout_info( return result; } +static enum bp_result update_slot_layout_info_v2( + struct dc_bios *dcb, + unsigned int i, + struct slot_layout_info *slot_layout_info) +{ + unsigned int record_offset; + struct atom_display_object_path_v3 *object; + struct atom_bracket_layout_record_v2 *record; + struct atom_common_record_header *record_header; + static enum bp_result result; + struct bios_parser *bp; + struct object_info_table *tbl; + struct display_object_info_table_v1_5 *v1_5; + struct graphics_object_id connector_id; + + record = NULL; + record_header = NULL; + result = BP_RESULT_NORECORD; + + bp = BP_FROM_DCB(dcb); + tbl = &bp->object_info_tbl; + v1_5 = tbl->v1_5; + + object = &v1_5->display_path[i]; + record_offset = (unsigned int) + (object->disp_recordoffset) + + (unsigned int)(bp->object_info_tbl_offset); + + for (;;) { + + record_header = (struct atom_common_record_header *) + GET_IMAGE(struct atom_common_record_header, + record_offset); + if (record_header == NULL) { + result = BP_RESULT_BADBIOSTABLE; + break; + } + + /* the end of the list */ + if (record_header->record_type == ATOM_RECORD_END_TYPE || + record_header->record_size == 0) { + break; + } + + if (record_header->record_type == + ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE && + sizeof(struct atom_bracket_layout_record_v2) + <= record_header->record_size) { + record = (struct atom_bracket_layout_record_v2 *) + (record_header); + result = BP_RESULT_OK; + break; + } + + record_offset += record_header->record_size; + } + + /* return if the record not found */ + if (result != BP_RESULT_OK) + return result; + + /* get slot sizes */ + connector_id = object_id_from_bios_object_id(object->display_objid); + + slot_layout_info->length = record->bracketlen; + slot_layout_info->width = record->bracketwidth; + slot_layout_info->num_of_connectors = v1_5->number_of_path; + slot_layout_info->connectors[i].position = record->conn_num; + slot_layout_info->connectors[i].connector_id = connector_id; + + switch (connector_id.id) { + case CONNECTOR_ID_SINGLE_LINK_DVID: + case CONNECTOR_ID_DUAL_LINK_DVID: + slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DVI_D; + slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DVI; + break; + + case CONNECTOR_ID_HDMI_TYPE_A: + slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_HDMI; + slot_layout_info->connectors[i].length = CONNECTOR_SIZE_HDMI; + break; + + case CONNECTOR_ID_DISPLAY_PORT: + if (record->mini_type == MINI_TYPE_NORMAL) { + slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DP; + slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DP; + } else { + slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_MINI_DP; + slot_layout_info->connectors[i].length = CONNECTOR_SIZE_MINI_DP; + } + break; + + default: + slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_UNKNOWN; + slot_layout_info->connectors[i].length = CONNECTOR_SIZE_UNKNOWN; + } + return result; +} static enum bp_result get_bracket_layout_record( struct dc_bios *dcb, @@ -2621,9 +3247,10 @@ static enum bp_result get_bracket_layout_record( { unsigned int i; struct bios_parser *bp = BP_FROM_DCB(dcb); - enum bp_result result; + static enum bp_result result; struct object_info_table *tbl; struct display_object_info_table_v1_4 *v1_4; + struct display_object_info_table_v1_5 *v1_5; if (slot_layout_info == NULL) { DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n"); @@ -2633,14 +3260,21 @@ static enum bp_result get_bracket_layout_record( v1_4 = tbl->v1_4; result = BP_RESULT_NORECORD; - for (i = 0; i < v1_4->number_of_path; ++i) { - - if (bracket_layout_id == - v1_4->display_path[i].display_objid) { - result = update_slot_layout_info(dcb, i, - slot_layout_info); + switch (bp->object_info_tbl.revision.minor) { + case 4: + default: + for (i = 0; i < v1_4->number_of_path; ++i) { + if (bracket_layout_id == + v1_4->display_path[i].display_objid) { + result = update_slot_layout_info(dcb, i, slot_layout_info); + break; + } + } + break; + case 5: + for (i = 0; i < v1_5->number_of_path; ++i) + result = update_slot_layout_info_v2(dcb, i, slot_layout_info); break; - } } return result; } @@ -2650,7 +3284,10 @@ static enum bp_result bios_get_board_layout_info( struct board_layout_info *board_layout_info) { unsigned int i; - enum bp_result record_result; + + struct bios_parser *bp; + + static enum bp_result record_result; const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = { GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1, @@ -2658,6 +3295,9 @@ static enum bp_result bios_get_board_layout_info( 0, 0 }; + + bp = BP_FROM_DCB(dcb); + if (board_layout_info == NULL) { DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n"); return BP_RESULT_BADINPUT; @@ -2692,99 +3332,6 @@ static uint16_t bios_parser_pack_data_tables( struct dc_bios *dcb, void *dst) { -#ifdef PACK_BIOS_DATA - struct bios_parser *bp = BP_FROM_DCB(dcb); - struct atom_rom_header_v2_2 *rom_header = NULL; - struct atom_rom_header_v2_2 *packed_rom_header = NULL; - struct atom_common_table_header *data_tbl_header = NULL; - struct atom_master_list_of_data_tables_v2_1 *data_tbl_list = NULL; - struct atom_master_data_table_v2_1 *packed_master_data_tbl = NULL; - struct atom_data_revision tbl_rev = {0}; - uint16_t *rom_header_offset = NULL; - const uint8_t *bios = bp->base.bios; - uint8_t *bios_dst = (uint8_t *)dst; - uint16_t packed_rom_header_offset; - uint16_t packed_masterdatatable_offset; - uint16_t packed_data_tbl_offset; - uint16_t data_tbl_offset; - unsigned int i; - - rom_header_offset = - GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); - - if (!rom_header_offset) - return 0; - - rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); - - if (!rom_header) - return 0; - - get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); - if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) - return 0; - - get_atom_data_table_revision(&bp->master_data_tbl->table_header, &tbl_rev); - if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 1)) - return 0; - - packed_rom_header_offset = - OFFSET_TO_ATOM_ROM_HEADER_POINTER + sizeof(*rom_header_offset); - - packed_masterdatatable_offset = - packed_rom_header_offset + rom_header->table_header.structuresize; - - packed_data_tbl_offset = - packed_masterdatatable_offset + - bp->master_data_tbl->table_header.structuresize; - - packed_rom_header = - (struct atom_rom_header_v2_2 *)(bios_dst + packed_rom_header_offset); - - packed_master_data_tbl = - (struct atom_master_data_table_v2_1 *)(bios_dst + - packed_masterdatatable_offset); - - memcpy(bios_dst, bios, OFFSET_TO_ATOM_ROM_HEADER_POINTER); - - *((uint16_t *)(bios_dst + OFFSET_TO_ATOM_ROM_HEADER_POINTER)) = - packed_rom_header_offset; - - memcpy(bios_dst + packed_rom_header_offset, rom_header, - rom_header->table_header.structuresize); - - packed_rom_header->masterdatatable_offset = packed_masterdatatable_offset; - - memcpy(&packed_master_data_tbl->table_header, - &bp->master_data_tbl->table_header, - sizeof(bp->master_data_tbl->table_header)); - - data_tbl_list = &bp->master_data_tbl->listOfdatatables; - - /* Each data table offset in data table list is 2 bytes, - * we can use that to iterate through listOfdatatables - * without knowing the name of each member. - */ - for (i = 0; i < sizeof(*data_tbl_list)/sizeof(uint16_t); i++) { - data_tbl_offset = *((uint16_t *)data_tbl_list + i); - - if (data_tbl_offset) { - data_tbl_header = - (struct atom_common_table_header *)(bios + data_tbl_offset); - - memcpy(bios_dst + packed_data_tbl_offset, data_tbl_header, - data_tbl_header->structuresize); - - *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = - packed_data_tbl_offset; - - packed_data_tbl_offset += data_tbl_header->structuresize; - } else { - *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 0; - } - } - return packed_data_tbl_offset; -#endif // TODO: There is data bytes alignment issue, disable it for now. return 0; } @@ -2814,6 +3361,13 @@ static struct atom_dc_golden_table_v1 *bios_get_golden_table( dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset; *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver; break; + case 5: + default: + /* For atom_display_controller_info_v4_5 there is no need to get golden table from + * dc_golden_table_offset as all these fields previously in golden table used for AUX + * pre-charge settings are now available directly in atom_display_controller_info_v4_5. + */ + break; } break; } @@ -2916,6 +3470,7 @@ static const struct dc_vbios_funcs vbios_funcs = { .bios_parser_destroy = firmware_parser_destroy, .get_board_layout_info = bios_get_board_layout_info, + /* TODO: use this fn in hw init?*/ .pack_data_tables = bios_parser_pack_data_tables, .get_atom_dc_golden_table = bios_get_atom_dc_golden_table, @@ -2929,6 +3484,8 @@ static const struct dc_vbios_funcs vbios_funcs = { .get_lttpr_caps = bios_parser_get_lttpr_caps, .get_lttpr_interop = bios_parser_get_lttpr_interop, + + .get_connector_speed_cap_info = bios_parser_get_connector_speed_cap_info, }; static bool bios_parser2_construct( @@ -3002,6 +3559,16 @@ static bool bios_parser2_construct( return false; bp->object_info_tbl.v1_4 = tbl_v1_4; + } else if (bp->object_info_tbl.revision.major == 1 + && bp->object_info_tbl.revision.minor == 5) { + struct display_object_info_table_v1_5 *tbl_v1_5; + + tbl_v1_5 = GET_IMAGE(struct display_object_info_table_v1_5, + bp->object_info_tbl_offset); + if (!tbl_v1_5) + return false; + + bp->object_info_tbl.v1_5 = tbl_v1_5; } else { ASSERT(0); return false; diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h index bf1f5c86e65c..41d02d473082 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h @@ -40,6 +40,7 @@ struct object_info_table { struct atom_data_revision revision; union { struct display_object_info_table_v1_4 *v1_4; + struct display_object_info_table_v1_5 *v1_5; }; }; diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c index f3792286f571..f22593bcb862 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c @@ -77,6 +77,8 @@ bool dal_bios_parser_init_cmd_tbl_helper2( case DCN_VERSION_3_1: case DCN_VERSION_3_15: case DCN_VERSION_3_16: + case DCN_VERSION_3_2: + case DCN_VERSION_3_21: *h = dal_cmd_tbl_helper_dce112_get_table2(); return true; diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index e803e59abd56..d145dcbca778 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -328,8 +328,8 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); return &clk_mgr->base; break; -#endif } +#endif default: ASSERT(0); /* Unknown Asic */ break; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index f14449401188..e3e3b2791632 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3054,11 +3054,15 @@ static void commit_planes_for_stream(struct dc *dc, } - if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) { - dc->hwss.interdependent_update_lock(dc, context, false); - } else { - dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false); - } +#ifdef CONFIG_DRM_AMD_DC_DCN + if (update_type != UPDATE_TYPE_FAST) + if (dc->hwss.commit_subvp_config) + dc->hwss.commit_subvp_config(dc, context); +#endif + if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) + dc->hwss.interdependent_update_lock(dc, context, false); + else + dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false); if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 6774dd8bb53e..b087452e4590 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -67,6 +67,8 @@ #include "dcn31/dcn31_resource.h" #include "dcn315/dcn315_resource.h" #include "dcn316/dcn316_resource.h" +#include "../dcn32/dcn32_resource.h" +#include "../dcn321/dcn321_resource.h" #define DC_LOGGER_INIT(logger) @@ -162,7 +164,11 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev)) dc_version = DCN_VERSION_3_16; break; - + case AMDGPU_FAMILY_GC_11_0_0: + dc_version = DCN_VERSION_3_2; + if (ASICREV_IS_GC_11_0_2(asic_id.hw_internal_rev)) + dc_version = DCN_VERSION_3_21; + break; default: dc_version = DCE_VERSION_UNKNOWN; break; @@ -258,6 +264,12 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, case DCN_VERSION_3_16: res_pool = dcn316_create_resource_pool(init_data, dc); break; + case DCN_VERSION_3_2: + res_pool = dcn32_create_resource_pool(init_data, dc); + break; + case DCN_VERSION_3_21: + res_pool = dcn321_create_resource_pool(init_data, dc); + break; #endif default: break; @@ -1982,6 +1994,11 @@ enum dc_status dc_remove_stream_from_ctx( dc->res_pool, del_pipe->stream_res.stream_enc, false); + /* Release link encoder from stream in new dc_state. */ + if (dc->res_pool->funcs->link_enc_unassign) + dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream); + +#if defined(CONFIG_DRM_AMD_DC_DCN) if (is_dp_128b_132b_signal(del_pipe)) { update_hpo_dp_stream_engine_usage( &new_ctx->res_ctx, dc->res_pool, @@ -1989,6 +2006,7 @@ enum dc_status dc_remove_stream_from_ctx( false); remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream); } +#endif if (del_pipe->stream_res.audio) update_audio_usage( diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 52d6da5ea9a7..691654653ebb 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -162,6 +162,10 @@ struct dc_color_caps { struct mpc_color_caps mpc; }; +struct dc_dmub_caps { + bool psr; +}; + struct dc_caps { uint32_t max_streams; uint32_t max_links; @@ -196,12 +200,22 @@ struct dc_caps { unsigned int cursor_cache_size; struct dc_plane_cap planes[MAX_PLANES]; struct dc_color_caps color; + struct dc_dmub_caps dmub_caps; bool dp_hpo; bool hdmi_frl_pcon_support; bool edp_dsc_support; bool vbios_lttpr_aware; bool vbios_lttpr_enable; uint32_t max_otg_num; +#ifdef CONFIG_DRM_AMD_DC_DCN + uint32_t max_cab_allocation_bytes; + uint32_t cache_line_size; + uint32_t cache_num_ways; + uint16_t subvp_fw_processing_delay_us; + uint16_t subvp_prefetch_end_to_mall_start_us; + uint16_t subvp_pstate_allow_width_us; + uint16_t subvp_vertical_int_margin_us; +#endif }; struct dc_bug_wa { @@ -427,6 +441,8 @@ struct dc_clocks { */ bool prev_p_state_change_support; bool fclk_prev_p_state_change_support; + int num_ways; + int prev_num_ways; enum dtm_pstate dtm_level; int max_supported_dppclk_khz; int max_supported_dispclk_khz; @@ -721,6 +737,9 @@ struct dc_debug_options { bool enable_z9_disable_interface; bool enable_sw_cntl_psr; union dpia_debug_options dpia_debug; + bool force_disable_subvp; + bool force_subvp_mclk_switch; + bool force_usr_allow; bool apply_vendor_specific_lttpr_wa; bool extended_blank_optimization; union aux_wake_wa_options aux_wake_wa; diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h index 67abda44eb1f..260ac4458870 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h @@ -156,6 +156,11 @@ struct dc_vbios_funcs { enum bp_result (*get_lttpr_interop)( struct dc_bios *dcb, uint8_t *dce_caps); + + enum bp_result (*get_connector_speed_cap_info)( + struct dc_bios *bios, + struct graphics_object_id object_id, + struct bp_connector_speed_cap_info *info); }; struct bios_registers { diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index aa7e3a07191d..d75416dc9fae 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -780,6 +780,7 @@ struct dc_crtc_timing { uint32_t v_sync_width; uint32_t pix_clk_100hz; + uint32_t min_refresh_in_uhz; uint32_t vic; uint32_t hdmi_vic; diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 58941f4defb3..772b4a61f166 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -145,6 +145,24 @@ struct test_pattern { unsigned int cust_pattern_size; }; +#ifdef CONFIG_DRM_AMD_DC_DCN +#define SUBVP_DRR_MARGIN_US 500 // 500us for DRR margin (SubVP + DRR) + +enum mall_stream_type { + SUBVP_NONE, // subvp not in use + SUBVP_MAIN, // subvp in use, this stream is main stream + SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream +}; + +struct mall_stream_config { + /* MALL stream config to indicate if the stream is phantom or not. + * We will use a phantom stream to indicate that the pipe is phantom. + */ + enum mall_stream_type type; + struct dc_stream_state *paired_stream; // master / slave stream +}; +#endif + struct dc_stream_state { // sink is deprecated, new code should not reference // this pointer @@ -255,6 +273,9 @@ struct dc_stream_state { bool has_non_synchronizable_pclk; bool vblank_synchronized; +#ifdef CONFIG_DRM_AMD_DC_DCN + struct mall_stream_config mall_stream_config; +#endif }; #define ABM_LEVEL_IMMEDIATE_DISABLE 255 diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h index b699d1b2ba83..e6c06325742a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h @@ -128,6 +128,21 @@ SRI(DC_ABM1_ACE_THRES_12, ABM, id), \ NBIO_SR(BIOS_SCRATCH_2) +#define ABM_DCN32_REG_LIST(id)\ + SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ + SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ + SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ + SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ + SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ + SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ + SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ + SRI(BL1_PWM_USER_LEVEL, ABM, id), \ + SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ + SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ + SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \ + SRI(DC_ABM1_ACE_THRES_12, ABM, id), \ + NBIO_SR(BIOS_SCRATCH_2) + #define ABM_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -203,6 +218,36 @@ #define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh) +#define ABM_MASK_SH_LIST_DCN32(mask_sh) \ + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_VMAX_SEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ + ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \ + BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ + ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \ + BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ + ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \ + BL1_PWM_USER_LEVEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ + ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ + ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) + #define ABM_REG_FIELD_LIST(type) \ type ABM1_HG_NUM_OF_BINS_SEL; \ type ABM1_HG_VMAX_SEL; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h index 9eec3524335f..e0c390fcc12c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h @@ -164,6 +164,10 @@ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) +#define CS_COMMON_MASK_SH_LIST_DCN3_2(mask_sh)\ + CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh),\ + CS_SF(OTG0_PIXEL_RATE_CNTL, PIPE0_DTO_SRC_SEL, mask_sh) + #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ SRII(PHASE, DP_DTO, 0),\ @@ -197,12 +201,23 @@ type DP_DTO0_MODULO; \ type DP_DTO0_ENABLE; +#if defined(CONFIG_DRM_AMD_DC_DCN) +#define CS_REG_FIELD_LIST_DCN32(type) \ + type PIPE0_DTO_SRC_SEL; +#endif + struct dce110_clk_src_shift { CS_REG_FIELD_LIST(uint8_t) +#if defined(CONFIG_DRM_AMD_DC_DCN) + CS_REG_FIELD_LIST_DCN32(uint8_t) +#endif }; struct dce110_clk_src_mask{ CS_REG_FIELD_LIST(uint32_t) +#if defined(CONFIG_DRM_AMD_DC_DCN) + CS_REG_FIELD_LIST_DCN32(uint32_t) +#endif }; struct dce110_clk_src_regs { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h index 39485bdeb90e..e48fd044f572 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h @@ -158,8 +158,39 @@ struct dcn_hubbub_registers { uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C; uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D; uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D; + uint32_t DCHUBBUB_ARB_USR_RETRAINING_CNTL; + uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A; + uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B; + uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C; + uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D; + uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A; + uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B; + uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C; + uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D; + uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A; + uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B; + uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C; + uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D; }; +#define HUBBUB_REG_FIELD_LIST_DCN32(type) \ + type DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE;\ + type DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE;\ + type DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST;\ + type DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE;\ + type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A;\ + type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B;\ + type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C;\ + type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D;\ + type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A;\ + type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B;\ + type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C;\ + type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D;\ + type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A;\ + type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B;\ + type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C;\ + type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D + /* set field name */ #define HUBBUB_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -337,6 +368,7 @@ struct dcn_hubbub_shift { HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t); HUBBUB_HVM_REG_FIELD_LIST(uint8_t); HUBBUB_RET_REG_FIELD_LIST(uint8_t); + HUBBUB_REG_FIELD_LIST_DCN32(uint8_t); }; struct dcn_hubbub_mask { @@ -344,6 +376,7 @@ struct dcn_hubbub_mask { HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t); HUBBUB_HVM_REG_FIELD_LIST(uint32_t); HUBBUB_RET_REG_FIELD_LIST(uint32_t); + HUBBUB_REG_FIELD_LIST_DCN32(uint32_t); }; struct dc; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index e3a62873c0e7..1cb206dc8352 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1375,11 +1375,6 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context) pipe_ctx->stream_res.tg = NULL; pipe_ctx->plane_res.hubp = NULL; - if (tg->funcs->is_tg_enabled(tg)) { - if (tg->funcs->init_odm) - tg->funcs->init_odm(tg); - } - tg->funcs->tg_init(tg); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h index c50c29984d51..df155cc2bfea 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h @@ -514,6 +514,7 @@ struct dcn_optc_registers { type DIG_UPDATE_POSITION_X;\ type DIG_UPDATE_POSITION_Y;\ type OTG_H_TIMING_DIV_MODE;\ + type OTG_H_TIMING_DIV_MODE_MANUAL;\ type OTG_DRR_TIMING_DBUF_UPDATE_MODE;\ type OTG_CRC_DSC_MODE;\ type OTG_CRC_DATA_STREAM_COMBINE_MODE;\ @@ -553,6 +554,7 @@ struct optc { int vupdate_offset; int vupdate_width; int vready_offset; + struct dc_crtc_timing orginal_patched_timing; enum signal_type signal; }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h index 293595a33982..02c77076fa49 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h @@ -73,6 +73,7 @@ SRI(HDMI_ACR_48_1, DIG, id),\ SRI(DP_DB_CNTL, DP, id), \ SRI(DP_MSA_MISC, DP, id), \ + SRI(DP_MSA_VBID_MISC, DP, id), \ SRI(DP_MSA_COLORIMETRY, DP, id), \ SRI(DP_MSA_TIMING_PARAM1, DP, id), \ SRI(DP_MSA_TIMING_PARAM2, DP, id), \ @@ -186,6 +187,7 @@ struct dcn10_stream_enc_registers { uint32_t HDMI_GENERIC_PACKET_CONTROL9; uint32_t HDMI_GENERIC_PACKET_CONTROL10; uint32_t DIG_CLOCK_PATTERN; + uint32_t DIG_FIFO_CTRL0; }; @@ -337,8 +339,14 @@ struct dcn10_stream_enc_registers { SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh),\ SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_HDCP) +#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ + SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh) +#else #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) +#endif #define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\ SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\ @@ -567,16 +575,33 @@ struct dcn10_stream_enc_registers { type DP_SEC_GSP11_ENABLE;\ type DP_SEC_GSP11_LINE_NUM +#define SE_REG_FIELD_LIST_DCN3_2(type) \ + type DIG_SYMCLK_FE_ON;\ + type DIG_FIFO_READ_START_LEVEL;\ + type DIG_FIFO_ENABLE;\ + type DIG_FIFO_RESET;\ + type DIG_FIFO_RESET_DONE + struct dcn10_stream_encoder_shift { SE_REG_FIELD_LIST_DCN1_0(uint8_t); +#if defined(CONFIG_DRM_AMD_DC_HDCP) + uint8_t HDMI_ACP_SEND; +#endif SE_REG_FIELD_LIST_DCN2_0(uint8_t); SE_REG_FIELD_LIST_DCN3_0(uint8_t); + SE_REG_FIELD_LIST_DCN3_2(uint8_t); + }; struct dcn10_stream_encoder_mask { SE_REG_FIELD_LIST_DCN1_0(uint32_t); +#if defined(CONFIG_DRM_AMD_DC_HDCP) + uint32_t HDMI_ACP_SEND; +#endif SE_REG_FIELD_LIST_DCN2_0(uint32_t); SE_REG_FIELD_LIST_DCN3_0(uint32_t); + SE_REG_FIELD_LIST_DCN3_2(uint32_t); + }; struct dcn10_stream_encoder { diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h index b3c9a9724efd..2b9d3e63191b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h @@ -133,6 +133,8 @@ type OTG_DROP_PIXEL[MAX_PIPES]; #define DCCG3_REG_FIELD_LIST(type) \ + type HDMICHARCLK0_EN;\ + type HDMICHARCLK0_SRC_SEL;\ type PHYASYMCLK_FORCE_EN;\ type PHYASYMCLK_FORCE_SRC_SEL;\ type PHYBSYMCLK_FORCE_EN;\ @@ -203,16 +205,45 @@ type PHYDSYMCLK_GATE_DISABLE; \ type PHYESYMCLK_GATE_DISABLE; +#define DCCG32_REG_FIELD_LIST(type) \ + type DPSTREAMCLK0_EN;\ + type DPSTREAMCLK1_EN;\ + type DPSTREAMCLK2_EN;\ + type DPSTREAMCLK3_EN;\ + type DPSTREAMCLK0_SRC_SEL;\ + type DPSTREAMCLK1_SRC_SEL;\ + type DPSTREAMCLK2_SRC_SEL;\ + type DPSTREAMCLK3_SRC_SEL;\ + type HDMISTREAMCLK0_EN;\ + type OTG0_PIXEL_RATE_DIVK1;\ + type OTG0_PIXEL_RATE_DIVK2;\ + type OTG1_PIXEL_RATE_DIVK1;\ + type OTG1_PIXEL_RATE_DIVK2;\ + type OTG2_PIXEL_RATE_DIVK1;\ + type OTG2_PIXEL_RATE_DIVK2;\ + type OTG3_PIXEL_RATE_DIVK1;\ + type OTG3_PIXEL_RATE_DIVK2;\ + type DTBCLK_P0_SRC_SEL;\ + type DTBCLK_P0_EN;\ + type DTBCLK_P1_SRC_SEL;\ + type DTBCLK_P1_EN;\ + type DTBCLK_P2_SRC_SEL;\ + type DTBCLK_P2_EN;\ + type DTBCLK_P3_SRC_SEL;\ + type DTBCLK_P3_EN; + struct dccg_shift { DCCG_REG_FIELD_LIST(uint8_t) DCCG3_REG_FIELD_LIST(uint8_t) DCCG31_REG_FIELD_LIST(uint8_t) + DCCG32_REG_FIELD_LIST(uint8_t) }; struct dccg_mask { DCCG_REG_FIELD_LIST(uint32_t) DCCG3_REG_FIELD_LIST(uint32_t) DCCG31_REG_FIELD_LIST(uint32_t) + DCCG32_REG_FIELD_LIST(uint32_t) }; struct dccg_registers { @@ -247,7 +278,8 @@ struct dccg_registers { uint32_t DCCG_GATE_DISABLE_CNTL3; uint32_t HDMISTREAMCLK0_DTO_PARAM; uint32_t DCCG_GATE_DISABLE_CNTL4; - + uint32_t OTG_PIXEL_RATE_DIV; + uint32_t DTBCLK_P_CNTL; }; struct dcn_dccg { diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h index 9204c3ef323b..efa2adf4f83d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h @@ -161,6 +161,12 @@ DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\ uint32_t DCN_DMDATA_VM_CNTL +#define DCN32_HUBP_REG_COMMON_VARIABLE_LIST \ + DCN30_HUBP_REG_COMMON_VARIABLE_LIST;\ + uint32_t DCHUBP_MALL_CONFIG;\ + uint32_t DCHUBP_VMPG_CONFIG;\ + uint32_t UCLK_PSTATE_FORCE + #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \ DCN_HUBP_REG_FIELD_BASE_LIST(type); \ type DMDATA_ADDRESS_HIGH;\ @@ -222,16 +228,29 @@ type CURSOR_REQ_MODE;\ type HUBP_SOFT_RESET +#define DCN32_HUBP_REG_FIELD_VARIABLE_LIST(type) \ + DCN31_HUBP_REG_FIELD_VARIABLE_LIST(type);\ + type USE_MALL_SEL; \ + type USE_MALL_FOR_CURSOR;\ + type VMPG_SIZE; \ + type PTE_BUFFER_MODE; \ + type BIGK_FRAGMENT_SIZE; \ + type FORCE_ONE_ROW_FOR_FRAME; \ + type DATA_UCLK_PSTATE_FORCE_EN; \ + type DATA_UCLK_PSTATE_FORCE_VALUE; \ + type CURSOR_UCLK_PSTATE_FORCE_EN; \ + type CURSOR_UCLK_PSTATE_FORCE_VALUE + struct dcn_hubp2_registers { - DCN30_HUBP_REG_COMMON_VARIABLE_LIST; + DCN32_HUBP_REG_COMMON_VARIABLE_LIST; }; struct dcn_hubp2_shift { - DCN31_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); + DCN32_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); }; struct dcn_hubp2_mask { - DCN31_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); + DCN32_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); }; struct dcn20_hubp { diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index ec6aa8d8b251..d00a27893ab0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -768,6 +768,10 @@ enum dc_status dcn20_enable_stream_timing( /* TODO enable stream if timing changed */ /* TODO unblank stream if DP */ + if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { + if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable) + pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg); + } return DC_OK; } @@ -1247,6 +1251,16 @@ void dcn20_pipe_control_lock( lock, &hw_locks, &inst_flags); + } else if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { + union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; + hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; + hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; + hw_lock_cmd.bits.lock_pipe = 1; + hw_lock_cmd.bits.otg_inst = pipe->stream_res.tg->inst; + hw_lock_cmd.bits.lock = lock; + if (!lock) + hw_lock_cmd.bits.should_release = 1; + dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { if (lock) pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); @@ -1564,10 +1578,12 @@ static void dcn20_update_dchubp_dpp( plane_state->update_flags.bits.addr_update) hws->funcs.update_plane_addr(dc, pipe_ctx); - - if (pipe_ctx->update_flags.bits.enable) hubp->funcs->set_blank(hubp, false); + /* If the stream paired with this plane is phantom, the plane is also phantom */ + if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM + && hubp->funcs->phantom_hubp_post_enable) + hubp->funcs->phantom_hubp_post_enable(hubp); } @@ -1578,6 +1594,7 @@ static void dcn20_program_pipe( { struct dce_hwseq *hws = dc->hwseq; /* Only need to unblank on top pipe */ + if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level) && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); @@ -1585,7 +1602,6 @@ static void dcn20_program_pipe( /* Only update TG on top pipe */ if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) { - pipe_ctx->stream_res.tg->funcs->program_global_sync( pipe_ctx->stream_res.tg, pipe_ctx->pipe_dlg_param.vready_offset, @@ -1593,7 +1609,12 @@ static void dcn20_program_pipe( pipe_ctx->pipe_dlg_param.vupdate_offset, pipe_ctx->pipe_dlg_param.vupdate_width); - pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); + if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) { + pipe_ctx->stream_res.tg->funcs->wait_for_state( + pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); + pipe_ctx->stream_res.tg->funcs->wait_for_state( + pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); + } pipe_ctx->stream_res.tg->funcs->set_vtg_params( pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true); @@ -1749,6 +1770,8 @@ void dcn20_program_front_end_for_ctx( pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp); } } + if (hws->funcs.program_mall_pipe_config) + hws->funcs.program_mall_pipe_config(dc, context); } void dcn20_post_unlock_program_front_end( @@ -2409,6 +2432,7 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) NULL, hubp->inst, mpcc_id); + dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); ASSERT(new_mpcc != NULL); diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c index a04ca4a98392..b683ad817106 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c @@ -195,7 +195,7 @@ static void enc3_update_hdmi_info_packet( } } -static void enc3_stream_encoder_update_hdmi_info_packets( +void enc3_stream_encoder_update_hdmi_info_packets( struct stream_encoder *enc, const struct encoder_info_frame *info_frame) { @@ -214,7 +214,7 @@ static void enc3_stream_encoder_update_hdmi_info_packets( enc3_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd); } -static void enc3_stream_encoder_stop_hdmi_info_packets( +void enc3_stream_encoder_stop_hdmi_info_packets( struct stream_encoder *enc) { struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); @@ -318,7 +318,7 @@ static void enc3_dp_set_dsc_config(struct stream_encoder *enc, } -static void enc3_dp_set_dsc_pps_info_packet(struct stream_encoder *enc, +void enc3_dp_set_dsc_pps_info_packet(struct stream_encoder *enc, bool enable, uint8_t *dsc_packed_pps, bool immediate_update) @@ -404,7 +404,7 @@ static void enc3_read_state(struct stream_encoder *enc, struct enc_state *s) } } -static void enc3_stream_encoder_update_dp_info_packets( +void enc3_stream_encoder_update_dp_info_packets( struct stream_encoder *enc, const struct encoder_info_frame *info_frame) { @@ -652,7 +652,7 @@ static void enc3_stream_encoder_hdmi_set_stream_attribute( REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); } -static void enc3_audio_mute_control( +void enc3_audio_mute_control( struct stream_encoder *enc, bool mute) { @@ -660,7 +660,7 @@ static void enc3_audio_mute_control( enc->afmt->funcs->audio_mute_control(enc->afmt, mute); } -static void enc3_se_dp_audio_setup( +void enc3_se_dp_audio_setup( struct stream_encoder *enc, unsigned int az_inst, struct audio_info *info) @@ -691,7 +691,7 @@ static void enc3_se_setup_dp_audio( enc->afmt->funcs->setup_dp_audio(enc->afmt); } -static void enc3_se_dp_audio_enable( +void enc3_se_dp_audio_enable( struct stream_encoder *enc) { enc1_se_enable_audio_clock(enc, true); @@ -757,7 +757,7 @@ static void enc3_se_setup_hdmi_audio( */ } -static void enc3_se_hdmi_audio_setup( +void enc3_se_hdmi_audio_setup( struct stream_encoder *enc, unsigned int az_inst, struct audio_info *info, diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h index 42140e73c3b2..d2207b35f15f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h @@ -287,4 +287,39 @@ void dcn30_dio_stream_encoder_construct( const struct dcn10_stream_encoder_shift *se_shift, const struct dcn10_stream_encoder_mask *se_mask); +void enc3_stream_encoder_update_hdmi_info_packets( + struct stream_encoder *enc, + const struct encoder_info_frame *info_frame); + +void enc3_stream_encoder_stop_hdmi_info_packets( + struct stream_encoder *enc); + +void enc3_stream_encoder_update_dp_info_packets( + struct stream_encoder *enc, + const struct encoder_info_frame *info_frame); + +void enc3_audio_mute_control( + struct stream_encoder *enc, + bool mute); + +void enc3_se_dp_audio_setup( + struct stream_encoder *enc, + unsigned int az_inst, + struct audio_info *info); + +void enc3_se_dp_audio_enable( + struct stream_encoder *enc); + +void enc3_se_hdmi_audio_setup( + struct stream_encoder *enc, + unsigned int az_inst, + struct audio_info *info, + struct audio_crtc_info *audio_crtc_info); + +void enc3_dp_set_dsc_pps_info_packet( + struct stream_encoder *enc, + bool enable, + uint8_t *dsc_packed_pps, + bool immediate_update); + #endif /* __DC_DIO_STREAM_ENCODER_DCN30_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c index ab3918c0a15b..9cca59bf2ae0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c @@ -41,9 +41,9 @@ dpp->tf_shift->field_name, dpp->tf_mask->field_name -static void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) +void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) { - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); + struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); REG_GET(DPP_CONTROL, DPP_CLOCK_ENABLE, &s->is_enabled); @@ -167,7 +167,7 @@ void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined t PRE_DEGAM_SELECT, degamma_lut_selection); } -static void dpp3_cnv_setup ( +void dpp3_cnv_setup ( struct dpp *dpp_base, enum surface_pixel_format format, enum expansion_mode mode, @@ -372,7 +372,7 @@ void dpp3_set_cursor_attributes( } -static bool dpp3_get_optimal_number_of_taps( +bool dpp3_get_optimal_number_of_taps( struct dpp *dpp, struct scaler_data *scl_data, const struct scaling_taps *in_taps) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h index ac644ae6b9f2..6263408d71fc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h @@ -588,6 +588,22 @@ void dpp3_program_CM_dealpha( struct dpp *dpp_base, uint32_t enable, uint32_t additive_blending); +void dpp30_read_state(struct dpp *dpp_base, + struct dcn_dpp_state *s); + +bool dpp3_get_optimal_number_of_taps( + struct dpp *dpp, + struct scaler_data *scl_data, + const struct scaling_taps *in_taps); + +void dpp3_cnv_setup ( + struct dpp *dpp_base, + enum surface_pixel_format format, + enum expansion_mode mode, + struct dc_csc_transform input_csc_color_matrix, + enum dc_color_space input_color_space, + struct cnv_alpha_2bit_lut *alpha_2bit_lut); + void dpp3_program_CM_bias( struct dpp *dpp_base, struct CM_bias_params *bias_params); diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c index 0ce0d6165f43..1981a71b961b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c @@ -44,7 +44,7 @@ #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) -static bool mpc3_is_dwb_idle( +bool mpc3_is_dwb_idle( struct mpc *mpc, int dwb_id) { @@ -59,7 +59,7 @@ static bool mpc3_is_dwb_idle( return false; } -static void mpc3_set_dwb_mux( +void mpc3_set_dwb_mux( struct mpc *mpc, int dwb_id, int mpcc_id) @@ -70,7 +70,7 @@ static void mpc3_set_dwb_mux( MPC_DWB0_MUX, mpcc_id); } -static void mpc3_disable_dwb_mux( +void mpc3_disable_dwb_mux( struct mpc *mpc, int dwb_id) { @@ -80,7 +80,7 @@ static void mpc3_disable_dwb_mux( MPC_DWB0_MUX, 0xf); } -static void mpc3_set_out_rate_control( +void mpc3_set_out_rate_control( struct mpc *mpc, int opp_id, bool enable, @@ -99,7 +99,7 @@ static void mpc3_set_out_rate_control( MPC_OUT_FLOW_CONTROL_COUNT, flow_control->flow_ctrl_cnt1); } -static enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id) +enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id) { /*Contrary to DCN2 and DCN1 wherein a single status register field holds this info; *in DCN3/3AG, we need to read two separate fields to retrieve the same info @@ -137,7 +137,7 @@ static enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id) return mode; } -static void mpc3_power_on_ogam_lut( +void mpc3_power_on_ogam_lut( struct mpc *mpc, int mpcc_id, bool power_on) { @@ -1035,7 +1035,7 @@ static void mpc3_set3dlut_ram10( } -static void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst) +void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst) { mpcc->mpcc_id = mpcc_inst; mpcc->dpp_id = 0xf; diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h index 34b9cedbd012..a4d8f77d43bc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h @@ -282,6 +282,73 @@ uint32_t MPCC_OGAM_RAMB_START_BASE_CNTL_R[MAX_MPCC]; \ uint32_t MPC_OUT_CSC_COEF_FORMAT +#define MPC_REG_VARIABLE_LIST_DCN32 \ + uint32_t MPCC_MCM_SHAPER_CONTROL[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_OFFSET_R[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_OFFSET_G[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_OFFSET_B[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_SCALE_R[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_SCALE_G_B[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_LUT_INDEX[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_LUT_DATA[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_B[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_G[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_R[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_B[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_G[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_R[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_REGION_0_1[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_REGION_2_3[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_REGION_4_5[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_REGION_6_7[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_REGION_8_9[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_REGION_10_11[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_REGION_12_13[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_REGION_14_15[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_REGION_16_17[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_REGION_18_19[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_REGION_20_21[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_REGION_22_23[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_REGION_24_25[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_REGION_26_27[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_REGION_28_29[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_REGION_30_31[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMA_REGION_32_33[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_B[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_G[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_R[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_B[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_G[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_R[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_REGION_0_1[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_REGION_2_3[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_REGION_4_5[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_REGION_6_7[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_REGION_8_9[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_REGION_10_11[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_REGION_12_13[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_REGION_14_15[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_REGION_16_17[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_REGION_18_19[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_REGION_20_21[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_REGION_22_23[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_REGION_24_25[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_REGION_26_27[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_REGION_28_29[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_REGION_30_31[MAX_MPCC]; \ + uint32_t MPCC_MCM_SHAPER_RAMB_REGION_32_33[MAX_MPCC]; \ + uint32_t MPCC_MCM_3DLUT_MODE[MAX_MPCC]; \ + uint32_t MPCC_MCM_3DLUT_INDEX[MAX_MPCC]; \ + uint32_t MPCC_MCM_3DLUT_DATA[MAX_MPCC]; \ + uint32_t MPCC_MCM_3DLUT_DATA_30BIT[MAX_MPCC]; \ + uint32_t MPCC_MCM_3DLUT_READ_WRITE_CONTROL[MAX_MPCC]; \ + uint32_t MPCC_MCM_3DLUT_OUT_NORM_FACTOR[MAX_MPCC]; \ + uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_R[MAX_MPCC]; \ + uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_G[MAX_MPCC]; \ + uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_B[MAX_MPCC]; \ + uint32_t MPCC_MCM_MEM_PWR_CTRL[MAX_MPCC] + #define MPC_COMMON_MASK_SH_LIST_DCN3_0(mask_sh) \ MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\ SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\ @@ -580,6 +647,53 @@ type MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS;\ type MPC_RMU_SHAPER_MODE_CURRENT +#define MPC_REG_FIELD_LIST_DCN32(type) \ + type MPCC_MCM_SHAPER_MEM_PWR_FORCE;\ + type MPCC_MCM_SHAPER_MEM_PWR_DIS;\ + type MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE;\ + type MPCC_MCM_3DLUT_MEM_PWR_FORCE;\ + type MPCC_MCM_3DLUT_MEM_PWR_DIS;\ + type MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE;\ + type MPCC_MCM_1DLUT_MEM_PWR_FORCE;\ + type MPCC_MCM_1DLUT_MEM_PWR_DIS;\ + type MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE;\ + type MPCC_MCM_SHAPER_MEM_PWR_STATE;\ + type MPCC_MCM_3DLUT_MEM_PWR_STATE;\ + type MPCC_MCM_1DLUT_MEM_PWR_STATE;\ + type MPCC_MCM_3DLUT_MODE; \ + type MPCC_MCM_3DLUT_SIZE; \ + type MPCC_MCM_3DLUT_MODE_CURRENT; \ + type MPCC_MCM_3DLUT_WRITE_EN_MASK;\ + type MPCC_MCM_3DLUT_RAM_SEL;\ + type MPCC_MCM_3DLUT_30BIT_EN;\ + type MPCC_MCM_3DLUT_CONFIG_STATUS;\ + type MPCC_MCM_3DLUT_READ_SEL;\ + type MPCC_MCM_3DLUT_INDEX;\ + type MPCC_MCM_3DLUT_DATA0;\ + type MPCC_MCM_3DLUT_DATA1;\ + type MPCC_MCM_3DLUT_DATA_30BIT;\ + type MPCC_MCM_SHAPER_LUT_MODE;\ + type MPCC_MCM_SHAPER_MODE_CURRENT;\ + type MPCC_MCM_SHAPER_OFFSET_R;\ + type MPCC_MCM_SHAPER_OFFSET_G;\ + type MPCC_MCM_SHAPER_OFFSET_B;\ + type MPCC_MCM_SHAPER_SCALE_R;\ + type MPCC_MCM_SHAPER_SCALE_G;\ + type MPCC_MCM_SHAPER_SCALE_B;\ + type MPCC_MCM_SHAPER_LUT_INDEX;\ + type MPCC_MCM_SHAPER_LUT_DATA;\ + type MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK;\ + type MPCC_MCM_SHAPER_LUT_WRITE_SEL;\ + type MPCC_MCM_SHAPER_CONFIG_STATUS;\ + type MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B;\ + type MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B;\ + type MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B;\ + type MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B;\ + type MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\ + type MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\ + type MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET;\ + type MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS + #define MPC_COMMON_MASK_SH_LIST_DCN303(mask_sh) \ MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\ SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\ @@ -758,14 +872,17 @@ struct dcn30_mpc_registers { MPC_REG_VARIABLE_LIST_DCN3_0; + MPC_REG_VARIABLE_LIST_DCN32; }; struct dcn30_mpc_shift { MPC_REG_FIELD_LIST_DCN3_0(uint8_t); + MPC_REG_FIELD_LIST_DCN32(uint8_t); }; struct dcn30_mpc_mask { MPC_REG_FIELD_LIST_DCN3_0(uint32_t); + MPC_REG_FIELD_LIST_DCN32(uint32_t); }; struct dcn30_mpc { @@ -841,4 +958,34 @@ void mpc3_set_rmu_mux( int rmu_idx, int value); +void mpc3_set_dwb_mux( + struct mpc *mpc, + int dwb_id, + int mpcc_id); + +void mpc3_disable_dwb_mux( + struct mpc *mpc, + int dwb_id); + +bool mpc3_is_dwb_idle( + struct mpc *mpc, + int dwb_id); + +void mpc3_set_out_rate_control( + struct mpc *mpc, + int opp_id, + bool enable, + bool rate_2x_mode, + struct mpc_dwb_flow_control *flow_control); + +void mpc3_power_on_ogam_lut( + struct mpc *mpc, int mpcc_id, + bool power_on); + +void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst); + +enum dc_lut_mode mpc3_get_ogam_current( + struct mpc *mpc, + int mpcc_id); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h index 97f11ef6e9f0..33bd12f5dc17 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h @@ -28,6 +28,7 @@ #include "dcn20/dcn20_optc.h" +#define V_TOTAL_REGS_DCN30_SRI(inst) #define OPTC_COMMON_REG_LIST_DCN3_BASE(inst) \ SRI(OTG_VSTARTUP_PARAM, OTG, inst),\ @@ -55,6 +56,7 @@ SRI(OTG_V_TOTAL_MAX, OTG, inst),\ SRI(OTG_V_TOTAL_MIN, OTG, inst),\ SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\ + V_TOTAL_REGS_DCN30_SRI(inst)\ SRI(OTG_TRIGA_CNTL, OTG, inst),\ SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\ SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\ @@ -80,6 +82,7 @@ SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\ SRI(OTG_GSL_CONTROL, OTG, inst),\ SRI(OTG_CRC_CNTL, OTG, inst),\ + SRI(OTG_CRC_CNTL2, OTG, inst),\ SRI(OTG_CRC0_DATA_RG, OTG, inst),\ SRI(OTG_CRC0_DATA_B, OTG, inst),\ SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\ @@ -108,6 +111,7 @@ SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ SR(DWB_SOURCE_SELECT) +#define DCN30_VTOTAL_REGS_SF(mask_sh) #define OPTC_COMMON_MASK_SH_LIST_DCN3_BASE(mask_sh)\ SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ @@ -161,6 +165,7 @@ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\ + DCN30_VTOTAL_REGS_SF(mask_sh)\ SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\ SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\ SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\ @@ -219,6 +224,10 @@ SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\ SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\ SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\ SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c index 4519ecef2e7b..13dbf99af220 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c @@ -158,10 +158,9 @@ static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst) } } -void dccg31_set_dpstreamclk( - struct dccg *dccg, - enum hdmistreamclk_source src, - int otg_inst) +void dccg31_set_dpstreamclk(struct dccg *dccg, + enum streamclk_source src, + int otg_inst) { if (src == REFCLK) dccg31_disable_dpstreamclk(dccg, otg_inst); @@ -662,6 +661,24 @@ void dccg31_init(struct dccg *dccg) } } +void dccg31_otg_add_pixel(struct dccg *dccg, + uint32_t otg_inst) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], + OTG_ADD_PIXEL[otg_inst], 1); +} + +void dccg31_otg_drop_pixel(struct dccg *dccg, + uint32_t otg_inst) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], + OTG_DROP_PIXEL[otg_inst], 1); +} + static const struct dccg_funcs dccg31_funcs = { .update_dpp_dto = dccg31_update_dpp_dto, .get_dccg_ref_freq = dccg31_get_dccg_ref_freq, @@ -674,6 +691,9 @@ static const struct dccg_funcs dccg31_funcs = { .set_physymclk = dccg31_set_physymclk, .set_dtbclk_dto = dccg31_set_dtbclk_dto, .set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto, + .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, + .otg_add_pixel = dccg31_otg_add_pixel, + .otg_drop_pixel = dccg31_otg_drop_pixel, .set_dispclk_change_mode = dccg31_set_dispclk_change_mode, .disable_dsc = dccg31_disable_dscclk, .enable_dsc = dccg31_enable_dscclk, diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h index f158c1ea214b..80bd80707991 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h @@ -28,10 +28,6 @@ #include "dcn30/dcn30_dccg.h" -#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\ - .field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix - - #define DCCG_REG_LIST_DCN31() \ SR(DPPCLK_DTO_CTRL),\ DCCG_SRII(DTO_PARAM, DPPCLK, 0),\ @@ -124,6 +120,10 @@ DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 1, mask_sh),\ DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 2, mask_sh),\ DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 3, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\ DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\ DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\ DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh), \ @@ -163,7 +163,7 @@ void dccg31_init(struct dccg *dccg); void dccg31_set_dpstreamclk( struct dccg *dccg, - enum hdmistreamclk_source src, + enum streamclk_source src, int otg_inst); void dccg31_enable_symclk32_se( @@ -194,8 +194,4 @@ void dccg31_set_audio_dtbclk_dto( struct dccg *dccg, const struct dtbclk_dto_params *params); -void dccg31_set_hdmistreamclk( - struct dccg *dccg, - enum hdmistreamclk_source src); - #endif //__DCN31_DCCG_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c index c51f7dca94f8..96fac715a77b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c @@ -213,26 +213,6 @@ void optc31_set_drr( } } -void optc3_init_odm(struct timing_generator *optc) -{ - struct optc *optc1 = DCN10TG_FROM_TG(optc); - - REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, - OPTC_NUM_OF_INPUT_SEGMENT, 0, - OPTC_SEG0_SRC_SEL, optc->inst, - OPTC_SEG1_SRC_SEL, 0xf, - OPTC_SEG2_SRC_SEL, 0xf, - OPTC_SEG3_SRC_SEL, 0xf - ); - - REG_SET(OTG_H_TIMING_CNTL, 0, - OTG_H_TIMING_DIV_MODE, 0); - - REG_SET(OPTC_MEMORY_CONFIG, 0, - OPTC_MEM_SEL, 0); - optc1->opp_count = 1; -} - static struct timing_generator_funcs dcn31_tg_funcs = { .validate_timing = optc1_validate_timing, .program_timing = optc1_program_timing, @@ -266,6 +246,7 @@ static struct timing_generator_funcs dcn31_tg_funcs = { .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable, .enable_optc_clock = optc1_enable_optc_clock, .set_drr = optc31_set_drr, + .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal, .set_vtotal_min_max = optc1_set_vtotal_min_max, .set_static_screen_control = optc1_set_static_screen_control, .program_stereo = optc1_program_stereo, @@ -292,7 +273,6 @@ static struct timing_generator_funcs dcn31_tg_funcs = { .program_manual_trigger = optc2_program_manual_trigger, .setup_manual_trigger = optc2_setup_manual_trigger, .get_hw_timing = optc1_get_hw_timing, - .init_odm = optc3_init_odm, }; void dcn31_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h index 9e881f2ce74b..3706e6f7880e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h @@ -98,7 +98,8 @@ SRI(OPTC_WIDTH_CONTROL, ODM, inst),\ SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ SRI(OTG_CRC_CNTL2, OTG, inst),\ - SR(DWB_SOURCE_SELECT) + SR(DWB_SOURCE_SELECT),\ + SRI(OTG_DRR_CONTROL, OTG, inst) #define OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh)\ SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ @@ -252,7 +253,8 @@ SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\ SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\ SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\ - SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh) + SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\ + SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) void dcn31_timing_generator_init(struct optc *optc1); diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c index 12633561be3f..5609ac6d6040 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c @@ -141,52 +141,45 @@ static void dccg32_set_dtbclk_p_src( /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */ void dccg32_set_dtbclk_dto( struct dccg *dccg, - int otg_inst, - int pixclk_khz, - int num_odm_segments, - const struct dc_crtc_timing *timing) + const struct dtbclk_dto_params *params) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); /* DTO Output Rate / Pixel Rate = 1/4 */ - int req_dtbclk_khz = pixclk_khz / 4; + int req_dtbclk_khz = params->pixclk_khz / 4; - if (dccg->ref_dtbclk_khz && req_dtbclk_khz) { + if (params->ref_dtbclk_khz && req_dtbclk_khz) { uint32_t modulo, phase; // phase / modulo = dtbclk / dtbclk ref - modulo = 0xffffffff; - phase = (((unsigned long long)modulo * req_dtbclk_khz) + dccg->ref_dtbclk_khz - 1) / dccg->ref_dtbclk_khz; + modulo = params->ref_dtbclk_khz * 1000; + phase = req_dtbclk_khz * 1000; - REG_WRITE(DTBCLK_DTO_MODULO[otg_inst], modulo); - REG_WRITE(DTBCLK_DTO_PHASE[otg_inst], phase); + REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); + REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase); - REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], - DTBCLK_DTO_ENABLE[otg_inst], 1); + REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], + DTBCLK_DTO_ENABLE[params->otg_inst], 1); - REG_WAIT(OTG_PIXEL_RATE_CNTL[otg_inst], - DTBCLKDTO_ENABLE_STATUS[otg_inst], 1, + REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst], + DTBCLKDTO_ENABLE_STATUS[params->otg_inst], 1, 1, 100); /* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */ - dccg32_set_pixel_rate_div(dccg, otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1); + dccg32_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1); /* The recommended programming sequence to enable DTBCLK DTO to generate * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should * be set only after DTO is enabled */ - REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], - PIPE_DTO_SRC_SEL[otg_inst], 2); - - dccg->dtbclk_khz[otg_inst] = req_dtbclk_khz; + REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], + PIPE_DTO_SRC_SEL[params->otg_inst], 2); } else { - REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], - DTBCLK_DTO_ENABLE[otg_inst], 0, - PIPE_DTO_SRC_SEL[otg_inst], 1); - - REG_WRITE(DTBCLK_DTO_MODULO[otg_inst], 0); - REG_WRITE(DTBCLK_DTO_PHASE[otg_inst], 0); + REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst], + DTBCLK_DTO_ENABLE[params->otg_inst], 0, + PIPE_DTO_SRC_SEL[params->otg_inst], 1); - dccg->dtbclk_khz[otg_inst] = 0; + REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0); + REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0); } } diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c index 62532da94913..4d7588f2ee79 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c @@ -211,8 +211,10 @@ static void enc32_stream_encoder_hdmi_set_stream_attribute( HDMI_GC_SEND, 1, HDMI_NULL_SEND, 1); +#if defined(CONFIG_DRM_AMD_DC_HDCP) /* Disable Audio Content Protection packet transmission */ REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0); +#endif /* following belongs to audio */ /* Enable Audio InfoFrame packet transmission. */ @@ -301,6 +303,21 @@ static void enc32_stream_encoder_dp_unblank( REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); + /* DIG Resync FIFO now needs to be explicitly enabled + */ + // TODO: Confirm if we need to wait for DIG_SYMCLK_FE_ON + REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000); + + REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1); + + REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000); + + REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0); + + REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000); + + REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1); + /* wait 100us for DIG/DP logic to prime * (i.e. a few video lines) */ @@ -354,6 +371,23 @@ static void enc32_read_state(struct stream_encoder *enc, struct enc_state *s) } } +static void enc32_stream_encoder_reset_fifo(struct stream_encoder *enc) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + uint32_t fifo_enabled; + + REG_GET(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, &fifo_enabled); + + if (fifo_enabled == 0) { + /* reset DIG resync FIFO */ + REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1); + /* TODO: fix timeout when wait for DIG_FIFO_RESET_DONE */ + //REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 1, 100); + udelay(1); + REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0); + REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 1, 100); + } +} static const struct stream_encoder_funcs dcn32_str_enc_funcs = { .dp_set_odm_combine = @@ -375,7 +409,7 @@ static const struct stream_encoder_funcs dcn32_str_enc_funcs = { .stop_dp_info_packets = enc1_stream_encoder_stop_dp_info_packets, .reset_fifo = - enc1_stream_encoder_reset_fifo, + enc32_stream_encoder_reset_fifo, .dp_blank = enc1_stream_encoder_dp_blank, .dp_unblank = diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h index 7241080b1553..77da0a13525b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h @@ -89,7 +89,8 @@ SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \ SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ SRI(DIG_FE_CNTL, DIG, id), \ - SRI(DIG_CLOCK_PATTERN, DIG, id) + SRI(DIG_CLOCK_PATTERN, DIG, id), \ + SRI(DIG_FIFO_CTRL0, DIG, id) #define SE_COMMON_MASK_SH_LIST_DCN32_BASE(mask_sh)\ @@ -233,12 +234,22 @@ SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE_REFERENCE, mask_sh),\ SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE, mask_sh),\ SE_SF(DIG0_DIG_FE_CNTL, DOLBY_VISION_EN, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, DIG_SYMCLK_FE_ON, mask_sh),\ SE_SF(DP0_DP_SEC_FRAMING4, DP_SST_SDP_SPLITTING, mask_sh),\ - SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh) + SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_HDCP) #define SE_COMMON_MASK_SH_LIST_DCN32(mask_sh)\ SE_COMMON_MASK_SH_LIST_DCN32_BASE(mask_sh),\ SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh) +#else +#define SE_COMMON_MASK_SH_LIST_DCN32(mask_sh)\ + SE_COMMON_MASK_SH_LIST_DCN32_BASE(mask_sh) +#endif void dcn32_dio_stream_encoder_construct( struct dcn10_stream_encoder *enc1, diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c index d0a222f1a09c..40afd33ffec6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c @@ -649,7 +649,7 @@ void dcn32_init_hw(struct dc *dc) * Otherwise, if taking control is not possible, we need to power * everything down. */ - if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) { + if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.seamless_boot_edp_requested) { hws->funcs.init_pipes(dc, dc->current_state); if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, @@ -661,7 +661,7 @@ void dcn32_init_hw(struct dc *dc) * To avoid this, power down hardware on boot * if DIG is turned on and seamless boot not enabled */ - if (dc->config.power_down_display_on_boot) { + if (dc->config.seamless_boot_edp_requested) { struct dc_link *edp_links[MAX_NUM_EDP]; struct dc_link *edp_link; diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c index f1ed25e972f2..88275ea4193c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c @@ -91,10 +91,18 @@ static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, i REG_UPDATE(OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mpcc_hactive); - REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); + REG_UPDATE(OTG_H_TIMING_CNTL, + OTG_H_TIMING_DIV_MODE, opp_cnt - 1); optc1->opp_count = opp_cnt; } +static void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + REG_UPDATE(OTG_H_TIMING_CNTL, + OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0); +} /** * Enable CRTC * Enable CRTC - call ASIC Control Object to enable Timing generator. @@ -157,6 +165,29 @@ void optc32_phantom_crtc_post_enable(struct timing_generator *optc) REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); } +static void optc32_set_odm_bypass(struct timing_generator *optc, + const struct dc_crtc_timing *dc_crtc_timing) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + enum h_timing_div_mode h_div = H_TIMING_NO_DIV; + + REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, + OPTC_NUM_OF_INPUT_SEGMENT, 0, + OPTC_SEG0_SRC_SEL, optc->inst, + OPTC_SEG1_SRC_SEL, 0xf, + OPTC_SEG2_SRC_SEL, 0xf, + OPTC_SEG3_SRC_SEL, 0xf + ); + + h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing); + REG_UPDATE(OTG_H_TIMING_CNTL, + OTG_H_TIMING_DIV_MODE, h_div); + + REG_SET(OPTC_MEMORY_CONFIG, 0, + OPTC_MEM_SEL, 0); + optc1->opp_count = 1; +} + static struct timing_generator_funcs dcn32_tg_funcs = { .validate_timing = optc1_validate_timing, @@ -206,8 +237,9 @@ static struct timing_generator_funcs dcn32_tg_funcs = { .set_dsc_config = optc3_set_dsc_config, .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, - .set_odm_bypass = optc3_set_odm_bypass, + .set_odm_bypass = optc32_set_odm_bypass, .set_odm_combine = optc32_set_odm_combine, + .set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode, .get_optc_source = optc2_get_optc_source, .set_out_mux = optc3_set_out_mux, .set_drr_trigger_window = optc3_set_drr_trigger_window, diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c index 17a287bc89ce..7ac6428aae52 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c @@ -77,7 +77,7 @@ #include "dcn/dcn_3_2_0_offset.h" #include "dcn/dcn_3_2_0_sh_mask.h" -#include "dcn/nbio_4_3_0_offset.h" +#include "nbio/nbio_4_3_0_offset.h" #include "reg_helper.h" #include "dce/dmub_abm.h" diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index f79dd40f8d81..8d4c74b0fc90 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -811,9 +811,14 @@ void dcn20_calculate_dlg_params( pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); - context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes; - context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode; - + if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { + // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests + context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0; + context->res_ctx.pipe_ctx[i].unbounded_req = false; + } else { + context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes; + context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode; + } if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = @@ -1013,6 +1018,31 @@ int dcn20_populate_dml_pipes_from_context( pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2; pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; pipes[pipe_cnt].dout.dp_lanes = 4; + if (res_ctx->pipe_ctx[i].stream->link) { + switch (res_ctx->pipe_ctx[i].stream->link->cur_link_settings.link_rate) { + case LINK_RATE_HIGH: + pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr; + break; + case LINK_RATE_HIGH2: + pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr2; + break; + case LINK_RATE_HIGH3: + pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr3; + break; + case LINK_RATE_UHBR10: + pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_uhbr10; + break; + case LINK_RATE_UHBR13_5: + pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_uhbr13p5; + break; + case LINK_RATE_UHBR20: + pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_uhbr20; + break; + default: + pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na; + break; + } + } pipes[pipe_cnt].dout.is_virtual = 0; pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min; pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max; @@ -1070,6 +1100,7 @@ int dcn20_populate_dml_pipes_from_context( pipes[pipe_cnt].dout.is_virtual = 1; pipes[pipe_cnt].dout.output_type = dm_dp; pipes[pipe_cnt].dout.dp_lanes = 4; + pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr2; } switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) { @@ -1138,7 +1169,8 @@ int dcn20_populate_dml_pipes_from_context( * bw calculations due to cursor on/off */ if (res_ctx->pipe_ctx[i].plane_state && - res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) + (res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE || + res_ctx->pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM)) pipes[pipe_cnt].pipe.src.num_cursors = 0; else pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors; @@ -1149,6 +1181,7 @@ int dcn20_populate_dml_pipes_from_context( if (!res_ctx->pipe_ctx[i].plane_state) { pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled; pipes[pipe_cnt].pipe.src.source_scan = dm_horz; + pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_0; pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s; pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile; pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable; @@ -1201,8 +1234,26 @@ int dcn20_populate_dml_pipes_from_context( pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz; + switch (pln->rotation) { + case ROTATION_ANGLE_0: + pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_0; + break; + case ROTATION_ANGLE_90: + pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_90; + break; + case ROTATION_ANGLE_180: + pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_180; + break; + case ROTATION_ANGLE_270: + pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_270; + break; + default: + break; + } pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y; pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y; + pipes[pipe_cnt].pipe.src.viewport_x_y = scl->viewport.x; + pipes[pipe_cnt].pipe.src.viewport_x_c = scl->viewport_c.x; pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width; pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width; pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 555d4d9e1454..0317af5bb8ca 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -195,6 +195,16 @@ struct resource_funcs { enum dc_status (*add_dsc_to_stream_resource)( struct dc *dc, struct dc_state *state, struct dc_stream_state *stream); + + void (*add_phantom_pipes)( + struct dc *dc, + struct dc_state *context, + display_e2e_pipe_params_st *pipes, + unsigned int pipe_cnt, + unsigned int index); + void (*remove_phantom_pipes)( + struct dc *dc, + struct dc_state *context); }; struct audio_support{ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index c1023cc84f55..b5acc6b9f3c9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -45,9 +45,10 @@ enum physymclk_clock_source { PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO. }; -enum hdmistreamclk_source { +enum streamclk_source { REFCLK, // Selects REFCLK as source for hdmistreamclk. DTBCLK0, // Selects DTBCLK0 as source for hdmistreamclk. + DPREFCLK, // Selects DPREFCLK as source for hdmistreamclk }; enum dentist_dispclk_change_mode { @@ -91,7 +92,7 @@ struct dccg_funcs { void (*set_dpstreamclk)( struct dccg *dccg, - enum hdmistreamclk_source src, + enum streamclk_source src, int otg_inst); void (*enable_symclk32_se)( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h index 9195dec294c2..e7571c6f5ead 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h @@ -47,6 +47,8 @@ struct dcn_hubbub_wm_set { uint32_t sr_enter; uint32_t sr_exit; uint32_t dram_clk_chanage; + uint32_t usr_retrain; + uint32_t fclk_pstate_change; }; struct dcn_hubbub_wm { @@ -168,6 +170,7 @@ struct hubbub_funcs { void (*program_det_size)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_in_kbyte); void (*program_compbuf_size)(struct hubbub *hubbub, unsigned compbuf_size_kb, bool safe_to_increase); void (*init_crb)(struct hubbub *hubbub); + void (*force_usr_retraining_allow)(struct hubbub *hubbub, bool allow); }; struct hubbub { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index ad69d78c4ac3..b2cdb6bfc9b8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -140,6 +140,9 @@ struct hubp_funcs { void (*set_blank)(struct hubp *hubp, bool blank); void (*set_blank_regs)(struct hubp *hubp, bool blank); +#ifdef CONFIG_DRM_AMD_DC_DCN + void (*phantom_hubp_post_enable)(struct hubp *hubp); +#endif void (*set_hubp_blank_en)(struct hubp *hubp, bool blank); void (*set_cursor_attributes)( @@ -193,6 +196,10 @@ struct hubp_funcs { bool (*hubp_in_blank)(struct hubp *hubp); void (*hubp_soft_reset)(struct hubp *hubp, bool reset); + void (*hubp_update_force_pstate_disallow)(struct hubp *hubp, bool allow); + void (*hubp_update_mall_sel)(struct hubp *hubp, uint32_t mall_sel); + void (*hubp_prepare_subvp_buffering)(struct hubp *hubp, bool enable); + void (*hubp_set_flip_int)(struct hubp *hubp); void (*program_extended_blank)(struct hubp *hubp, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 8798cfa11a4d..b72fb314d804 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -37,6 +37,7 @@ struct cstate_pstate_watermarks_st { uint32_t cstate_enter_plus_exit_z8_ns; uint32_t cstate_enter_plus_exit_ns; uint32_t pstate_change_ns; + uint32_t fclk_pstate_change_ns; }; struct dcn_watermarks { @@ -46,6 +47,7 @@ struct dcn_watermarks { uint32_t frac_urg_bw_flip; int32_t urgent_latency_ns; struct cstate_pstate_watermarks_st cstate_pstate; + uint32_t usr_retraining_ns; }; struct dcn_watermark_set { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h index 678c2065e5e8..36ec56524afd 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -164,6 +164,10 @@ struct stream_encoder_funcs { void (*stop_dp_info_packets)( struct stream_encoder *enc); + void (*reset_fifo)( + struct stream_encoder *enc + ); + void (*dp_blank)( struct dc_link *link, struct stream_encoder *enc); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 554d2e33bd7f..a89b2230cd2c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -174,6 +174,9 @@ struct timing_generator_funcs { bool (*enable_crtc)(struct timing_generator *tg); bool (*disable_crtc)(struct timing_generator *tg); +#ifdef CONFIG_DRM_AMD_DC_DCN + void (*phantom_crtc_post_enable)(struct timing_generator *tg); +#endif bool (*immediate_disable_crtc)(struct timing_generator *tg); bool (*is_counter_moving)(struct timing_generator *tg); void (*get_position)(struct timing_generator *tg, @@ -293,6 +296,7 @@ struct timing_generator_funcs { void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing); void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt, struct dc_crtc_timing *timing); + void (*set_h_timing_div_manual_mode)(struct timing_generator *optc, bool manual_mode); void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params); void (*set_gsl_source_select)(struct timing_generator *optc, int group_idx, @@ -310,8 +314,10 @@ struct timing_generator_funcs { uint32_t slave_pixel_clock_100Hz, uint8_t master_clock_divider, uint8_t slave_clock_divider); - - void (*init_odm)(struct timing_generator *tg); + bool (*validate_vmin_vmax)(struct timing_generator *optc, + int vmin, int vmax); + bool (*validate_vtotal_change_limit)(struct timing_generator *optc, + uint32_t vtotal_change_limit); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 05053f3b4ab7..eb616a4ed508 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -244,6 +244,8 @@ struct hw_sequencer_funcs { struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id); + + void (*commit_subvp_config)(struct dc *dc, struct dc_state *context); }; void color_space_to_black_color( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h index d2cb0e794500..fd869e93cf54 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h @@ -145,6 +145,11 @@ struct hwseq_private_funcs { void (*PLAT_58856_wa)(struct dc_state *context, struct pipe_ctx *pipe_ctx); void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable); +#ifdef CONFIG_DRM_AMD_DC_DCN + void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context); + void (*subvp_update_force_pstate)(struct dc *dc, struct dc_state *context); + void (*update_mall_sel)(struct dc *dc, struct dc_state *context); +#endif }; struct dce_hwseq { diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 2369f38ed06f..58158764adc0 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -205,6 +205,13 @@ bool get_temp_dp_link_res(struct dc_link *link, struct link_resource *link_res, struct dc_link_settings *link_settings); +#if defined(CONFIG_DRM_AMD_DC_DCN) +struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt( + const struct resource_context *res_ctx, + const struct resource_pool *pool, + const struct dc_link *link); +#endif + void reset_syncd_pipes_from_disabled_pipes(struct dc *dc, struct dc_state *context); diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h index cf4027cc3f4c..83058bcbb2e8 100644 --- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h +++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h @@ -335,4 +335,14 @@ struct bp_soc_bb_info { uint32_t dram_sr_enter_exit_latency_100ns; }; +struct bp_connector_speed_cap_info { + uint32_t DP_HBR2_EN:1; + uint32_t DP_HBR3_EN:1; + uint32_t HDMI_6GB_EN:1; + uint32_t DP_UHBR10_EN:1; + uint32_t DP_UHBR13_5_EN:1; + uint32_t DP_UHBR20_EN:1; + uint32_t RESERVED:29; +}; + #endif /*__DAL_BIOS_PARSER_TYPES_H__ */ -- cgit v1.2.3 From 3b1229741eda70116e0163affdda377484a788ae Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Wed, 18 May 2022 14:11:20 +0800 Subject: drm/amdgpu/mes11: update mes11 api interface fix mes11 api interface. Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/mes_v11_api_def.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/include/mes_v11_api_def.h b/drivers/gpu/drm/amd/include/mes_v11_api_def.h index e30064477d82..f9d02d7bdf77 100644 --- a/drivers/gpu/drm/amd/include/mes_v11_api_def.h +++ b/drivers/gpu/drm/amd/include/mes_v11_api_def.h @@ -193,7 +193,7 @@ struct MES_LOG_BUFFER { }; enum MES_SWIP_TO_HWIP_DEF { - MES_MAX_HWIP_SEGMENT = 6, + MES_MAX_HWIP_SEGMENT = 8, }; union MESAPI_SET_HW_RESOURCES { -- cgit v1.2.3 From 577359ca178262a64236cc96299714dbff21e9c7 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Wed, 23 Feb 2022 19:05:09 -0500 Subject: drm/amd/display: Add DM support for DCN32/DCN321 Add Display Manager specific changes for DCN3.2.x. DM handles the interaction between the core DC modesetting code and the drm modesetting infrastructure. Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1c23a844b161..7280db2821ef 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -118,6 +118,11 @@ MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB); #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin" MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB); +#define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin" +MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB); +#define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin" +MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB); + #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); @@ -1803,6 +1808,8 @@ static int load_dmcu_fw(struct amdgpu_device *adev) case IP_VERSION(3, 1, 3): case IP_VERSION(3, 1, 5): case IP_VERSION(3, 1, 6): + case IP_VERSION(3, 2, 0): + case IP_VERSION(3, 2, 1): return 0; default: break; @@ -1926,6 +1933,14 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) dmub_asic = DMUB_ASIC_DCN316; fw_name_dmub = FIRMWARE_DCN316_DMUB; break; + case IP_VERSION(3, 2, 0): + dmub_asic = DMUB_ASIC_DCN32; + fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB; + break; + case IP_VERSION(3, 2, 1): + dmub_asic = DMUB_ASIC_DCN321; + fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB; + break; default: /* ASIC doesn't support DMUB. */ return 0; @@ -4235,6 +4250,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case IP_VERSION(3, 1, 3): case IP_VERSION(3, 1, 5): case IP_VERSION(3, 1, 6): + case IP_VERSION(3, 2, 0): + case IP_VERSION(3, 2, 1): case IP_VERSION(2, 1, 0): if (register_outbox_irq_handlers(dm->adev)) { DRM_ERROR("DM: Failed to initialize IRQ\n"); @@ -4253,6 +4270,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case IP_VERSION(3, 1, 3): case IP_VERSION(3, 1, 5): case IP_VERSION(3, 1, 6): + case IP_VERSION(3, 2, 0): + case IP_VERSION(3, 2, 1): psr_feature_enabled = true; break; default: @@ -4370,6 +4389,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case IP_VERSION(3, 1, 3): case IP_VERSION(3, 1, 5): case IP_VERSION(3, 1, 6): + case IP_VERSION(3, 2, 0): + case IP_VERSION(3, 2, 1): if (dcn10_register_irq_handlers(dm->adev)) { DRM_ERROR("DM: Failed to initialize IRQ\n"); goto fail; @@ -4556,6 +4577,8 @@ static int dm_early_init(void *handle) case IP_VERSION(3, 1, 3): case IP_VERSION(3, 1, 5): case IP_VERSION(3, 1, 6): + case IP_VERSION(3, 2, 0): + case IP_VERSION(3, 2, 1): adev->mode_info.num_crtc = 4; adev->mode_info.num_hpd = 4; adev->mode_info.num_dig = 4; -- cgit v1.2.3 From 85b0cc35efab0cbc78c083d4506250bea6a755ad Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Mon, 25 Apr 2022 18:33:23 -0400 Subject: drm/amd/display: add DCN32 to IP discovery table [Why&How] Add DCN32 to IP discovery to enable automatic initialization of AMDGPU Display Manager Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 47f0344205ed..91f21b725a43 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1709,6 +1709,8 @@ static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(3, 1, 3): case IP_VERSION(3, 1, 5): case IP_VERSION(3, 1, 6): + case IP_VERSION(3, 2, 0): + case IP_VERSION(3, 2, 1): amdgpu_device_ip_block_add(adev, &dm_ip_block); break; default: -- cgit v1.2.3 From 49401d3a5c86f5ead12ea7cbe98031edb512b13a Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Tue, 31 May 2022 09:51:40 +0800 Subject: drm/amd/amdgpu: align the cg and pg settings align the cg and pg settings between gc_v11_0 and gc_v11_2 Signed-off-by: Kenneth Feng Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc21.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 9e18a2b22607..09efef506e8f 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -555,8 +555,11 @@ static int soc21_common_early_init(void *handle) adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_REPEATER_FGCG | AMD_CG_SUPPORT_VCN_MGCG | - AMD_CG_SUPPORT_JPEG_MGCG; + AMD_CG_SUPPORT_JPEG_MGCG | + AMD_CG_SUPPORT_ATHUB_MGCG | + AMD_CG_SUPPORT_ATHUB_LS; adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG | -- cgit v1.2.3 From 543036a2de71f14f8ad566c858e5e9ff61736a86 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Mon, 21 Feb 2022 15:33:05 -0500 Subject: drm/amd: Add GFX11 modifiers support to AMDGPU (v3) GFX11 IP introduces new tiling mode. Various combinations of DCC settings are possible and the most preferred settings must be exposed for optimal use of the hardware. add_gfx11_modifiers() is based on recommendation from Marek for the preferred tiling modifier that are most efficient for the hardware. v2: microtiling fix noticed by Marek v3: keep Z tiling check Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 52 +++++++++++++--- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 76 ++++++++++++++++++++++- include/uapi/drm/drm_fourcc.h | 2 + 3 files changed, 117 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 17c9bbe0cbc5..8ef489fad707 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -30,6 +30,9 @@ #include "atom.h" #include "amdgpu_connectors.h" #include "amdgpu_display.h" +#include "soc15_common.h" +#include "gc/gc_11_0_0_offset.h" +#include "gc/gc_11_0_0_sh_mask.h" #include #include @@ -663,6 +666,11 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) { struct amdgpu_device *adev = drm_to_adev(afb->base.dev); uint64_t modifier = 0; + int num_pipes = 0; + int num_pkrs = 0; + + num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; + num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes; if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { modifier = DRM_FORMAT_MOD_LINEAR; @@ -675,7 +683,7 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) int bank_xor_bits = 0; int packers = 0; int rb = 0; - int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); + int pipes = ilog2(num_pipes); uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B); switch (swizzle >> 2) { @@ -691,12 +699,17 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) case 6: /* 64 KiB _X */ block_size_bits = 16; break; + case 7: /* 256 KiB */ + block_size_bits = 18; + break; default: /* RESERVED or VAR */ return -EINVAL; } - if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) + version = AMD_FMT_MOD_TILE_VER_GFX11; + else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS; else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0)) version = AMD_FMT_MOD_TILE_VER_GFX10; @@ -707,19 +720,33 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) case 0: /* Z microtiling */ return -EINVAL; case 1: /* S microtiling */ - if (!has_xor) - version = AMD_FMT_MOD_TILE_VER_GFX9; + if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { + if (!has_xor) + version = AMD_FMT_MOD_TILE_VER_GFX9; + } break; case 2: - if (!has_xor && afb->base.format->cpp[0] != 4) - version = AMD_FMT_MOD_TILE_VER_GFX9; + if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { + if (!has_xor && afb->base.format->cpp[0] != 4) + version = AMD_FMT_MOD_TILE_VER_GFX9; + } break; case 3: break; } if (has_xor) { + if (num_pipes == num_pkrs && num_pkrs == 0) { + DRM_ERROR("invalid number of pipes and packers\n"); + return -EINVAL; + } + switch (version) { + case AMD_FMT_MOD_TILE_VER_GFX11: + pipe_xor_bits = min(block_size_bits - 8, pipes); + packers = min(block_size_bits - 8 - pipe_xor_bits, + ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs)); + break; case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: pipe_xor_bits = min(block_size_bits - 8, pipes); packers = min(block_size_bits - 8 - pipe_xor_bits, @@ -753,9 +780,10 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) u64 render_dcc_offset; /* Enable constant encode on RAVEN2 and later. */ - bool dcc_constant_encode = adev->asic_type > CHIP_RAVEN || + bool dcc_constant_encode = (adev->asic_type > CHIP_RAVEN || (adev->asic_type == CHIP_RAVEN && - adev->external_rev_id >= 0x81); + adev->external_rev_id >= 0x81)) && + adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0); int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B : dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B : @@ -870,10 +898,11 @@ static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned, return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12); } case AMD_FMT_MOD_TILE_VER_GFX10: - case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: { + case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: + case AMD_FMT_MOD_TILE_VER_GFX11: { int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); - if (ver == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 && + if (ver >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 && AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2) ++pipes_log2; @@ -966,6 +995,9 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) case DC_SW_64KB_S_X: block_size_log2 = 16; break; + case DC_SW_VAR_S_X: + block_size_log2 = 18; + break; default: drm_dbg_kms(rfb->base.dev, "Swizzle mode with unknown block size: %d\n", swizzle); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7280db2821ef..872b7899b645 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -89,10 +89,14 @@ #include "dcn/dcn_1_0_offset.h" #include "dcn/dcn_1_0_sh_mask.h" #include "soc15_hw_ip.h" +#include "soc15_common.h" #include "vega10_ip_offset.h" #include "soc15_common.h" +#include "gc/gc_11_0_0_offset.h" +#include "gc/gc_11_0_0_sh_mask.h" + #include "modules/inc/mod_freesync.h" #include "modules/power/power_helpers.h" #include "modules/inc/mod_info_packet.h" @@ -4888,7 +4892,9 @@ fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev, unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier); unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier); - unsigned int pipes_log2 = min(4u, mod_pipe_xor_bits); + unsigned int pipes_log2; + + pipes_log2 = min(5u, mod_pipe_xor_bits); fill_gfx9_tiling_info_from_device(adev, tiling_info); @@ -5224,8 +5230,69 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev, AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); } +static void +add_gfx11_modifiers(struct amdgpu_device *adev, + uint64_t **mods, uint64_t *size, uint64_t *capacity) +{ + int num_pipes = 0; + int pipe_xor_bits = 0; + int num_pkrs = 0; + int pkrs = 0; + u32 gb_addr_config; + unsigned swizzle_r_x; + uint64_t modifier_r_x; + uint64_t modifier_dcc_best; + uint64_t modifier_dcc_4k; + + /* TODO: GFX11 IP HW init hasnt finish and we get zero if we read from + * adev->gfx.config.gb_addr_config_fields.num_{pkrs,pipes} */ + gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); + ASSERT(gb_addr_config != 0); + + num_pkrs = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); + pkrs = ilog2(num_pkrs); + num_pipes = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PIPES); + pipe_xor_bits = ilog2(num_pipes); + + /* R_X swizzle modes are the best for rendering and DCC requires them. */ + swizzle_r_x = num_pipes > 16 ? AMD_FMT_MOD_TILE_GFX11_256K_R_X : + AMD_FMT_MOD_TILE_GFX9_64K_R_X; + + modifier_r_x = AMD_FMT_MOD | + AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) | + AMD_FMT_MOD_SET(TILE, swizzle_r_x) | + AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | + AMD_FMT_MOD_SET(PACKERS, pkrs); + + /* DCC_CONSTANT_ENCODE is not set because it can't vary with gfx11 (it's implied to be 1). */ + modifier_dcc_best = modifier_r_x | + AMD_FMT_MOD_SET(DCC, 1) | + AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 0) | + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B); + + /* DCC settings for 4K and greater resolutions. (required by display hw) */ + modifier_dcc_4k = modifier_r_x | + AMD_FMT_MOD_SET(DCC, 1) | + AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B); + + add_modifier(mods, size, capacity, modifier_dcc_best); + add_modifier(mods, size, capacity, modifier_dcc_4k); + + add_modifier(mods, size, capacity, modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1)); + add_modifier(mods, size, capacity, modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1)); + + add_modifier(mods, size, capacity, modifier_r_x); + + add_modifier(mods, size, capacity, AMD_FMT_MOD | + AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) | + AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D)); +} + static int -get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods) +get_plane_modifiers(struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods) { uint64_t size = 0, capacity = 128; *mods = NULL; @@ -5257,6 +5324,9 @@ get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, u else add_gfx10_1_modifiers(adev, mods, &size, &capacity); break; + case AMDGPU_FAMILY_GC_11_0_0: + add_gfx11_modifiers(adev, mods, &size, &capacity); + break; } add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); @@ -5295,7 +5365,7 @@ fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev, dcc->enable = 1; dcc->meta_pitch = afb->base.pitches[1]; dcc->independent_64b_blks = independent_64b_blks; - if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) { + if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) { if (independent_64b_blks && independent_128b_blks) dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl; else if (independent_128b_blks) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index f1972154a594..1d717c75e171 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -1363,6 +1363,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) #define AMD_FMT_MOD_TILE_VER_GFX9 1 #define AMD_FMT_MOD_TILE_VER_GFX10 2 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 +#define AMD_FMT_MOD_TILE_VER_GFX11 4 /* * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical @@ -1378,6 +1379,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 +#define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31 #define AMD_FMT_MOD_DCC_BLOCK_64B 0 #define AMD_FMT_MOD_DCC_BLOCK_128B 1 -- cgit v1.2.3 From e42ce1366ae806ba2c1f884997703be68df428f4 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Tue, 1 Mar 2022 16:15:03 -0500 Subject: drm/amd/display: Fix USBC link creation [Description] Add USBC connector ID to align with new VBIOS parsing. Add seperate DCN321 link encoder due to different PHY version affecting DP ALT related registers. Signed-off-by: Dillon Varone Acked-by: Jerry Zuo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 1 + .../gpu/drm/amd/display/dc/bios/command_table.c | 4 +- .../drm/amd/display/dc/dcn10/dcn10_link_encoder.h | 6 + .../amd/display/dc/dcn10/dcn10_stream_encoder.h | 3 + .../amd/display/dc/dcn32/dcn32_dio_link_encoder.c | 15 +- .../amd/display/dc/dcn32/dcn32_dio_link_encoder.h | 20 ++- drivers/gpu/drm/amd/display/dc/dcn321/Makefile | 2 +- .../display/dc/dcn321/dcn321_dio_link_encoder.c | 199 +++++++++++++++++++++ .../display/dc/dcn321/dcn321_dio_link_encoder.h | 42 +++++ .../drm/amd/display/dc/dcn321/dcn321_resource.c | 3 +- .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 2 + .../drm/amd/display/include/bios_parser_types.h | 3 +- 12 files changed, 292 insertions(+), 8 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c create mode 100644 drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.h diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c index bbc0a5769e88..3540b46765fb 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c @@ -3224,6 +3224,7 @@ static enum bp_result update_slot_layout_info_v2( break; case CONNECTOR_ID_DISPLAY_PORT: + case CONNECTOR_ID_USBC: if (record->mini_type == MINI_TYPE_NORMAL) { slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DP; slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DP; diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c index 32efa92422e8..818a529cacc3 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c @@ -522,8 +522,8 @@ static enum bp_result transmitter_control_v2( */ params.acConfig.ucEncoderSel = 1; - if (CONNECTOR_ID_DISPLAY_PORT == connector_id - || CONNECTOR_ID_USBC == connector_id) + if (CONNECTOR_ID_DISPLAY_PORT == connector_id || + CONNECTOR_ID_USBC == connector_id) /* Bit4: DP connector flag * =0 connector is none-DP connector * =1 connector is DP connector diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h index 663aac0a164a..773380ef4997 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h @@ -167,6 +167,7 @@ struct dcn10_link_enc_registers { uint32_t DIO_LINKD_CNTL; uint32_t DIO_LINKE_CNTL; uint32_t DIO_LINKF_CNTL; + uint32_t DIG_FIFO_CTRL0; }; #define LE_SF(reg_name, field_name, post_fix)\ @@ -472,11 +473,15 @@ struct dcn10_link_enc_registers { type HPO_DP_ENC_SEL;\ type HPO_HDMI_ENC_SEL +#define DCN32_LINK_ENCODER_REG_FIELD_LIST(type) \ + type DIG_FIFO_OUTPUT_PIXEL_MODE + struct dcn10_link_enc_shift { DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t); DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t); DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t); DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t); + DCN32_LINK_ENCODER_REG_FIELD_LIST(uint8_t); }; struct dcn10_link_enc_mask { @@ -484,6 +489,7 @@ struct dcn10_link_enc_mask { DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t); DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t); DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t); + DCN32_LINK_ENCODER_REG_FIELD_LIST(uint32_t); }; struct dcn10_link_encoder { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h index 02c77076fa49..dd9bb86da4de 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h @@ -659,6 +659,9 @@ void enc1_stream_encoder_send_immediate_sdp_message( void enc1_stream_encoder_stop_dp_info_packets( struct stream_encoder *enc); +void enc1_stream_encoder_reset_fifo( + struct stream_encoder *enc); + void enc1_stream_encoder_dp_blank( struct dc_link *link, struct stream_encoder *enc); diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c index 7170a9aa82a4..d6855d4f749b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c @@ -33,6 +33,7 @@ #include "stream_encoder.h" #include "i2caux_interface.h" #include "dc_bios_types.h" +#include "link_enc_cfg.h" #include "gpio_service_interface.h" @@ -125,7 +126,7 @@ bool dcn32_link_encoder_is_in_alt_mode(struct link_encoder *enc) if (enc->features.flags.bits.DP_IS_USB_C) { /* if value == 1 alt mode is disabled, otherwise it is enabled */ - //REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable); + REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable); is_usb_c_alt_mode = (dp_alt_mode_disable == 0); } @@ -142,13 +143,19 @@ void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc, /* in usb c dp2 mode, max lane count is 2 */ if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) { -// REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode); + REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode); if (!is_in_usb_c_dp4_mode) link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); } } +void enc32_set_dig_output_mode(struct link_encoder *enc, uint8_t pix_per_container) +{ + struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); + REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container); +} + static const struct link_encoder_funcs dcn32_link_enc_funcs = { .read_state = link_enc2_read_state, .validate_output_with_stream = @@ -179,6 +186,7 @@ static const struct link_encoder_funcs dcn32_link_enc_funcs = { .is_in_alt_mode = dcn32_link_encoder_is_in_alt_mode, .get_max_link_cap = dcn32_link_encoder_get_max_link_cap, .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux, + .set_dig_output_mode = enc32_set_dig_output_mode, }; void dcn32_link_encoder_construct( @@ -203,6 +211,9 @@ void dcn32_link_encoder_construct( enc10->base.hpd_source = init_data->hpd_source; enc10->base.connector = init_data->connector; + if (enc10->base.connector.id == CONNECTOR_ID_USBC) + enc10->base.features.flags.bits.DP_IS_USB_C = 1; + enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; enc10->base.features = *enc_features; diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h index e880b76d5f25..749a1e8cb811 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h @@ -26,7 +26,15 @@ #ifndef __DC_LINK_ENCODER__DCN32_H__ #define __DC_LINK_ENCODER__DCN32_H__ -#include "dcn30/dcn30_dio_link_encoder.h" +#include "dcn31/dcn31_dio_link_encoder.h" + +#define LE_DCN32_REG_LIST(id)\ + LE_DCN31_REG_LIST(id),\ + SRI(DIG_FIFO_CTRL0, DIG, id) + +#define LINK_ENCODER_MASK_SH_LIST_DCN32(mask_sh) \ + LINK_ENCODER_MASK_SH_LIST_DCN31(mask_sh),\ + LE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, mask_sh) void dcn32_link_encoder_construct( struct dcn20_link_encoder *enc20, @@ -38,5 +46,15 @@ void dcn32_link_encoder_construct( const struct dcn10_link_enc_shift *link_shift, const struct dcn10_link_enc_mask *link_mask); +void enc32_hw_init(struct link_encoder *enc); + +void dcn32_link_encoder_enable_dp_output( + struct link_encoder *enc, + const struct dc_link_settings *link_settings, + enum clock_source_id clock_source); + +void enc32_set_dig_output_mode( + struct link_encoder *enc, + uint8_t pix_per_container); #endif /* __DC_LINK_ENCODER__DCN32_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/Makefile b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile index 99515cb3ed31..9b61d08700ca 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn321/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile @@ -10,7 +10,7 @@ # # Makefile for dcn321. -DCN321 = dcn321_resource.o +DCN321 = dcn321_resource.o dcn321_dio_link_encoder.o CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o := -mhard-float -msse diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c new file mode 100644 index 000000000000..49682a31ecbd --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c @@ -0,0 +1,199 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + + +#include "reg_helper.h" + +#include "core_types.h" +#include "link_encoder.h" +#include "dcn321_dio_link_encoder.h" +#include "dcn31/dcn31_dio_link_encoder.h" +#include "stream_encoder.h" +#include "i2caux_interface.h" +#include "dc_bios_types.h" + +#include "gpio_service_interface.h" + +#ifndef MIN +#define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) +#endif + +#define CTX \ + enc10->base.ctx +#define DC_LOGGER \ + enc10->base.ctx->logger + +#define REG(reg)\ + (enc10->link_regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + enc10->link_shift->field_name, enc10->link_mask->field_name + +#define AUX_REG(reg)\ + (enc10->aux_regs->reg) + +#define AUX_REG_READ(reg_name) \ + dm_read_reg(CTX, AUX_REG(reg_name)) + +#define AUX_REG_WRITE(reg_name, val) \ + dm_write_reg(CTX, AUX_REG(reg_name), val) + +static const struct link_encoder_funcs dcn321_link_enc_funcs = { + .read_state = link_enc2_read_state, + .validate_output_with_stream = + dcn30_link_encoder_validate_output_with_stream, + .hw_init = enc32_hw_init, + .setup = dcn10_link_encoder_setup, + .enable_tmds_output = dcn10_link_encoder_enable_tmds_output, + .enable_dp_output = dcn32_link_encoder_enable_dp_output, + .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output, + .disable_output = dcn10_link_encoder_disable_output, + .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings, + .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern, + .update_mst_stream_allocation_table = + dcn10_link_encoder_update_mst_stream_allocation_table, + .psr_program_dp_dphy_fast_training = + dcn10_psr_program_dp_dphy_fast_training, + .psr_program_secondary_packet = dcn10_psr_program_secondary_packet, + .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe, + .enable_hpd = dcn10_link_encoder_enable_hpd, + .disable_hpd = dcn10_link_encoder_disable_hpd, + .is_dig_enabled = dcn10_is_dig_enabled, + .destroy = dcn10_link_encoder_destroy, + .fec_set_enable = enc2_fec_set_enable, + .fec_set_ready = enc2_fec_set_ready, + .fec_is_active = enc2_fec_is_active, + .get_dig_frontend = dcn10_get_dig_frontend, + .get_dig_mode = dcn10_get_dig_mode, + .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode, + .get_max_link_cap = dcn20_link_encoder_get_max_link_cap, + .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux, + .set_dig_output_mode = enc32_set_dig_output_mode, +}; + +void dcn321_link_encoder_construct( + struct dcn20_link_encoder *enc20, + const struct encoder_init_data *init_data, + const struct encoder_feature_support *enc_features, + const struct dcn10_link_enc_registers *link_regs, + const struct dcn10_link_enc_aux_registers *aux_regs, + const struct dcn10_link_enc_hpd_registers *hpd_regs, + const struct dcn10_link_enc_shift *link_shift, + const struct dcn10_link_enc_mask *link_mask) +{ + struct bp_connector_speed_cap_info bp_cap_info = {0}; + const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; + enum bp_result result = BP_RESULT_OK; + struct dcn10_link_encoder *enc10 = &enc20->enc10; + + enc10->base.funcs = &dcn321_link_enc_funcs; + enc10->base.ctx = init_data->ctx; + enc10->base.id = init_data->encoder; + + enc10->base.hpd_source = init_data->hpd_source; + enc10->base.connector = init_data->connector; + + if (enc10->base.connector.id == CONNECTOR_ID_USBC) + enc10->base.features.flags.bits.DP_IS_USB_C = 1; + + enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; + + enc10->base.features = *enc_features; + + enc10->base.transmitter = init_data->transmitter; + + /* set the flag to indicate whether driver poll the I2C data pin + * while doing the DP sink detect + */ + +/* if (dal_adapter_service_is_feature_supported(as, + FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) + enc10->base.features.flags.bits. + DP_SINK_DETECT_POLL_DATA_PIN = true;*/ + + enc10->base.output_signals = + SIGNAL_TYPE_DVI_SINGLE_LINK | + SIGNAL_TYPE_DVI_DUAL_LINK | + SIGNAL_TYPE_LVDS | + SIGNAL_TYPE_DISPLAY_PORT | + SIGNAL_TYPE_DISPLAY_PORT_MST | + SIGNAL_TYPE_EDP | + SIGNAL_TYPE_HDMI_TYPE_A; + + enc10->link_regs = link_regs; + enc10->aux_regs = aux_regs; + enc10->hpd_regs = hpd_regs; + enc10->link_shift = link_shift; + enc10->link_mask = link_mask; + + switch (enc10->base.transmitter) { + case TRANSMITTER_UNIPHY_A: + enc10->base.preferred_engine = ENGINE_ID_DIGA; + break; + case TRANSMITTER_UNIPHY_B: + enc10->base.preferred_engine = ENGINE_ID_DIGB; + break; + case TRANSMITTER_UNIPHY_C: + enc10->base.preferred_engine = ENGINE_ID_DIGC; + break; + case TRANSMITTER_UNIPHY_D: + enc10->base.preferred_engine = ENGINE_ID_DIGD; + break; + case TRANSMITTER_UNIPHY_E: + enc10->base.preferred_engine = ENGINE_ID_DIGE; + break; + default: + ASSERT_CRITICAL(false); + enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; + } + + /* default to one to mirror Windows behavior */ + enc10->base.features.flags.bits.HDMI_6GB_EN = 1; + + if (bp_funcs->get_connector_speed_cap_info) + result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios, + enc10->base.connector, &bp_cap_info); + + /* Override features with DCE-specific values */ + if (result == BP_RESULT_OK) { + enc10->base.features.flags.bits.IS_HBR2_CAPABLE = + bp_cap_info.DP_HBR2_EN; + enc10->base.features.flags.bits.IS_HBR3_CAPABLE = + bp_cap_info.DP_HBR3_EN; + enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; + enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1; + enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN; + enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN; + enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN; + } else { + DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", + __func__, + result); + } + if (enc10->base.ctx->dc->debug.hdmi20_disable) { + enc10->base.features.flags.bits.HDMI_6GB_EN = 0; + } +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.h new file mode 100644 index 000000000000..2205f39b0a24 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.h @@ -0,0 +1,42 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_LINK_ENCODER__DCN321_H__ +#define __DC_LINK_ENCODER__DCN321_H__ + +#include "dcn32/dcn32_dio_link_encoder.h" + +void dcn321_link_encoder_construct( + struct dcn20_link_encoder *enc20, + const struct encoder_init_data *init_data, + const struct encoder_feature_support *enc_features, + const struct dcn10_link_enc_registers *link_regs, + const struct dcn10_link_enc_aux_registers *aux_regs, + const struct dcn10_link_enc_hpd_registers *hpd_regs, + const struct dcn10_link_enc_shift *link_shift, + const struct dcn10_link_enc_mask *link_mask); + + +#endif /* __DC_LINK_ENCODER__DCN321_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c index 6bc477a212b0..4db2cdf7c9e5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c @@ -62,6 +62,7 @@ #include "dcn31/dcn31_apg.h" #include "dcn31/dcn31_dio_link_encoder.h" #include "dcn32/dcn32_dio_link_encoder.h" +#include "dcn321_dio_link_encoder.h" #include "dce/dce_clock_source.h" #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" @@ -1253,7 +1254,7 @@ static struct link_encoder *dcn321_link_encoder_create( if (!enc20) return NULL; - dcn32_link_encoder_construct(enc20, + dcn321_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, &link_enc_regs[enc_init_data->transmitter], diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 2013a70603ae..d8433c679201 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -200,6 +200,8 @@ struct link_encoder_funcs { struct link_encoder *enc, enum encoder_type_select sel, uint32_t hpo_inst); + void (*set_dig_output_mode)( + struct link_encoder *enc, uint8_t pix_per_container); }; /* diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h index 83058bcbb2e8..812377d9e48f 100644 --- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h +++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h @@ -342,7 +342,8 @@ struct bp_connector_speed_cap_info { uint32_t DP_UHBR10_EN:1; uint32_t DP_UHBR13_5_EN:1; uint32_t DP_UHBR20_EN:1; - uint32_t RESERVED:29; + uint32_t DP_IS_USB_C:1; + uint32_t RESERVED:28; }; #endif /*__DAL_BIOS_PARSER_TYPES_H__ */ -- cgit v1.2.3 From 3dc35cf8789ac93d656f255539f9b37c5051ebf6 Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Mon, 28 Feb 2022 17:24:00 -0500 Subject: drm/amd/display: Add missing instance for clock source register [Description] Need to add inst 5 for clk_src_regs because there are 5 PHY instances in DCN32 & DCN321. Signed-off-by: Alvin Lee Acked-by: Jerry Zuo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 3 ++- drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c index 7ac6428aae52..ca9da3d4b1b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c @@ -330,7 +330,8 @@ static const struct dce110_clk_src_regs clk_src_regs[] = { clk_src_regs(0, A), clk_src_regs(1, B), clk_src_regs(2, C), - clk_src_regs(3, D) + clk_src_regs(3, D), + clk_src_regs(4, E) }; static const struct dce110_clk_src_shift cs_shift = { diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c index 4db2cdf7c9e5..28e4d7904d54 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c @@ -333,7 +333,8 @@ static const struct dce110_clk_src_regs clk_src_regs[] = { clk_src_regs(0, A), clk_src_regs(1, B), clk_src_regs(2, C), - clk_src_regs(3, D) + clk_src_regs(3, D), + clk_src_regs(4, E) }; static const struct dce110_clk_src_shift cs_shift = { -- cgit v1.2.3 From 2cb6915dcf70a2bf7ee10fcf3f56b083beec1086 Mon Sep 17 00:00:00 2001 From: Eric Bernstein Date: Thu, 3 Mar 2022 14:11:46 -0500 Subject: drm/amd/display: Use DTBCLK for valid pixel clock Use DTBCLK for valid pixel clock generation Signed-off-by: Eric Bernstein Acked-by: Jerry Zuo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 20 ++++++++++++++------ drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 17 +++++++++++++++++ 2 files changed, 31 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c index 5609ac6d6040..b78775e8c13c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c @@ -42,12 +42,6 @@ #define DC_LOGGER \ dccg->ctx->logger -enum pixel_rate_div { - PIXEL_RATE_DIV_BY_1 = 0, - PIXEL_RATE_DIV_BY_2 = 1, - PIXEL_RATE_DIV_BY_4 = 3 -}; - static void dccg32_set_pixel_rate_div( struct dccg *dccg, uint32_t otg_inst, @@ -183,6 +177,19 @@ void dccg32_set_dtbclk_dto( } } +void dccg32_set_valid_pixel_rate( + struct dccg *dccg, + int otg_inst, + int pixclk_khz) +{ + struct dtbclk_dto_params dto_params = {0}; + + dto_params.otg_inst = otg_inst; + dto_params.pixclk_khz = pixclk_khz; + + dccg32_set_dtbclk_dto(dccg, &dto_params); +} + static void dccg32_get_dccg_ref_freq(struct dccg *dccg, unsigned int xtalin_freq_inKhz, unsigned int *dccg_ref_freq_inKhz) @@ -260,6 +267,7 @@ static const struct dccg_funcs dccg32_funcs = { .disable_symclk32_le = dccg31_disable_symclk32_le, .set_physymclk = dccg31_set_physymclk, .set_dtbclk_dto = dccg32_set_dtbclk_dto, + .set_valid_pixel_rate = dccg32_set_valid_pixel_rate, .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto, .otg_add_pixel = dccg32_otg_add_pixel, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index b5acc6b9f3c9..8b450a7274ae 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -56,6 +56,12 @@ enum dentist_dispclk_change_mode { DISPCLK_CHANGE_MODE_RAMPING, }; +enum pixel_rate_div { + PIXEL_RATE_DIV_BY_1 = 0, + PIXEL_RATE_DIV_BY_2 = 1, + PIXEL_RATE_DIV_BY_4 = 3 +}; + struct dccg { struct dc_context *ctx; const struct dccg_funcs *funcs; @@ -139,6 +145,17 @@ struct dccg_funcs { struct dccg *dccg, int inst); +void (*set_pixel_rate_div)( + struct dccg *dccg, + uint32_t otg_inst, + enum pixel_rate_div k1, + enum pixel_rate_div k2); + +void (*set_valid_pixel_rate)( + struct dccg *dccg, + int otg_inst, + int pixclk_khz); + }; #endif //__DAL_DCCG_H__ -- cgit v1.2.3 From 542a0f2ef9ea2ccfadf2b8a3b53368c61fc97a0f Mon Sep 17 00:00:00 2001 From: Huang Rui Date: Fri, 20 May 2022 11:04:04 +0800 Subject: drm/amdgpu: introduce two work mode for imu IMU has two work mode such as debug mode and mission mode. Current GC v11_0_0 is using the debug mode. Acked-by: Alex Deucher Signed-off-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h | 6 ++++++ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 1 + drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 30 +++++++++++++++++------------- 3 files changed, 24 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h index 56cf127cdf93..cfc4a92837f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h @@ -24,6 +24,11 @@ #ifndef __AMDGPU_IMU_H__ #define __AMDGPU_IMU_H__ +enum imu_work_mode { + DEBUG_MODE, + MISSION_MODE +}; + struct amdgpu_imu_funcs { int (*init_microcode)(struct amdgpu_device *adev); int (*load_microcode)(struct amdgpu_device *adev); @@ -46,6 +51,7 @@ struct imu_rlc_ram_golden { struct amdgpu_imu { const struct amdgpu_imu_funcs *funcs; + enum imu_work_mode mode; }; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 10e180b2d0f5..abe22749cccc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6292,6 +6292,7 @@ static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) { + adev->gfx.imu.mode = DEBUG_MODE; adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; } diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c index d63d3f2b8a16..05d2b93a534c 100644 --- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c @@ -125,9 +125,11 @@ static void imu_v11_0_setup(struct amdgpu_device *adev) WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff); WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff); - imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16); - imu_reg_val |= 0x1; - WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val); + if (adev->gfx.imu.mode == DEBUG_MODE) { + imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16); + imu_reg_val |= 0x1; + WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val); + } //disble imu Rtavfs, SmsRepair, DfllBTC, and ClkB imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10); @@ -144,16 +146,18 @@ static int imu_v11_0_start(struct amdgpu_device *adev) imu_reg_val &= 0xfffffffe; WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val); - for (i = 0; i < adev->usec_timeout; i++) { - imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); - if ((imu_reg_val & 0x1f) == 0x1f) - break; - udelay(1); - } - - if (i >= adev->usec_timeout) { - dev_err(adev->dev, "init imu: IMU start timeout\n"); - return -ETIMEDOUT; + if (adev->gfx.imu.mode == DEBUG_MODE) { + for (i = 0; i < adev->usec_timeout; i++) { + imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); + if ((imu_reg_val & 0x1f) == 0x1f) + break; + udelay(1); + } + + if (i >= adev->usec_timeout) { + dev_err(adev->dev, "init imu: IMU start timeout\n"); + return -ETIMEDOUT; + } } return 0; -- cgit v1.2.3 From a839a73b18157fe30eb4acd2a1f1ffdb890762ff Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Tue, 8 Mar 2022 15:32:06 -0500 Subject: drm/amd/display: Add guard for FCLK pstate message to PMFW for DCN321 [WHY?] DCN321 does not support FCLK DPM, and thus it should not send messages to PMFW regarding it. Signed-off-by: Dillon Varone Acked-by: Jerry Zuo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 419cc83b3d21..4ff12b816614 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -346,7 +346,8 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); } - if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) { + if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) && + clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21) { clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support; /* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */ -- cgit v1.2.3 From 9761843250f1367043ae2a483461af287aecc879 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Tue, 8 Mar 2022 18:45:08 -0500 Subject: drm/amd/display: Various DML fixes to enable higher timings Fixes to enable higher rate timings for DCN3.2.x. Signed-off-by: Dillon Varone Signed-off-by: Chaitanya Dhere Signed-off-by: Nevenko Stupar Acked-by: Jerry Zuo Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c | 4 +-- .../gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 33 ++++++++++++++-------- .../gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 27 ++---------------- 3 files changed, 26 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c index 27813374f2bb..99eb239bbc7b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c @@ -65,7 +65,7 @@ static void dcn32_init_crb(struct hubbub *hubbub) REG_SET_2(COMPBUF_RESERVED_SPACE, 0, COMPBUF_RESERVED_SPACE_64B, hubbub2->pixel_chunk_size / 32, COMPBUF_RESERVED_SPACE_ZS, hubbub2->pixel_chunk_size / 128); - REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x17F); + REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x47F); } static void dcn32_program_det_size(struct hubbub *hubbub, int hubp_inst, unsigned int det_buffer_size_in_kbyte) @@ -119,8 +119,8 @@ static void dcn32_program_compbuf_size(struct hubbub *hubbub, unsigned int compb ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size + hubbub2->det3_size + compbuf_size_segments <= hubbub2->crb_size_segs); REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_segments); - REG_WAIT(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, compbuf_size_segments, 1, 100); hubbub2->compbuf_size_segments = compbuf_size_segments; + ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &compbuf_size_segments) && !compbuf_size_segments); } } diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c index ca9da3d4b1b5..8a10a7a4c3e1 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c @@ -3015,13 +3015,30 @@ int dcn32_populate_dml_pipes_from_context( } pipe_cnt++; } - context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE; - if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { - if (!is_dual_plane(pipe->plane_state->format)) { - context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; - pipes[0].pipe.src.unbounded_req_mode = true; + switch (pipe_cnt) { + case 1: + context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_MAX_DET_SIZE; + if (pipe->plane_state && !dc->debug.disable_z9_mpc) { + if (!is_dual_plane(pipe->plane_state->format)) { + context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE; + pipes[0].pipe.src.unbounded_req_mode = true; + if (pipe->plane_state->src_rect.width >= 5120 && + pipe->plane_state->src_rect.height >= 2880) + context->bw_ctx.dml.ip.det_buffer_size_kbytes = 320; // 5K or higher + } } + break; + case 2: + context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_MAX_DET_SIZE / 2; // 576 KB (9 segments) + break; + case 3: + context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_MAX_DET_SIZE / 3; // 384 KB (6 segments) + break; + case 4: + default: + context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE; // 256 KB (4 segments) + break; } return pipe_cnt; @@ -3283,7 +3300,6 @@ void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display * possible with firmware driven vertical blank stretching. */ // context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching; - context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported) @@ -3339,11 +3355,6 @@ void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display if (!context->res_ctx.pipe_ctx[i].stream) continue; - /* cstate disabled on 201 */ -// if (dc->ctx->dce_version == DCN_VERSION_2_01) -// cstate_en = false; - - context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml, &context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes, pipe_cnt, pipe_idx); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index 8d4c74b0fc90..eeec40f6fd0a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -1018,31 +1018,8 @@ int dcn20_populate_dml_pipes_from_context( pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2; pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; pipes[pipe_cnt].dout.dp_lanes = 4; - if (res_ctx->pipe_ctx[i].stream->link) { - switch (res_ctx->pipe_ctx[i].stream->link->cur_link_settings.link_rate) { - case LINK_RATE_HIGH: - pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr; - break; - case LINK_RATE_HIGH2: - pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr2; - break; - case LINK_RATE_HIGH3: - pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr3; - break; - case LINK_RATE_UHBR10: - pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_uhbr10; - break; - case LINK_RATE_UHBR13_5: - pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_uhbr13p5; - break; - case LINK_RATE_UHBR20: - pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_uhbr20; - break; - default: - pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na; - break; - } - } + if (res_ctx->pipe_ctx[i].stream->link) + pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na; pipes[pipe_cnt].dout.is_virtual = 0; pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min; pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max; -- cgit v1.2.3 From e06c5f59ffe1006f1c6f533113b72ad48a6d4564 Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Mon, 14 Mar 2022 19:54:53 -0400 Subject: drm/amd/display: Implement WM table transfer for DCN32/DCN321 Add support for watermark table transfers. Signed-off-by: Alvin Lee Acked-by: Jerry Zuo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 4ff12b816614..93fbecbc8065 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -444,6 +444,7 @@ void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr) } static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base) { + unsigned int i; struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table; @@ -455,6 +456,12 @@ static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base) memset(table, 0, sizeof(*table)); + /* collect valid ranges, place in pmfw table */ + for (i = 0; i < WM_SET_COUNT; i++) + if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) { + table->Watermarks.WatermarkRow[i].WmSetting = i; + table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type; + } dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32); dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF); dcn32_smu_transfer_wm_table_dram_2_smu(clk_mgr); -- cgit v1.2.3 From b3f2c796634613bca511266b37084560f36b67c1 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Thu, 24 Mar 2022 14:59:09 -0400 Subject: drm/amd/display: add missing interrupt handlers for DCN32/DCN321 Signed-off-by: Aurabindo Pillai Acked-by: Jerry Zuo Signed-off-by: Alex Deucher --- .../amd/display/dc/irq/dcn32/irq_service_dcn32.c | 65 +++++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c index 3f9d6531c563..3a213ca2f077 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c @@ -54,6 +54,18 @@ enum dc_irq_source to_dal_irq_source_dcn32( return DC_IRQ_SOURCE_VBLANK5; case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: return DC_IRQ_SOURCE_VBLANK6; + case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC1_VLINE0; + case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC2_VLINE0; + case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC3_VLINE0; + case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC4_VLINE0; + case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC5_VLINE0; + case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC6_VLINE0; case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: return DC_IRQ_SOURCE_PFLIP1; case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: @@ -78,7 +90,8 @@ enum dc_irq_source to_dal_irq_source_dcn32( return DC_IRQ_SOURCE_VUPDATE5; case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: return DC_IRQ_SOURCE_VUPDATE6; - + case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT: + return DC_IRQ_SOURCE_DMCUB_OUTBOX; case DCN_1_0__SRCID__DC_HPD1_INT: /* generic src_id for all HPD and HPDRX interrupts */ switch (ext_id) { @@ -168,6 +181,16 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = { .ack = NULL }; +static const struct irq_source_info_funcs outbox_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static const struct irq_source_info_funcs vline0_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + #undef BASE_INNER #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg @@ -179,6 +202,10 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = { BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg ## block ## id ## _ ## reg_name +#define SRI_DMUB(reg_name)\ + BASE(reg ## reg_name ## _BASE_IDX) + \ + reg ## reg_name + #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ .enable_reg = SRI(reg1, block, reg_num),\ .enable_mask = \ @@ -193,6 +220,20 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = { .ack_value = \ block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ +#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ + .enable_reg = SRI_DMUB(reg1),\ + .enable_mask = \ + reg1 ## __ ## mask1 ## _MASK,\ + .enable_value = {\ + reg1 ## __ ## mask1 ## _MASK,\ + ~reg1 ## __ ## mask1 ## _MASK \ + },\ + .ack_reg = SRI_DMUB(reg2),\ + .ack_mask = \ + reg2 ## __ ## mask2 ## _MASK,\ + .ack_value = \ + reg2 ## __ ## mask2 ## _MASK \ + #define hpd_int_entry(reg_num)\ [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ IRQ_REG_ENTRY(HPD, reg_num,\ @@ -237,6 +278,21 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = { .funcs = &vblank_irq_info_funcs\ } +#define vline0_int_entry(reg_num)\ + [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\ + OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\ + .funcs = &vline0_irq_info_funcs\ + } +#define dmub_outbox_int_entry()\ + [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\ + IRQ_REG_ENTRY_DMUB(\ + DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\ + DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\ + .funcs = &outbox_irq_info_funcs\ + } + #define dummy_irq_entry() \ {\ .funcs = &dummy_irq_info_funcs\ @@ -339,6 +395,13 @@ irq_source_info_dcn32[DAL_IRQ_SOURCES_NUMBER] = { vblank_int_entry(1), vblank_int_entry(2), vblank_int_entry(3), + vline0_int_entry(0), + vline0_int_entry(1), + vline0_int_entry(2), + vline0_int_entry(3), + [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(), + [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(), + dmub_outbox_int_entry(), }; static const struct irq_service_funcs irq_service_funcs_dcn32 = { -- cgit v1.2.3 From 6a640b95b061fe340214ebd4638974b8b6f08efe Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Thu, 24 Mar 2022 15:42:17 -0400 Subject: drm/amd/display: disable idle optimizations Disable idle optimizations until SMU can handle them to prevent DMUB timeout and subsequent system freeze Signed-off-by: Aurabindo Pillai Acked-by: Jerry Zuo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c index 8a10a7a4c3e1..64d1a6bf0683 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c @@ -976,6 +976,7 @@ static const struct dc_debug_options debug_defaults_drv = { .timing_trace = false, .clock_trace = true, .disable_pplib_clock_request = false, + .disable_idle_power_optimizations = true, .pipe_split_policy = MPC_SPLIT_DYNAMIC, .force_single_disp_pipe_split = false, .disable_dcc = DCC_ENABLE, -- cgit v1.2.3 From cbd3e8440e2e6a4d83479235c9bf278b89360946 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Fri, 20 May 2022 21:03:09 +0800 Subject: drm/amdgpu: print umc correctable error address Signed-off-by: Stanley.Yang Acked-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 5 +++ drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 50 +++++++++++++++++++++- drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 1 + 3 files changed, 54 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index 28e603243b67..bf5a95104ec1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -333,6 +333,11 @@ struct ecc_info_per_ch { struct umc_ecc_info { struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM]; + + /* Determine smu ecctable whether support + * record correctable error address + */ + int record_ce_addr_supported; }; struct amdgpu_ras { diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c index 606892dbea1c..bf7524f16b66 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c @@ -119,6 +119,24 @@ static void umc_v6_7_ecc_info_query_correctable_error_count(struct amdgpu_device *error_count += 1; umc_v6_7_query_error_status_helper(adev, mc_umc_status, umc_reg_offset); + + if (ras->umc_ecc.record_ce_addr_supported) { + uint64_t err_addr, soc_pa; + uint32_t channel_index = + adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; + + err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_ceumc_addr; + err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); + /* translate umc channel address to soc pa, 3 parts are included */ + soc_pa = ADDR_OF_8KB_BLOCK(err_addr) | + ADDR_OF_256B_BLOCK(channel_index) | + OFFSET_IN_256B_BLOCK(err_addr); + + /* The umc channel bits are not original values, they are hashed */ + SET_CHANNEL_HASH(channel_index, soc_pa); + + dev_info(adev->dev, "Error Address(PA): 0x%llx\n", soc_pa); + } } } @@ -251,7 +269,9 @@ static void umc_v6_7_ecc_info_query_ras_error_address(struct amdgpu_device *adev static void umc_v6_7_query_correctable_error_count(struct amdgpu_device *adev, uint32_t umc_reg_offset, - unsigned long *error_count) + unsigned long *error_count, + uint32_t ch_inst, + uint32_t umc_inst) { uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; uint32_t ecc_err_cnt, ecc_err_cnt_addr; @@ -295,6 +315,31 @@ static void umc_v6_7_query_correctable_error_count(struct amdgpu_device *adev, *error_count += 1; umc_v6_7_query_error_status_helper(adev, mc_umc_status, umc_reg_offset); + + { + uint64_t err_addr, soc_pa; + uint32_t mc_umc_addrt0; + uint32_t channel_index; + + mc_umc_addrt0 = + SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); + + channel_index = + adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; + + err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4); + err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); + + /* translate umc channel address to soc pa, 3 parts are included */ + soc_pa = ADDR_OF_8KB_BLOCK(err_addr) | + ADDR_OF_256B_BLOCK(channel_index) | + OFFSET_IN_256B_BLOCK(err_addr); + + /* The umc channel bits are not original values, they are hashed */ + SET_CHANNEL_HASH(channel_index, soc_pa); + + dev_info(adev->dev, "Error Address(PA): 0x%llx\n", soc_pa); + } } } @@ -395,7 +440,8 @@ static void umc_v6_7_query_ras_error_count(struct amdgpu_device *adev, ch_inst); umc_v6_7_query_correctable_error_count(adev, umc_reg_offset, - &(err_data->ce_count)); + &(err_data->ce_count), + ch_inst, umc_inst); umc_v6_7_querry_uncorrectable_error_count(adev, umc_reg_offset, &(err_data->ue_count)); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index bf124bc98b80..bb3c23821323 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -1884,6 +1884,7 @@ static ssize_t aldebaran_get_ecc_info(struct smu_context *smu, ecc_info_per_channel->mca_ceumc_addr = ecc_table->EccInfo_V2[i].mca_ceumc_addr; } + eccinfo->record_ce_addr_supported = 1; } return ret; -- cgit v1.2.3 From 1908a07cffdfc7c57ba5116418c3f2b5ef05e0f6 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Fri, 1 Apr 2022 16:45:40 -0400 Subject: drm/amd/display: Select correct DTO source [WHY&HOW] Change criteria for setting DTO source value, and always set it regardless of the signal type. Signed-off-by: Dillon Varone Acked-by: Aurabindo Pillai Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 845aa8a1027d..4b57657b5322 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -992,7 +992,18 @@ static bool dcn31_program_pix_clk( REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100); REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000); } +#if defined(CONFIG_DRM_AMD_DC_DCN) + /* Enable DTO */ + if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) + REG_UPDATE_2(PIXEL_RATE_CNTL[inst], + DP_DTO0_ENABLE, 1, + PIPE0_DTO_SRC_SEL, 1); + else + REG_UPDATE(PIXEL_RATE_CNTL[inst], + DP_DTO0_ENABLE, 1); +#else REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); +#endif } else { if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) { unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; @@ -1004,10 +1015,26 @@ static bool dcn31_program_pix_clk( REG_WRITE(MODULO[inst], dp_dto_ref_100hz); /* Enable DTO */ + #if defined(CONFIG_DRM_AMD_DC_DCN) + if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) + REG_UPDATE_2(PIXEL_RATE_CNTL[inst], + DP_DTO0_ENABLE, 1, + PIPE0_DTO_SRC_SEL, 1); + else + REG_UPDATE(PIXEL_RATE_CNTL[inst], + DP_DTO0_ENABLE, 1); + #else REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); + #endif return true; } +#if defined(CONFIG_DRM_AMD_DC_DCN) + if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) + REG_UPDATE(PIXEL_RATE_CNTL[inst], + PIPE0_DTO_SRC_SEL, 0); +#endif + /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ bp_pc_params.controller_id = pix_clk_params->controller_id; bp_pc_params.pll_id = clock_source->id; -- cgit v1.2.3 From 218987fdead218ae0e714cd9059bc9fc480220f9 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Tue, 5 Apr 2022 16:13:45 -0400 Subject: drm/amd/display: use updated clock source init routine [why] Use correct clock source initialization routine for DCN32/321 Signed-off-by: Charlene Liu Acked-by: Aurabindo Pillai Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c index 64d1a6bf0683..7772beadd000 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c @@ -1090,7 +1090,7 @@ static struct clock_source *dcn32_clock_source_create( if (!clk_src) return NULL; - if (dcn3_clk_src_construct(clk_src, ctx, bios, id, + if (dcn31_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { clk_src->base.dp_clk_src = dp_clk_src; return &clk_src->base; diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c index 28e4d7904d54..0b420466b6dd 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c @@ -1088,7 +1088,7 @@ static struct clock_source *dcn321_clock_source_create( if (!clk_src) return NULL; - if (dcn3_clk_src_construct(clk_src, ctx, bios, id, + if (dcn31_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { clk_src->base.dp_clk_src = dp_clk_src; return &clk_src->base; -- cgit v1.2.3 From 9fe5d08fc8230adb64128986ee4af267a54e56dd Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Thu, 14 Apr 2022 16:57:17 -0400 Subject: drm/amd/display: Ensure that DMCUB fw in use is loaded by DC and not VBIOS [Why?] On wake from S3/S4, driver checks if DMUB is initialized. On S4 VBIOS loads DMUB, and driver does not reload as it appears to be initialized already. [How?] Add a check for the DAL_FW bit to ensure that loaded FW is from driver and not VBIOS. Signed-off-by: Dillon Varone Signed-off-by: Fangzhi Zuo Reviewed-by: Aurabindo Pillai Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c index 0a498082ccc6..d298f6016e0b 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c @@ -299,11 +299,13 @@ void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub) { + union dmub_fw_boot_status status; uint32_t is_hw_init; + status.all = REG_READ(DMCUB_SCRATCH0); REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); - return is_hw_init != 0; + return is_hw_init != 0 && status.bits.dal_fw; } bool dmub_dcn32_is_supported(struct dmub_srv *dmub) -- cgit v1.2.3 From 16600b7d66367482dc8526f8bc3a30b32aaef329 Mon Sep 17 00:00:00 2001 From: Huang Rui Date: Fri, 20 May 2022 11:04:05 +0800 Subject: drm/amdgpu: use the callback function for reset status polling on IMU Switch to use the callback function to poll the reset status on IMU. Because it will have different sequency on other ASICs. v2: drop unused variable (Alex) Acked-by: Alex Deucher Signed-off-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h | 1 + drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 37 ++++++++++++++++++++------------- 2 files changed, 24 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h index cfc4a92837f0..484e936812e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h @@ -35,6 +35,7 @@ struct amdgpu_imu_funcs { void (*setup_imu)(struct amdgpu_device *adev); int (*start_imu)(struct amdgpu_device *adev); void (*program_rlc_ram)(struct amdgpu_device *adev); + int (*wait_for_reset_status)(struct amdgpu_device *adev); }; struct imu_rlc_ram_golden { diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c index 05d2b93a534c..fd053158abbd 100644 --- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c @@ -117,6 +117,25 @@ static int imu_v11_0_load_microcode(struct amdgpu_device *adev) return 0; } +static int imu_v11_0_wait_for_reset_status(struct amdgpu_device *adev) +{ + int i, imu_reg_val = 0; + + for (i = 0; i < adev->usec_timeout; i++) { + imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); + if ((imu_reg_val & 0x1f) == 0x1f) + break; + udelay(1); + } + + if (i >= adev->usec_timeout) { + dev_err(adev->dev, "init imu: IMU start timeout\n"); + return -ETIMEDOUT; + } + + return 0; +} + static void imu_v11_0_setup(struct amdgpu_device *adev) { int imu_reg_val; @@ -139,26 +158,15 @@ static void imu_v11_0_setup(struct amdgpu_device *adev) static int imu_v11_0_start(struct amdgpu_device *adev) { - int imu_reg_val, i; + int imu_reg_val; //Start IMU by set GFX_IMU_CORE_CTRL.CRESET = 0 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL); imu_reg_val &= 0xfffffffe; WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val); - if (adev->gfx.imu.mode == DEBUG_MODE) { - for (i = 0; i < adev->usec_timeout; i++) { - imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); - if ((imu_reg_val & 0x1f) == 0x1f) - break; - udelay(1); - } - - if (i >= adev->usec_timeout) { - dev_err(adev->dev, "init imu: IMU start timeout\n"); - return -ETIMEDOUT; - } - } + if (adev->gfx.imu.mode == DEBUG_MODE) + return imu_v11_0_wait_for_reset_status(adev); return 0; } @@ -368,4 +376,5 @@ const struct amdgpu_imu_funcs gfx_v11_0_imu_funcs = { .setup_imu = imu_v11_0_setup, .start_imu = imu_v11_0_start, .program_rlc_ram = imu_v11_0_program_rlc_ram, + .wait_for_reset_status = imu_v11_0_wait_for_reset_status, }; -- cgit v1.2.3 From d57716702deac8e0ec440739eb4cd6eb0872ddd4 Mon Sep 17 00:00:00 2001 From: Huang Rui Date: Thu, 12 May 2022 16:03:34 +0800 Subject: drm/amdgpu: add mmhub v3_0_1 headers Add mmhub v3_0_1 headers, because there are many differeces with v3_0_0. v2: squash in updates (Alex) Signed-off-by: Huang Rui Reviewed-by: Tim Huang Signed-off-by: Alex Deucher --- .../include/asic_reg/mmhub/mmhub_3_0_1_offset.h | 1769 +++++ .../include/asic_reg/mmhub/mmhub_3_0_1_sh_mask.h | 7483 ++++++++++++++++++++ 2 files changed, 9252 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_offset.h new file mode 100644 index 000000000000..6baac6ae2007 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_offset.h @@ -0,0 +1,1769 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _mmhub_3_0_1_OFFSET_HEADER +#define _mmhub_3_0_1_OFFSET_HEADER + + + +// addressBlock: mmhub_dagbdec +// base address: 0x68000 +#define regDAGB0_RDCLI0 0x0000 +#define regDAGB0_RDCLI0_BASE_IDX 1 +#define regDAGB0_RDCLI1 0x0001 +#define regDAGB0_RDCLI1_BASE_IDX 1 +#define regDAGB0_RDCLI2 0x0002 +#define regDAGB0_RDCLI2_BASE_IDX 1 +#define regDAGB0_RDCLI3 0x0003 +#define regDAGB0_RDCLI3_BASE_IDX 1 +#define regDAGB0_RDCLI4 0x0004 +#define regDAGB0_RDCLI4_BASE_IDX 1 +#define regDAGB0_RDCLI5 0x0005 +#define regDAGB0_RDCLI5_BASE_IDX 1 +#define regDAGB0_RDCLI6 0x0006 +#define regDAGB0_RDCLI6_BASE_IDX 1 +#define regDAGB0_RDCLI7 0x0007 +#define regDAGB0_RDCLI7_BASE_IDX 1 +#define regDAGB0_RDCLI8 0x0008 +#define regDAGB0_RDCLI8_BASE_IDX 1 +#define regDAGB0_RDCLI9 0x0009 +#define regDAGB0_RDCLI9_BASE_IDX 1 +#define regDAGB0_RDCLI10 0x000a +#define regDAGB0_RDCLI10_BASE_IDX 1 +#define regDAGB0_RDCLI11 0x000b +#define regDAGB0_RDCLI11_BASE_IDX 1 +#define regDAGB0_RDCLI12 0x000c +#define regDAGB0_RDCLI12_BASE_IDX 1 +#define regDAGB0_RDCLI13 0x000d +#define regDAGB0_RDCLI13_BASE_IDX 1 +#define regDAGB0_RDCLI14 0x000e +#define regDAGB0_RDCLI14_BASE_IDX 1 +#define regDAGB0_RDCLI15 0x000f +#define regDAGB0_RDCLI15_BASE_IDX 1 +#define regDAGB0_RDCLI16 0x0010 +#define regDAGB0_RDCLI16_BASE_IDX 1 +#define regDAGB0_RDCLI17 0x0011 +#define regDAGB0_RDCLI17_BASE_IDX 1 +#define regDAGB0_RDCLI18 0x0012 +#define regDAGB0_RDCLI18_BASE_IDX 1 +#define regDAGB0_RDCLI19 0x0013 +#define regDAGB0_RDCLI19_BASE_IDX 1 +#define regDAGB0_RDCLI20 0x0014 +#define regDAGB0_RDCLI20_BASE_IDX 1 +#define regDAGB0_RDCLI21 0x0015 +#define regDAGB0_RDCLI21_BASE_IDX 1 +#define regDAGB0_RDCLI22 0x0016 +#define regDAGB0_RDCLI22_BASE_IDX 1 +#define regDAGB0_RDCLI23 0x0017 +#define regDAGB0_RDCLI23_BASE_IDX 1 +#define regDAGB0_RDCLI24 0x0018 +#define regDAGB0_RDCLI24_BASE_IDX 1 +#define regDAGB0_RDCLI25 0x0019 +#define regDAGB0_RDCLI25_BASE_IDX 1 +#define regDAGB0_RDCLI26 0x001a +#define regDAGB0_RDCLI26_BASE_IDX 1 +#define regDAGB0_RDCLI27 0x001b +#define regDAGB0_RDCLI27_BASE_IDX 1 +#define regDAGB0_RDCLI28 0x001c +#define regDAGB0_RDCLI28_BASE_IDX 1 +#define regDAGB0_RDCLI29 0x001d +#define regDAGB0_RDCLI29_BASE_IDX 1 +#define regDAGB0_RD_CNTL 0x001e +#define regDAGB0_RD_CNTL_BASE_IDX 1 +#define regDAGB0_RD_IO_CNTL 0x001f +#define regDAGB0_RD_IO_CNTL_BASE_IDX 1 +#define regDAGB0_RD_GMI_CNTL 0x0020 +#define regDAGB0_RD_GMI_CNTL_BASE_IDX 1 +#define regDAGB0_RD_ADDR_DAGB 0x0021 +#define regDAGB0_RD_ADDR_DAGB_BASE_IDX 1 +#define regDAGB0_RD_CGTT_CLK_CTRL 0x0022 +#define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0023 +#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0024 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0025 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x0026 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x0027 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x0028 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 1 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x0029 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 1 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST3 0x002a +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST3_BASE_IDX 1 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER3 0x002b +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER3_BASE_IDX 1 +#define regDAGB0_RD_VC0_CNTL 0x002c +#define regDAGB0_RD_VC0_CNTL_BASE_IDX 1 +#define regDAGB0_RD_VC1_CNTL 0x002d +#define regDAGB0_RD_VC1_CNTL_BASE_IDX 1 +#define regDAGB0_RD_VC2_CNTL 0x002e +#define regDAGB0_RD_VC2_CNTL_BASE_IDX 1 +#define regDAGB0_RD_VC3_CNTL 0x002f +#define regDAGB0_RD_VC3_CNTL_BASE_IDX 1 +#define regDAGB0_RD_VC4_CNTL 0x0030 +#define regDAGB0_RD_VC4_CNTL_BASE_IDX 1 +#define regDAGB0_RD_VC5_CNTL 0x0031 +#define regDAGB0_RD_VC5_CNTL_BASE_IDX 1 +#define regDAGB0_RD_IO_VC_CNTL 0x0032 +#define regDAGB0_RD_IO_VC_CNTL_BASE_IDX 1 +#define regDAGB0_RD_GMI_VC_CNTL 0x0033 +#define regDAGB0_RD_GMI_VC_CNTL_BASE_IDX 1 +#define regDAGB0_RD_CNTL_MISC 0x0034 +#define regDAGB0_RD_CNTL_MISC_BASE_IDX 1 +#define regDAGB0_RD_TLB_CREDIT 0x0035 +#define regDAGB0_RD_TLB_CREDIT_BASE_IDX 1 +#define regDAGB0_RDCLI_ASK_PENDING 0x0036 +#define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX 1 +#define regDAGB0_RDCLI_GO_PENDING 0x0037 +#define regDAGB0_RDCLI_GO_PENDING_BASE_IDX 1 +#define regDAGB0_RDCLI_GBLSEND_PENDING 0x0038 +#define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 1 +#define regDAGB0_RDCLI_TLB_PENDING 0x0039 +#define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX 1 +#define regDAGB0_RDCLI_OARB_PENDING 0x003a +#define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX 1 +#define regDAGB0_RDCLI_ASK2ARB_PENDING 0x003b +#define regDAGB0_RDCLI_ASK2ARB_PENDING_BASE_IDX 1 +#define regDAGB0_RDCLI_ASK2DF_PENDING 0x003c +#define regDAGB0_RDCLI_ASK2DF_PENDING_BASE_IDX 1 +#define regDAGB0_RDCLI_OSD_PENDING 0x003d +#define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX 1 +#define regDAGB0_RDCLI_ASK_OSD_PENDING 0x003e +#define regDAGB0_RDCLI_ASK_OSD_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI0 0x003f +#define regDAGB0_WRCLI0_BASE_IDX 1 +#define regDAGB0_WRCLI1 0x0040 +#define regDAGB0_WRCLI1_BASE_IDX 1 +#define regDAGB0_WRCLI2 0x0041 +#define regDAGB0_WRCLI2_BASE_IDX 1 +#define regDAGB0_WRCLI3 0x0042 +#define regDAGB0_WRCLI3_BASE_IDX 1 +#define regDAGB0_WRCLI4 0x0043 +#define regDAGB0_WRCLI4_BASE_IDX 1 +#define regDAGB0_WRCLI5 0x0044 +#define regDAGB0_WRCLI5_BASE_IDX 1 +#define regDAGB0_WRCLI6 0x0045 +#define regDAGB0_WRCLI6_BASE_IDX 1 +#define regDAGB0_WRCLI7 0x0046 +#define regDAGB0_WRCLI7_BASE_IDX 1 +#define regDAGB0_WRCLI8 0x0047 +#define regDAGB0_WRCLI8_BASE_IDX 1 +#define regDAGB0_WRCLI9 0x0048 +#define regDAGB0_WRCLI9_BASE_IDX 1 +#define regDAGB0_WRCLI10 0x0049 +#define regDAGB0_WRCLI10_BASE_IDX 1 +#define regDAGB0_WRCLI11 0x004a +#define regDAGB0_WRCLI11_BASE_IDX 1 +#define regDAGB0_WRCLI12 0x004b +#define regDAGB0_WRCLI12_BASE_IDX 1 +#define regDAGB0_WRCLI13 0x004c +#define regDAGB0_WRCLI13_BASE_IDX 1 +#define regDAGB0_WRCLI14 0x004d +#define regDAGB0_WRCLI14_BASE_IDX 1 +#define regDAGB0_WRCLI15 0x004e +#define regDAGB0_WRCLI15_BASE_IDX 1 +#define regDAGB0_WRCLI16 0x004f +#define regDAGB0_WRCLI16_BASE_IDX 1 +#define regDAGB0_WRCLI17 0x0050 +#define regDAGB0_WRCLI17_BASE_IDX 1 +#define regDAGB0_WRCLI18 0x0051 +#define regDAGB0_WRCLI18_BASE_IDX 1 +#define regDAGB0_WRCLI19 0x0052 +#define regDAGB0_WRCLI19_BASE_IDX 1 +#define regDAGB0_WRCLI20 0x0053 +#define regDAGB0_WRCLI20_BASE_IDX 1 +#define regDAGB0_WRCLI21 0x0054 +#define regDAGB0_WRCLI21_BASE_IDX 1 +#define regDAGB0_WRCLI22 0x0055 +#define regDAGB0_WRCLI22_BASE_IDX 1 +#define regDAGB0_WRCLI23 0x0056 +#define regDAGB0_WRCLI23_BASE_IDX 1 +#define regDAGB0_WRCLI24 0x0057 +#define regDAGB0_WRCLI24_BASE_IDX 1 +#define regDAGB0_WRCLI25 0x0058 +#define regDAGB0_WRCLI25_BASE_IDX 1 +#define regDAGB0_WRCLI26 0x0059 +#define regDAGB0_WRCLI26_BASE_IDX 1 +#define regDAGB0_WRCLI27 0x005a +#define regDAGB0_WRCLI27_BASE_IDX 1 +#define regDAGB0_WRCLI28 0x005b +#define regDAGB0_WRCLI28_BASE_IDX 1 +#define regDAGB0_WRCLI29 0x005c +#define regDAGB0_WRCLI29_BASE_IDX 1 +#define regDAGB0_WR_CNTL 0x005d +#define regDAGB0_WR_CNTL_BASE_IDX 1 +#define regDAGB0_WR_IO_CNTL 0x005e +#define regDAGB0_WR_IO_CNTL_BASE_IDX 1 +#define regDAGB0_WR_GMI_CNTL 0x005f +#define regDAGB0_WR_GMI_CNTL_BASE_IDX 1 +#define regDAGB0_WR_ADDR_DAGB 0x0060 +#define regDAGB0_WR_ADDR_DAGB_BASE_IDX 1 +#define regDAGB0_WR_CGTT_CLK_CTRL 0x0061 +#define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0062 +#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0063 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0064 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0065 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0066 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST2 0x0067 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX 1 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0x0068 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 1 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST3 0x0069 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST3_BASE_IDX 1 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER3 0x006a +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER3_BASE_IDX 1 +#define regDAGB0_WR_DATA_DAGB 0x006b +#define regDAGB0_WR_DATA_DAGB_BASE_IDX 1 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST0 0x006c +#define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x006d +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST1 0x006e +#define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x006f +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST2 0x0070 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX 1 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0x0071 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX 1 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST3 0x0072 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST3_BASE_IDX 1 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER3 0x0073 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER3_BASE_IDX 1 +#define regDAGB0_WR_VC0_CNTL 0x0074 +#define regDAGB0_WR_VC0_CNTL_BASE_IDX 1 +#define regDAGB0_WR_VC1_CNTL 0x0075 +#define regDAGB0_WR_VC1_CNTL_BASE_IDX 1 +#define regDAGB0_WR_VC2_CNTL 0x0076 +#define regDAGB0_WR_VC2_CNTL_BASE_IDX 1 +#define regDAGB0_WR_VC3_CNTL 0x0077 +#define regDAGB0_WR_VC3_CNTL_BASE_IDX 1 +#define regDAGB0_WR_VC4_CNTL 0x0078 +#define regDAGB0_WR_VC4_CNTL_BASE_IDX 1 +#define regDAGB0_WR_VC5_CNTL 0x0079 +#define regDAGB0_WR_VC5_CNTL_BASE_IDX 1 +#define regDAGB0_WR_IO_VC_CNTL 0x007a +#define regDAGB0_WR_IO_VC_CNTL_BASE_IDX 1 +#define regDAGB0_WR_GMI_VC_CNTL 0x007b +#define regDAGB0_WR_GMI_VC_CNTL_BASE_IDX 1 +#define regDAGB0_WR_CNTL_MISC 0x007c +#define regDAGB0_WR_CNTL_MISC_BASE_IDX 1 +#define regDAGB0_WR_TLB_CREDIT 0x007d +#define regDAGB0_WR_TLB_CREDIT_BASE_IDX 1 +#define regDAGB0_WR_DATA_CREDIT 0x007e +#define regDAGB0_WR_DATA_CREDIT_BASE_IDX 1 +#define regDAGB0_WR_MISC_CREDIT 0x007f +#define regDAGB0_WR_MISC_CREDIT_BASE_IDX 1 +#define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1 0x0080 +#define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX 1 +#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x0081 +#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 1 +#define regDAGB0_WRCLI_ASK_PENDING 0x0082 +#define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_GO_PENDING 0x0083 +#define regDAGB0_WRCLI_GO_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_GBLSEND_PENDING 0x0084 +#define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_TLB_PENDING 0x0085 +#define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_OARB_PENDING 0x0086 +#define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_ASK2ARB_PENDING 0x0087 +#define regDAGB0_WRCLI_ASK2ARB_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_ASK2DF_PENDING 0x0088 +#define regDAGB0_WRCLI_ASK2DF_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_OSD_PENDING 0x0089 +#define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_ASK_OSD_PENDING 0x008a +#define regDAGB0_WRCLI_ASK_OSD_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_DBUS_ASK_PENDING 0x008b +#define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_DBUS_GO_PENDING 0x008c +#define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x008d +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 1 +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x008e +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 1 +#define regDAGB0_DAGB_DLY 0x008f +#define regDAGB0_DAGB_DLY_BASE_IDX 1 +#define regDAGB0_CNTL_MISC 0x0090 +#define regDAGB0_CNTL_MISC_BASE_IDX 1 +#define regDAGB0_CNTL_MISC2 0x0091 +#define regDAGB0_CNTL_MISC2_BASE_IDX 1 +#define regDAGB0_FIFO_EMPTY 0x0092 +#define regDAGB0_FIFO_EMPTY_BASE_IDX 1 +#define regDAGB0_FIFO_FULL 0x0093 +#define regDAGB0_FIFO_FULL_BASE_IDX 1 +#define regDAGB0_RD_CREDITS_FULL 0x0094 +#define regDAGB0_RD_CREDITS_FULL_BASE_IDX 1 +#define regDAGB0_WR_CREDITS_FULL 0x0095 +#define regDAGB0_WR_CREDITS_FULL_BASE_IDX 1 +#define regDAGB0_PERFCOUNTER_LO 0x0096 +#define regDAGB0_PERFCOUNTER_LO_BASE_IDX 1 +#define regDAGB0_PERFCOUNTER_HI 0x0097 +#define regDAGB0_PERFCOUNTER_HI_BASE_IDX 1 +#define regDAGB0_PERFCOUNTER0_CFG 0x0098 +#define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regDAGB0_PERFCOUNTER1_CFG 0x0099 +#define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regDAGB0_PERFCOUNTER2_CFG 0x009a +#define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regDAGB0_PERFCOUNTER_RSLT_CNTL 0x009b +#define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regDAGB0_L1TLB_REG_RW 0x009c +#define regDAGB0_L1TLB_REG_RW_BASE_IDX 1 +#define regDAGB0_RESERVE1 0x009d +#define regDAGB0_RESERVE1_BASE_IDX 1 +#define regDAGB0_RESERVE2 0x009e +#define regDAGB0_RESERVE2_BASE_IDX 1 +#define regDAGB0_RESERVE3 0x009f +#define regDAGB0_RESERVE3_BASE_IDX 1 +#define regDAGB0_RESERVE4 0x00a0 +#define regDAGB0_RESERVE4_BASE_IDX 1 +#define regDAGB0_SDP_RD_BW_CNTL 0x00a1 +#define regDAGB0_SDP_RD_BW_CNTL_BASE_IDX 1 +#define regDAGB0_SDP_PRIORITY_OVERRIDE 0x00a2 +#define regDAGB0_SDP_PRIORITY_OVERRIDE_BASE_IDX 1 +#define regDAGB0_SDP_RD_PRIORITY 0x00a3 +#define regDAGB0_SDP_RD_PRIORITY_BASE_IDX 1 +#define regDAGB0_SDP_WR_PRIORITY 0x00a4 +#define regDAGB0_SDP_WR_PRIORITY_BASE_IDX 1 +#define regDAGB0_SDP_RD_CLI2SDP_VC_MAP 0x00a5 +#define regDAGB0_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX 1 +#define regDAGB0_SDP_WR_CLI2SDP_VC_MAP 0x00a6 +#define regDAGB0_SDP_WR_CLI2SDP_VC_MAP_BASE_IDX 1 +#define regDAGB0_SDP_ENABLE 0x00a7 +#define regDAGB0_SDP_ENABLE_BASE_IDX 1 +#define regDAGB0_SDP_CREDITS 0x00a8 +#define regDAGB0_SDP_CREDITS_BASE_IDX 1 +#define regDAGB0_SDP_TAG_RESERVE0 0x00a9 +#define regDAGB0_SDP_TAG_RESERVE0_BASE_IDX 1 +#define regDAGB0_SDP_TAG_RESERVE1 0x00aa +#define regDAGB0_SDP_TAG_RESERVE1_BASE_IDX 1 +#define regDAGB0_SDP_VCC_RESERVE0 0x00ab +#define regDAGB0_SDP_VCC_RESERVE0_BASE_IDX 1 +#define regDAGB0_SDP_VCC_RESERVE1 0x00ac +#define regDAGB0_SDP_VCC_RESERVE1_BASE_IDX 1 +#define regDAGB0_SDP_ERR_STATUS 0x00ad +#define regDAGB0_SDP_ERR_STATUS_BASE_IDX 1 +#define regDAGB0_SDP_REQ_CNTL 0x00ae +#define regDAGB0_SDP_REQ_CNTL_BASE_IDX 1 +#define regDAGB0_SDP_MISC_AON 0x00af +#define regDAGB0_SDP_MISC_AON_BASE_IDX 1 +#define regDAGB0_SDP_MISC 0x00b0 +#define regDAGB0_SDP_MISC_BASE_IDX 1 +#define regDAGB0_SDP_MISC2 0x00b1 +#define regDAGB0_SDP_MISC2_BASE_IDX 1 +#define regDAGB0_SDP_VCD_RESERVE0 0x00b3 +#define regDAGB0_SDP_VCD_RESERVE0_BASE_IDX 1 +#define regDAGB0_SDP_VCD_RESERVE1 0x00b4 +#define regDAGB0_SDP_VCD_RESERVE1_BASE_IDX 1 +#define regDAGB0_SDP_ARB_CNTL0 0x00b5 +#define regDAGB0_SDP_ARB_CNTL0_BASE_IDX 1 +#define regDAGB0_SDP_ARB_CNTL1 0x00b6 +#define regDAGB0_SDP_ARB_CNTL1_BASE_IDX 1 +#define regDAGB0_SDP_CGTT_CLK_CTRL 0x00b7 +#define regDAGB0_SDP_CGTT_CLK_CTRL_BASE_IDX 1 +#define regDAGB0_SDP_LATENCY_SAMPLING 0x00b8 +#define regDAGB0_SDP_LATENCY_SAMPLING_BASE_IDX 1 + + +// addressBlock: mmhub_pctldec +// base address: 0x68e00 +#define regPCTL_CTRL 0x0380 +#define regPCTL_CTRL_BASE_IDX 1 +#define regPCTL_MMHUB_DEEPSLEEP_IB 0x0381 +#define regPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX 1 +#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382 +#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 1 +#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x0383 +#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 1 +#define regPCTL_PG_IGNORE_DEEPSLEEP 0x0384 +#define regPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 1 +#define regPCTL_PG_IGNORE_DEEPSLEEP_IB 0x0385 +#define regPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 1 +#define regPCTL_SLICE0_CFG_DAGB_WRBUSY 0x0386 +#define regPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX 1 +#define regPCTL_SLICE0_CFG_DAGB_RDBUSY 0x0387 +#define regPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX 1 +#define regPCTL_SLICE0_CFG_DS_ALLOW 0x0388 +#define regPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX 1 +#define regPCTL_SLICE0_CFG_DS_ALLOW_IB 0x0389 +#define regPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 1 +#define regPCTL_SLICE1_CFG_DAGB_WRBUSY 0x038a +#define regPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX 1 +#define regPCTL_SLICE1_CFG_DAGB_RDBUSY 0x038b +#define regPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX 1 +#define regPCTL_SLICE1_CFG_DS_ALLOW 0x038c +#define regPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX 1 +#define regPCTL_SLICE1_CFG_DS_ALLOW_IB 0x038d +#define regPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 1 +#define regPCTL_UTCL2_MISC 0x038e +#define regPCTL_UTCL2_MISC_BASE_IDX 1 +#define regPCTL_SLICE0_MISC 0x038f +#define regPCTL_SLICE0_MISC_BASE_IDX 1 +#define regPCTL_SLICE1_MISC 0x0390 +#define regPCTL_SLICE1_MISC_BASE_IDX 1 +#define regPCTL_RENG_CTRL 0x0391 +#define regPCTL_RENG_CTRL_BASE_IDX 1 +#define regPCTL_UTCL2_RENG_EXECUTE 0x0392 +#define regPCTL_UTCL2_RENG_EXECUTE_BASE_IDX 1 +#define regPCTL_SLICE0_RENG_EXECUTE 0x0393 +#define regPCTL_SLICE0_RENG_EXECUTE_BASE_IDX 1 +#define regPCTL_SLICE1_RENG_EXECUTE 0x0394 +#define regPCTL_SLICE1_RENG_EXECUTE_BASE_IDX 1 +#define regPCTL_UTCL2_RENG_RAM_INDEX 0x0395 +#define regPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX 1 +#define regPCTL_UTCL2_RENG_RAM_DATA 0x0396 +#define regPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX 1 +#define regPCTL_SLICE0_RENG_RAM_INDEX 0x0397 +#define regPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX 1 +#define regPCTL_SLICE0_RENG_RAM_DATA 0x0398 +#define regPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX 1 +#define regPCTL_SLICE1_RENG_RAM_INDEX 0x0399 +#define regPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX 1 +#define regPCTL_SLICE1_RENG_RAM_DATA 0x039a +#define regPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX 1 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x039b +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x039c +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x039d +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x039e +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x039f +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a0 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a1 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x03a2 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x03a3 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x03a4 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x03a5 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x03a6 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a7 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a8 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x03a9 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x03aa +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x03ab +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x03ac +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x03ad +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03ae +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03af +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 +#define regPCTL_STATUS 0x03b0 +#define regPCTL_STATUS_BASE_IDX 1 +#define regPCTL_PERFCOUNTER_LO 0x03b1 +#define regPCTL_PERFCOUNTER_LO_BASE_IDX 1 +#define regPCTL_PERFCOUNTER_HI 0x03b2 +#define regPCTL_PERFCOUNTER_HI_BASE_IDX 1 +#define regPCTL_PERFCOUNTER0_CFG 0x03b3 +#define regPCTL_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regPCTL_PERFCOUNTER1_CFG 0x03b4 +#define regPCTL_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regPCTL_PERFCOUNTER_RSLT_CNTL 0x03b5 +#define regPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regPCTL_RESERVED_0 0x03b6 +#define regPCTL_RESERVED_0_BASE_IDX 1 +#define regPCTL_RESERVED_1 0x03b7 +#define regPCTL_RESERVED_1_BASE_IDX 1 +#define regPCTL_RESERVED_2 0x03b8 +#define regPCTL_RESERVED_2_BASE_IDX 1 +#define regPCTL_RESERVED_3 0x03b9 +#define regPCTL_RESERVED_3_BASE_IDX 1 + + +// addressBlock: mmhub_l1tlb_mmutcl1pfdec +// base address: 0x69600 +#define regMMMC_VM_MX_L1_TLB0_STATUS 0x0588 +#define regMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLB1_STATUS 0x0589 +#define regMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLB2_STATUS 0x058a +#define regMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLB3_STATUS 0x058b +#define regMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLB4_STATUS 0x058c +#define regMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLB5_STATUS 0x058d +#define regMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLB6_STATUS 0x058e +#define regMMMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLB7_STATUS 0x058f +#define regMMMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 1 + + +// addressBlock: mmhub_l1tlb_mmutcl1pldec +// base address: 0x69670 +#define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG 0x059c +#define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG 0x059d +#define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG 0x059e +#define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG 0x059f +#define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x05a0 +#define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_l1tlb_mmutcl1prdec +// base address: 0x69690 +#define regMMMC_VM_MX_L1_PERFCOUNTER_LO 0x05a4 +#define regMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 1 +#define regMMMC_VM_MX_L1_PERFCOUNTER_HI 0x05a5 +#define regMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: mmhub_l1tlb_mmvmtlspfdec +// base address: 0x696c0 +#define regMMMC_VM_MX_L1_TLS0_CNTL 0x05b0 +#define regMMMC_VM_MX_L1_TLS0_CNTL_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL0 0x05b1 +#define regMMMC_VM_MX_L1_TLS0_CNTL0_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL1 0x05b2 +#define regMMMC_VM_MX_L1_TLS0_CNTL1_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL2 0x05b3 +#define regMMMC_VM_MX_L1_TLS0_CNTL2_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL3 0x05b4 +#define regMMMC_VM_MX_L1_TLS0_CNTL3_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL4 0x05b5 +#define regMMMC_VM_MX_L1_TLS0_CNTL4_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL5 0x05b6 +#define regMMMC_VM_MX_L1_TLS0_CNTL5_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL6 0x05b7 +#define regMMMC_VM_MX_L1_TLS0_CNTL6_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL7 0x05b8 +#define regMMMC_VM_MX_L1_TLS0_CNTL7_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL8 0x05b9 +#define regMMMC_VM_MX_L1_TLS0_CNTL8_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL9 0x05ba +#define regMMMC_VM_MX_L1_TLS0_CNTL9_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL10 0x05bb +#define regMMMC_VM_MX_L1_TLS0_CNTL10_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL11 0x05bc +#define regMMMC_VM_MX_L1_TLS0_CNTL11_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL12 0x05bd +#define regMMMC_VM_MX_L1_TLS0_CNTL12_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL13 0x05be +#define regMMMC_VM_MX_L1_TLS0_CNTL13_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL14 0x05bf +#define regMMMC_VM_MX_L1_TLS0_CNTL14_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL15 0x05c0 +#define regMMMC_VM_MX_L1_TLS0_CNTL15_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL16 0x05c1 +#define regMMMC_VM_MX_L1_TLS0_CNTL16_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL17 0x05c2 +#define regMMMC_VM_MX_L1_TLS0_CNTL17_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL18 0x05c3 +#define regMMMC_VM_MX_L1_TLS0_CNTL18_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL19 0x05c4 +#define regMMMC_VM_MX_L1_TLS0_CNTL19_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL20 0x05c5 +#define regMMMC_VM_MX_L1_TLS0_CNTL20_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL21 0x05c6 +#define regMMMC_VM_MX_L1_TLS0_CNTL21_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL22 0x05c7 +#define regMMMC_VM_MX_L1_TLS0_CNTL22_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL23 0x05c8 +#define regMMMC_VM_MX_L1_TLS0_CNTL23_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL24 0x05c9 +#define regMMMC_VM_MX_L1_TLS0_CNTL24_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL25 0x05ca +#define regMMMC_VM_MX_L1_TLS0_CNTL25_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL26 0x05cb +#define regMMMC_VM_MX_L1_TLS0_CNTL26_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL27 0x05cc +#define regMMMC_VM_MX_L1_TLS0_CNTL27_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL28 0x05cd +#define regMMMC_VM_MX_L1_TLS0_CNTL28_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL29 0x05ce +#define regMMMC_VM_MX_L1_TLS0_CNTL29_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL30 0x05cf +#define regMMMC_VM_MX_L1_TLS0_CNTL30_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL31 0x05d0 +#define regMMMC_VM_MX_L1_TLS0_CNTL31_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL32 0x05d1 +#define regMMMC_VM_MX_L1_TLS0_CNTL32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL33 0x05d2 +#define regMMMC_VM_MX_L1_TLS0_CNTL33_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL34 0x05d3 +#define regMMMC_VM_MX_L1_TLS0_CNTL34_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL35 0x05d4 +#define regMMMC_VM_MX_L1_TLS0_CNTL35_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL36 0x05d5 +#define regMMMC_VM_MX_L1_TLS0_CNTL36_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_CNTL37 0x05d6 +#define regMMMC_VM_MX_L1_TLS0_CNTL37_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32 0x05d7 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32 0x05d8 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32 0x05d9 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32 0x05da +#define regMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32 0x05db +#define regMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32 0x05dc +#define regMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32 0x05dd +#define regMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32 0x05de +#define regMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32 0x05df +#define regMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32 0x05e0 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32 0x05e1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32 0x05e2 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32 0x05e3 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32 0x05e4 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32 0x05e5 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32 0x05e6 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32 0x05e7 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32 0x05e8 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32 0x05e9 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32 0x05ea +#define regMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32 0x05eb +#define regMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32 0x05ec +#define regMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32 0x05ed +#define regMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32 0x05ee +#define regMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32 0x05ef +#define regMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32 0x05f0 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32 0x05f1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32 0x05f2 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32 0x05f3 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32 0x05f4 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32 0x05f5 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32 0x05f6 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32 0x05f7 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32 0x05f8 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32 0x05f9 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32 0x05fa +#define regMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32 0x05fb +#define regMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32 0x05fc +#define regMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32 0x05fd +#define regMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32 0x05fe +#define regMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32 0x05ff +#define regMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32 0x0600 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32 0x0601 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32 0x0602 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32 0x0603 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32 0x0604 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32 0x0605 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32 0x0606 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32 0x0607 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32 0x0608 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32 0x0609 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32 0x060a +#define regMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32 0x060b +#define regMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32 0x060c +#define regMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32 0x060d +#define regMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32 0x060e +#define regMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32 0x060f +#define regMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32 0x0610 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32 0x0611 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32 0x0612 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32 0x0613 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32 0x0614 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32 0x0615 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32 0x0616 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32 0x0617 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32 0x0618 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32 0x0619 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32 0x061a +#define regMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32 0x061b +#define regMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32 0x061c +#define regMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32 0x061d +#define regMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32 0x061e +#define regMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32 0x061f +#define regMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32 0x0620 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32 0x0621 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32 0x0622 +#define regMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32 0x0623 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32 0x0624 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32 0x0625 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32 0x0626 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32 0x0627 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32 0x0628 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32 0x0629 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32 0x062a +#define regMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32 0x062b +#define regMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32 0x062c +#define regMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32 0x062d +#define regMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32 0x062e +#define regMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32 0x062f +#define regMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32 0x0630 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32 0x0631 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32 0x0632 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32 0x0633 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32 0x0634 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32 0x0635 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32 0x0636 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32 0x0637 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32 0x0638 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32 0x0639 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32 0x063a +#define regMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32 0x063b +#define regMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32 0x063c +#define regMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32 0x063d +#define regMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32 0x063e +#define regMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32 0x063f +#define regMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32 0x0640 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32 0x0641 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32 0x0642 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32 0x0643 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32 0x0644 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32 0x0645 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32 0x0646 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32 0x0647 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32 0x0648 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32 0x0649 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32 0x064a +#define regMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32 0x064b +#define regMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32 0x064c +#define regMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32 0x064d +#define regMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32 0x064e +#define regMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32 0x064f +#define regMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32 0x0650 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32 0x0651 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32 0x0652 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32 0x0653 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32 0x0654 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32 0x0655 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32 0x0656 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32 0x0657 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32 0x0658 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32 0x0659 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32 0x065a +#define regMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32 0x065b +#define regMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32 0x065c +#define regMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32 0x065d +#define regMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32 0x065e +#define regMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32 0x065f +#define regMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32 0x0660 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32 0x0661 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32 0x0662 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32 0x0663 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32 0x0664 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32 0x0665 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32 0x0666 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32 0x0667 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32 0x0668 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32 0x0669 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32 0x066a +#define regMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32 0x066b +#define regMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32 0x066c +#define regMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32 0x066d +#define regMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32 0x066e +#define regMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32 0x066f +#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32 0x0670 +#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32 0x0671 +#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32 0x0672 +#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS 0x0673 +#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32 0x0674 +#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32 0x0675 +#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 +#define regMMVM_L2_SAW_CNTL 0x0676 +#define regMMVM_L2_SAW_CNTL_BASE_IDX 1 +#define regMMVM_L2_SAW_CNTL2 0x0677 +#define regMMVM_L2_SAW_CNTL2_BASE_IDX 1 +#define regMMVM_L2_SAW_CNTL3 0x0678 +#define regMMVM_L2_SAW_CNTL3_BASE_IDX 1 +#define regMMVM_L2_SAW_CNTL4 0x0679 +#define regMMVM_L2_SAW_CNTL4_BASE_IDX 1 +#define regMMVM_L2_SAW_CONTEXT0_CNTL 0x067a +#define regMMVM_L2_SAW_CONTEXT0_CNTL_BASE_IDX 1 +#define regMMVM_L2_SAW_CONTEXT0_CNTL2 0x067b +#define regMMVM_L2_SAW_CONTEXT0_CNTL2_BASE_IDX 1 +#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x067c +#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x067d +#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x067e +#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x067f +#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x0680 +#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0681 +#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_L2_SAW_CONTEXTS_DISABLE 0x0682 +#define regMMVM_L2_SAW_CONTEXTS_DISABLE_BASE_IDX 1 +#define regMMVM_L2_SAW_PIPES_BUSY_LO32 0x0683 +#define regMMVM_L2_SAW_PIPES_BUSY_LO32_BASE_IDX 1 +#define regMMVM_L2_SAW_PIPES_BUSY_HI32 0x0684 +#define regMMVM_L2_SAW_PIPES_BUSY_HI32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS 0x0685 +#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32 0x0686 +#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32 0x0687 +#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmatcl2dec +// base address: 0x69b00 +#define regMM_ATC_L2_CNTL 0x06c0 +#define regMM_ATC_L2_CNTL_BASE_IDX 1 +#define regMM_ATC_L2_CNTL2 0x06c1 +#define regMM_ATC_L2_CNTL2_BASE_IDX 1 +#define regMM_ATC_L2_CACHE_DATA0 0x06c4 +#define regMM_ATC_L2_CACHE_DATA0_BASE_IDX 1 +#define regMM_ATC_L2_CACHE_DATA1 0x06c5 +#define regMM_ATC_L2_CACHE_DATA1_BASE_IDX 1 +#define regMM_ATC_L2_CACHE_DATA2 0x06c6 +#define regMM_ATC_L2_CACHE_DATA2_BASE_IDX 1 +#define regMM_ATC_L2_CNTL3 0x06c7 +#define regMM_ATC_L2_CNTL3_BASE_IDX 1 +#define regMM_ATC_L2_CNTL4 0x06c8 +#define regMM_ATC_L2_CNTL4_BASE_IDX 1 +#define regMM_ATC_L2_CNTL5 0x06c9 +#define regMM_ATC_L2_CNTL5_BASE_IDX 1 +#define regMM_ATC_L2_MM_GROUP_RT_CLASSES 0x06ca +#define regMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 +#define regMM_ATC_L2_STATUS 0x06cb +#define regMM_ATC_L2_STATUS_BASE_IDX 1 +#define regMM_ATC_L2_STATUS2 0x06cc +#define regMM_ATC_L2_STATUS2_BASE_IDX 1 +#define regMM_ATC_L2_MISC_CG 0x06cd +#define regMM_ATC_L2_MISC_CG_BASE_IDX 1 +#define regMM_ATC_L2_MEM_POWER_LS 0x06ce +#define regMM_ATC_L2_MEM_POWER_LS_BASE_IDX 1 +#define regMM_ATC_L2_CGTT_CLK_CTRL 0x06cf +#define regMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 1 +#define regMM_ATC_L2_SDPPORT_CTRL 0x06d2 +#define regMM_ATC_L2_SDPPORT_CTRL_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvml2pfdec +// base address: 0x69c00 +#define regMMVM_L2_CNTL 0x0700 +#define regMMVM_L2_CNTL_BASE_IDX 1 +#define regMMVM_L2_CNTL2 0x0701 +#define regMMVM_L2_CNTL2_BASE_IDX 1 +#define regMMVM_L2_CNTL3 0x0702 +#define regMMVM_L2_CNTL3_BASE_IDX 1 +#define regMMVM_L2_STATUS 0x0703 +#define regMMVM_L2_STATUS_BASE_IDX 1 +#define regMMVM_DUMMY_PAGE_FAULT_CNTL 0x0704 +#define regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 1 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0705 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 1 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0706 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_CNTL 0x0707 +#define regMMVM_INVALIDATE_CNTL_BASE_IDX 1 +#define regMMVM_L2_PROTECTION_FAULT_CNTL 0x0708 +#define regMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 1 +#define regMMVM_L2_PROTECTION_FAULT_CNTL2 0x0709 +#define regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 1 +#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x070a +#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 1 +#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x070b +#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 1 +#define regMMVM_L2_PROTECTION_FAULT_STATUS 0x070c +#define regMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 1 +#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x070d +#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 +#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x070e +#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x070f +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 1 +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0710 +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 1 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0712 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 1 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0713 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 1 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0714 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 1 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0715 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 1 +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0716 +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 1 +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0717 +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 1 +#define regMMVM_L2_CNTL4 0x0718 +#define regMMVM_L2_CNTL4_BASE_IDX 1 +#define regMMVM_L2_MM_GROUP_RT_CLASSES 0x0719 +#define regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 +#define regMMVM_L2_BANK_SELECT_RESERVED_CID 0x071a +#define regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 1 +#define regMMVM_L2_BANK_SELECT_RESERVED_CID2 0x071b +#define regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 1 +#define regMMVM_L2_CACHE_PARITY_CNTL 0x071c +#define regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 1 +#define regMMVM_L2_CGTT_CLK_CTRL 0x071d +#define regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 1 +#define regMMVM_L2_CNTL5 0x071e +#define regMMVM_L2_CNTL5_BASE_IDX 1 +#define regMMVM_L2_GCR_CNTL 0x071f +#define regMMVM_L2_GCR_CNTL_BASE_IDX 1 +#define regMMVM_L2_CGTT_BUSY_CTRL 0x0720 +#define regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX 1 +#define regMMVM_L2_PTE_CACHE_DUMP_CNTL 0x0721 +#define regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 1 +#define regMMVM_L2_PTE_CACHE_DUMP_READ 0x0722 +#define regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 1 +#define regMMVM_L2_BANK_SELECT_MASKS 0x0725 +#define regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX 1 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x0726 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 1 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x0727 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 1 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x0728 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 1 +#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x0729 +#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 1 +#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x072a +#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvml2vcdec +// base address: 0x69d00 +#define regMMVM_CONTEXT0_CNTL 0x0740 +#define regMMVM_CONTEXT0_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT1_CNTL 0x0741 +#define regMMVM_CONTEXT1_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT2_CNTL 0x0742 +#define regMMVM_CONTEXT2_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT3_CNTL 0x0743 +#define regMMVM_CONTEXT3_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT4_CNTL 0x0744 +#define regMMVM_CONTEXT4_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT5_CNTL 0x0745 +#define regMMVM_CONTEXT5_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT6_CNTL 0x0746 +#define regMMVM_CONTEXT6_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT7_CNTL 0x0747 +#define regMMVM_CONTEXT7_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT8_CNTL 0x0748 +#define regMMVM_CONTEXT8_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT9_CNTL 0x0749 +#define regMMVM_CONTEXT9_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT10_CNTL 0x074a +#define regMMVM_CONTEXT10_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT11_CNTL 0x074b +#define regMMVM_CONTEXT11_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT12_CNTL 0x074c +#define regMMVM_CONTEXT12_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT13_CNTL 0x074d +#define regMMVM_CONTEXT13_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT14_CNTL 0x074e +#define regMMVM_CONTEXT14_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT15_CNTL 0x074f +#define regMMVM_CONTEXT15_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXTS_DISABLE 0x0750 +#define regMMVM_CONTEXTS_DISABLE_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG0_SEM 0x0751 +#define regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG1_SEM 0x0752 +#define regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG2_SEM 0x0753 +#define regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG3_SEM 0x0754 +#define regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG4_SEM 0x0755 +#define regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG5_SEM 0x0756 +#define regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG6_SEM 0x0757 +#define regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG7_SEM 0x0758 +#define regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG8_SEM 0x0759 +#define regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG9_SEM 0x075a +#define regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG10_SEM 0x075b +#define regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG11_SEM 0x075c +#define regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG12_SEM 0x075d +#define regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG13_SEM 0x075e +#define regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG14_SEM 0x075f +#define regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG15_SEM 0x0760 +#define regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG16_SEM 0x0761 +#define regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG17_SEM 0x0762 +#define regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG0_REQ 0x0763 +#define regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG1_REQ 0x0764 +#define regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG2_REQ 0x0765 +#define regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG3_REQ 0x0766 +#define regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG4_REQ 0x0767 +#define regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG5_REQ 0x0768 +#define regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG6_REQ 0x0769 +#define regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG7_REQ 0x076a +#define regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG8_REQ 0x076b +#define regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG9_REQ 0x076c +#define regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG10_REQ 0x076d +#define regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG11_REQ 0x076e +#define regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG12_REQ 0x076f +#define regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG13_REQ 0x0770 +#define regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG14_REQ 0x0771 +#define regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG15_REQ 0x0772 +#define regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG16_REQ 0x0773 +#define regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG17_REQ 0x0774 +#define regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG0_ACK 0x0775 +#define regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG1_ACK 0x0776 +#define regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG2_ACK 0x0777 +#define regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG3_ACK 0x0778 +#define regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG4_ACK 0x0779 +#define regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG5_ACK 0x077a +#define regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG6_ACK 0x077b +#define regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG7_ACK 0x077c +#define regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG8_ACK 0x077d +#define regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG9_ACK 0x077e +#define regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG10_ACK 0x077f +#define regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG11_ACK 0x0780 +#define regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG12_ACK 0x0781 +#define regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG13_ACK 0x0782 +#define regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG14_ACK 0x0783 +#define regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG15_ACK 0x0784 +#define regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG16_ACK 0x0785 +#define regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG17_ACK 0x0786 +#define regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0787 +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0788 +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0789 +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x078a +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x078b +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x078c +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x078d +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x078e +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x078f +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0790 +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0791 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0792 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0793 +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0794 +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0795 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0796 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0797 +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0798 +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0799 +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x079a +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x079b +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x079c +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x079d +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x079e +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x079f +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x07a0 +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x07a1 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x07a2 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x07a3 +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x07a4 +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x07a5 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x07a6 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x07a7 +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x07a8 +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x07a9 +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x07aa +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x07ab +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x07ac +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x07ad +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x07ae +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x07af +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x07b0 +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x07b1 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x07b2 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x07b3 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x07b4 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x07b5 +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x07b6 +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x07b7 +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x07b8 +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x07b9 +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x07ba +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x07bb +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x07bc +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x07bd +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x07be +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x07bf +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x07c0 +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x07c1 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x07c2 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x07c3 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x07c4 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x07c5 +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x07c6 +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x07c7 +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x07c8 +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x07c9 +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x07ca +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x07cb +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x07cc +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x07cd +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x07ce +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x07cf +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x07d0 +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x07d1 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x07d2 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x07d3 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x07d4 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x07d5 +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x07d6 +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x07d7 +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x07d8 +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x07d9 +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x07da +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x07db +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x07dc +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x07dd +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x07de +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x07df +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x07e0 +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x07e1 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x07e2 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x07e3 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x07e4 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x07e5 +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x07e6 +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x07e7 +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x07e8 +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x07e9 +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x07ea +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x07eb +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x07ec +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x07ed +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x07ee +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x07ef +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x07f0 +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x07f1 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x07f2 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x07f3 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x07f4 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x07f5 +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x07f6 +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x07f7 +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x07f8 +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x07f9 +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x07fa +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x07fb +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x07fc +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x07fd +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x07fe +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x07ff +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0800 +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0801 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0802 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0803 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0804 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0805 +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0806 +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0807 +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0808 +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0809 +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x080a +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080b +#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080c +#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080d +#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080e +#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080f +#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0810 +#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0811 +#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0812 +#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0813 +#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0814 +#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0815 +#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0816 +#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0817 +#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0818 +#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0819 +#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x081a +#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x081b +#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvml2pldec +// base address: 0x6a090 +#define regMMMC_VM_L2_PERFCOUNTER0_CFG 0x0824 +#define regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regMMMC_VM_L2_PERFCOUNTER1_CFG 0x0825 +#define regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regMMMC_VM_L2_PERFCOUNTER2_CFG 0x0826 +#define regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regMMMC_VM_L2_PERFCOUNTER3_CFG 0x0827 +#define regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regMMMC_VM_L2_PERFCOUNTER4_CFG 0x0828 +#define regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 +#define regMMMC_VM_L2_PERFCOUNTER5_CFG 0x0829 +#define regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 +#define regMMMC_VM_L2_PERFCOUNTER6_CFG 0x082a +#define regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 +#define regMMMC_VM_L2_PERFCOUNTER7_CFG 0x082b +#define regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 +#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x082c +#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regMMUTCL2_PERFCOUNTER0_CFG 0x082d +#define regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regMMUTCL2_PERFCOUNTER1_CFG 0x082e +#define regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regMMUTCL2_PERFCOUNTER2_CFG 0x082f +#define regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regMMUTCL2_PERFCOUNTER3_CFG 0x0830 +#define regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL 0x0831 +#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvml2prdec +// base address: 0x6a0e0 +#define regMMMC_VM_L2_PERFCOUNTER_LO 0x0838 +#define regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define regMMMC_VM_L2_PERFCOUNTER_HI 0x0839 +#define regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 +#define regMMUTCL2_PERFCOUNTER_LO 0x083a +#define regMMUTCL2_PERFCOUNTER_LO_BASE_IDX 1 +#define regMMUTCL2_PERFCOUNTER_HI 0x083b +#define regMMUTCL2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec +// base address: 0x6a130 +#define regMMVM_PCIE_ATS_CNTL 0x084c +#define regMMVM_PCIE_ATS_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec +// base address: 0x6a340 +#define regMMMC_VM_NB_MMIOBASE 0x08d0 +#define regMMMC_VM_NB_MMIOBASE_BASE_IDX 1 +#define regMMMC_VM_NB_MMIOLIMIT 0x08d1 +#define regMMMC_VM_NB_MMIOLIMIT_BASE_IDX 1 +#define regMMMC_VM_NB_PCI_CTRL 0x08d2 +#define regMMMC_VM_NB_PCI_CTRL_BASE_IDX 1 +#define regMMMC_VM_NB_PCI_ARB 0x08d3 +#define regMMMC_VM_NB_PCI_ARB_BASE_IDX 1 +#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1 0x08d4 +#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 1 +#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2 0x08d5 +#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 1 +#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2 0x08d6 +#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 1 +#define regMMMC_VM_FB_OFFSET 0x08d7 +#define regMMMC_VM_FB_OFFSET_BASE_IDX 1 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x08d8 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 1 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x08d9 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 1 +#define regMMMC_VM_STEERING 0x08da +#define regMMMC_VM_STEERING_BASE_IDX 1 +#define regMMMC_SHARED_VIRT_RESET_REQ 0x08db +#define regMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX 1 +#define regMMMC_MEM_POWER_LS 0x08dc +#define regMMMC_MEM_POWER_LS_BASE_IDX 1 +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x08dd +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 1 +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x08de +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 1 +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x08df +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 1 +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x08e0 +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 1 +#define regMMMC_VM_APT_CNTL 0x08e1 +#define regMMMC_VM_APT_CNTL_BASE_IDX 1 +#define regMMMC_VM_LOCAL_FB_ADDRESS_START 0x08e2 +#define regMMMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX 1 +#define regMMMC_VM_LOCAL_FB_ADDRESS_END 0x08e3 +#define regMMMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX 1 +#define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 0x08e4 +#define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX 1 +#define regMMUTCL2_CGTT_CLK_CTRL 0x08e5 +#define regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 1 +#define regMMMC_SHARED_ACTIVE_FCN_ID 0x08e6 +#define regMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 +#define regMMUTCL2_CGTT_BUSY_CTRL 0x08e7 +#define regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX 1 +#define regMMUTCL2_HARVEST_BYPASS_GROUPS 0x08e8 +#define regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 1 +#define regMMUTCL2_GROUP_RET_FAULT_STATUS 0x08ea +#define regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec +// base address: 0x6a3b0 +#define regMMMC_VM_FB_LOCATION_BASE 0x08ec +#define regMMMC_VM_FB_LOCATION_BASE_BASE_IDX 1 +#define regMMMC_VM_FB_LOCATION_TOP 0x08ed +#define regMMMC_VM_FB_LOCATION_TOP_BASE_IDX 1 +#define regMMMC_VM_AGP_TOP 0x08ee +#define regMMMC_VM_AGP_TOP_BASE_IDX 1 +#define regMMMC_VM_AGP_BOT 0x08ef +#define regMMMC_VM_AGP_BOT_BASE_IDX 1 +#define regMMMC_VM_AGP_BASE 0x08f0 +#define regMMMC_VM_AGP_BASE_BASE_IDX 1 +#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x08f1 +#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 1 +#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08f2 +#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLB_CNTL 0x08f3 +#define regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec +// base address: 0x6a400 +#define regMM_ATC_L2_PERFCOUNTER_LO 0x0900 +#define regMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define regMM_ATC_L2_PERFCOUNTER_HI 0x0901 +#define regMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec +// base address: 0x6a420 +#define regMM_ATC_L2_PERFCOUNTER0_CFG 0x0908 +#define regMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regMM_ATC_L2_PERFCOUNTER1_CFG 0x0909 +#define regMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x090a +#define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvml2pspdec +// base address: 0x6aa50 +#define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID 0x0a94 +#define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX 1 +#define regMMVM_IOMMU_CONTROL_REGISTER 0x0a97 +#define regMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 +#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x0a98 +#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 +#define regMMUTC_TRANSLATION_FAULT_CNTL0 0x0a99 +#define regMMUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX 1 +#define regMMUTC_TRANSLATION_FAULT_CNTL1 0x0a9a +#define regMMUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mml2tlbpspdec +// base address: 0x6aa80 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 0x0aa0 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmatcl2pspdec +// base address: 0x6aa90 +#define regMM_ATC_L2_IOV_MODE_CNTL 0x0aa4 +#define regMM_ATC_L2_IOV_MODE_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mml2tlbpfdec +// base address: 0x6aac0 +#define regMML2TLB_TLB0_STATUS 0x0ab1 +#define regMML2TLB_TLB0_STATUS_BASE_IDX 1 +#define regMML2TLB_TMZ_CNTL 0x0ab2 +#define regMML2TLB_TMZ_CNTL_BASE_IDX 1 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x0ab3 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 1 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x0ab4 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 1 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x0ab5 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 1 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x0ab6 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 1 +#define regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ 0x0ab7 +#define regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mml2tlbpldec +// base address: 0x6ab00 +#define regMML2TLB_PERFCOUNTER0_CFG 0x0ac0 +#define regMML2TLB_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regMML2TLB_PERFCOUNTER1_CFG 0x0ac1 +#define regMML2TLB_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regMML2TLB_PERFCOUNTER2_CFG 0x0ac2 +#define regMML2TLB_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regMML2TLB_PERFCOUNTER3_CFG 0x0ac3 +#define regMML2TLB_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regMML2TLB_PERFCOUNTER_RSLT_CNTL 0x0ac4 +#define regMML2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mml2tlbprdec +// base address: 0x6ab20 +#define regMML2TLB_PERFCOUNTER_LO 0x0ac8 +#define regMML2TLB_PERFCOUNTER_LO_BASE_IDX 1 +#define regMML2TLB_PERFCOUNTER_HI 0x0ac9 +#define regMML2TLB_PERFCOUNTER_HI_BASE_IDX 1 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_sh_mask.h new file mode 100644 index 000000000000..f949666f0667 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_sh_mask.h @@ -0,0 +1,7483 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _mmhub_3_0_1_SH_MASK_HEADER +#define _mmhub_3_0_1_SH_MASK_HEADER + + +// addressBlock: mmhub_dagbdec +//DAGB0_RDCLI0 +#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI1 +#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI2 +#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI3 +#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI4 +#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI5 +#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI6 +#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI7 +#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI8 +#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI9 +#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI10 +#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI11 +#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI12 +#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI13 +#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI14 +#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI15 +#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI16 +#define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI17 +#define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI18 +#define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI19 +#define DAGB0_RDCLI19__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI19__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI19__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI19__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI19__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI19__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI19__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI19__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI19__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI19__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI19__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI19__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI20 +#define DAGB0_RDCLI20__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI20__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI20__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI20__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI20__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI20__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI20__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI20__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI20__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI20__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI20__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI20__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI21 +#define DAGB0_RDCLI21__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI21__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI21__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI21__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI21__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI21__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI21__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI21__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI21__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI21__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI21__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI21__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI22 +#define DAGB0_RDCLI22__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI22__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI22__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI22__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI22__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI22__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI22__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI22__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI22__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI22__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI22__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI22__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI23 +#define DAGB0_RDCLI23__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI23__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI23__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI23__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI23__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI23__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI23__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI23__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI23__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI23__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI23__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI23__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI24 +#define DAGB0_RDCLI24__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI24__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI24__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI24__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI24__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI24__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI24__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI24__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI24__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI24__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI24__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI24__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI24__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI24__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI24__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI24__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI24__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI25 +#define DAGB0_RDCLI25__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI25__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI25__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI25__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI25__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI25__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI25__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI25__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI25__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI25__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI25__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI25__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI25__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI25__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI25__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI25__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI25__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI26 +#define DAGB0_RDCLI26__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI26__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI26__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI26__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI26__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI26__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI26__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI26__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI26__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI26__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI26__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI26__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI26__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI26__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI26__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI26__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI26__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI27 +#define DAGB0_RDCLI27__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI27__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI27__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI27__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI27__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI27__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI27__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI27__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI27__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI27__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI27__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI27__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI27__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI27__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI27__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI27__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI27__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI28 +#define DAGB0_RDCLI28__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI28__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI28__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI28__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI28__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI28__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI28__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI28__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI28__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI28__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI28__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI28__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI28__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI28__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI28__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI28__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI28__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI29 +#define DAGB0_RDCLI29__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI29__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI29__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI29__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI29__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI29__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI29__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI29__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI29__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI29__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI29__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI29__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI29__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI29__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI29__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI29__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI29__MAX_OSD_MASK 0xFC000000L +//DAGB0_RD_CNTL +#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 +#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 +#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0xc +#define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xf +#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL +#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L +#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x00007000L +#define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN_MASK 0x00008000L +//DAGB0_RD_IO_CNTL +#define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 +#define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 +#define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 +#define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa +#define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd +#define DAGB0_RD_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 +#define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L +#define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL +#define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L +#define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L +#define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L +#define DAGB0_RD_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L +//DAGB0_RD_GMI_CNTL +#define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 +#define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 +#define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 +#define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa +#define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd +#define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 +#define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L +#define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL +#define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L +#define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L +#define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L +#define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L +//DAGB0_RD_ADDR_DAGB +#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB0_RD_CGTT_CLK_CTRL +#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST2 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER2 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST3 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER3 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L +//DAGB0_RD_VC0_CNTL +#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC1_CNTL +#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC2_CNTL +#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC3_CNTL +#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC4_CNTL +#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC5_CNTL +#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_IO_VC_CNTL +#define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB0_RD_IO_VC_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_IO_VC_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB0_RD_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_GMI_VC_CNTL +#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB0_RD_GMI_VC_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_CNTL_MISC +#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB0_RD_CNTL_MISC__UTCL2_VCI__SHIFT 0x6 +#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB0_RD_CNTL_MISC__UTCL2_VCI_MASK 0x000001C0L +//DAGB0_RD_TLB_CREDIT +#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB0_RDCLI_ASK_PENDING +#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_GO_PENDING +#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_GBLSEND_PENDING +#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_TLB_PENDING +#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_OARB_PENDING +#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_ASK2ARB_PENDING +#define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_ASK2DF_PENDING +#define DAGB0_RDCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_OSD_PENDING +#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_ASK_OSD_PENDING +#define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI0 +#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI1 +#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI2 +#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI3 +#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI4 +#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI5 +#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI6 +#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI7 +#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI8 +#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI9 +#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI10 +#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI11 +#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI12 +#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI13 +#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI14 +#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI15 +#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI16 +#define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI17 +#define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI18 +#define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI19 +#define DAGB0_WRCLI19__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI19__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI19__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI19__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI19__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI19__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI19__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI19__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI19__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI19__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI19__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI19__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI20 +#define DAGB0_WRCLI20__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI20__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI20__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI20__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI20__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI20__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI20__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI20__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI20__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI20__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI20__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI20__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI21 +#define DAGB0_WRCLI21__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI21__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI21__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI21__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI21__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI21__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI21__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI21__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI21__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI21__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI21__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI21__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI22 +#define DAGB0_WRCLI22__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI22__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI22__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI22__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI22__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI22__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI22__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI22__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI22__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI22__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI22__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI22__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI23 +#define DAGB0_WRCLI23__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI23__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI23__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI23__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI23__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI23__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI23__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI23__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI23__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI23__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI23__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI23__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI24 +#define DAGB0_WRCLI24__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI24__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI24__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI24__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI24__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI24__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI24__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI24__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI24__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI24__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI24__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI24__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI24__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI24__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI24__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI24__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI24__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI25 +#define DAGB0_WRCLI25__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI25__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI25__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI25__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI25__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI25__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI25__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI25__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI25__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI25__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI25__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI25__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI25__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI25__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI25__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI25__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI25__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI26 +#define DAGB0_WRCLI26__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI26__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI26__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI26__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI26__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI26__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI26__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI26__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI26__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI26__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI26__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI26__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI26__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI26__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI26__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI26__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI26__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI27 +#define DAGB0_WRCLI27__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI27__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI27__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI27__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI27__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI27__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI27__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI27__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI27__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI27__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI27__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI27__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI27__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI27__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI27__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI27__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI27__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI28 +#define DAGB0_WRCLI28__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI28__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI28__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI28__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI28__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI28__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI28__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI28__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI28__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI28__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI28__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI28__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI28__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI28__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI28__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI28__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI28__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI29 +#define DAGB0_WRCLI29__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI29__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI29__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI29__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI29__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI29__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI29__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI29__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI29__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI29__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI29__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI29__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI29__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI29__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI29__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI29__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI29__MAX_OSD_MASK 0xFC000000L +//DAGB0_WR_CNTL +#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 +#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 +#define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xc +#define DAGB0_WR_CNTL__UPDATE_FED__SHIFT 0xd +#define DAGB0_WR_CNTL__UPDATE_NACK__SHIFT 0xe +#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL +#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L +#define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN_MASK 0x00001000L +#define DAGB0_WR_CNTL__UPDATE_FED_MASK 0x00002000L +#define DAGB0_WR_CNTL__UPDATE_NACK_MASK 0x00004000L +//DAGB0_WR_IO_CNTL +#define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 +#define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 +#define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 +#define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa +#define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd +#define DAGB0_WR_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 +#define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L +#define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL +#define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L +#define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L +#define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L +#define DAGB0_WR_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L +//DAGB0_WR_GMI_CNTL +#define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 +#define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 +#define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 +#define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa +#define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd +#define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 +#define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L +#define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL +#define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L +#define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L +#define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L +#define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L +//DAGB0_WR_ADDR_DAGB +#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB0_WR_CGTT_CLK_CTRL +#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST2 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER2 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST3 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER3 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB +#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB0_WR_DATA_DAGB_MAX_BURST0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_MAX_BURST1 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_MAX_BURST2 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER2 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_MAX_BURST3 +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER3 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L +//DAGB0_WR_VC0_CNTL +#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC1_CNTL +#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC2_CNTL +#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC3_CNTL +#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC4_CNTL +#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC5_CNTL +#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_IO_VC_CNTL +#define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB0_WR_IO_VC_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_IO_VC_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB0_WR_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_GMI_VC_CNTL +#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB0_WR_GMI_VC_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_CNTL_MISC +#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT 0x6 +#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB0_WR_CNTL_MISC__HDP_CID_MASK 0x000007C0L +//DAGB0_WR_TLB_CREDIT +#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB0_WR_DATA_CREDIT +#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 +#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 +#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 +#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 +#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL +#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L +#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L +#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L +//DAGB0_WR_MISC_CREDIT +#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 +#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 +#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL +#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L +//DAGB0_WR_DATA_FIFO_CREDIT_CNTL1 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L +//DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x1a +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1b +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1c +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x03F00000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x04000000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x08000000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x10000000L +//DAGB0_WRCLI_ASK_PENDING +#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GO_PENDING +#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GBLSEND_PENDING +#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_TLB_PENDING +#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_OARB_PENDING +#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_ASK2ARB_PENDING +#define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_ASK2DF_PENDING +#define DAGB0_WRCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_OSD_PENDING +#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_ASK_OSD_PENDING +#define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_DBUS_ASK_PENDING +#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_DBUS_GO_PENDING +#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL +//DAGB0_DAGB_DLY +#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB0_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB0_CNTL_MISC +#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x0 +#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x0000003FL +//DAGB0_CNTL_MISC2 +#define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT 0x0 +#define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT 0x1 +#define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT 0x2 +#define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT 0x3 +#define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT 0x4 +#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0x5 +#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT 0x6 +#define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT 0x7 +#define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT 0x8 +#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0x9 +#define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0xa +#define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT 0xb +#define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK 0x00000001L +#define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK 0x00000002L +#define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK 0x00000004L +#define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK 0x00000008L +#define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK 0x00000010L +#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000020L +#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK 0x00000040L +#define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK 0x00000080L +#define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK 0x00000100L +#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000200L +#define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK 0x00000400L +#define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK 0x00000800L +//DAGB0_FIFO_EMPTY +#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x0001FFFFL +//DAGB0_FIFO_FULL +#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB0_FIFO_FULL__FULL_MASK 0x0000FFFFL +//DAGB0_RD_CREDITS_FULL +#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0000007FL +//DAGB0_WR_CREDITS_FULL +#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0001FFFFL +//DAGB0_PERFCOUNTER_LO +#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB0_PERFCOUNTER_HI +#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB0_PERFCOUNTER0_CFG +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER1_CFG +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER2_CFG +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER_RSLT_CNTL +#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB0_L1TLB_REG_RW +#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 +#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 +#define DAGB0_L1TLB_REG_RW__RESERVE__SHIFT 0x2 +#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L +#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L +#define DAGB0_L1TLB_REG_RW__RESERVE_MASK 0x3FFFFFFCL +//DAGB0_RESERVE1 +#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE2 +#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE3 +#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE4 +#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_SDP_RD_BW_CNTL +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW__SHIFT 0x1 +#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT 0x9 +#define DAGB0_SDP_RD_BW_CNTL__MIN_BW__SHIFT 0xa +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT 0xd +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_MASK 0x000001FEL +#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK 0x00000200L +#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_MASK 0x00001C00L +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK 0x0007E000L +//DAGB0_SDP_PRIORITY_OVERRIDE +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT 0x0 +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT 0x9 +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT 0xa +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT 0xb +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT 0xc +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT 0xd +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT 0xe +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT 0x10 +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT 0x14 +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT 0x19 +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT 0x1a +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT 0x1b +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT 0x1c +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT 0x1d +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT 0x1e +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK 0x0000000FL +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK 0x00000200L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK 0x00000400L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK 0x00000800L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK 0x00001000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK 0x00002000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK 0x00004000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK 0x000F0000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK 0x01F00000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK 0x02000000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK 0x04000000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK 0x08000000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK 0x10000000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK 0x20000000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK 0x40000000L +//DAGB0_SDP_RD_PRIORITY +#define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT 0x0 +#define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT 0x4 +#define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT 0x8 +#define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT 0xc +#define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT 0x10 +#define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT 0x14 +#define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK 0x0000000FL +#define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK 0x000000F0L +#define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK 0x00000F00L +#define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK 0x0000F000L +#define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK 0x000F0000L +#define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK 0x00F00000L +//DAGB0_SDP_WR_PRIORITY +#define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY__SHIFT 0x0 +#define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY__SHIFT 0x4 +#define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY__SHIFT 0x8 +#define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY__SHIFT 0xc +#define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY__SHIFT 0x10 +#define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY__SHIFT 0x14 +#define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY_MASK 0x0000000FL +#define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY_MASK 0x000000F0L +#define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY_MASK 0x00000F00L +#define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY_MASK 0x0000F000L +#define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY_MASK 0x000F0000L +#define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY_MASK 0x00F00000L +//DAGB0_SDP_RD_CLI2SDP_VC_MAP +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L +//DAGB0_SDP_WR_CLI2SDP_VC_MAP +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L +//DAGB0_SDP_ENABLE +#define DAGB0_SDP_ENABLE__ENABLE__SHIFT 0x0 +#define DAGB0_SDP_ENABLE__ENABLE_MASK 0x00000001L +//DAGB0_SDP_CREDITS +#define DAGB0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define DAGB0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define DAGB0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define DAGB0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define DAGB0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define DAGB0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x01FF0000L +//DAGB0_SDP_TAG_RESERVE0 +#define DAGB0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define DAGB0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define DAGB0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define DAGB0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define DAGB0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define DAGB0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define DAGB0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define DAGB0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//DAGB0_SDP_TAG_RESERVE1 +#define DAGB0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define DAGB0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define DAGB0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define DAGB0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define DAGB0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define DAGB0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define DAGB0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define DAGB0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//DAGB0_SDP_VCC_RESERVE0 +#define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//DAGB0_SDP_VCC_RESERVE1 +#define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//DAGB0_SDP_ERR_STATUS +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define DAGB0_SDP_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe +#define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf +#define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 +#define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 +#define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define DAGB0_SDP_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +#define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L +#define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L +#define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L +#define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L +#define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L +//DAGB0_SDP_REQ_CNTL +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L +//DAGB0_SDP_MISC_AON +#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 +#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 +#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L +#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L +//DAGB0_SDP_MISC +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x0 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x1 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x2 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x3 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0x4 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0x5 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0x6 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0x7 +#define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x8 +#define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x9 +#define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xb +#define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xd +#define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xf +#define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT 0x14 +#define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT 0x15 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000001L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000002L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000004L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000008L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000010L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000020L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00000040L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00000080L +#define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000100L +#define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000600L +#define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00001800L +#define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00006000L +#define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x000F8000L +#define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK 0x00100000L +#define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK 0x00200000L +//DAGB0_SDP_MISC2 +#define DAGB0_SDP_MISC2__RRET_SWAP_MODE__SHIFT 0x0 +#define DAGB0_SDP_MISC2__BLOCK_REQUESTS__SHIFT 0x1 +#define DAGB0_SDP_MISC2__REQUESTS_BLOCKED__SHIFT 0x2 +#define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT 0x3 +#define DAGB0_SDP_MISC2__RRET_SWAP_MODE_MASK 0x00000001L +#define DAGB0_SDP_MISC2__BLOCK_REQUESTS_MASK 0x00000002L +#define DAGB0_SDP_MISC2__REQUESTS_BLOCKED_MASK 0x00000004L +#define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK 0x00000008L +//DAGB0_SDP_VCD_RESERVE0 +#define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//DAGB0_SDP_VCD_RESERVE1 +#define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x12 +#define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x00040000L +//DAGB0_SDP_ARB_CNTL0 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT 0x0 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT 0x1 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT 0x2 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT 0x3 +#define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT 0x4 +#define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT 0x5 +#define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT 0x6 +#define DAGB0_SDP_ARB_CNTL0__DED_MODE__SHIFT 0x7 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK 0x00000001L +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK 0x00000002L +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK 0x00000004L +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK 0x00000008L +#define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK 0x00000010L +#define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK 0x00000020L +#define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK 0x00000040L +#define DAGB0_SDP_ARB_CNTL0__DED_MODE_MASK 0x00000080L +//DAGB0_SDP_ARB_CNTL1 +#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT 0x0 +#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT 0x8 +#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT 0x10 +#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT 0x18 +#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK 0x00007F00L +#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK 0x007F0000L +#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK 0x7F000000L +//DAGB0_SDP_CGTT_CLK_CTRL +#define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_SDP_LATENCY_SAMPLING +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L + + +// addressBlock: mmhub_pctldec +//PCTL_CTRL +#define PCTL_CTRL__PG_ENABLE__SHIFT 0x0 +#define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1 +#define PCTL_CTRL__RSMU_RDTIMER_ENABLE__SHIFT 0x4 +#define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD__SHIFT 0x5 +#define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x7 +#define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xe +#define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x13 +#define PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT 0x14 +#define PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT 0x15 +#define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD__SHIFT 0x16 +#define PCTL_CTRL__ZSC_TIMER_ENABLE__SHIFT 0x1b +#define PCTL_CTRL__Z9_PWRDOWN__SHIFT 0x1c +#define PCTL_CTRL__Z9_PWRUP__SHIFT 0x1d +#define PCTL_CTRL__SNR_DISABLE__SHIFT 0x1e +#define PCTL_CTRL__WRACK_GUARD__SHIFT 0x1f +#define PCTL_CTRL__PG_ENABLE_MASK 0x00000001L +#define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL +#define PCTL_CTRL__RSMU_RDTIMER_ENABLE_MASK 0x00000010L +#define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD_MASK 0x00000060L +#define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00003F80L +#define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0007C000L +#define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00080000L +#define PCTL_CTRL__UTCL2_LEGACY_MODE_MASK 0x00100000L +#define PCTL_CTRL__SDP_DISCONNECT_MODE_MASK 0x00200000L +#define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD_MASK 0x07C00000L +#define PCTL_CTRL__ZSC_TIMER_ENABLE_MASK 0x08000000L +#define PCTL_CTRL__Z9_PWRDOWN_MASK 0x10000000L +#define PCTL_CTRL__Z9_PWRUP_MASK 0x20000000L +#define PCTL_CTRL__SNR_DISABLE_MASK 0x40000000L +#define PCTL_CTRL__WRACK_GUARD_MASK 0x80000000L +//PCTL_MMHUB_DEEPSLEEP_IB +#define PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa +#define PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb +#define PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc +#define PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd +#define PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe +#define PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf +#define PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10 +#define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f +#define PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L +#define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L +//PCTL_MMHUB_DEEPSLEEP_OVERRIDE +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L +//PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L +//PCTL_PG_IGNORE_DEEPSLEEP +#define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa +#define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb +#define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc +#define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd +#define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe +#define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf +#define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11 +#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L +#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L +//PCTL_PG_IGNORE_DEEPSLEEP_IB +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L +//PCTL_SLICE0_CFG_DAGB_WRBUSY +#define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL_SLICE0_CFG_DAGB_RDBUSY +#define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL_SLICE0_CFG_DS_ALLOW +#define PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL_SLICE0_CFG_DS_ALLOW_IB +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL_SLICE1_CFG_DAGB_WRBUSY +#define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL_SLICE1_CFG_DAGB_RDBUSY +#define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL_SLICE1_CFG_DS_ALLOW +#define PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL_SLICE1_CFG_DS_ALLOW_IB +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL_UTCL2_MISC +#define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 +#define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb +#define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc +#define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf +#define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 +#define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 +#define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 +#define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a +#define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000007FFL +#define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L +#define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L +#define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L +#define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L +#define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +#define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L +#define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L +#define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L +//PCTL_SLICE0_MISC +#define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 +#define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 +#define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 +#define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a +#define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT 0x1e +#define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT 0x1f +#define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL +#define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +#define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L +#define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L +#define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L +#define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK 0x40000000L +#define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK 0x80000000L +//PCTL_SLICE1_MISC +#define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 +#define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 +#define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 +#define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a +#define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT 0x1e +#define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT 0x1f +#define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL +#define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +#define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L +#define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L +#define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L +#define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK 0x40000000L +#define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK 0x80000000L +//PCTL_RENG_CTRL +#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +//PCTL_UTCL2_RENG_EXECUTE +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L +//PCTL_SLICE0_RENG_EXECUTE +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L +//PCTL_SLICE1_RENG_EXECUTE +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L +//PCTL_UTCL2_RENG_RAM_INDEX +#define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL +//PCTL_UTCL2_RENG_RAM_DATA +#define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL_SLICE0_RENG_RAM_INDEX +#define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL_SLICE0_RENG_RAM_DATA +#define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL_SLICE1_RENG_RAM_INDEX +#define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL_SLICE1_RENG_RAM_DATA +#define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L +//PCTL_STATUS +#define PCTL_STATUS__MMHUB_CONFIG_DONE__SHIFT 0x0 +#define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE__SHIFT 0x1 +#define PCTL_STATUS__MMHUB_FENCE_REQ__SHIFT 0x2 +#define PCTL_STATUS__MMHUB_FENCE_ACK__SHIFT 0x3 +#define PCTL_STATUS__MMHUB_IDLE__SHIFT 0x4 +#define PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT 0x5 +#define PCTL_STATUS__RSMU_RDTIMEOUT_CNT__SHIFT 0x7 +#define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR__SHIFT 0xf +#define PCTL_STATUS__MMHUB_POWER__SHIFT 0x10 +#define PCTL_STATUS__RENG_RAM_STALE__SHIFT 0x11 +#define PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT 0x12 +#define PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT 0x13 +#define PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT 0x14 +#define PCTL_STATUS__MMHUB_CONFIG_DONE_MASK 0x00000001L +#define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE_MASK 0x00000002L +#define PCTL_STATUS__MMHUB_FENCE_REQ_MASK 0x00000004L +#define PCTL_STATUS__MMHUB_FENCE_ACK_MASK 0x00000008L +#define PCTL_STATUS__MMHUB_IDLE_MASK 0x00000010L +#define PCTL_STATUS__PGFSM_CMD_STATUS_MASK 0x00000060L +#define PCTL_STATUS__RSMU_RDTIMEOUT_CNT_MASK 0x00007F80L +#define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR_MASK 0x00008000L +#define PCTL_STATUS__MMHUB_POWER_MASK 0x00010000L +#define PCTL_STATUS__RENG_RAM_STALE_MASK 0x00020000L +#define PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK 0x00040000L +#define PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK 0x00080000L +#define PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK 0x00100000L +//PCTL_PERFCOUNTER_LO +#define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//PCTL_PERFCOUNTER_HI +#define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//PCTL_PERFCOUNTER0_CFG +#define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//PCTL_PERFCOUNTER1_CFG +#define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//PCTL_PERFCOUNTER_RSLT_CNTL +#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//PCTL_RESERVED_0 +#define PCTL_RESERVED_0__WORD__SHIFT 0x0 +#define PCTL_RESERVED_0__BYTE__SHIFT 0x10 +#define PCTL_RESERVED_0__BIT7__SHIFT 0x18 +#define PCTL_RESERVED_0__BIT6__SHIFT 0x19 +#define PCTL_RESERVED_0__BIT5__SHIFT 0x1a +#define PCTL_RESERVED_0__BIT4__SHIFT 0x1b +#define PCTL_RESERVED_0__BIT3__SHIFT 0x1c +#define PCTL_RESERVED_0__BIT2__SHIFT 0x1d +#define PCTL_RESERVED_0__BIT1__SHIFT 0x1e +#define PCTL_RESERVED_0__BIT0__SHIFT 0x1f +#define PCTL_RESERVED_0__WORD_MASK 0x0000FFFFL +#define PCTL_RESERVED_0__BYTE_MASK 0x00FF0000L +#define PCTL_RESERVED_0__BIT7_MASK 0x01000000L +#define PCTL_RESERVED_0__BIT6_MASK 0x02000000L +#define PCTL_RESERVED_0__BIT5_MASK 0x04000000L +#define PCTL_RESERVED_0__BIT4_MASK 0x08000000L +#define PCTL_RESERVED_0__BIT3_MASK 0x10000000L +#define PCTL_RESERVED_0__BIT2_MASK 0x20000000L +#define PCTL_RESERVED_0__BIT1_MASK 0x40000000L +#define PCTL_RESERVED_0__BIT0_MASK 0x80000000L +//PCTL_RESERVED_1 +#define PCTL_RESERVED_1__WORD__SHIFT 0x0 +#define PCTL_RESERVED_1__BYTE__SHIFT 0x10 +#define PCTL_RESERVED_1__BIT7__SHIFT 0x18 +#define PCTL_RESERVED_1__BIT6__SHIFT 0x19 +#define PCTL_RESERVED_1__BIT5__SHIFT 0x1a +#define PCTL_RESERVED_1__BIT4__SHIFT 0x1b +#define PCTL_RESERVED_1__BIT3__SHIFT 0x1c +#define PCTL_RESERVED_1__BIT2__SHIFT 0x1d +#define PCTL_RESERVED_1__BIT1__SHIFT 0x1e +#define PCTL_RESERVED_1__BIT0__SHIFT 0x1f +#define PCTL_RESERVED_1__WORD_MASK 0x0000FFFFL +#define PCTL_RESERVED_1__BYTE_MASK 0x00FF0000L +#define PCTL_RESERVED_1__BIT7_MASK 0x01000000L +#define PCTL_RESERVED_1__BIT6_MASK 0x02000000L +#define PCTL_RESERVED_1__BIT5_MASK 0x04000000L +#define PCTL_RESERVED_1__BIT4_MASK 0x08000000L +#define PCTL_RESERVED_1__BIT3_MASK 0x10000000L +#define PCTL_RESERVED_1__BIT2_MASK 0x20000000L +#define PCTL_RESERVED_1__BIT1_MASK 0x40000000L +#define PCTL_RESERVED_1__BIT0_MASK 0x80000000L +//PCTL_RESERVED_2 +#define PCTL_RESERVED_2__WORD__SHIFT 0x0 +#define PCTL_RESERVED_2__BYTE__SHIFT 0x10 +#define PCTL_RESERVED_2__BIT7__SHIFT 0x18 +#define PCTL_RESERVED_2__BIT6__SHIFT 0x19 +#define PCTL_RESERVED_2__BIT5__SHIFT 0x1a +#define PCTL_RESERVED_2__BIT4__SHIFT 0x1b +#define PCTL_RESERVED_2__BIT3__SHIFT 0x1c +#define PCTL_RESERVED_2__BIT2__SHIFT 0x1d +#define PCTL_RESERVED_2__BIT1__SHIFT 0x1e +#define PCTL_RESERVED_2__BIT0__SHIFT 0x1f +#define PCTL_RESERVED_2__WORD_MASK 0x0000FFFFL +#define PCTL_RESERVED_2__BYTE_MASK 0x00FF0000L +#define PCTL_RESERVED_2__BIT7_MASK 0x01000000L +#define PCTL_RESERVED_2__BIT6_MASK 0x02000000L +#define PCTL_RESERVED_2__BIT5_MASK 0x04000000L +#define PCTL_RESERVED_2__BIT4_MASK 0x08000000L +#define PCTL_RESERVED_2__BIT3_MASK 0x10000000L +#define PCTL_RESERVED_2__BIT2_MASK 0x20000000L +#define PCTL_RESERVED_2__BIT1_MASK 0x40000000L +#define PCTL_RESERVED_2__BIT0_MASK 0x80000000L +//PCTL_RESERVED_3 +#define PCTL_RESERVED_3__WORD__SHIFT 0x0 +#define PCTL_RESERVED_3__BYTE__SHIFT 0x10 +#define PCTL_RESERVED_3__BIT7__SHIFT 0x18 +#define PCTL_RESERVED_3__BIT6__SHIFT 0x19 +#define PCTL_RESERVED_3__BIT5__SHIFT 0x1a +#define PCTL_RESERVED_3__BIT4__SHIFT 0x1b +#define PCTL_RESERVED_3__BIT3__SHIFT 0x1c +#define PCTL_RESERVED_3__BIT2__SHIFT 0x1d +#define PCTL_RESERVED_3__BIT1__SHIFT 0x1e +#define PCTL_RESERVED_3__BIT0__SHIFT 0x1f +#define PCTL_RESERVED_3__WORD_MASK 0x0000FFFFL +#define PCTL_RESERVED_3__BYTE_MASK 0x00FF0000L +#define PCTL_RESERVED_3__BIT7_MASK 0x01000000L +#define PCTL_RESERVED_3__BIT6_MASK 0x02000000L +#define PCTL_RESERVED_3__BIT5_MASK 0x04000000L +#define PCTL_RESERVED_3__BIT4_MASK 0x08000000L +#define PCTL_RESERVED_3__BIT3_MASK 0x10000000L +#define PCTL_RESERVED_3__BIT2_MASK 0x20000000L +#define PCTL_RESERVED_3__BIT1_MASK 0x40000000L +#define PCTL_RESERVED_3__BIT0_MASK 0x80000000L + + +// addressBlock: mmhub_l1tlb_mmutcl1pfdec +//MMMC_VM_MX_L1_TLB0_STATUS +#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 +#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L +//MMMC_VM_MX_L1_TLB1_STATUS +#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 +#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L +//MMMC_VM_MX_L1_TLB2_STATUS +#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 +#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L +//MMMC_VM_MX_L1_TLB3_STATUS +#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 +#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L +//MMMC_VM_MX_L1_TLB4_STATUS +#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 +#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L +//MMMC_VM_MX_L1_TLB5_STATUS +#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 +#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L +//MMMC_VM_MX_L1_TLB6_STATUS +#define MMMC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 +#define MMMC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L +//MMMC_VM_MX_L1_TLB7_STATUS +#define MMMC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 +#define MMMC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L + + +// addressBlock: mmhub_l1tlb_mmutcl1pldec +//MMMC_VM_MX_L1_PERFCOUNTER0_CFG +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_MX_L1_PERFCOUNTER1_CFG +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_MX_L1_PERFCOUNTER2_CFG +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_MX_L1_PERFCOUNTER3_CFG +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_l1tlb_mmutcl1prdec +//MMMC_VM_MX_L1_PERFCOUNTER_LO +#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_PERFCOUNTER_HI +#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_l1tlb_mmvmtlspfdec +//MMMC_VM_MX_L1_TLS0_CNTL +#define MMMC_VM_MX_L1_TLS0_CNTL__PREFETCH_COUNT__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x4 +#define MMMC_VM_MX_L1_TLS0_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x5 +#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_SNOOP_SELECT__SHIFT 0x6 +#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SYSTEM__SHIFT 0x8 +#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SNOOP__SHIFT 0x9 +#define MMMC_VM_MX_L1_TLS0_CNTL__DEBUG_ECO_BITS__SHIFT 0x10 +#define MMMC_VM_MX_L1_TLS0_CNTL__PREFETCH_COUNT_MASK 0x0000000FL +#define MMMC_VM_MX_L1_TLS0_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000010L +#define MMMC_VM_MX_L1_TLS0_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000020L +#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_SNOOP_SELECT_MASK 0x000000C0L +#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SYSTEM_MASK 0x00000100L +#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SNOOP_MASK 0x00000200L +#define MMMC_VM_MX_L1_TLS0_CNTL__DEBUG_ECO_BITS_MASK 0xFFFF0000L +//MMMC_VM_MX_L1_TLS0_CNTL0 +#define MMMC_VM_MX_L1_TLS0_CNTL0__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL0__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL0__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL0__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL0__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL0__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL1 +#define MMMC_VM_MX_L1_TLS0_CNTL1__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL1__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL1__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL1__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL1__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL1__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL2 +#define MMMC_VM_MX_L1_TLS0_CNTL2__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL2__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL2__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL2__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL2__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL2__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL3 +#define MMMC_VM_MX_L1_TLS0_CNTL3__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL3__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL3__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL3__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL3__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL3__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL4 +#define MMMC_VM_MX_L1_TLS0_CNTL4__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL4__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL4__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL4__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL4__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL4__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL5 +#define MMMC_VM_MX_L1_TLS0_CNTL5__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL5__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL5__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL5__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL5__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL5__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL6 +#define MMMC_VM_MX_L1_TLS0_CNTL6__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL6__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL6__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL6__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL6__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL6__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL7 +#define MMMC_VM_MX_L1_TLS0_CNTL7__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL7__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL7__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL7__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL7__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL7__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL8 +#define MMMC_VM_MX_L1_TLS0_CNTL8__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL8__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL8__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL8__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL8__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL8__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL9 +#define MMMC_VM_MX_L1_TLS0_CNTL9__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL9__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL9__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL9__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL9__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL9__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL10 +#define MMMC_VM_MX_L1_TLS0_CNTL10__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL10__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL10__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL10__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL10__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL10__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL11 +#define MMMC_VM_MX_L1_TLS0_CNTL11__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL11__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL11__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL11__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL11__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL11__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL12 +#define MMMC_VM_MX_L1_TLS0_CNTL12__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL12__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL12__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL12__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL12__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL12__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL13 +#define MMMC_VM_MX_L1_TLS0_CNTL13__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL13__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL13__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL13__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL13__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL13__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL14 +#define MMMC_VM_MX_L1_TLS0_CNTL14__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL14__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL14__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL14__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL14__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL14__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL15 +#define MMMC_VM_MX_L1_TLS0_CNTL15__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL15__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL15__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL15__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL15__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL15__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL16 +#define MMMC_VM_MX_L1_TLS0_CNTL16__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL16__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL16__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL16__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL16__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL16__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL17 +#define MMMC_VM_MX_L1_TLS0_CNTL17__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL17__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL17__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL17__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL17__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL17__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL18 +#define MMMC_VM_MX_L1_TLS0_CNTL18__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL18__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL18__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL18__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL18__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL18__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL19 +#define MMMC_VM_MX_L1_TLS0_CNTL19__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL19__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL19__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL19__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL19__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL19__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL20 +#define MMMC_VM_MX_L1_TLS0_CNTL20__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL20__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL20__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL20__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL20__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL20__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL21 +#define MMMC_VM_MX_L1_TLS0_CNTL21__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL21__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL21__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL21__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL21__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL21__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL22 +#define MMMC_VM_MX_L1_TLS0_CNTL22__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL22__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL22__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL22__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL22__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL22__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL23 +#define MMMC_VM_MX_L1_TLS0_CNTL23__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL23__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL23__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL23__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL23__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL23__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL24 +#define MMMC_VM_MX_L1_TLS0_CNTL24__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL24__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL24__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL24__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL24__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL24__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL25 +#define MMMC_VM_MX_L1_TLS0_CNTL25__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL25__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL25__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL25__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL25__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL25__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL26 +#define MMMC_VM_MX_L1_TLS0_CNTL26__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL26__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL26__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL26__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL26__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL26__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL27 +#define MMMC_VM_MX_L1_TLS0_CNTL27__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL27__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL27__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL27__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL27__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL27__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL28 +#define MMMC_VM_MX_L1_TLS0_CNTL28__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL28__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL28__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL28__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL28__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL28__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL29 +#define MMMC_VM_MX_L1_TLS0_CNTL29__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL29__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL29__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL29__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL29__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL29__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL30 +#define MMMC_VM_MX_L1_TLS0_CNTL30__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL30__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL30__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL30__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL30__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL30__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL31 +#define MMMC_VM_MX_L1_TLS0_CNTL31__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL31__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL31__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL31__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL31__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL31__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL32 +#define MMMC_VM_MX_L1_TLS0_CNTL32__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL32__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL32__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL32__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL32__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL32__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL33 +#define MMMC_VM_MX_L1_TLS0_CNTL33__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL33__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL33__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL33__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL33__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL33__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL34 +#define MMMC_VM_MX_L1_TLS0_CNTL34__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL34__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL34__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL34__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL34__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL34__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL35 +#define MMMC_VM_MX_L1_TLS0_CNTL35__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL35__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL35__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL35__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL35__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL35__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL36 +#define MMMC_VM_MX_L1_TLS0_CNTL36__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL36__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL36__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL36__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL36__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL36__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_CNTL37 +#define MMMC_VM_MX_L1_TLS0_CNTL37__REQ_STREAM_ID__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_CNTL37__EN__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_CNTL37__PREFETCH_DONE__SHIFT 0xd +#define MMMC_VM_MX_L1_TLS0_CNTL37__REQ_STREAM_ID_MASK 0x000001FFL +#define MMMC_VM_MX_L1_TLS0_CNTL37__EN_MASK 0x00001000L +#define MMMC_VM_MX_L1_TLS0_CNTL37__PREFETCH_DONE_MASK 0x00002000L +//MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32__START_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32 +#define MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32__START_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32__START_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32__END_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32 +#define MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32__END_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32__END_ADDR_HI4_MASK 0x0000000FL +//MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32 +#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32__INVALIDATE_STREAM_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32__INVALIDATE_STREAM_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32 +#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32__INVALIDATE_STREAM_HI6__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32__INVALIDATE_STREAM_HI6_MASK 0x0000003FL +//MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32 +#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32__INVALIDATE_REQUEST_PENDING_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32__INVALIDATE_REQUEST_PENDING_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32 +#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32__INVALIDATE_REQUEST_PENDING_HI6__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32__INVALIDATE_REQUEST_PENDING_HI6_MASK 0x0000003FL +//MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS +#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc +#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18 +#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19 +#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d +#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0x000000FFL +#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x001FF000L +#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x01000000L +#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1E000000L +#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000L +//MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32 +#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32 +#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//MMVM_L2_SAW_CNTL +#define MMVM_L2_SAW_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define MMVM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define MMVM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define MMVM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define MMVM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define MMVM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define MMVM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define MMVM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define MMVM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define MMVM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define MMVM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define MMVM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a +#define MMVM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c +#define MMVM_L2_SAW_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define MMVM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define MMVM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL +#define MMVM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define MMVM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define MMVM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define MMVM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define MMVM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define MMVM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define MMVM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define MMVM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L +#define MMVM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0x0C000000L +#define MMVM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000L +//MMVM_L2_SAW_CNTL2 +#define MMVM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define MMVM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define MMVM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define MMVM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define MMVM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17 +#define MMVM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define MMVM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define MMVM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define MMVM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define MMVM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define MMVM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define MMVM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x03800000L +#define MMVM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L +#define MMVM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L +//MMVM_L2_SAW_CNTL3 +#define MMVM_L2_SAW_CNTL3__BANK_SELECT__SHIFT 0x0 +#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define MMVM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f +#define MMVM_L2_SAW_CNTL3__BANK_SELECT_MASK 0x0000003FL +#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L +#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L +#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L +#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L +#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define MMVM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L +#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L +//MMVM_L2_SAW_CNTL4 +#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT 0x7 +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT 0x8 +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT 0x9 +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT 0xa +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT 0xb +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT 0xc +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT 0xd +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT 0xe +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT 0xf +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT 0x10 +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT 0x11 +#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT 0x12 +#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK 0x00000040L +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK 0x00000080L +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK 0x00000100L +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK 0x00000200L +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK 0x00000400L +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK 0x00000800L +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK 0x00001000L +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK 0x00002000L +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK 0x00004000L +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK 0x00008000L +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK 0x00010000L +#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK 0x00020000L +#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK 0x00040000L +//MMVM_L2_SAW_CONTEXT0_CNTL +#define MMVM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 +#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 +#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb +#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe +#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 +#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 +#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 +#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 +#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x1c +#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x1d +#define MMVM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L +#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L +#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L +#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L +#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L +#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L +#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00800000L +#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0F000000L +#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x10000000L +#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x20000000L +//MMVM_L2_SAW_CONTEXT0_CNTL2 +#define MMVM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 +#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 +#define MMVM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 +#define MMVM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 +#define MMVM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x00000002L +#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x00000004L +#define MMVM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L +#define MMVM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L +//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_L2_SAW_CONTEXTS_DISABLE +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +//MMVM_L2_SAW_PIPES_BUSY_LO32 +#define MMVM_L2_SAW_PIPES_BUSY_LO32__PIPES_BUSY_LO32__SHIFT 0x0 +#define MMVM_L2_SAW_PIPES_BUSY_LO32__PIPES_BUSY_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_SAW_PIPES_BUSY_HI32 +#define MMVM_L2_SAW_PIPES_BUSY_HI32__PIPES_BUSY_HI32__SHIFT 0x0 +#define MMVM_L2_SAW_PIPES_BUSY_HI32__PIPES_BUSY_HI32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS +#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__ABORT_STATUS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__STREAM_ID__SHIFT 0x3 +#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__ABORT_STATUS_MASK 0x00000006L +#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__STREAM_ID_MASK 0x000001F8L +//MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32 +#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32 +#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL + + +// addressBlock: mmhub_mmutcl2_mmatcl2dec +//MM_ATC_L2_CNTL +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8 +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf +#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10 +#define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13 +#define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x14 +#define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x16 +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L +#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L +#define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L +#define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00300000L +#define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x0FC00000L +//MM_ATC_L2_CNTL2 +#define MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 +#define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6 +#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9 +#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb +#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc +#define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xf +#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x12 +#define MM_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL +#define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L +#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L +#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L +#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L +#define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00038000L +#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00FC0000L +//MM_ATC_L2_CACHE_DATA0 +#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 +#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 +#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 +#define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x18 +#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L +#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L +#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x00FFFFFCL +#define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x0F000000L +//MM_ATC_L2_CACHE_DATA1 +#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 +#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL +//MM_ATC_L2_CACHE_DATA2 +#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 +#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL +//MM_ATC_L2_CNTL3 +#define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0 +#define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE__SHIFT 0x6 +#define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0xc +#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x12 +#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x15 +#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x1b +#define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x1e +#define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL +#define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L +#define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x0003F000L +#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x001C0000L +#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x07E00000L +#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x38000000L +#define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x40000000L +//MM_ATC_L2_CNTL4 +#define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0 +#define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE__SHIFT 0x6 +#define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0xc +#define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL +#define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L +#define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x0003F000L +//MM_ATC_L2_CNTL5 +#define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0 +#define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa +#define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL +#define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L +//MM_ATC_L2_MM_GROUP_RT_CLASSES +#define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 +#define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL +//MM_ATC_L2_STATUS +#define MM_ATC_L2_STATUS__BUSY__SHIFT 0x0 +#define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT 0x1 +#define MM_ATC_L2_STATUS__BUSY_MASK 0x00000001L +#define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK 0x00000002L +//MM_ATC_L2_STATUS2 +#define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 +#define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 +#define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL +#define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L +//MM_ATC_L2_MISC_CG +#define MM_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 +#define MM_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 +#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MM_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L +#define MM_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L +#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L +//MM_ATC_L2_MEM_POWER_LS +#define MM_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define MM_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define MM_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define MM_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//MM_ATC_L2_CGTT_CLK_CTRL +#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//MM_ATC_L2_SDPPORT_CTRL +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L + + +// addressBlock: mmhub_mmutcl2_mmvml2pfdec +//MMVM_L2_CNTL +#define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a +#define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL +#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L +#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L +//MMVM_L2_CNTL2 +#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 +#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L +#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L +#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L +//MMVM_L2_CNTL3 +#define MMVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f +#define MMVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L +#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L +#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L +//MMVM_L2_STATUS +#define MMVM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 +#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 +#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 +#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 +#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 +#define MMVM_L2_STATUS__L2_BUSY_MASK 0x00000001L +#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL +#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L +#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L +#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L +#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L +#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L +//MMVM_DUMMY_PAGE_FAULT_CNTL +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL +//MMVM_DUMMY_PAGE_FAULT_ADDR_LO32 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//MMVM_DUMMY_PAGE_FAULT_ADDR_HI32 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL +//MMVM_INVALIDATE_CNTL +#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 +#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 +#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL +#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L +//MMVM_L2_PROTECTION_FAULT_CNTL +#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 +#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 +#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 +#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 +#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 +#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 +#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 +#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd +#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d +#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e +#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f +#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L +#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L +#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L +#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L +#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L +#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L +#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L +#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L +#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L +#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L +#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L +//MMVM_L2_PROTECTION_FAULT_CNTL2 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL +#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L +//MMVM_L2_PROTECTION_FAULT_MM_CNTL3 +#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//MMVM_L2_PROTECTION_FAULT_MM_CNTL4 +#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//MMVM_L2_PROTECTION_FAULT_STATUS +#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 +#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 +#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 +#define MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 +#define MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 +#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 +#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 +#define MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 +#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 +#define MMVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT 0x1d +#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L +#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL +#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L +#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L +#define MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L +#define MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L +#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L +#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L +#define MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L +#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L +#define MMVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK 0x20000000L +//MMVM_L2_PROTECTION_FAULT_ADDR_LO32 +#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_PROTECTION_FAULT_ADDR_HI32 +#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL +//MMVM_L2_CNTL4 +#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 +#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 +#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 +#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c +#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d +#define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e +#define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT 0x1f +#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL +#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L +#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L +#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L +#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L +#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L +#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L +#define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L +#define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK 0x80000000L +//MMVM_L2_MM_GROUP_RT_CLASSES +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L +//MMVM_L2_BANK_SELECT_RESERVED_CID +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L +//MMVM_L2_BANK_SELECT_RESERVED_CID2 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L +//MMVM_L2_CACHE_PARITY_CNTL +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L +//MMVM_L2_CGTT_CLK_CTRL +#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//MMVM_L2_CNTL5 +#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 +#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT 0xe +#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT 0xf +#define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF__SHIFT 0x10 +#define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT 0x11 +#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L +#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK 0x00004000L +#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK 0x00008000L +#define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF_MASK 0x00010000L +#define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK 0x00020000L +//MMVM_L2_GCR_CNTL +#define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 +#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 +#define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L +#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL +//MMVM_L2_CGTT_BUSY_CTRL +#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 +#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL +#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L +//MMVM_L2_PTE_CACHE_DUMP_CNTL +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT 0x0 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT 0x1 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT 0x4 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT 0x8 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT 0xc +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT 0x10 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK 0x00000001L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK 0x00000002L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK 0x000000F0L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK 0x00000F00L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK 0x0000F000L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK 0xFFFF0000L +//MMVM_L2_PTE_CACHE_DUMP_READ +#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT 0x0 +#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK 0xFFFFFFFFL +//MMVM_L2_BANK_SELECT_MASKS +#define MMVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT 0x0 +#define MMVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT 0x4 +#define MMVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT 0x8 +#define MMVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT 0xc +#define MMVM_L2_BANK_SELECT_MASKS__MASK0_MASK 0x0000000FL +#define MMVM_L2_BANK_SELECT_MASKS__MASK1_MASK 0x000000F0L +#define MMVM_L2_BANK_SELECT_MASKS__MASK2_MASK 0x00000F00L +#define MMVM_L2_BANK_SELECT_MASKS__MASK3_MASK 0x0000F000L +//MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT 0x0 +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT 0xa +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK 0x000003FFL +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK 0x00000400L +//MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT 0x0 +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT 0xa +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK 0x000003FFL +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK 0x00000400L +//MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT 0x0 +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT 0xa +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK 0x000003FFL +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK 0x00000400L +//MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT 0x0 +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT 0xa +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK 0x000003FFL +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK 0x00000400L +//MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT 0xa +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK 0x00000400L + + +// addressBlock: mmhub_mmutcl2_mmvml2vcdec +//MMVM_CONTEXT0_CNTL +#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT1_CNTL +#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT2_CNTL +#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT3_CNTL +#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT4_CNTL +#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT5_CNTL +#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT6_CNTL +#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT7_CNTL +#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT8_CNTL +#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT9_CNTL +#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT10_CNTL +#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT11_CNTL +#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT12_CNTL +#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT13_CNTL +#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT14_CNTL +#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT15_CNTL +#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXTS_DISABLE +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +//MMVM_INVALIDATE_ENG0_SEM +#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG1_SEM +#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG2_SEM +#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG3_SEM +#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG4_SEM +#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG5_SEM +#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG6_SEM +#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG7_SEM +#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG8_SEM +#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG9_SEM +#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG10_SEM +#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG11_SEM +#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG12_SEM +#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG13_SEM +#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG14_SEM +#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG15_SEM +#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG16_SEM +#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG17_SEM +#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG0_REQ +#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG1_REQ +#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG2_REQ +#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG3_REQ +#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG4_REQ +#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG5_REQ +#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG6_REQ +#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG7_REQ +#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG8_REQ +#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG9_REQ +#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG10_REQ +#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG11_REQ +#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG12_REQ +#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG13_REQ +#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG14_REQ +#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG15_REQ +#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG16_REQ +#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG17_REQ +#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG0_ACK +#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG1_ACK +#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG2_ACK +#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG3_ACK +#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG4_ACK +#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG5_ACK +#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG6_ACK +#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG7_ACK +#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG8_ACK +#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG9_ACK +#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG10_ACK +#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG11_ACK +#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG12_ACK +#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG13_ACK +#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG14_ACK +#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG15_ACK +#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG16_ACK +#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG17_ACK +#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L + + +// addressBlock: mmhub_mmutcl2_mmvml2pldec +//MMMC_VM_L2_PERFCOUNTER0_CFG +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER1_CFG +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER2_CFG +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER3_CFG +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER4_CFG +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER5_CFG +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER6_CFG +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER7_CFG +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMUTCL2_PERFCOUNTER0_CFG +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER1_CFG +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER2_CFG +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER3_CFG +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER_RSLT_CNTL +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_mmutcl2_mmvml2prdec +//MMMC_VM_L2_PERFCOUNTER_LO +#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMMC_VM_L2_PERFCOUNTER_HI +#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMUTCL2_PERFCOUNTER_LO +#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMUTCL2_PERFCOUNTER_HI +#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec +//MMVM_PCIE_ATS_CNTL +#define MMVM_PCIE_ATS_CNTL__STU__SHIFT 0x10 +#define MMVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f +#define MMVM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L +#define MMVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L + + +// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec +//MMMC_VM_NB_MMIOBASE +#define MMMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 +#define MMMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL +//MMMC_VM_NB_MMIOLIMIT +#define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 +#define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL +//MMMC_VM_NB_PCI_CTRL +#define MMMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 +#define MMMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L +//MMMC_VM_NB_PCI_ARB +#define MMMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 +#define MMMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L +//MMMC_VM_NB_TOP_OF_DRAM_SLOT1 +#define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 +#define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L +//MMMC_VM_NB_LOWER_TOP_OF_DRAM2 +#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 +#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 +#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L +#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L +//MMMC_VM_NB_UPPER_TOP_OF_DRAM2 +#define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 +#define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL +//MMMC_VM_FB_OFFSET +#define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL +//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL +//MMMC_VM_STEERING +#define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define MMMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L +//MMMC_SHARED_VIRT_RESET_REQ +#define MMMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define MMMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define MMMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define MMMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L +//MMMC_MEM_POWER_LS +#define MMMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define MMMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define MMMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define MMMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//MMMC_VM_CACHEABLE_DRAM_ADDRESS_START +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//MMMC_VM_CACHEABLE_DRAM_ADDRESS_END +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//MMMC_VM_LOCAL_SYSMEM_ADDRESS_START +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//MMMC_VM_LOCAL_SYSMEM_ADDRESS_END +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//MMMC_VM_APT_CNTL +#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 +#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 +#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x2 +#define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x4 +#define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT 0x5 +#define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT 0x6 +#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L +#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L +#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK 0x0000000CL +#define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000010L +#define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK 0x00000020L +#define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK 0x000000C0L +//MMMC_VM_LOCAL_FB_ADDRESS_START +#define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//MMMC_VM_LOCAL_FB_ADDRESS_END +#define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL +#define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L +//MMUTCL2_CGTT_CLK_CTRL +#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//MMMC_SHARED_ACTIVE_FCN_ID +#define MMMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MMMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1e +#define MMMC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define MMMC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x40000000L +//MMUTCL2_CGTT_BUSY_CTRL +#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 +#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL +#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L +//MMUTCL2_HARVEST_BYPASS_GROUPS +#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT 0x0 +#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK 0xFFFFFFFFL +//MMUTCL2_GROUP_RET_FAULT_STATUS +#define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT 0x0 +#define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec +//MMMC_VM_FB_LOCATION_BASE +#define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//MMMC_VM_FB_LOCATION_TOP +#define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//MMMC_VM_AGP_TOP +#define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define MMMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//MMMC_VM_AGP_BOT +#define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define MMMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//MMMC_VM_AGP_BASE +#define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define MMMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//MMMC_VM_SYSTEM_APERTURE_LOW_ADDR +#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR +#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//MMMC_VM_MX_L1_TLB_CNTL +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L +#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L + + +// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec +//MM_ATC_L2_PERFCOUNTER_LO +#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MM_ATC_L2_PERFCOUNTER_HI +#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec +//MM_ATC_L2_PERFCOUNTER0_CFG +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MM_ATC_L2_PERFCOUNTER1_CFG +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MM_ATC_L2_PERFCOUNTER_RSLT_CNTL +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_mmutcl2_mmvml2pspdec +//MMUTCL2_TRANSLATION_BYPASS_BY_VMID +#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT 0x0 +#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT 0x10 +#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK 0x0000FFFFL +#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK 0xFFFF0000L +//MMVM_IOMMU_CONTROL_REGISTER +#define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 +#define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L +//MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER +#define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd +#define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L +//MMUTC_TRANSLATION_FAULT_CNTL0 +#define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT 0x0 +#define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK 0xFFFFFFFFL +//MMUTC_TRANSLATION_FAULT_CNTL1 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT 0x0 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT 0x4 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT 0x5 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT 0x6 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK 0x0000000FL +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK 0x00000010L +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK 0x00000020L +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK 0x00000040L + + +// addressBlock: mmhub_mmutcl2_mml2tlbpspdec +//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT 0x0 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK 0x00000001L + + +// addressBlock: mmhub_mmutcl2_mmatcl2pspdec +//MM_ATC_L2_IOV_MODE_CNTL +#define MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN__SHIFT 0x0 +#define MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN_MASK 0x00000001L + + +// addressBlock: mmhub_mmutcl2_mml2tlbpfdec +//MML2TLB_TLB0_STATUS +#define MML2TLB_TLB0_STATUS__BUSY__SHIFT 0x0 +#define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 +#define MML2TLB_TLB0_STATUS__BUSY_MASK 0x00000001L +#define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +#define MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L +//MML2TLB_TMZ_CNTL +#define MML2TLB_TMZ_CNTL__TMZ_MODULATION__SHIFT 0x0 +#define MML2TLB_TMZ_CNTL__TMZ_MODULATION_MASK 0x00000001L +//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL +//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x8 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xc +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xd +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0xf +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x10 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x11 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x12 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1e +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00000F00L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00001000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x00006000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00008000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00010000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00020000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x07FC0000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x40000000L +//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL +//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT 0x10 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x15 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x16 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT 0x18 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1f +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK 0x00010000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x001C0000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00200000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00C00000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK 0x01000000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x80000000L +//MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ +#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 +#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE__SHIFT 0xa +#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL +#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE_MASK 0x00000400L + + +// addressBlock: mmhub_mmutcl2_mml2tlbpldec +//MML2TLB_PERFCOUNTER0_CFG +#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MML2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MML2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MML2TLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MML2TLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MML2TLB_PERFCOUNTER1_CFG +#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MML2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MML2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MML2TLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MML2TLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MML2TLB_PERFCOUNTER2_CFG +#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MML2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MML2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MML2TLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MML2TLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MML2TLB_PERFCOUNTER3_CFG +#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MML2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MML2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MML2TLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MML2TLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MML2TLB_PERFCOUNTER_RSLT_CNTL +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_mmutcl2_mml2tlbprdec +//MML2TLB_PERFCOUNTER_LO +#define MML2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MML2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MML2TLB_PERFCOUNTER_HI +#define MML2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MML2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + +#endif -- cgit v1.2.3 From 10c4ad3ae025dd0e343a09d2ea4b0e71f8d10797 Mon Sep 17 00:00:00 2001 From: Huang Rui Date: Thu, 12 May 2022 16:13:07 +0800 Subject: drm/amdgpu: add mmhub v3_0_1 ip block This adds mmhub v3_0_1 ip block support v2: rebase (Alex) Signed-off-by: Huang Rui Reviewed-by: Tim Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/Makefile | 3 +- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 4 + drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c | 555 ++++++++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.h | 28 ++ 4 files changed, 589 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 3e0e2eb7e235..a87e42c2c8dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -88,7 +88,8 @@ amdgpu-y += \ gmc_v8_0.o \ gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \ gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o mmhub_v2_3.o \ - mmhub_v1_7.o gfxhub_v3_0.o mmhub_v3_0.o mmhub_v3_0_2.o gmc_v11_0.o + mmhub_v1_7.o gfxhub_v3_0.o mmhub_v3_0.o mmhub_v3_0_2.o gmc_v11_0.o \ + mmhub_v3_0_1.o # add UMC block amdgpu-y += \ diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 7f4b480ae66e..9c225553f5b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -37,6 +37,7 @@ #include "nbio_v4_3.h" #include "gfxhub_v3_0.h" #include "mmhub_v3_0.h" +#include "mmhub_v3_0_1.h" #include "mmhub_v3_0_2.h" #include "athub_v3_0.h" @@ -548,6 +549,9 @@ static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev) static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev) { switch (adev->ip_versions[MMHUB_HWIP][0]) { + case IP_VERSION(3, 0, 1): + adev->mmhub.funcs = &mmhub_v3_0_1_funcs; + break; case IP_VERSION(3, 0, 2): adev->mmhub.funcs = &mmhub_v3_0_2_funcs; break; diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c new file mode 100644 index 000000000000..cac72ced94c8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c @@ -0,0 +1,555 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "amdgpu.h" +#include "mmhub_v3_0_1.h" + +#include "mmhub/mmhub_3_0_1_offset.h" +#include "mmhub/mmhub_3_0_1_sh_mask.h" +#include "navi10_enum.h" + +#include "soc15_common.h" + +#define regMMVM_L2_CNTL3_DEFAULT 0x80100007 +#define regMMVM_L2_CNTL4_DEFAULT 0x000000c1 +#define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0 + +static const char *mmhub_client_ids_v3_0_1[][2] = { + [0][0] = "VMC", + [4][0] = "DCEDMC", + [5][0] = "DCEVGA", + [6][0] = "MP0", + [7][0] = "MP1", + [8][0] = "MPIO", + [16][0] = "HDP", + [17][0] = "LSDMA", + [18][0] = "JPEG", + [19][0] = "VCNU0", + [21][0] = "VSCH", + [22][0] = "VCNU1", + [23][0] = "VCN1", + [32+20][0] = "VCN0", + [2][1] = "DBGUNBIO", + [3][1] = "DCEDWB", + [4][1] = "DCEDMC", + [5][1] = "DCEVGA", + [6][1] = "MP0", + [7][1] = "MP1", + [8][1] = "MPIO", + [10][1] = "DBGU0", + [11][1] = "DBGU1", + [12][1] = "DBGU2", + [13][1] = "DBGU3", + [14][1] = "XDP", + [15][1] = "OSSSYS", + [16][1] = "HDP", + [17][1] = "LSDMA", + [18][1] = "JPEG", + [19][1] = "VCNU0", + [20][1] = "VCN0", + [21][1] = "VSCH", + [22][1] = "VCNU1", + [23][1] = "VCN1", +}; + +static uint32_t mmhub_v3_0_1_get_invalidate_req(unsigned int vmid, + uint32_t flush_type) +{ + u32 req = 0; + + /* invalidate using legacy mode on vmid*/ + req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, + PER_VMID_INVALIDATE_REQ, 1 << vmid); + req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); + req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); + req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); + req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); + req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); + req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); + req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, + CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); + + return req; +} + +static void +mmhub_v3_0_1_print_l2_protection_fault_status(struct amdgpu_device *adev, + uint32_t status) +{ + uint32_t cid, rw; + const char *mmhub_cid = NULL; + + cid = REG_GET_FIELD(status, + MMVM_L2_PROTECTION_FAULT_STATUS, CID); + rw = REG_GET_FIELD(status, + MMVM_L2_PROTECTION_FAULT_STATUS, RW); + + dev_err(adev->dev, + "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", + status); + + switch (adev->ip_versions[MMHUB_HWIP][0]) { + case IP_VERSION(3, 0, 1): + mmhub_cid = mmhub_client_ids_v3_0_1[cid][rw]; + break; + default: + mmhub_cid = NULL; + break; + } + + dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", + mmhub_cid ? mmhub_cid : "unknown", cid); + dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", + REG_GET_FIELD(status, + MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); + dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", + REG_GET_FIELD(status, + MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); + dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", + REG_GET_FIELD(status, + MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); + dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", + REG_GET_FIELD(status, + MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); + dev_err(adev->dev, "\t RW: 0x%x\n", rw); +} + +static void mmhub_v3_0_1_setup_vm_pt_regs(struct amdgpu_device *adev, + uint32_t vmid, + uint64_t page_table_base) +{ + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; + + WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, + hub->ctx_addr_distance * vmid, + lower_32_bits(page_table_base)); + + WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, + hub->ctx_addr_distance * vmid, + upper_32_bits(page_table_base)); +} + +static void mmhub_v3_0_1_init_gart_aperture_regs(struct amdgpu_device *adev) +{ + uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); + + mmhub_v3_0_1_setup_vm_pt_regs(adev, 0, pt_base); + + WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, + (u32)(adev->gmc.gart_start >> 12)); + WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, + (u32)(adev->gmc.gart_start >> 44)); + + WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, + (u32)(adev->gmc.gart_end >> 12)); + WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, + (u32)(adev->gmc.gart_end >> 44)); +} + +static void mmhub_v3_0_1_init_system_aperture_regs(struct amdgpu_device *adev) +{ + uint64_t value; + uint32_t tmp; + + /* Program the AGP BAR */ + WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); + WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); + WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); + + /* + * the new L1 policy will block SRIOV guest from writing + * these regs, and they will be programed at host. + * so skip programing these regs. + */ + /* Program the system aperture low logical page number. */ + WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, + adev->gmc.vram_start >> 18); + WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, + adev->gmc.vram_end >> 18); + + /* Set default page address. */ + value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + + adev->vm_manager.vram_base_offset; + WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, + (u32)(value >> 12)); + WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, + (u32)(value >> 44)); + + /* Program "protection fault". */ + WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, + (u32)(adev->dummy_page_addr >> 12)); + WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, + (u32)((u64)adev->dummy_page_addr >> 44)); + + tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, + ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); + WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); +} + +static void mmhub_v3_0_1_init_tlb_regs(struct amdgpu_device *adev) +{ + uint32_t tmp; + + /* Setup TLB control */ + tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); + + tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); + tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); + tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, + ENABLE_ADVANCED_DRIVER_MODEL, 1); + tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, + SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); + tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); + tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, + MTYPE, MTYPE_UC); /* UC, uncached */ + + WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); +} + +static void mmhub_v3_0_1_init_cache_regs(struct amdgpu_device *adev) +{ + uint32_t tmp; + + /* Setup L2 cache */ + tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, + ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); + /* XXX for emulation, Refer to closed source code.*/ + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, + 0); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); + WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); + + tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); + WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp); + + tmp = regMMVM_L2_CNTL3_DEFAULT; + if (adev->gmc.translate_further) { + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, + L2_CACHE_BIGK_FRAGMENT_SIZE, 9); + } else { + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, + L2_CACHE_BIGK_FRAGMENT_SIZE, 6); + } + WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp); + + tmp = regMMVM_L2_CNTL4_DEFAULT; + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); + WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp); + + tmp = regMMVM_L2_CNTL5_DEFAULT; + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); + WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp); +} + +static void mmhub_v3_0_1_enable_system_domain(struct amdgpu_device *adev) +{ + uint32_t tmp; + + tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); + WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp); +} + +static void mmhub_v3_0_1_disable_identity_aperture(struct amdgpu_device *adev) +{ + WREG32_SOC15(MMHUB, 0, + regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, + 0xFFFFFFFF); + WREG32_SOC15(MMHUB, 0, + regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, + 0x0000000F); + + WREG32_SOC15(MMHUB, 0, + regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); + WREG32_SOC15(MMHUB, 0, + regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); + + WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, + 0); + WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, + 0); +} + +static void mmhub_v3_0_1_setup_vmid_config(struct amdgpu_device *adev) +{ + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; + int i; + uint32_t tmp; + + for (i = 0; i <= 14; i++) { + tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, + adev->vm_manager.num_level); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, + 1); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, + READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, + PAGE_TABLE_BLOCK_SIZE, + adev->vm_manager.block_size - 9); + /* Send no-retry XNACK on fault to suppress VM fault storm. */ + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, + !amdgpu_noretry); + WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, + i * hub->ctx_distance, tmp); + WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, + i * hub->ctx_addr_distance, 0); + WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, + i * hub->ctx_addr_distance, 0); + WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, + i * hub->ctx_addr_distance, + lower_32_bits(adev->vm_manager.max_pfn - 1)); + WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, + i * hub->ctx_addr_distance, + upper_32_bits(adev->vm_manager.max_pfn - 1)); + } + + hub->vm_cntx_cntl = tmp; +} + +static void mmhub_v3_0_1_program_invalidation(struct amdgpu_device *adev) +{ + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; + unsigned i; + + for (i = 0; i < 18; ++i) { + WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, + i * hub->eng_addr_distance, 0xffffffff); + WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, + i * hub->eng_addr_distance, 0x1f); + } +} + +static int mmhub_v3_0_1_gart_enable(struct amdgpu_device *adev) +{ + /* GART Enable. */ + mmhub_v3_0_1_init_gart_aperture_regs(adev); + mmhub_v3_0_1_init_system_aperture_regs(adev); + mmhub_v3_0_1_init_tlb_regs(adev); + mmhub_v3_0_1_init_cache_regs(adev); + + mmhub_v3_0_1_enable_system_domain(adev); + mmhub_v3_0_1_disable_identity_aperture(adev); + mmhub_v3_0_1_setup_vmid_config(adev); + mmhub_v3_0_1_program_invalidation(adev); + + return 0; +} + +static void mmhub_v3_0_1_gart_disable(struct amdgpu_device *adev) +{ + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; + u32 tmp; + u32 i; + + /* Disable all tables */ + for (i = 0; i < 16; i++) + WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL, + i * hub->ctx_distance, 0); + + /* Setup TLB control */ + tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); + tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); + tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, + ENABLE_ADVANCED_DRIVER_MODEL, 0); + WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); + + /* Setup L2 cache */ + tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); + WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); + WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0); +} + +/** + * mmhub_v3_0_1_set_fault_enable_default - update GART/VM fault handling + * + * @adev: amdgpu_device pointer + * @value: true redirects VM faults to the default page + */ +static void mmhub_v3_0_1_set_fault_enable_default(struct amdgpu_device *adev, + bool value) +{ + u32 tmp; + + tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, + PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, + PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, + TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, + value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, + NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, + READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + if (!value) { + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, + CRASH_ON_NO_RETRY_FAULT, 1); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, + CRASH_ON_RETRY_FAULT, 1); + } + WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp); +} + +static const struct amdgpu_vmhub_funcs mmhub_v3_0_1_vmhub_funcs = { + .print_l2_protection_fault_status = mmhub_v3_0_1_print_l2_protection_fault_status, + .get_invalidate_req = mmhub_v3_0_1_get_invalidate_req, +}; + +static void mmhub_v3_0_1_init(struct amdgpu_device *adev) +{ + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; + + hub->ctx0_ptb_addr_lo32 = + SOC15_REG_OFFSET(MMHUB, 0, + regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); + hub->ctx0_ptb_addr_hi32 = + SOC15_REG_OFFSET(MMHUB, 0, + regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); + hub->vm_inv_eng0_sem = + SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM); + hub->vm_inv_eng0_req = + SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ); + hub->vm_inv_eng0_ack = + SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK); + hub->vm_context0_cntl = + SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL); + hub->vm_l2_pro_fault_status = + SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS); + hub->vm_l2_pro_fault_cntl = + SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); + + hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL; + hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - + regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; + hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ - + regMMVM_INVALIDATE_ENG0_REQ; + hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - + regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; + + hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; + + hub->vmhub_funcs = &mmhub_v3_0_1_vmhub_funcs; +} + +static u64 mmhub_v3_0_1_get_fb_location(struct amdgpu_device *adev) +{ + u64 base; + + base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); + base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; + base <<= 24; + + return base; +} + +static u64 mmhub_v3_0_1_get_mc_fb_offset(struct amdgpu_device *adev) +{ + return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; +} + +static void mmhub_v3_0_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, + bool enable) +{ + //TODO +} + +static void mmhub_v3_0_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, + bool enable) +{ + //TODO +} + +static int mmhub_v3_0_1_set_clockgating(struct amdgpu_device *adev, + enum amd_clockgating_state state) +{ + mmhub_v3_0_1_update_medium_grain_clock_gating(adev, + state == AMD_CG_STATE_GATE); + mmhub_v3_0_1_update_medium_grain_light_sleep(adev, + state == AMD_CG_STATE_GATE); + return 0; +} + +static void mmhub_v3_0_1_get_clockgating(struct amdgpu_device *adev, u64 *flags) +{ + //TODO +} + +const struct amdgpu_mmhub_funcs mmhub_v3_0_1_funcs = { + .init = mmhub_v3_0_1_init, + .get_fb_location = mmhub_v3_0_1_get_fb_location, + .get_mc_fb_offset = mmhub_v3_0_1_get_mc_fb_offset, + .gart_enable = mmhub_v3_0_1_gart_enable, + .set_fault_enable_default = mmhub_v3_0_1_set_fault_enable_default, + .gart_disable = mmhub_v3_0_1_gart_disable, + .set_clockgating = mmhub_v3_0_1_set_clockgating, + .get_clockgating = mmhub_v3_0_1_get_clockgating, + .setup_vm_pt_regs = mmhub_v3_0_1_setup_vm_pt_regs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.h new file mode 100644 index 000000000000..4c1246735e7d --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.h @@ -0,0 +1,28 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __MMHUB_V3_0_1_H__ +#define __MMHUB_V3_0_1_H__ + +extern const struct amdgpu_mmhub_funcs mmhub_v3_0_1_funcs; + +#endif -- cgit v1.2.3 From 8763e4c1a0e6710dccb8fccba96fcd6caaa50cae Mon Sep 17 00:00:00 2001 From: Huang Rui Date: Tue, 17 May 2022 14:58:41 +0800 Subject: drm/amdgpu/pm: update MP v13_0_4 smu message register marco Update MP v13_0_4 register macro for SMU message v2: squash in missed case (Alex) Signed-off-by: Huang Rui Reviewed-by: Tim Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 5de7da75d14a..5215ead4978f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -51,6 +51,15 @@ #define mmMP1_SMN_C2PMSG_90 0x029a #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_66_V13_0_4 0x0282 +#define mmMP1_SMN_C2PMSG_66_V13_0_4_BASE_IDX 1 + +#define mmMP1_SMN_C2PMSG_82_V13_0_4 0x0292 +#define mmMP1_SMN_C2PMSG_82_V13_0_4_BASE_IDX 1 + +#define mmMP1_SMN_C2PMSG_90_V13_0_4 0x029a +#define mmMP1_SMN_C2PMSG_90_V13_0_4_BASE_IDX 1 + /* SMU 13.0.5 has its specific mailbox messaging registers */ #define mmMP1_C2PMSG_2 (0xbee142 + 0xb00000 / 4) @@ -92,6 +101,8 @@ static void smu_cmn_read_arg(struct smu_context *smu, if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) *arg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34); + else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) + *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4); else *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); } @@ -141,6 +152,8 @@ static u32 __smu_cmn_poll_stat(struct smu_context *smu) for ( ; timeout > 0; timeout--) { if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) reg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33); + else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) + reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90_V13_0_4); else reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0) @@ -167,6 +180,9 @@ static void __smu_cmn_reg_print_error(struct smu_context *smu, if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) { msg_idx = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2); prm = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34); + } else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) { + msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66_V13_0_4); + prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4); } else { msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66); prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); @@ -268,6 +284,10 @@ static void __smu_cmn_send_msg(struct smu_context *smu, WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33, 0); WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34, param); WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2, msg); + } else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) { + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90_V13_0_4, 0); + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4, param); + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66_V13_0_4, msg); } else { WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param); -- cgit v1.2.3 From 7101ab97e3b00ec1c68d09826bb0521d17783673 Mon Sep 17 00:00:00 2001 From: Huang Rui Date: Wed, 18 May 2022 21:19:32 +0800 Subject: drm/amdgpu/pm: implement the SMU_MSG_EnableGfxImu function GC v11_0_1 asic needs to issue the EnableGfxImu message after start IMU. Signed-off-by: Huang Rui Reviewed-by: Tim Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 14 ++++++++++++++ drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 2 ++ drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 9 ++++++++- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 7 +++++++ drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 2 ++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 10 ++++++++++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 1 + 7 files changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index d1bf073adf54..956b6ce81c84 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -107,6 +107,20 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block return ret; } +int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev) +{ + struct smu_context *smu = adev->powerplay.pp_handle; + int ret = -EOPNOTSUPP; + + mutex_lock(&adev->pm.mutex); + ret = smu_set_gfx_power_up_by_imu(smu); + mutex_unlock(&adev->pm.mutex); + + msleep(10); + + return ret; +} + int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h index 3e78b3057277..524fb09437e5 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h @@ -386,6 +386,8 @@ int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev); int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, enum pp_mp1_state mp1_state); +int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev); + int amdgpu_dpm_baco_exit(struct amdgpu_device *adev); int amdgpu_dpm_baco_enter(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index a601024ba4de..ae595ee544dc 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -134,6 +134,14 @@ int smu_get_dpm_freq_range(struct smu_context *smu, return ret; } +int smu_set_gfx_power_up_by_imu(struct smu_context *smu) +{ + if (!smu->ppt_funcs && !smu->ppt_funcs->set_gfx_power_up_by_imu) + return -EOPNOTSUPP; + + return smu->ppt_funcs->set_gfx_power_up_by_imu(smu); +} + static u32 smu_get_mclk(void *handle, bool low) { struct smu_context *smu = handle; @@ -2467,7 +2475,6 @@ static int smu_set_power_profile_mode(void *handle, return smu_bump_power_profile_mode(smu, param, param_size); } - static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) { struct smu_context *smu = handle; diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index a6a7b6c33683..c3d5a616e572 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -697,6 +697,11 @@ struct pptable_funcs { */ int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable); + /** + * @set_gfx_power_up_by_imu: Enable GFX engine with IMU + */ + int (*set_gfx_power_up_by_imu)(struct smu_context *smu); + /** * @read_sensor: Read data from a sensor. * &sensor: Sensor to read data from. @@ -1438,6 +1443,8 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); +int smu_set_gfx_power_up_by_imu(struct smu_context *smu); + int smu_set_ac_dc(struct smu_context *smu); int smu_allow_xgmi_power_down(struct smu_context *smu, bool en); diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h index 036fd2810ecc..08270d8528d9 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h @@ -292,6 +292,8 @@ int smu_v13_0_baco_enter(struct smu_context *smu); int smu_v13_0_baco_exit(struct smu_context *smu); +int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu); + int smu_v13_0_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 7be4f6875a7b..a56dddc9fb88 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -2297,6 +2297,16 @@ int smu_v13_0_baco_exit(struct smu_context *smu) SMU_BACO_STATE_EXIT); } +int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu) +{ + uint16_t index; + + index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, + SMU_MSG_EnableGfxImu); + + return smu_cmn_send_msg_without_waiting(smu, index, 0); +} + int smu_v13_0_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c index 5a17b51aa0f9..29fcce04a91a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c @@ -1030,6 +1030,7 @@ static const struct pptable_funcs smu_v13_0_4_ppt_funcs = { .force_clk_levels = smu_v13_0_4_force_clk_levels, .set_performance_level = smu_v13_0_4_set_performance_level, .set_fine_grain_gfx_freq_parameters = smu_v13_0_4_set_fine_grain_gfx_freq_parameters, + .set_gfx_power_up_by_imu = smu_v13_0_set_gfx_power_up_by_imu, }; void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu) -- cgit v1.2.3 From 80d46fff373775fdea9917a7d13f6fb6fa5147ad Mon Sep 17 00:00:00 2001 From: Huang Rui Date: Wed, 18 May 2022 22:05:03 +0800 Subject: drm/amdgpu: add apu sequence in the imu v11 APU required to issue the enable GFX IMU message after IMU reset. Signed-off-by: Huang Rui Reviewed-by: Tim Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 +++++- drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 7 ++++--- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index abe22749cccc..5f20b41bcb93 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6292,7 +6292,11 @@ static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) { - adev->gfx.imu.mode = DEBUG_MODE; + if (adev->flags & AMD_IS_APU) + adev->gfx.imu.mode = MISSION_MODE; + else + adev->gfx.imu.mode = DEBUG_MODE; + adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; } diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c index fd053158abbd..76383baa3929 100644 --- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c @@ -24,6 +24,7 @@ #include #include "amdgpu.h" #include "amdgpu_imu.h" +#include "amdgpu_dpm.h" #include "gc/gc_11_0_0_offset.h" #include "gc/gc_11_0_0_sh_mask.h" @@ -165,10 +166,10 @@ static int imu_v11_0_start(struct amdgpu_device *adev) imu_reg_val &= 0xfffffffe; WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val); - if (adev->gfx.imu.mode == DEBUG_MODE) - return imu_v11_0_wait_for_reset_status(adev); + if (adev->flags & AMD_IS_APU) + amdgpu_dpm_set_gfx_power_up_by_imu(adev); - return 0; + return imu_v11_0_wait_for_reset_status(adev); } static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11[] = -- cgit v1.2.3 From cb12d72b426caa7594890c62df69fe4b83c96e58 Mon Sep 17 00:00:00 2001 From: Xiaojian Du Date: Fri, 20 May 2022 22:27:57 +0800 Subject: drm/amdgpu: add CSDMA reg offsets for NBIO v7.7.0 This patch will add CSDMA reg offsets for NBIO v7.7.0 Signed-off-by: Xiaojian Du Acked-by: Roman Li Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_offset.h | 4 ++++ drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_offset.h index 162d9017b238..2ed95790a600 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_offset.h @@ -4005,6 +4005,8 @@ #define regGDC0_BIF_VCN0_DOORBELL_RANGE_BASE_IDX 3 #define regGDC0_BIF_RLC_DOORBELL_RANGE 0x4f0af5 #define regGDC0_BIF_RLC_DOORBELL_RANGE_BASE_IDX 3 +#define regGDC0_BIF_CSDMA_DOORBELL_RANGE 0x4f0afb +#define regGDC0_BIF_CSDMA_DOORBELL_RANGE_BASE_IDX 3 #define regGDC0_ATDMA_MISC_CNTL 0x4f0afd #define regGDC0_ATDMA_MISC_CNTL_BASE_IDX 3 #define regGDC0_BIF_DOORBELL_FENCE_CNTL 0x4f0afe @@ -21535,6 +21537,8 @@ #define regGDC1_BIF_SDMA4_DOORBELL_RANGE_BASE_IDX 5 #define regGDC1_BIF_SDMA5_DOORBELL_RANGE 0x2ffc0efa #define regGDC1_BIF_SDMA5_DOORBELL_RANGE_BASE_IDX 5 +#define regGDC1_BIF_CSDMA_DOORBELL_RANGE 0x2ffc0efb +#define regGDC1_BIF_CSDMA_DOORBELL_RANGE_BASE_IDX 5 #define regGDC1_ATDMA_MISC_CNTL 0x2ffc0efd #define regGDC1_ATDMA_MISC_CNTL_BASE_IDX 5 #define regGDC1_BIF_DOORBELL_FENCE_CNTL 0x2ffc0efe diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h index cc3f04cfdbf7..eb62a18fcc48 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h @@ -31641,6 +31641,11 @@ #define GDC0_BIF_RLC_DOORBELL_RANGE__SIZE__SHIFT 0x10 #define GDC0_BIF_RLC_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL #define GDC0_BIF_RLC_DOORBELL_RANGE__SIZE_MASK 0x001F0000L +//GDC0_BIF_CSDMA_DOORBELL_RANGE +#define GDC0_BIF_CSDMA_DOORBELL_RANGE__OFFSET__SHIFT 0x2 +#define GDC0_BIF_CSDMA_DOORBELL_RANGE__SIZE__SHIFT 0x10 +#define GDC0_BIF_CSDMA_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL +#define GDC0_BIF_CSDMA_DOORBELL_RANGE__SIZE_MASK 0x00FF0000L //GDC0_ATDMA_MISC_CNTL #define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0 #define GDC0_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1 @@ -119765,6 +119770,11 @@ #define GDC1_BIF_SDMA5_DOORBELL_RANGE__SIZE__SHIFT 0x10 #define GDC1_BIF_SDMA5_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL #define GDC1_BIF_SDMA5_DOORBELL_RANGE__SIZE_MASK 0x001F0000L +//GDC1_BIF_CSDMA_DOORBELL_RANGE +#define GDC1_BIF_CSDMA_DOORBELL_RANGE__OFFSET__SHIFT 0x2 +#define GDC1_BIF_CSDMA_DOORBELL_RANGE__SIZE__SHIFT 0x10 +#define GDC1_BIF_CSDMA_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL +#define GDC1_BIF_CSDMA_DOORBELL_RANGE__SIZE_MASK 0x00FF0000L //GDC1_ATDMA_MISC_CNTL #define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0 #define GDC1_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1 -- cgit v1.2.3 From 72b5f23ccb0aee46029476cbb072074384aef591 Mon Sep 17 00:00:00 2001 From: Xiaojian Du Date: Fri, 20 May 2022 21:33:29 +0800 Subject: drm/amdgpu: fix sdma doorbell issue on SDMA v6.0 and NBIO v7.7 This patch will fix sdma doorbell issue on SDMA v6.0 and NBIO v7.7.0. NBIO v7.7.0 uses a new reg function -- Common SDMA to allow a common doorbell range for all SDMA queues, this is different to the old NBIO version. This patch will add configuration for CSDMA and enable SDMA doorbell function. Signed-off-by: Xiaojian Du Reviewed-by: Tim Huang Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c index cdc0c9779848..e786b825cea9 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c @@ -58,10 +58,16 @@ static void nbio_v7_7_sdma_doorbell_range(struct amdgpu_device *adev, int instan bool use_doorbell, int doorbell_index, int doorbell_size) { - u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE); + u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_CSDMA_DOORBELL_RANGE); u32 doorbell_range = RREG32_PCIE_PORT(reg); if (use_doorbell) { + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC0_BIF_CSDMA_DOORBELL_RANGE, + OFFSET, doorbell_index); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC0_BIF_CSDMA_DOORBELL_RANGE, + SIZE, doorbell_size); doorbell_range = REG_SET_FIELD(doorbell_range, GDC0_BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); -- cgit v1.2.3 From 3ccb9ea9976022034d8fffd8d929d6e70a24e0c6 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Thu, 14 Apr 2022 17:03:28 -0400 Subject: drm/amd/display: Add additional guard for FCLK pstate message for DCN321 Signed-off-by: Dillon Varone Signed-off-by: Fangzhi Zuo Acked-by: Aurabindo Pillai Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 93fbecbc8065..9d2d2cda5543 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -346,8 +346,8 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); } - if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) && - clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21) { + if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && + should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) { clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support; /* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */ @@ -368,7 +368,8 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support)) dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); - if (clk_mgr_base->clks.fclk_p_state_change_support && + if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && + clk_mgr_base->clks.fclk_p_state_change_support && (update_uclk || !clk_mgr_base->clks.fclk_prev_p_state_change_support)) { /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */ dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED); -- cgit v1.2.3 From 2388a778bdacad0c936dbb01048362864847f8ad Mon Sep 17 00:00:00 2001 From: Fangzhi Zuo Date: Tue, 19 Apr 2022 15:49:48 -0400 Subject: drm/amd/display: Halve DTB Clock Value for DCN32 VBIOS default clock value was halved, so the hardcoded dtb value should be halved as well. dtb clock should come from SMU eventually, but now dtb clock switching is not fully supported yet in SMU. Halve the dtb hardcoded value for now to have UHBR10 light up. Will rely on SMU for dtb clock switching once available. The w/a is for DCN32 only, DCN321 should adopt the original value. Signed-off-by: Fangzhi Zuo Acked-by: Aurabindo Pillai Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 9d2d2cda5543..774de29fa532 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -599,7 +599,7 @@ void dcn32_clk_mgr_construct( clk_mgr->dfs_ref_freq_khz = 100000; clk_mgr->base.dprefclk_khz = 717000; /* Changed as per DCN3.2_clock_frequency doc */ - clk_mgr->dccg->ref_dtbclk_khz = 477800; + clk_mgr->dccg->ref_dtbclk_khz = 268750; /* integer part is now VCO frequency in kHz */ clk_mgr->base.dentist_vco_freq_khz = 4300000;//dcn32_get_vco_frequency_from_reg(clk_mgr); -- cgit v1.2.3 From 9d6b2041761ff6d5a33941919c8b5a805ecbed6c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 24 May 2022 10:02:16 -0400 Subject: drm/amdgpu: convert sienna_cichlid_populate_umd_state_clk() to use IP version Rather than asic type. Reviewed-by: Guchun Chen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 6b452e3f5ee3..1c5ce9c5cba9 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -1464,19 +1464,19 @@ static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu) pstate_table->socclk_pstate.min = soc_table->min; pstate_table->socclk_pstate.peak = soc_table->max; - switch (adev->asic_type) { - case CHIP_SIENNA_CICHLID: - case CHIP_NAVY_FLOUNDER: + switch (adev->ip_versions[MP1_HWIP][0]) { + case IP_VERSION(11, 0, 7): + case IP_VERSION(11, 0, 11): pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK; pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK; pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK; break; - case CHIP_DIMGREY_CAVEFISH: + case IP_VERSION(11, 0, 12): pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK; pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK; pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK; break; - case CHIP_BEIGE_GOBY: + case IP_VERSION(11, 0, 13): pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK; pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK; pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK; -- cgit v1.2.3 From 1d6c363330834fa534c1c7ee01620ff134aade1f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 24 May 2022 09:55:51 -0400 Subject: drm/amdgpu: simplify the logic in amdgpu_device_parse_gpu_info_fw() Drop all of the extra cases in the default case. Reviewed-by: Guchun Chen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29 ----------------------------- 1 file changed, 29 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index e9155dc1c30c..00ed666811b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1942,35 +1942,6 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) } switch (adev->asic_type) { -#ifdef CONFIG_DRM_AMDGPU_SI - case CHIP_VERDE: - case CHIP_TAHITI: - case CHIP_PITCAIRN: - case CHIP_OLAND: - case CHIP_HAINAN: -#endif -#ifdef CONFIG_DRM_AMDGPU_CIK - case CHIP_BONAIRE: - case CHIP_HAWAII: - case CHIP_KAVERI: - case CHIP_KABINI: - case CHIP_MULLINS: -#endif - case CHIP_TOPAZ: - case CHIP_TONGA: - case CHIP_FIJI: - case CHIP_POLARIS10: - case CHIP_POLARIS11: - case CHIP_POLARIS12: - case CHIP_VEGAM: - case CHIP_CARRIZO: - case CHIP_STONEY: - case CHIP_VEGA20: - case CHIP_ALDEBARAN: - case CHIP_SIENNA_CICHLID: - case CHIP_NAVY_FLOUNDER: - case CHIP_DIMGREY_CAVEFISH: - case CHIP_BEIGE_GOBY: default: return 0; case CHIP_VEGA10: -- cgit v1.2.3 From be77243327d962a87bcf03615bae12d73efb9b7c Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Mon, 18 Apr 2022 14:39:20 -0400 Subject: drm/amd/display: set dram speed for all states [WHY?] If higher states have memory speed set to 0 MT/s currently they do not get set to the highest value which can cause validation failures. [HOW?] Set unpopulated higher states to max value. Signed-off-by: Dillon Varone Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 6 +++++- drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c index 7772beadd000..3f93b1f2d872 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c @@ -3549,7 +3549,6 @@ static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw dcn3_2_soc.clock_limits[i].state = i; dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; - dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; /* Fill all states with max values of all these clocks */ dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; @@ -3568,6 +3567,11 @@ static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw else dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; + if (!dram_speed_mts[i] && i > 0) + dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts; + else + dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; + /* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */ /* PHYCLK_D18, PHYCLK_D32 */ dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz; diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c index 0b420466b6dd..27d3aa7d751f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c @@ -1899,7 +1899,6 @@ static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b dcn3_21_soc.clock_limits[i].state = i; dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; dcn3_21_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; - dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; /* Fill all states with max values of all these clocks */ dcn3_21_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; @@ -1918,6 +1917,11 @@ static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b else dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; + if (!dram_speed_mts[i] && i > 0) + dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts; + else + dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; + /* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */ /* PHYCLK_D18, PHYCLK_D32 */ dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz; -- cgit v1.2.3 From ac1ac694f7173a0fbb0b60ab0f26226dd334479a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 24 May 2022 10:27:33 -0400 Subject: drm/amdgpu: convert nbio_v2_3_clear_doorbell_interrupt() to IP version Check IP version rather than asic type. Reviewed-by: Guchun Chen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c index 6cd1fb2eb913..34c610b9157d 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c @@ -547,7 +547,7 @@ static void nbio_v2_3_clear_doorbell_interrupt(struct amdgpu_device *adev) { uint32_t reg, reg_data; - if (adev->asic_type != CHIP_SIENNA_CICHLID) + if (adev->ip_versions[NBIO_HWIP][0] != IP_VERSION(3, 3, 0)) return; reg = RREG32_SOC15(NBIO, 0, mmBIF_RB_CNTL); -- cgit v1.2.3 From 2cfe34e18970d26bff73c63f16c76dae22138d19 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 26 May 2022 12:48:51 -0400 Subject: drm/amdgpu/gmc11: enable AGP aperture MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the AGP aperture on chips with GMC v11. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c | 7 ++++--- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 1 + drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c | 6 +++--- 4 files changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c index 5eccaa2c7ca0..f99d7641bb21 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c @@ -154,10 +154,11 @@ static void gfxhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev) { uint64_t value; - /* Disable AGP. */ + /* Program the AGP BAR */ WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); - WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, 0); - WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, 0x00FFFFFF); + WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); + WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); + /* Program the system aperture low logical page number. */ WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 9c225553f5b5..454a25cc0046 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -611,6 +611,7 @@ static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, amdgpu_gmc_vram_location(adev, &adev->gmc, base); amdgpu_gmc_gart_location(adev, mc); + amdgpu_gmc_agp_location(adev, mc); /* base offset of vram pages */ adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c index bc11b2de37ae..4926fa82c1c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c @@ -169,10 +169,10 @@ static void mmhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev) uint64_t value; uint32_t tmp; - /* Disable AGP. */ + /* Program the AGP BAR */ WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); - WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0); - WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF); + WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); + WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); if (!amdgpu_sriov_vf(adev)) { /* diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c index 770be0a8f7ce..5e5b884d8357 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c @@ -162,10 +162,10 @@ static void mmhub_v3_0_2_init_system_aperture_regs(struct amdgpu_device *adev) uint64_t value; uint32_t tmp; - /* Disable AGP. */ + /* Program the AGP BAR */ WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); - WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0); - WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF); + WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); + WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); if (!amdgpu_sriov_vf(adev)) { /* -- cgit v1.2.3 From 2267a195e28cc438cb45936c4562f958502d4038 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Wed, 13 Apr 2022 17:54:19 -0400 Subject: drm/amd/display: Disable DTB Ref Clock Switching in dcn32 [How & Why] To be enabled once PMFW supports it. Signed-off-by: Dillon Varone Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 774de29fa532..f147c65137c6 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -607,6 +607,10 @@ void dcn32_clk_mgr_construct( if (clk_mgr->base.dentist_vco_freq_khz == 0) clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */ + if (clk_mgr->dccg->ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) { + clk_mgr->dccg->ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk; + } + if (clk_mgr->base.boot_snapshot.dprefclk != 0) { //ASSERT(clk_mgr->base.dprefclk_khz == clk_mgr->base.boot_snapshot.dprefclk); //clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk; -- cgit v1.2.3 From da1db031cd30fefc99d1c82211d3c24b73857bbe Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 26 May 2022 11:55:36 -0400 Subject: drm/amdgpu/swsmu: add SMU mailbox registers in SMU context So we can eventaully use them in the common smu code for accessing the SMU mailboxes without needing a lot of per asic logic in the common code. Reviewed-by: Yang Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 4 ++++ drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h | 2 ++ drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 2 ++ drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 1 + .../gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 1 + drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 1 + .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 1 + drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 9 +++++++++ drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 1 + drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 14 ++++++++++++++ drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 1 + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 18 ++++++++++++++++++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1 + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 14 ++++++++++++++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 14 ++++++++++++++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 1 + drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 1 + 17 files changed, 86 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index c3d5a616e572..6d51e4340aad 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -563,6 +563,10 @@ struct smu_context struct stb_context stb_context; struct firmware pptable_firmware; + + u32 param_reg; + u32 msg_reg; + u32 resp_reg; }; struct i2c_adapter; diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h index acb3be292096..a9215494dcdd 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h @@ -316,5 +316,7 @@ int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable); int smu_v11_0_restore_user_od_settings(struct smu_context *smu); +void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu); + #endif #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h index 08270d8528d9..fe9c47c87abc 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h @@ -300,5 +300,7 @@ int smu_v13_0_od_edit_dpm_table(struct smu_context *smu, uint32_t size); int smu_v13_0_set_default_dpm_tables(struct smu_context *smu); + +void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu); #endif #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c index 201563072189..bfabcd3c45aa 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c @@ -2509,4 +2509,5 @@ void arcturus_set_ppt_funcs(struct smu_context *smu) smu->table_map = arcturus_table_map; smu->pwr_src_map = arcturus_pwr_src_map; smu->workload_map = arcturus_workload_map; + smu_v11_0_set_smu_mailbox_registers(smu); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c index f1a4a720d426..ca4d97b7f576 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c @@ -591,4 +591,5 @@ void cyan_skillfish_set_ppt_funcs(struct smu_context *smu) smu->message_map = cyan_skillfish_message_map; smu->table_map = cyan_skillfish_table_map; smu->is_apu = true; + smu_v11_0_set_smu_mailbox_registers(smu); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index 5f22fc3430f4..0bcd4fe0ef17 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -3580,4 +3580,5 @@ void navi10_set_ppt_funcs(struct smu_context *smu) smu->table_map = navi10_table_map; smu->pwr_src_map = navi10_pwr_src_map; smu->workload_map = navi10_workload_map; + smu_v11_0_set_smu_mailbox_registers(smu); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 1c5ce9c5cba9..b71860e5324a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -4357,4 +4357,5 @@ void sienna_cichlid_set_ppt_funcs(struct smu_context *smu) smu->table_map = sienna_cichlid_table_map; smu->pwr_src_map = sienna_cichlid_pwr_src_map; smu->workload_map = sienna_cichlid_workload_map; + smu_v11_0_set_smu_mailbox_registers(smu); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index b87f550af26b..974b8fe1dbb6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -2197,3 +2197,12 @@ int smu_v11_0_restore_user_od_settings(struct smu_context *smu) return ret; } + +void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + + smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); + smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); + smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index 5551e1426ef5..e2d8ac90cf36 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -2213,4 +2213,5 @@ void vangogh_set_ppt_funcs(struct smu_context *smu) smu->table_map = vangogh_table_map; smu->workload_map = vangogh_workload_map; smu->is_apu = true; + smu_v11_0_set_smu_mailbox_registers(smu); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c index 012e3bd99cc2..85e22210963f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c @@ -41,6 +41,15 @@ #undef pr_info #undef pr_debug +#define mmMP1_SMN_C2PMSG_66 0x0282 +#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 + +#define mmMP1_SMN_C2PMSG_82 0x0292 +#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 + +#define mmMP1_SMN_C2PMSG_90 0x029a +#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 + static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), @@ -1447,6 +1456,8 @@ static const struct pptable_funcs renoir_ppt_funcs = { void renoir_set_ppt_funcs(struct smu_context *smu) { + struct amdgpu_device *adev = smu->adev; + smu->ppt_funcs = &renoir_ppt_funcs; smu->message_map = renoir_message_map; smu->clock_map = renoir_clk_map; @@ -1454,4 +1465,7 @@ void renoir_set_ppt_funcs(struct smu_context *smu) smu->workload_map = renoir_workload_map; smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION; smu->is_apu = true; + smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); + smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); + smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index bb3c23821323..1133edd34e4d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -2147,4 +2147,5 @@ void aldebaran_set_ppt_funcs(struct smu_context *smu) smu->clock_map = aldebaran_clk_map; smu->feature_map = aldebaran_feature_mask_map; smu->table_map = aldebaran_table_map; + smu_v13_0_set_smu_mailbox_registers(smu); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index a56dddc9fb88..6db10e49db7e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -60,6 +60,15 @@ MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin"); MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin"); MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin"); +#define mmMP1_SMN_C2PMSG_66 0x0282 +#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 + +#define mmMP1_SMN_C2PMSG_82 0x0292 +#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 + +#define mmMP1_SMN_C2PMSG_90 0x029a +#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 + #define SMU13_VOLTAGE_SCALE 4 #define LINK_WIDTH_MAX 6 @@ -2396,3 +2405,12 @@ int smu_v13_0_set_default_dpm_tables(struct smu_context *smu) return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); } + +void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + + smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); + smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); + smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index 5c74a72577c6..418480e0c077 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -1651,4 +1651,5 @@ void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu) smu->table_map = smu_v13_0_0_table_map; smu->pwr_src_map = smu_v13_0_0_pwr_src_map; smu->workload_map = smu_v13_0_0_workload_map; + smu_v13_0_set_smu_mailbox_registers(smu); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c index 29fcce04a91a..196670345552 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c @@ -43,6 +43,15 @@ #undef pr_info #undef pr_debug +#define mmMP1_SMN_C2PMSG_66 0x0282 +#define mmMP1_SMN_C2PMSG_66_BASE_IDX 1 + +#define mmMP1_SMN_C2PMSG_82 0x0292 +#define mmMP1_SMN_C2PMSG_82_BASE_IDX 1 + +#define mmMP1_SMN_C2PMSG_90 0x029a +#define mmMP1_SMN_C2PMSG_90_BASE_IDX 1 + #define FEATURE_MASK(feature) (1ULL << feature) #define SMC_DPM_FEATURE ( \ @@ -1035,9 +1044,14 @@ static const struct pptable_funcs smu_v13_0_4_ppt_funcs = { void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu) { + struct amdgpu_device *adev = smu->adev; + smu->ppt_funcs = &smu_v13_0_4_ppt_funcs; smu->message_map = smu_v13_0_4_message_map; smu->feature_map = smu_v13_0_4_feature_mask_map; smu->table_map = smu_v13_0_4_table_map; smu->is_apu = true; + smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); + smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); + smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c index b81711c4ff33..47360ef5c175 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c @@ -42,6 +42,15 @@ #undef pr_info #undef pr_debug +#define mmMP1_C2PMSG_2 (0xbee142 + 0xb00000 / 4) +#define mmMP1_C2PMSG_2_BASE_IDX 0 + +#define mmMP1_C2PMSG_34 (0xbee262 + 0xb00000 / 4) +#define mmMP1_C2PMSG_34_BASE_IDX 0 + +#define mmMP1_C2PMSG_33 (0xbee261 + 0xb00000 / 4) +#define mmMP1_C2PMSG_33_BASE_IDX 0 + #define FEATURE_MASK(feature) (1ULL << feature) #define SMC_DPM_FEATURE ( \ FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -1049,9 +1058,14 @@ static const struct pptable_funcs smu_v13_0_5_ppt_funcs = { void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu) { + struct amdgpu_device *adev = smu->adev; + smu->ppt_funcs = &smu_v13_0_5_ppt_funcs; smu->message_map = smu_v13_0_5_message_map; smu->feature_map = smu_v13_0_5_feature_mask_map; smu->table_map = smu_v13_0_5_table_map; smu->is_apu = true; + smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_34); + smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_2); + smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_33); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index 4e1861fb2c6a..bdea7bca3805 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -1594,4 +1594,5 @@ void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu) smu->table_map = smu_v13_0_7_table_map; smu->pwr_src_map = smu_v13_0_7_pwr_src_map; smu->workload_map = smu_v13_0_7_workload_map; + smu_v13_0_set_smu_mailbox_registers(smu); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c index feff4f8c927c..70cbc46341a3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c @@ -1203,4 +1203,5 @@ void yellow_carp_set_ppt_funcs(struct smu_context *smu) smu->feature_map = yellow_carp_feature_mask_map; smu->table_map = yellow_carp_table_map; smu->is_apu = true; + smu_v13_0_set_smu_mailbox_registers(smu); } -- cgit v1.2.3 From 3378aed7e2ec7212889116335a2120a6e35c80ce Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Mon, 11 Apr 2022 10:29:57 -0400 Subject: drm/amd/display: change dsc image width cap for dcn32 and dcn321 Set appropriate caps for DCN3.2.x. Signed-off-by: Dillon Varone Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 3 +++ drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c index 3f93b1f2d872..f2850071478c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c @@ -1695,6 +1695,9 @@ static struct display_stream_compressor *dcn32_dsc_create( } dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); + + dsc->max_image_width = 6016; + return &dsc->base; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c index 27d3aa7d751f..376dd586b643 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c @@ -1679,6 +1679,9 @@ static struct display_stream_compressor *dcn321_dsc_create( } dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); + + dsc->max_image_width = 6016; + return &dsc->base; } -- cgit v1.2.3 From 7a09f61f8e842dd027afa1ce8be8bd86062c8a7b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 26 May 2022 12:04:38 -0400 Subject: drm/amdgpu/swsmu: use new register offsets for smu_cmn.c Use the per asic offsets so the we don't have to have asic specific logic in the common code. Reviewed-by: Luben Tuikov Reviewed-by: Yang Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 77 ++++------------------------------ 1 file changed, 7 insertions(+), 70 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 5215ead4978f..53cd62ccab5d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -37,40 +37,6 @@ #undef pr_info #undef pr_debug -/* - * Although these are defined in each ASIC's specific header file. - * They share the same definitions and values. That makes common - * APIs for SMC messages issuing for all ASICs possible. - */ -#define mmMP1_SMN_C2PMSG_66 0x0282 -#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 - -#define mmMP1_SMN_C2PMSG_82 0x0292 -#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 - -#define mmMP1_SMN_C2PMSG_90 0x029a -#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 - -#define mmMP1_SMN_C2PMSG_66_V13_0_4 0x0282 -#define mmMP1_SMN_C2PMSG_66_V13_0_4_BASE_IDX 1 - -#define mmMP1_SMN_C2PMSG_82_V13_0_4 0x0292 -#define mmMP1_SMN_C2PMSG_82_V13_0_4_BASE_IDX 1 - -#define mmMP1_SMN_C2PMSG_90_V13_0_4 0x029a -#define mmMP1_SMN_C2PMSG_90_V13_0_4_BASE_IDX 1 - -/* SMU 13.0.5 has its specific mailbox messaging registers */ - -#define mmMP1_C2PMSG_2 (0xbee142 + 0xb00000 / 4) -#define mmMP1_C2PMSG_2_BASE_IDX 0 - -#define mmMP1_C2PMSG_34 (0xbee262 + 0xb00000 / 4) -#define mmMP1_C2PMSG_34_BASE_IDX 0 - -#define mmMP1_C2PMSG_33 (0xbee261 + 0xb00000 / 4) -#define mmMP1_C2PMSG_33_BASE_IDX 0 - #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL #undef __SMU_DUMMY_MAP @@ -99,12 +65,7 @@ static void smu_cmn_read_arg(struct smu_context *smu, { struct amdgpu_device *adev = smu->adev; - if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) - *arg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34); - else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) - *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4); - else - *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); + *arg = RREG32(smu->param_reg); } /* Redefine the SMU error codes here. @@ -150,12 +111,7 @@ static u32 __smu_cmn_poll_stat(struct smu_context *smu) u32 reg; for ( ; timeout > 0; timeout--) { - if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) - reg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33); - else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) - reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90_V13_0_4); - else - reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); + reg = RREG32(smu->resp_reg); if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0) break; @@ -177,16 +133,8 @@ static void __smu_cmn_reg_print_error(struct smu_context *smu, switch (reg_c2pmsg_90) { case SMU_RESP_NONE: { - if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) { - msg_idx = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2); - prm = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34); - } else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) { - msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66_V13_0_4); - prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4); - } else { - msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66); - prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); - } + msg_idx = RREG32(smu->msg_reg); + prm = RREG32(smu->param_reg); dev_err_ratelimited(adev->dev, "SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x%08X SMN_C2PMSG_82:0x%08X", msg_idx, prm); @@ -280,20 +228,9 @@ static void __smu_cmn_send_msg(struct smu_context *smu, { struct amdgpu_device *adev = smu->adev; - if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) { - WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33, 0); - WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34, param); - WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2, msg); - } else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) { - WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90_V13_0_4, 0); - WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4, param); - WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66_V13_0_4, msg); - } else { - WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); - WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param); - WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); - } - + WREG32(smu->resp_reg, 0); + WREG32(smu->param_reg, param); + WREG32(smu->msg_reg, msg); } /** -- cgit v1.2.3 From 4c1b3d0803aef6d39913f1e9d2cfe2c1ccce18e8 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 30 May 2022 14:42:25 +0300 Subject: drm/amdgpu: delete duplicate condition in gfx_v11_0_soft_reset() We know that "grbm_soft_reset" is true because we're already inside an if (grbm_soft_reset) condition. No need to test again. Signed-off-by: Dan Carpenter Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 5f20b41bcb93..ca37289c644f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4780,19 +4780,17 @@ static int gfx_v11_0_soft_reset(void *handle) /* Disable MEC parsing/prefetching */ gfx_v11_0_cp_compute_enable(adev, false); - if (grbm_soft_reset) { - tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); - tmp |= grbm_soft_reset; - dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); - WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); - tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); - - udelay(50); - - tmp &= ~grbm_soft_reset; - WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); - tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); - } + tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); + tmp |= grbm_soft_reset; + dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); + tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~grbm_soft_reset; + WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); + tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); /* Wait a little for things to settle down */ udelay(50); -- cgit v1.2.3 From e87b92c6af537843daf7da9235e622988bae7eae Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Thu, 7 Apr 2022 12:04:42 -0400 Subject: drm/amd/display: do not override CURSOR_REQ_MODE when SubVP is not enabled [Why] HUBP_UNBOUNDED_REQ_MODE and CURSOR_REQ_MODE are normally set together. In hubp32_prepare_subvp_buffering() call, CURSOR_REQ_MODE is set based on whether SubVP is enabled or not. For non MPO case, both REQ_MODE registers are set to 1. But since SubVP is not enabled, then CURSOR_REQ_MODE is set to 0, overriding the previous value. [How] Do not set CURSOR_REQ_MODE to 0 if SubVP is not enabled. This will allow CURSOR_REQ_MODE to stay as 1 in the non MPO case. Add note to follow up and check case for single pipe MPO and SubVP enabled as this would cause both REQ_MODE registers to be set to 0 but SubVP enabled would override CURSOR_REQ_MODE to 1. Signed-off-by: Samson Tam Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c index 40afd33ffec6..8eed05aad54c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c @@ -555,10 +555,13 @@ void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context) struct hubp *hubp = pipe->plane_res.hubp; if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) { + /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases + * - need to investigate single pipe MPO + SubVP case to + * see if CURSOR_REQ_MODE will be back to 1 for SubVP + * when it should be 0 for MPO + */ if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) { hubp->funcs->hubp_prepare_subvp_buffering(hubp, true); - } else { - hubp->funcs->hubp_prepare_subvp_buffering(hubp, false); } } } -- cgit v1.2.3 From b5a0168e1406176cf98487833b7468a1ea5872d3 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 24 May 2022 10:11:33 -0400 Subject: drm/amdgpu: fix up comment in amdgpu_device_asic_has_dc_support() LVDS support was implemented in DC a while ago. Just DAC support is left to do. Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 00ed666811b1..4831148342b7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3287,7 +3287,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) case CHIP_MULLINS: /* * We have systems in the wild with these ASICs that require - * LVDS and VGA support which is not supported with DC. + * VGA support which is not supported with DC. * * Fallback to the non-DC driver here by default so as not to * cause regressions. -- cgit v1.2.3 From 452e9214431f1f6385bb20fdf6e1b5692947071f Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Tue, 5 Apr 2022 14:46:30 -0400 Subject: drm/amd/display: Remove W/A for ODM memory pins [Description] By default we can now set ODM_MEM_VBLANK_PWR_MODE=1 Signed-off-by: Alvin Lee Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c index f2850071478c..b492eb424d19 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c @@ -997,7 +997,7 @@ static const struct dc_debug_options debug_defaults_drv = { .dscl = false, .cm = false, .mpc = false, - .optc = false, + .optc = true, } }, .use_max_lb = true, diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c index 376dd586b643..780409eb0e98 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c @@ -994,7 +994,7 @@ static const struct dc_debug_options debug_defaults_drv = { .dscl = false, .cm = false, .mpc = false, - .optc = false, + .optc = true, } }, .use_max_lb = true, -- cgit v1.2.3 From 49f594995a9255ff734f79c1fc22bd06119ebe8f Mon Sep 17 00:00:00 2001 From: Jun Lei Date: Sun, 20 Feb 2022 13:58:51 -0500 Subject: drm/amd/display: add new pixel rate programming [why] New dividers in DCCG need to be programmed depending on encoder/stream type since pixels per clock in OTG/DIO is different DIO also needs additional programming depending on pixels per clock Signed-off-by: Jun Lei Signed-off-by: Alex Deucher Signed-off-by: Rodrigo Siqueira --- .../amd/display/dc/dcn10/dcn10_stream_encoder.h | 1 + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 14 +++++ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 1 + .../display/dc/dcn32/dcn32_dio_stream_encoder.h | 3 +- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 72 ++++++++++++++++++++-- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h | 2 + drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 1 + drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 3 +- .../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 3 + .../drm/amd/display/dc/inc/hw_sequencer_private.h | 3 + 10 files changed, 95 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h index dd9bb86da4de..f8d22ba6a6e4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h @@ -576,6 +576,7 @@ struct dcn10_stream_enc_registers { type DP_SEC_GSP11_LINE_NUM #define SE_REG_FIELD_LIST_DCN3_2(type) \ + type DIG_FIFO_OUTPUT_PIXEL_MODE;\ type DIG_SYMCLK_FE_ON;\ type DIG_FIFO_READ_START_LEVEL;\ type DIG_FIFO_ENABLE;\ diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index d00a27893ab0..aed8ab06b41d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -661,7 +661,17 @@ enum dc_status dcn20_enable_stream_timing( struct mpc_dwb_flow_control flow_control; struct mpc *mpc = dc->res_pool->mpc; bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing)); + unsigned int k1_div = PIXEL_RATE_DIV_NA; + unsigned int k2_div = PIXEL_RATE_DIV_NA; + if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { + hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); + + dc->res_pool->dccg->funcs->set_pixel_rate_div( + dc->res_pool->dccg, + pipe_ctx->stream_res.tg->inst, + k1_div, k2_div); + } /* by upper caller loop, pipe0 is parent pipe and be called first. * back end is set up by for pipe0. Other children pipe share back end * with pipe 0. No program is needed. @@ -2485,6 +2495,10 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) tg->funcs->set_early_control(tg, early_control); + if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode) + pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc, + timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 ? 2 : 1); + /* enable audio only within mode set */ if (pipe_ctx->stream_res.audio != NULL) { if (is_dp_128b_132b_signal(pipe_ctx)) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c index b78775e8c13c..070be7e8ad0d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c @@ -272,6 +272,7 @@ static const struct dccg_funcs dccg32_funcs = { .set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto, .otg_add_pixel = dccg32_otg_add_pixel, .otg_drop_pixel = dccg32_otg_drop_pixel, + .set_pixel_rate_div = dccg32_set_pixel_rate_div, }; struct dccg *dccg32_create( diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h index 77da0a13525b..042bc9aca944 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h @@ -240,7 +240,8 @@ SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, mask_sh),\ SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, mask_sh),\ SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET, mask_sh),\ - SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, mask_sh) + SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, mask_sh) #if defined(CONFIG_DRM_AMD_DC_HDCP) #define SE_COMMON_MASK_SH_LIST_DCN32(mask_sh)\ diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c index 8eed05aad54c..5994edc3dd0c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c @@ -47,6 +47,7 @@ #include "clk_mgr.h" #include "dsc.h" #include "dcn20/dcn20_optc.h" +#include "dc_link_dp.h" #define DC_LOGGER_INIT(logger) @@ -836,20 +837,44 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) } } +/* +* Given any pipe_ctx, return the total ODM combine factor, and optionally return +* the OPPids which are used +* */ +static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) +{ + unsigned int opp_count = 1; + struct pipe_ctx *odm_pipe; + + /* First get to the top pipe */ + for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe) + ; + + /* First pipe is always used */ + if (opp_instances) + opp_instances[0] = odm_pipe->stream_res.opp->inst; + + /* Find and count odm pipes, if any */ + for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { + if (opp_instances) + opp_instances[opp_count] = odm_pipe->stream_res.opp->inst; + opp_count++; + } + + return opp_count; +} + void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) { struct pipe_ctx *odm_pipe; - int opp_cnt = 1; - int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; + int opp_cnt = 0; + int opp_inst[MAX_PIPES] = {0}; bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing)); struct mpc_dwb_flow_control flow_control; struct mpc *mpc = dc->res_pool->mpc; int i; - for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { - opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; - opp_cnt++; - } + opp_cnt = get_odm_config(pipe_ctx, opp_inst); if (opp_cnt > 1) pipe_ctx->stream_res.tg->funcs->set_odm_combine( @@ -892,3 +917,38 @@ void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx * update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); } +unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div) +{ + struct dc_stream_state *stream = pipe_ctx->stream; + unsigned int odm_combine_factor = 0; + + odm_combine_factor = get_odm_config(pipe_ctx, NULL); + + if (is_dp_128b_132b_signal(pipe_ctx)) { + *k2_div = PIXEL_RATE_DIV_BY_1; + } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) { + *k1_div = PIXEL_RATE_DIV_BY_1; + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) + *k2_div = PIXEL_RATE_DIV_BY_2; + else + *k2_div = PIXEL_RATE_DIV_BY_4; + } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { + *k1_div = PIXEL_RATE_DIV_BY_1; + *k2_div = PIXEL_RATE_DIV_BY_2; + } else if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { + *k1_div = PIXEL_RATE_DIV_BY_2; + *k2_div = PIXEL_RATE_DIV_BY_2; + } else { + if (odm_combine_factor == 1) + *k2_div = PIXEL_RATE_DIV_BY_4; + else if (odm_combine_factor == 2) + *k2_div = PIXEL_RATE_DIV_BY_2; + } + } + + if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA)) + ASSERT(false); + + return odm_combine_factor; +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h index 737a7fac5cf9..2a5bdcf58bc6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h @@ -61,4 +61,6 @@ void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context); void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); +unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div); + #endif /* __DC_HWSS_DCN32_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c index d1e3db1bc488..7f492734f881 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c @@ -141,6 +141,7 @@ static const struct hwseq_private_funcs dcn32_private_funcs = { .program_mall_pipe_config = dcn32_program_mall_pipe_config, .subvp_update_force_pstate = dcn32_subvp_update_force_pstate, .update_mall_sel = dcn32_update_mall_sel, + .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values, }; void dcn32_hw_sequencer_init_functions(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index 8b450a7274ae..e0dd04626eb5 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -59,7 +59,8 @@ enum dentist_dispclk_change_mode { enum pixel_rate_div { PIXEL_RATE_DIV_BY_1 = 0, PIXEL_RATE_DIV_BY_2 = 1, - PIXEL_RATE_DIV_BY_4 = 3 + PIXEL_RATE_DIV_BY_4 = 3, + PIXEL_RATE_DIV_NA = 0xF }; struct dccg { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h index 36ec56524afd..e5fe0f6adc86 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -247,6 +247,9 @@ struct stream_encoder_funcs { uint32_t (*get_fifo_cal_average_level)( struct stream_encoder *enc); + + void (*set_input_mode)( + struct stream_encoder *enc, unsigned int pix_per_container); }; struct hpo_dp_stream_encoder_state { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h index fd869e93cf54..62a62e4fc4a8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h @@ -149,6 +149,9 @@ struct hwseq_private_funcs { void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context); void (*subvp_update_force_pstate)(struct dc *dc, struct dc_state *context); void (*update_mall_sel)(struct dc *dc, struct dc_state *context); + unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx, + unsigned int *k1_div, + unsigned int *k2_div); #endif }; -- cgit v1.2.3 From 6ea843e01bce520cf5dea86bc30c5133e0d0822d Mon Sep 17 00:00:00 2001 From: Jingwen Zhu Date: Tue, 15 Mar 2022 13:15:27 +0800 Subject: drm/amd/display: set link fec status during init for DCN32 We can now enable FEC. Signed-off-by: Jingwen Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c index 5994edc3dd0c..04360553a43f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c @@ -635,8 +635,12 @@ void dcn32_init_hw(struct dc *dc) /* Check for enabled DIG to identify enabled display */ if (link->link_enc->funcs->is_dig_enabled && - link->link_enc->funcs->is_dig_enabled(link->link_enc)) + link->link_enc->funcs->is_dig_enabled(link->link_enc)) { link->link_status.link_active = true; + if (link->link_enc->funcs->fec_is_active && + link->link_enc->funcs->fec_is_active(link->link_enc)) + link->fec_state = dc_link_fec_enabled; + } } /* Power gate DSCs */ -- cgit v1.2.3 From e127306d433ff99f29d1b083c6b3aa128bbd9c5e Mon Sep 17 00:00:00 2001 From: Jun Lei Date: Sun, 20 Feb 2022 14:33:56 -0500 Subject: drm/amd/display: Introduce new update_clocks logic [why] DCN has sidebands to control some clocks, it is useful for clk_mgr to always update the clocks it explicitly controls rather than skip them because it enables more configurations to work without SMU [how] only skip handling clocks where SMU manages the frequency for clocks with DENTIST sideband (DISP/DPP), only skip the voltage request when SMU not available, but otherwise proceed normally Signed-off-by: Jun Lei Signed-off-by: Alex Deucher --- .../amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 125 ++++++++++++--------- 1 file changed, 73 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index f147c65137c6..9f35a74a1d7d 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -310,69 +310,84 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, if (display_count == 0) enter_display_off = true; - if (enter_display_off == safe_to_lower) - dcn30_smu_set_num_of_displays(clk_mgr, display_count); + if (clk_mgr->smu_present) { + if (enter_display_off == safe_to_lower) + dcn30_smu_set_num_of_displays(clk_mgr, display_count); - if (dc->debug.force_min_dcfclk_mhz > 0) - new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? - new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); + if (dc->debug.force_min_dcfclk_mhz > 0) + new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? + new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); - if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { - clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz)); - } + if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { + clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz)); + } - if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { - clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; - dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz)); - } + if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { + clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; + dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz)); + } - if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) - /* We don't actually care about socclk, don't notify SMU of hard min */ - clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; + if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) + /* We don't actually care about socclk, don't notify SMU of hard min */ + clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; - clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; - clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support; + clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; + clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support; + clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways; - total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context); - p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0); - fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0); - if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) { - clk_mgr_base->clks.p_state_change_support = p_state_change_support; + if (clk_mgr_base->clks.num_ways != new_clocks->num_ways && + clk_mgr_base->clks.num_ways < new_clocks->num_ways) { + clk_mgr_base->clks.num_ways = new_clocks->num_ways; + dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways); + } - /* to disable P-State switching, set UCLK min = max */ - if (!clk_mgr_base->clks.p_state_change_support) - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); - } + total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context); + p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0); + fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0); + if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) { + clk_mgr_base->clks.p_state_change_support = p_state_change_support; + + /* to disable P-State switching, set UCLK min = max */ + if (!clk_mgr_base->clks.p_state_change_support) + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, + clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); + } + + if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && + should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) { + clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support; - if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && - should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) { - clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support; + /* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */ + if (!clk_mgr_base->clks.fclk_p_state_change_support) { + /* Handle code for sending a message to PMFW that FCLK P-state change is not supported */ + dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED); + } + } - /* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */ - if (!clk_mgr_base->clks.fclk_p_state_change_support) { - /* Handle code for sending a message to PMFW that FCLK P-state change is not supported */ - dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED); + /* Always update saved value, even if new value not set due to P-State switching unsupported */ + if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { + clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; + update_uclk = true; } - } - /* Always update saved value, even if new value not set due to P-State switching unsupported */ - if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { - clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; - update_uclk = true; - } + /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */ + if (clk_mgr_base->clks.p_state_change_support && + (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support)) + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); + + if (clk_mgr_base->clks.fclk_p_state_change_support && + (update_uclk || !clk_mgr_base->clks.fclk_prev_p_state_change_support)) { - /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */ - if (clk_mgr_base->clks.p_state_change_support && - (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support)) - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); + /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */ + dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED); + } - if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && - clk_mgr_base->clks.fclk_p_state_change_support && - (update_uclk || !clk_mgr_base->clks.fclk_prev_p_state_change_support)) { - /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */ - dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED); + if (clk_mgr_base->clks.num_ways != new_clocks->num_ways && + clk_mgr_base->clks.num_ways > new_clocks->num_ways) { + clk_mgr_base->clks.num_ways = new_clocks->num_ways; + dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways); + } } if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) { @@ -380,13 +395,19 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, dpp_clock_lowered = true; clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz)); + + if (clk_mgr->smu_present) + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz)); + update_dppclk = true; } if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz)); + + if (clk_mgr->smu_present) + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz)); + update_dispclk = true; } -- cgit v1.2.3 From 0c9ed6044c5d08562d38d56e94279badef39e4c7 Mon Sep 17 00:00:00 2001 From: Chaitanya Dhere Date: Mon, 11 Apr 2022 13:37:21 -0400 Subject: drm/amd/display: FCLK P-state support updates [Why] Previously we used to send FCLK P-state enable messages upon each call to update_clocks based on dml output. This resulted in increased message transactions between DC and PMFW. [How] Update the code to check safe_to_lower status and send the message based on dml input only on boot. This reduces message transactions. Also remove other unwanted code based on current code status. Signed-off-by: Chaitanya Dhere Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 11 +++++++---- .../drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h | 1 - 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 9f35a74a1d7d..3d2807fc769f 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -284,7 +284,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, bool dpp_clock_lowered = false; struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; bool force_reset = false; - bool update_uclk = false; + bool update_uclk = false, update_fclk = false; bool p_state_change_support; bool fclk_p_state_change_support; int total_plane_count; @@ -371,14 +371,17 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, update_uclk = true; } + /* Always update saved value, even if new value not set due to P-State switching unsupported. Also check safe_to_lower for FCLK */ + if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_prev_p_state_change_support)) { + update_fclk = true; + } + /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */ if (clk_mgr_base->clks.p_state_change_support && (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support)) dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); - if (clk_mgr_base->clks.fclk_p_state_change_support && - (update_uclk || !clk_mgr_base->clks.fclk_prev_p_state_change_support)) { - + if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && clk_mgr_base->clks.fclk_p_state_change_support && update_fclk) { /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */ dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED); } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h index 11b25de1527f..674a52dbecad 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h @@ -33,7 +33,6 @@ #define FCLK_PSTATE_SUPPORTED 0x01 /* TODO Remove this MSG ID define after it becomes available in dalsmc */ -#define DALSMC_MSG_SetFclkSwitchAllow 0x11 #define DALSMC_MSG_SetCabForUclkPstate 0x12 #define DALSMC_Result_OK 0x1 -- cgit v1.2.3 From 327f79d7a1d2dcc10aeda05983c4d1532dd0830a Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Fri, 4 Mar 2022 09:34:58 -0500 Subject: drm/amd/display: Updates for OTG and DCCG clocks Use DTBCLK for valid pixel clock generation Signed-off-by: Samson Tam Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 5 ++++- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h | 4 ++++ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h | 1 + 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h index df155cc2bfea..3fe5882ed018 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h @@ -514,7 +514,6 @@ struct dcn_optc_registers { type DIG_UPDATE_POSITION_X;\ type DIG_UPDATE_POSITION_Y;\ type OTG_H_TIMING_DIV_MODE;\ - type OTG_H_TIMING_DIV_MODE_MANUAL;\ type OTG_DRR_TIMING_DBUF_UPDATE_MODE;\ type OTG_CRC_DSC_MODE;\ type OTG_CRC_DATA_STREAM_COMBINE_MODE;\ @@ -522,13 +521,17 @@ struct dcn_optc_registers { type OTG_CRC_DATA_FORMAT;\ type OTG_V_TOTAL_LAST_USED_BY_DRR; +#define TG_REG_FIELD_LIST_DCN3_2(type) \ + type OTG_H_TIMING_DIV_MODE_MANUAL; struct dcn_optc_shift { TG_REG_FIELD_LIST(uint8_t) + TG_REG_FIELD_LIST_DCN3_2(uint8_t) }; struct dcn_optc_mask { TG_REG_FIELD_LIST(uint32_t) + TG_REG_FIELD_LIST_DCN3_2(uint32_t) }; struct optc { diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h index 0e54c0a105a1..1c46fad0977b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h @@ -45,6 +45,7 @@ SR(PHYDSYMCLK_CLOCK_CNTL),\ SR(PHYESYMCLK_CLOCK_CNTL),\ SR(DPSTREAMCLK_CNTL),\ + SR(HDMISTREAMCLK_CNTL),\ SR(SYMCLK32_SE_CNTL),\ SR(SYMCLK32_LE_CNTL),\ DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\ @@ -98,6 +99,8 @@ DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_SRC_SEL, mask_sh),\ DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_SRC_SEL, mask_sh),\ DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_EN, mask_sh),\ + DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_DTO_FORCE_DIS, mask_sh),\ + DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_SRC_SEL, mask_sh),\ DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\ DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\ DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\ @@ -143,6 +146,7 @@ DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\ DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\ DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\ + DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\ DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h index e07b317ed3f4..5e57c39235fa 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h @@ -245,6 +245,7 @@ SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\ SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ + SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) -- cgit v1.2.3 From 214d72f62978c28fe27d22d0d498d04493e9ce86 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Tue, 26 Apr 2022 14:29:15 -0400 Subject: drm/amd/display: update disp pattern generator routine for DCN30 Signed-off-by: Aurabindo Pillai Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 33 ++-------------------- 1 file changed, 2 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c index 782b8db451b4..ecdc7c781217 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c @@ -959,35 +959,6 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc, const struct tg_color *solid_color, int width, int height, int offset) { - struct stream_resource *stream_res = &pipe_ctx->stream_res; - struct pipe_ctx *mpcc_pipe; - - if (test_pattern != CONTROLLER_DP_TEST_PATTERN_VIDEOMODE) { - pipe_ctx->vtp_locked = false; - /* turning on DPG */ - stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space, - color_depth, solid_color, width, height, offset); - - /* Defer hubp blank if tg is locked */ - if (stream_res->tg->funcs->is_tg_enabled(stream_res->tg)) { - if (stream_res->tg->funcs->is_locked(stream_res->tg)) - pipe_ctx->vtp_locked = true; - else { - /* Blank HUBP to allow p-state during blank on all timings */ - pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, true); - - for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) - mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true); - } - } - } else { - /* turning off DPG */ - pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, false); - for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) - if (mpcc_pipe->plane_res.hubp) - mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, false); - - stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space, - color_depth, solid_color, width, height, offset); - } + pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, + color_space, color_depth, solid_color, width, height, offset); } -- cgit v1.2.3 From 80fb7a409c64ef304e4040320e87dbb2f10968ca Mon Sep 17 00:00:00 2001 From: Martin Leung Date: Sun, 20 Feb 2022 21:44:26 -0500 Subject: drm/amd/display: cleaning up smu_if to add future flexibility This commit cleans up code that uses old variables and adds some SMU interfaces for future flexibility. Signed-off-by: Martin Leung Signed-off-by: Alex Deucher --- .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c | 19 ++++--- .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h | 7 +-- .../dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h | 63 ++++++++++++++++++++++ drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 5 +- 4 files changed, 78 insertions(+), 16 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c index 35e8afe6db93..95ab268e9179 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c @@ -27,6 +27,8 @@ #include "clk_mgr_internal.h" #include "reg_helper.h" +#include "dalsmc.h" +#include "smu13_driver_if.h" #define mmDAL_MSG_REG 0x1628A #define mmDAL_ARG_REG 0x16273 @@ -38,8 +40,6 @@ mm ## reg_name #include "logger_types.h" -#include "dalsmc.h" -#include "smu13_driver_if.h" #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } @@ -100,14 +100,6 @@ void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool e DALSMC_MSG_SetFclkSwitchAllow, enable ? FCLK_PSTATE_SUPPORTED : FCLK_PSTATE_NOTSUPPORTED, NULL); } -void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) -{ - smu_print("SMU Transfer WM table DRAM 2 SMU\n"); - - dcn32_smu_send_msg_with_param(clk_mgr, - DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL); -} - void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways) { smu_print("Numways for SubVP : %d\n", num_ways); @@ -115,3 +107,10 @@ void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsig dcn32_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetCabForUclkPstate, num_ways, NULL); } +void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) +{ + smu_print("SMU Transfer WM table DRAM 2 SMU\n"); + + dcn32_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL); +} diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h index 674a52dbecad..5f69cdcb9885 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h @@ -37,12 +37,9 @@ #define DALSMC_Result_OK 0x1 void -dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, - bool enable); - +dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable); void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); - void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways); - +void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); #endif /* __DCN32_CLK_MGR_SMU_MSG_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h new file mode 100644 index 000000000000..d30fbbdd1792 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h @@ -0,0 +1,63 @@ +// This is a stripped-down version of the smu13_driver_if.h file for the relevant DAL interfaces. + +#define SMU13_DRIVER_IF_VERSION 0x18 + +//Only Clks that have DPM descriptors are listed here +typedef enum { + PPCLK_GFXCLK = 0, + PPCLK_SOCCLK, + PPCLK_UCLK, + PPCLK_FCLK, + PPCLK_DCLK_0, + PPCLK_VCLK_0, + PPCLK_DCLK_1, + PPCLK_VCLK_1, + PPCLK_DISPCLK, + PPCLK_DPPCLK, + PPCLK_DPREFCLK, + PPCLK_DCFCLK, + PPCLK_DTBCLK, + PPCLK_COUNT, +} PPCLK_e; + +typedef struct { + uint8_t WmSetting; + uint8_t Flags; + uint8_t Padding[2]; + +} WatermarkRowGeneric_t; + +#define NUM_WM_RANGES 4 + +typedef enum { + WATERMARKS_CLOCK_RANGE = 0, + WATERMARKS_DUMMY_PSTATE, + WATERMARKS_MALL, + WATERMARKS_COUNT, +} WATERMARKS_FLAGS_e; + +typedef struct { + // Watermarks + WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; +} Watermarks_t; + +typedef struct { + Watermarks_t Watermarks; + uint32_t Spare[16]; + + uint32_t MmHubPadding[8]; // SMU internal use +} WatermarksExternal_t; + +// Table types +#define TABLE_PMFW_PPTABLE 0 +#define TABLE_COMBO_PPTABLE 1 +#define TABLE_WATERMARKS 2 +#define TABLE_AVFS_PSM_DEBUG 3 +#define TABLE_PMSTATUSLOG 4 +#define TABLE_SMU_METRICS 5 +#define TABLE_DRIVER_SMU_CONFIG 6 +#define TABLE_ACTIVITY_MONITOR_COEFF 7 +#define TABLE_OVERDRIVE 8 +#define TABLE_I2C_COMMANDS 9 +#define TABLE_DRIVER_INFO 10 +#define TABLE_COUNT 11 diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c index d298f6016e0b..a76da0131add 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c @@ -39,7 +39,10 @@ const struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs = { #define DMUB_SR(reg) REG_OFFSET_EXP(reg), - { DMUB_DCN32_REGS() }, + { + DMUB_DCN32_REGS() + DMCUB_INTERNAL_REGS() + }, #undef DMUB_SR #define DMUB_SF(reg, field) FD_MASK(reg, field), -- cgit v1.2.3 From b6a93844145395068574cbbfaf3aea91d1f24f1a Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Mon, 21 Mar 2022 10:22:19 -0400 Subject: drm/amd/display: Match dprefclk with clk registers Update base.dprefclk_khz to match result from dcn32_dump_clk_registers() Signed-off-by: Samson Tam Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 3d2807fc769f..6a1d7c86e6b7 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -622,7 +622,11 @@ void dcn32_clk_mgr_construct( clk_mgr->ss_on_dprefclk = false; clk_mgr->dfs_ref_freq_khz = 100000; - clk_mgr->base.dprefclk_khz = 717000; /* Changed as per DCN3.2_clock_frequency doc */ + /* Changed from DCN3.2_clock_frequency doc to match + * dcn32_dump_clk_registers from 4 * dentist_vco_freq_khz / + * dprefclk DID divider + */ + clk_mgr->base.dprefclk_khz = 716666; clk_mgr->dccg->ref_dtbclk_khz = 268750; /* integer part is now VCO frequency in kHz */ @@ -636,8 +640,7 @@ void dcn32_clk_mgr_construct( } if (clk_mgr->base.boot_snapshot.dprefclk != 0) { - //ASSERT(clk_mgr->base.dprefclk_khz == clk_mgr->base.boot_snapshot.dprefclk); - //clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk; + clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk; } dcn32_clock_read_ss_info(clk_mgr); -- cgit v1.2.3 From 405bb9eea36a02798631e8409f1182705699d092 Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Fri, 29 Apr 2022 20:41:10 -0400 Subject: drm/amd/display: Implement DTBCLK ref switching on dcn32 [WHY & HOW] Implements DTB ref clock switching with reg key default to OFF. Refactors dccg DTBCLK logic to not store redundant state information dccg. Also removes duplicated functions that should be inherited from other dcn versions. Signed-off-by: Alvin Lee Signed-off-by: Alex Deucher --- .../amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 87 ++++++++++++++++++---- .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c | 18 +++++ .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h | 1 + drivers/gpu/drm/amd/display/dc/dc.h | 5 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 9 +-- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 1 + drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 2 + .../gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 12 ++- .../drm/amd/display/dc/dcn321/dcn321_resource.c | 11 ++- drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 3 +- 10 files changed, 118 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 6a1d7c86e6b7..1db61029481b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -29,9 +29,11 @@ #include "dcn32/dcn32_clk_mgr_smu_msg.h" #include "dcn20/dcn20_clk_mgr.h" #include "dce100/dce_clk_mgr.h" +#include "dcn31/dcn31_clk_mgr.h" #include "reg_helper.h" #include "core_types.h" #include "dm_helpers.h" +#include "dc_link_dp.h" #include "atomfirmware.h" #include "smu13_driver_if.h" @@ -253,9 +255,10 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, &num_levels); /* DTBCLK */ - dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK, - &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, - &num_levels); + if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) + dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK, + &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, + &num_levels); /* DISPCLK */ dcn32_init_single_clock(clk_mgr, PPCLK_DISPCLK, @@ -270,6 +273,39 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) dcn32_build_wm_range_table(clk_mgr); } +static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, + struct dc_state *context, + int ref_dtbclk_khz) +{ + struct dccg *dccg = clk_mgr->dccg; + uint32_t tg_mask = 0; + int i; + + for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct dtbclk_dto_params dto_params = {0}; + + /* use mask to program DTO once per tg */ + if (pipe_ctx->stream_res.tg && + !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) { + tg_mask |= (1 << pipe_ctx->stream_res.tg->inst); + + dto_params.otg_inst = pipe_ctx->stream_res.tg->inst; + dto_params.ref_dtbclk_khz = ref_dtbclk_khz; + + if (is_dp_128b_132b_signal(pipe_ctx)) { + dto_params.pixclk_khz = pipe_ctx->stream->phy_pix_clk; + + if (pipe_ctx->stream_res.audio != NULL) + dto_params.req_audio_dtbclk_khz = 24000; + } + + dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params); + //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params); + } + } +} + static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool safe_to_lower) @@ -320,7 +356,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz)); + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz)); } if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { @@ -350,7 +386,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, /* to disable P-State switching, set UCLK min = max */ if (!clk_mgr_base->clks.p_state_change_support) - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); } @@ -379,7 +415,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */ if (clk_mgr_base->clks.p_state_change_support && (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support)) - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && clk_mgr_base->clks.fclk_p_state_change_support && update_fclk) { /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */ @@ -400,7 +436,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; if (clk_mgr->smu_present) - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz)); + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz)); update_dppclk = true; } @@ -409,11 +445,25 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; if (clk_mgr->smu_present) - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz)); + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz)); update_dispclk = true; } + if (!new_clocks->dtbclk_en) { + new_clocks->ref_dtbclk_khz = 0; + } + + /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */ + if (!dc->debug.disable_dtb_ref_clk_switch && + should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) { + /* DCCG requires KHz precision for DTBCLK */ + clk_mgr_base->clks.ref_dtbclk_khz = + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz)); + + dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz); + } + if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { if (dpp_clock_lowered) { /* if clock is being lowered, increase DTO before lowering refclk */ @@ -502,13 +552,13 @@ static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current if (current_mode) { if (clk_mgr_base->clks.p_state_change_support) - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); else - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); } else { - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); } } @@ -584,7 +634,7 @@ static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base) static struct clk_mgr_funcs dcn32_funcs = { - .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, + .get_dp_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, .update_clocks = dcn32_update_clocks, .init_clocks = dcn32_init_clocks, .notify_wm_ranges = dcn32_notify_wm_ranges, @@ -627,7 +677,13 @@ void dcn32_clk_mgr_construct( * dprefclk DID divider */ clk_mgr->base.dprefclk_khz = 716666; - clk_mgr->dccg->ref_dtbclk_khz = 268750; + if (ctx->dc->debug.disable_dtb_ref_clk_switch) { + //initialize DTB ref clock value if DPM disabled + if (ctx->dce_version == DCN_VERSION_3_21) + clk_mgr->base.clks.ref_dtbclk_khz = 477800; + else + clk_mgr->base.clks.ref_dtbclk_khz = 268750; + } /* integer part is now VCO frequency in kHz */ clk_mgr->base.dentist_vco_freq_khz = 4300000;//dcn32_get_vco_frequency_from_reg(clk_mgr); @@ -635,8 +691,9 @@ void dcn32_clk_mgr_construct( if (clk_mgr->base.dentist_vco_freq_khz == 0) clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */ - if (clk_mgr->dccg->ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) { - clk_mgr->dccg->ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk; + if (ctx->dc->debug.disable_dtb_ref_clk_switch && + clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) { + clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk; } if (clk_mgr->base.boot_snapshot.dprefclk != 0) { diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c index 95ab268e9179..d7c99e9179be 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c @@ -114,3 +114,21 @@ void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) dcn32_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL); } + +/* Returns the actual frequency that was set in MHz, 0 on failure */ +unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz) +{ + uint32_t response = 0; + + /* bits 23:16 for clock type, lower 16 bits for frequency in MHz */ + uint32_t param = (clk << 16) | freq_mhz; + + smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz); + + dcn32_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_SetHardMinByFreq, param, &response); + + smu_print("SMU Frequency set = %d KHz\n", response); + + return response; +} diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h index 5f69cdcb9885..352435edbd79 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h @@ -41,5 +41,6 @@ dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways); void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); +unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz); #endif /* __DCN32_CLK_MGR_SMU_MSG_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 691654653ebb..7bb67ab979e1 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -432,7 +432,6 @@ struct dc_clocks { enum dcn_zstate_support_state zstate_support; bool dtbclk_en; int ref_dtbclk_khz; - int dtbclk_khz; bool fclk_p_state_change_support; enum dcn_pwr_state pwr_state; /* @@ -740,11 +739,11 @@ struct dc_debug_options { bool force_disable_subvp; bool force_subvp_mclk_switch; bool force_usr_allow; + /* uses value at boot and disables switch */ + bool disable_dtb_ref_clk_switch; bool apply_vendor_specific_lttpr_wa; bool extended_blank_optimization; union aux_wake_wa_options aux_wake_wa; - /* uses value at boot and disables switch */ - bool disable_dtb_ref_clk_switch; uint8_t psr_power_use_phy_fsm; enum dml_hostvm_override_opts dml_hostvm_override; }; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index a76523c95ab2..631a8a2f9fc3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2191,18 +2191,15 @@ static void dce110_setup_audio_dto( build_audio_output(context, pipe_ctx, &audio_output); if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { - struct dtbclk_dto_params dto_params = {0}; + /* disable audio DTBCLK DTO */ + dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( + dc->res_pool->dccg, 0); pipe_ctx->stream_res.audio->funcs->wall_dto_setup( pipe_ctx->stream_res.audio, pipe_ctx->stream->signal, &audio_output.crtc_info, &audio_output.pll_info); - - dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( - dc->res_pool->dccg, - &dto_params); - } else pipe_ctx->stream_res.audio->funcs->wall_dto_setup( pipe_ctx->stream_res.audio, diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c index 13dbf99af220..8eeb3b69b5b9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c @@ -590,6 +590,7 @@ void dccg31_set_audio_dtbclk_dto( phase = div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1), params->ref_dtbclk_khz); + REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, modulo); REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, phase); diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c index 070be7e8ad0d..08232d05d894 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c @@ -179,11 +179,13 @@ void dccg32_set_dtbclk_dto( void dccg32_set_valid_pixel_rate( struct dccg *dccg, + int ref_dtbclk_khz, int otg_inst, int pixclk_khz) { struct dtbclk_dto_params dto_params = {0}; + dto_params.ref_dtbclk_khz = ref_dtbclk_khz; dto_params.otg_inst = otg_inst; dto_params.pixclk_khz = pixclk_khz; diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c index b492eb424d19..1ea6d258a20d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c @@ -3306,6 +3306,7 @@ void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display // context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching; context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); + context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000; if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported) context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false; else @@ -3560,10 +3561,15 @@ static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw dcn3_2_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3; /* Populate from bw_params for DTBCLK, SOCCLK */ - if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0) - dcn3_2_soc.clock_limits[i].dtbclk_mhz = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz; - else + if (i > 0) { + if (!bw_params->clk_table.entries[i].dtbclk_mhz) { + dcn3_2_soc.clock_limits[i].dtbclk_mhz = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz; + } else { + dcn3_2_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; + } + } else if (bw_params->clk_table.entries[i].dtbclk_mhz) { dcn3_2_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; + } if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz; diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c index 780409eb0e98..48af91affb0c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c @@ -1910,10 +1910,15 @@ static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b dcn3_21_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3; /* Populate from bw_params for DTBCLK, SOCCLK */ - if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0) - dcn3_21_soc.clock_limits[i].dtbclk_mhz = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz; - else + if (i > 0) { + if (!bw_params->clk_table.entries[i].dtbclk_mhz) { + dcn3_21_soc.clock_limits[i].dtbclk_mhz = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz; + } else { + dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; + } + } else if (bw_params->clk_table.entries[i].dtbclk_mhz) { dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; + } if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) dcn3_21_soc.clock_limits[i].socclk_mhz = dcn3_21_soc.clock_limits[i-1].socclk_mhz; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index e0dd04626eb5..025169457cc8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -70,7 +70,7 @@ struct dccg { int ref_dppclk; //int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */ //int audio_dtbclk_khz;/* TODO needs to be removed */ - int ref_dtbclk_khz;/* TODO needs to be removed */ + //int ref_dtbclk_khz;/* TODO needs to be removed */ }; struct dtbclk_dto_params { @@ -154,6 +154,7 @@ void (*set_pixel_rate_div)( void (*set_valid_pixel_rate)( struct dccg *dccg, + int ref_dtbclk_khz, int otg_inst, int pixclk_khz); -- cgit v1.2.3 From 3e80a5b068a5fedc69ada30ba1a2d1e0b76dfc25 Mon Sep 17 00:00:00 2001 From: Duncan Ma Date: Thu, 31 Mar 2022 15:13:22 -0400 Subject: drm/amd/display: Add ODM seamless boot support Revised validation logic when marking for seamless boot. Init resources accordingly when Pre-OS has ODM enabled. Reset ODM when transitioning Pre-OS odm to Post-OS non-odm to avoid corruption. Apply logic to set odm accordingly upon commit. Signed-off-by: Duncan Ma Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 9 ++++++++- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 5 +++++ drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c | 21 +++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 4 ++-- .../drm/amd/display/dc/inc/hw/timing_generator.h | 2 ++ 5 files changed, 38 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index b087452e4590..7072b79d1207 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -2165,7 +2165,7 @@ static int acquire_resource_from_hw_enabled_state( if (pipe_ctx->stream_res.tg->funcs->get_optc_source) pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg, - &numPipes, &id_src[0], &id_src[1]); + &numPipes, &id_src[0], &id_src[1]); if (id_src[0] == 0xf && id_src[1] == 0xf) { id_src[0] = tg_inst; @@ -2177,6 +2177,8 @@ static int acquire_resource_from_hw_enabled_state( if (id_src[i] == 0xf) return -1; + pipe_ctx = &res_ctx->pipe_ctx[id_src[i]]; + pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; pipe_ctx->plane_res.mi = pool->mis[id_src[i]]; pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]]; @@ -2190,13 +2192,17 @@ static int acquire_resource_from_hw_enabled_state( if (pool->mpc->funcs->read_mpcc_state) { struct mpcc_state s = {0}; + pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s); + if (s.dpp_id < MAX_MPCC) pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id; + if (s.bot_mpcc_id < MAX_MPCC) pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot = &pool->mpc->mpcc_array[s.bot_mpcc_id]; + if (s.opp_id < MAX_OPP) pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id; } @@ -2205,6 +2211,7 @@ static int acquire_resource_from_hw_enabled_state( if (id_src[i] >= pool->timing_generator_count) { id_src[i] = pool->timing_generator_count - 1; + pipe_ctx->stream_res.tg = pool->timing_generators[id_src[i]]; pipe_ctx->stream_res.opp = pool->opps[id_src[i]]; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 1cb206dc8352..e3a62873c0e7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1375,6 +1375,11 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context) pipe_ctx->stream_res.tg = NULL; pipe_ctx->plane_res.hubp = NULL; + if (tg->funcs->is_tg_enabled(tg)) { + if (tg->funcs->init_odm) + tg->funcs->init_odm(tg); + } + tg->funcs->tg_init(tg); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c index 96fac715a77b..c4304f25ce95 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c @@ -213,6 +213,26 @@ void optc31_set_drr( } } +void optc3_init_odm(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, + OPTC_NUM_OF_INPUT_SEGMENT, 0, + OPTC_SEG0_SRC_SEL, optc->inst, + OPTC_SEG1_SRC_SEL, 0xf, + OPTC_SEG2_SRC_SEL, 0xf, + OPTC_SEG3_SRC_SEL, 0xf + ); + + REG_SET(OTG_H_TIMING_CNTL, 0, + OTG_H_TIMING_DIV_MODE, 0); + + REG_SET(OPTC_MEMORY_CONFIG, 0, + OPTC_MEM_SEL, 0); + optc1->opp_count = 1; +} + static struct timing_generator_funcs dcn31_tg_funcs = { .validate_timing = optc1_validate_timing, .program_timing = optc1_program_timing, @@ -273,6 +293,7 @@ static struct timing_generator_funcs dcn31_tg_funcs = { .program_manual_trigger = optc2_program_manual_trigger, .setup_manual_trigger = optc2_setup_manual_trigger, .get_hw_timing = optc1_get_hw_timing, + .init_odm = optc3_init_odm, }; void dcn31_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c index 04360553a43f..a10ec5919194 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c @@ -657,7 +657,7 @@ void dcn32_init_hw(struct dc *dc) * Otherwise, if taking control is not possible, we need to power * everything down. */ - if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.seamless_boot_edp_requested) { + if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { hws->funcs.init_pipes(dc, dc->current_state); if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, @@ -669,7 +669,7 @@ void dcn32_init_hw(struct dc *dc) * To avoid this, power down hardware on boot * if DIG is turned on and seamless boot not enabled */ - if (dc->config.seamless_boot_edp_requested) { + if (!dc->config.seamless_boot_edp_requested) { struct dc_link *edp_links[MAX_NUM_EDP]; struct dc_link *edp_link; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index a89b2230cd2c..62d4683f17a2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -318,6 +318,8 @@ struct timing_generator_funcs { int vmin, int vmax); bool (*validate_vtotal_change_limit)(struct timing_generator *optc, uint32_t vtotal_change_limit); + + void (*init_odm)(struct timing_generator *tg); }; #endif -- cgit v1.2.3 From d8e4fb9112e88d8d87ffbc38fa511e7118042d4f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 1 Jun 2022 22:22:07 -0400 Subject: drm/amdgpu/display: Protect some functions with CONFIG_DRM_AMD_DC_DCN Protect remove_hpo_dp_link_enc_from_ctx() and release_hpo_dp_link_enc() with CONFIG_DRM_AMD_DC_DCN as the functions are only called from code that is protected by CONFIG_DRM_AMD_DC_DCN. Fixes build fail with -Werror=unused-function. Fixes: 9b0e0d433f74 ("drm/amd/display: Add dependant changes for DCN32/321") Reported-by: Stephen Rothwell Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher Cc: Aurabindo Pillai --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 7072b79d1207..9bbdfcd6b3a4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1801,6 +1801,7 @@ static inline void retain_hpo_dp_link_enc( res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]++; } +#if defined(CONFIG_DRM_AMD_DC_DCN) static inline void release_hpo_dp_link_enc( struct resource_context *res_ctx, int enc_index) @@ -1808,6 +1809,7 @@ static inline void release_hpo_dp_link_enc( ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0); res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]--; } +#endif static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx, const struct resource_pool *pool, @@ -1832,6 +1834,7 @@ static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx, return pipe_ctx->link_res.hpo_dp_link_enc != NULL; } +#if defined(CONFIG_DRM_AMD_DC_DCN) static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx, struct pipe_ctx *pipe_ctx, struct dc_stream_state *stream) @@ -1845,6 +1848,7 @@ static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx, pipe_ctx->link_res.hpo_dp_link_enc = NULL; } } +#endif /* TODO: release audio object */ void update_audio_usage( -- cgit v1.2.3 From 8b67e738ca17fb52a275b1cc0191dfce0e9cd7a5 Mon Sep 17 00:00:00 2001 From: Alan Liu Date: Thu, 2 Jun 2022 19:41:58 +0800 Subject: drm/amdgpu/display/dc: Add ACP_DATA register Define ixAZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA Define AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK/SHIFT Reviewed-by: Harry Wentland Signed-off-by: Alan Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h | 1 + drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h index 6df651a94b0a..581ba639b4ea 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h @@ -6981,6 +6981,7 @@ #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23 #define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24 #define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x27 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h index fa1f4374fafe..fd387c7363b6 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h @@ -13639,6 +13639,8 @@ #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 #define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40 #define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x40 +#define AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x7f #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0xff00 -- cgit v1.2.3 From 83eb5385b4f021c2674b1d78675bfd10443cdf74 Mon Sep 17 00:00:00 2001 From: David Zhang Date: Mon, 14 Mar 2022 11:31:12 -0400 Subject: drm/amd/display: align dmub cmd header to latest dmub FW to support PSR-SU [why] PSR-SU is implemented in upstreamed dmub FW but not enabled on DM and DC. We'd add necessary and missing definitions in dmub cmd header to align w/ the up-to-date DMUB FW for PSR-SU support. [how] Add definitions and items below into dmub cmd header: - DMUB psr version enumeration for PSR-SU - dirty rectangle structure - psr debug flag of forcing full frame update - dmub command of updating dirty rectangle and cursor infor - dmub psr command type of setting sink vtotal in PSR active - dmub psr su debug flags structure - dmub cmd structure for - updating dirty rectangle - cursor infor - setting sink vtotal - dmub ringbuffer command items Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 250 +++++++++++++++++++++++- 1 file changed, 245 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 8fc1846f0708..f6ad1b8c7034 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -101,6 +101,11 @@ /* Trace buffer offset for entry */ #define TRACE_BUFFER_ENTRY_OFFSET 16 +/** + * Maximum number of dirty rects supported by FW. + */ +#define DMUB_MAX_DIRTY_RECTS 3 + /** * * PSR control version legacy @@ -165,6 +170,31 @@ union dmub_addr { uint64_t quad_part; /*<< 64 bit address */ }; +/** + * Dirty rect definition. + */ +struct dmub_rect { + /** + * Dirty rect x offset. + */ + uint32_t x; + + /** + * Dirty rect y offset. + */ + uint32_t y; + + /** + * Dirty rect width. + */ + uint32_t width; + + /** + * Dirty rect height. + */ + uint32_t height; +}; + /** * Flags that can be set by driver to change some PSR behaviour. */ @@ -177,6 +207,12 @@ union dmub_psr_debug_flags { * Enable visual confirm in FW. */ uint32_t visual_confirm : 1; + + /** + * Force all selective updates to bw full frame updates. + */ + uint32_t force_full_frame_update : 1; + /** * Use HW Lock Mgr object to do HW locking in FW. */ @@ -616,6 +652,14 @@ enum dmub_cmd_type { * Command type used for all ABM commands. */ DMUB_CMD__ABM = 66, + /** + * Command type used to update dirty rects in FW. + */ + DMUB_CMD__UPDATE_DIRTY_RECT = 67, + /** + * Command type used to update cursor info in FW. + */ + DMUB_CMD__UPDATE_CURSOR_INFO = 68, /** * Command type used for HW locking in FW. */ @@ -1439,6 +1483,10 @@ enum dmub_cmd_psr_type { * Forces PSR enabled until an explicit PSR disable call. */ DMUB_CMD__PSR_FORCE_STATIC = 5, + /** + * Set vtotal in psr active for FreeSync PSR. + */ + DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, /** * Set PSR power option */ @@ -1453,6 +1501,10 @@ enum psr_version { * PSR version 1. */ PSR_VERSION_1 = 0, + /** + * Freesync PSR SU. + */ + PSR_VERSION_SU_1 = 1, /** * PSR not supported. */ @@ -1620,9 +1672,15 @@ struct dmub_cmd_psr_copy_settings_data { */ uint8_t frame_cap_ind; /** - * Explicit padding to 4 byte boundary. + * Granularity of Y offset supported by sink. */ - uint8_t pad[2]; + uint8_t su_y_granularity; + /** + * Indicates whether sink should start capturing + * immediately following active scan line, + * or starting with the 2nd active scan line. + */ + uint8_t line_capture_indication; /** * Multi-display optimizations are implemented on certain ASICs. */ @@ -1633,9 +1691,13 @@ struct dmub_cmd_psr_copy_settings_data { */ uint16_t init_sdp_deadline; /** - * Explicit padding to 4 byte boundary. + * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities + */ + uint8_t rate_control_caps ; + /* + * Force PSRSU always doing full frame update */ - uint16_t pad2; + uint8_t force_ffu_mode; /** * Length of each horizontal line in us. */ @@ -1827,6 +1889,164 @@ struct dmub_rb_cmd_psr_force_static { struct dmub_cmd_psr_force_static_data psr_force_static_data; }; +/** + * PSR SU debug flags. + */ +union dmub_psr_su_debug_flags { + /** + * PSR SU debug flags. + */ + struct { + /** + * Update dirty rect in SW only. + */ + uint8_t update_dirty_rect_only : 1; + /** + * Reset the cursor/plane state before processing the call. + */ + uint8_t reset_state : 1; + } bitfields; + + /** + * Union for debug flags. + */ + uint32_t u32All; +}; + +/** + * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. + * This triggers a selective update for PSR SU. + */ +struct dmub_cmd_update_dirty_rect_data { + /** + * Dirty rects from OS. + */ + struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; + /** + * PSR SU debug flags. + */ + union dmub_psr_su_debug_flags debug_flags; + /** + * OTG HW instance. + */ + uint8_t pipe_idx; + /** + * Number of dirty rects. + */ + uint8_t dirty_rect_count; + /** + * PSR control version. + */ + uint8_t cmd_version; + /** + * Panel Instance. + * Panel isntance to identify which psr_state to use + * Currently the support is only for 0 or 1 + */ + uint8_t panel_inst; +}; + +/** + * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. + */ +struct dmub_rb_cmd_update_dirty_rect { + /** + * Command header. + */ + struct dmub_cmd_header header; + /** + * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. + */ + struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; +}; + +/** + * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. + */ +struct dmub_cmd_update_cursor_info_data { + /** + * Cursor dirty rects. + */ + struct dmub_rect cursor_rect; + /** + * PSR SU debug flags. + */ + union dmub_psr_su_debug_flags debug_flags; + /** + * Cursor enable/disable. + */ + uint8_t enable; + /** + * OTG HW instance. + */ + uint8_t pipe_idx; + /** + * PSR control version. + */ + uint8_t cmd_version; + /** + * Panel Instance. + * Panel isntance to identify which psr_state to use + * Currently the support is only for 0 or 1 + */ + uint8_t panel_inst; +}; +/** + * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. + */ +struct dmub_rb_cmd_update_cursor_info { + /** + * Command header. + */ + struct dmub_cmd_header header; + /** + * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. + */ + struct dmub_cmd_update_cursor_info_data update_cursor_info_data; +}; + +/** + * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. + */ +struct dmub_cmd_psr_set_vtotal_data { + /** + * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. + */ + uint16_t psr_vtotal_idle; + /** + * PSR control version. + */ + uint8_t cmd_version; + /** + * Panel Instance. + * Panel isntance to identify which psr_state to use + * Currently the support is only for 0 or 1 + */ + uint8_t panel_inst; + /* + * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. + */ + uint16_t psr_vtotal_su; + /** + * Explicit padding to 4 byte boundary. + */ + uint8_t pad2[2]; +}; + +/** + * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. + */ +struct dmub_rb_cmd_psr_set_vtotal { + /** + * Command header. + */ + struct dmub_cmd_header header; + /** + * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. + */ + struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; +}; + /** * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. */ @@ -1937,6 +2157,10 @@ enum hw_lock_client { * Driver is the client of HW Lock Manager. */ HW_LOCK_CLIENT_DRIVER = 0, + /** + * PSR SU is the client of HW Lock Manager. + */ + HW_LOCK_CLIENT_PSR_SU = 1, /** * Invalid client. */ @@ -2640,7 +2864,6 @@ struct dmub_rb_cmd_get_usbc_cable_id { * union dmub_rb_cmd - DMUB inbox command. */ union dmub_rb_cmd { - struct dmub_rb_cmd_lock_hw lock_hw; /** * Elements shared with all commands. */ @@ -2701,6 +2924,23 @@ union dmub_rb_cmd { * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. */ struct dmub_rb_cmd_psr_force_static psr_force_static; + /** + * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. + */ + struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; + /** + * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. + */ + struct dmub_rb_cmd_update_cursor_info update_cursor_info; + /** + * Definition of a DMUB_CMD__HW_LOCK command. + * Command is used by driver and FW. + */ + struct dmub_rb_cmd_lock_hw lock_hw; + /** + * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. + */ + struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; /** * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. */ -- cgit v1.2.3 From b3d0c0f2dfbe610ae5ac6b2d70dd450645dce3cb Mon Sep 17 00:00:00 2001 From: David Zhang Date: Tue, 3 May 2022 18:36:28 -0400 Subject: drm/amd/display: feed PSR-SU as psr version to dmub FW [why & how] set psr version as PSR-SU in kernel-FW interface function to ensure the correct dmub command parameter is fed into FW. Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index 1d4f0c45b536..f1411a22cf1e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -133,6 +133,9 @@ static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state * case DC_PSR_VERSION_1: cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_1; break; + case DC_PSR_VERSION_SU_1: + cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_SU_1; + break; case DC_PSR_VERSION_UNSUPPORTED: default: cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_UNSUPPORTED; -- cgit v1.2.3 From 1da5dab029c08e178784a0750203365ea7c3b4f4 Mon Sep 17 00:00:00 2001 From: David Zhang Date: Fri, 29 Apr 2022 15:55:16 -0400 Subject: drm/amd/display: combine dirty rectangles in DMUB FW [why] In PSR-SU design, the DMUB FW handles the combination of multiple dirty rectangles. [how] - create DC dmub update dirty rectangle helper which sends the dirty rectangles per pipe from DC to DMUB, and DMUB FW will handle to combine the dirty RECTs - call the helper from DC commit plane update function. Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 54 ++++++++++++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dc_stream.h | 5 +++ 2 files changed, 59 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e3e3b2791632..d4173be11903 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -72,6 +72,9 @@ #include "dmub/dmub_srv.h" #include "i2caux_interface.h" + +#include "dce/dmub_psr.h" + #include "dce/dmub_hw_lock_mgr.h" #include "dc_trace.h" @@ -2824,6 +2827,55 @@ static void commit_planes_do_stream_update(struct dc *dc, } } +void dc_dmub_update_dirty_rect(struct dc *dc, + int surface_count, + struct dc_stream_state *stream, + struct dc_surface_update *srf_updates, + struct dc_state *context) +{ + union dmub_rb_cmd cmd; + struct dc_context *dc_ctx = dc->ctx; + struct dmub_cmd_update_dirty_rect_data *update_dirty_rect; + unsigned int i, j; + + if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1) + return; + + memset(&cmd, 0x0, sizeof(cmd)); + cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT; + cmd.update_dirty_rect.header.sub_type = 0; + cmd.update_dirty_rect.header.payload_bytes = + sizeof(cmd.update_dirty_rect) - + sizeof(cmd.update_dirty_rect.header); + update_dirty_rect = &cmd.update_dirty_rect.update_dirty_rect_data; + for (i = 0; i < surface_count; i++) { + struct dc_plane_state *plane_state = srf_updates[i].surface; + const struct dc_flip_addrs *flip_addr = srf_updates[i].flip_addr; + + if (!srf_updates[i].surface || !flip_addr) + continue; + /* Do not send in immediate flip mode */ + if (srf_updates[i].surface->flip_immediate) + continue; + + update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count; + memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects, + sizeof(flip_addr->dirty_rects)); + for (j = 0; j < dc->res_pool->pipe_count; j++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; + + if (pipe_ctx->stream != stream) + continue; + if (pipe_ctx->plane_state != plane_state) + continue; + + update_dirty_rect->pipe_idx = j; + dc_dmub_srv_cmd_queue(dc_ctx->dmub_srv, &cmd); + dc_dmub_srv_cmd_execute(dc_ctx->dmub_srv); + } + } +} + static void commit_planes_for_stream(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, @@ -2911,6 +2963,8 @@ static void commit_planes_for_stream(struct dc *dc, dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true); } + dc_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context); + // Stream updates if (stream_update) commit_planes_do_stream_update(dc, stream, stream_update, update_type, context); diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 772b4a61f166..f8f66790d09b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -550,4 +550,9 @@ bool dc_stream_get_crtc_position(struct dc *dc, struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream); +void dc_dmub_update_dirty_rect(struct dc *dc, + int surface_count, + struct dc_stream_state *stream, + struct dc_surface_update *srf_updates, + struct dc_state *context); #endif /* DC_STREAM_H_ */ -- cgit v1.2.3 From 3a6dce778de7c120a37983d80b6ccc8c2c4ff6ec Mon Sep 17 00:00:00 2001 From: David Zhang Date: Fri, 29 Apr 2022 17:32:56 -0400 Subject: drm/amd/display: update GSP1 generic info packet for PSRSU [why & how] Based on PSRSU specification, every selective update frame need to use two SDP to indicate the frame active range. So we occupy another GSP1 for PSRSU execution. Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c index b683ad817106..1a26ce87c16e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c @@ -419,6 +419,21 @@ void enc3_stream_encoder_update_dp_info_packets( &info_frame->vsc, true); } + /* TODO: VSC SDP at packetIndex 1 should be restricted only if PSR-SU on. + * There should have another Infopacket type (e.g. vsc_psrsu) for PSR_SU. + * In addition, currently the driver check the valid bit then update and + * send the corresponding Infopacket. For PSR-SU, the SDP only be sent + * while entering PSR-SU mode. So we need another parameter(e.g. send) + * in dc_info_packet to indicate which infopacket should be enabled by + * default here. + */ + if (info_frame->vsc.valid) { + enc->vpg->funcs->update_generic_info_packet( + enc->vpg, + 1, /* packetIndex */ + &info_frame->vsc, + true); + } if (info_frame->spd.valid) { enc->vpg->funcs->update_generic_info_packet( enc->vpg, -- cgit v1.2.3 From aa303964bc349914de8e1d3ff7b517581839d01b Mon Sep 17 00:00:00 2001 From: David Zhang Date: Fri, 29 Apr 2022 17:38:14 -0400 Subject: drm/amd/display: revise Start/End SDP data [why & how] We need to implement the VSC packet rev4 that is required by PSRSU. Follow the eDP 1.5 spec pg. 257 changes in v2: ------------------- - set vsc packet rev2 for PSR1 Cc: Chandan Vurdigerenataraj Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/modules/info_packet/info_packet.c | 29 ++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c index 79bc207415bc..27ceba9d6d65 100644 --- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c +++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c @@ -145,8 +145,10 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream, stereo3dSupport = true; } - /*VSC packet set to 2 when DP revision >= 1.2*/ - if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) + /* VSC packet set to 4 for PSR-SU, or 2 for PSR1 */ + if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) + vsc_packet_revision = vsc_packet_rev4; + else if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) vsc_packet_revision = vsc_packet_rev2; /* Update to revision 5 for extended colorimetry support */ @@ -159,6 +161,29 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream, if (vsc_packet_revision == vsc_packet_undefined) return; + if (vsc_packet_revision == vsc_packet_rev4) { + /* Secondary-data Packet ID = 0*/ + info_packet->hb0 = 0x00; + /* 07h - Packet Type Value indicating Video + * Stream Configuration packet + */ + info_packet->hb1 = 0x07; + /* 04h = VSC SDP supporting 3D stereo + PSR/PSR2 + Y-coordinate + * (applies to eDP v1.4 or higher). + */ + info_packet->hb2 = 0x04; + /* 0Eh = VSC SDP supporting 3D stereo + PSR2 + * (HB2 = 04h), with Y-coordinate of first scan + * line of the SU region + */ + info_packet->hb3 = 0x0E; + + for (i = 0; i < 28; i++) + info_packet->sb[i] = 0; + + info_packet->valid = true; + } + if (vsc_packet_revision == vsc_packet_rev2) { /* Secondary-data Packet ID = 0*/ info_packet->hb0 = 0x00; -- cgit v1.2.3 From 6d1044a070b2eef0be45f3b99274a6cebee25053 Mon Sep 17 00:00:00 2001 From: David Zhang Date: Mon, 2 May 2022 11:05:56 -0400 Subject: drm/amd/display: program PSR2 DPCD Configuration [Why] To support PSR2 Source DPCD configuration [How] Update the PSR2 Source DPCD settings while the PSR2 enabled Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 23 +++++++++++++++++++++- .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 13 +++++++++++- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 55a8f58ee239..97bb2d876426 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -3206,6 +3206,7 @@ bool dc_link_setup_psr(struct dc_link *link, unsigned int panel_inst; /* updateSinkPsrDpcdConfig*/ union dpcd_psr_configuration psr_configuration; + union dpcd_alpm_configuration alpm_configuration; psr_context->controllerId = CONTROLLER_ID_UNDEFINED; @@ -3231,7 +3232,7 @@ bool dc_link_setup_psr(struct dc_link *link, psr_config->psr_frame_capture_indication_req; /* Check for PSR v2*/ - if (psr_config->psr_version == 0x2) { + if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) { /* For PSR v2 selective update. * Indicates whether sink should start capturing * immediately following active scan line, @@ -3242,6 +3243,14 @@ bool dc_link_setup_psr(struct dc_link *link, * IRQ_HPD when CRC mismatch is detected. */ psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR = 1; + /* For PSR v2, set the bit when the Source device will + * be enabling PSR2 operation. + */ + psr_configuration.bits.ENABLE_PSR2 = 1; + /* For PSR v2, the Sink device must be able to receive + * SU region updates early in the frame time. + */ + psr_configuration.bits.EARLY_TRANSPORT_ENABLE = 1; } dm_helpers_dp_write_dpcd( @@ -3251,6 +3260,18 @@ bool dc_link_setup_psr(struct dc_link *link, &psr_configuration.raw, sizeof(psr_configuration.raw)); + if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) { + memset(&alpm_configuration, 0, sizeof(alpm_configuration)); + + alpm_configuration.bits.ENABLE = 1; + dm_helpers_dp_write_dpcd( + link->ctx, + link, + DP_RECEIVER_ALPM_CONFIG, + &alpm_configuration.raw, + sizeof(alpm_configuration.raw)); + } + psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel; psr_context->transmitterId = link->link_enc->transmitter; psr_context->engineId = link->link_enc->preferred_engine; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index d8433c679201..6e6bd007babc 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -85,7 +85,18 @@ union dpcd_psr_configuration { unsigned char LINE_CAPTURE_INDICATION : 1; /* For eDP 1.4, PSR v2*/ unsigned char IRQ_HPD_WITH_CRC_ERROR : 1; - unsigned char RESERVED : 2; + unsigned char ENABLE_PSR2 : 1; + /* For eDP 1.5, PSR v2 w/ early transport */ + unsigned char EARLY_TRANSPORT_ENABLE : 1; + } bits; + unsigned char raw; +}; + +union dpcd_alpm_configuration { + struct { + unsigned char ENABLE : 1; + unsigned char IRQ_HPD_ENABLE : 1; + unsigned char RESERVED : 6; } bits; unsigned char raw; }; -- cgit v1.2.3 From 651d7ee63f338b82d18273c30e9ea804ae174342 Mon Sep 17 00:00:00 2001 From: Somalapuram Amaranath Date: Thu, 2 Jun 2022 12:54:58 +0530 Subject: drm/amdgpu: save the reset dump register value for devcoredump Allocate memory for register value and use the same values for devcoredump. v1 -> v2: Change krealloc_array() to kmalloc_array() v2 -> v3: Fix alignment Signed-off-by: Somalapuram Amaranath Reviewed-by: Shashank Sharma Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 7 +++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++--- 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 3ec7427c018c..1525fa1d6798 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1044,6 +1044,7 @@ struct amdgpu_device { /* reset dump register */ uint32_t *reset_dump_reg_list; + uint32_t *reset_dump_reg_value; int num_regs; bool scpm_enabled; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index eedb12f6b8a3..f3ac7912c29c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -1709,17 +1709,24 @@ static ssize_t amdgpu_reset_dump_register_list_write(struct file *f, i++; } while (len < size); + new = kmalloc_array(i, sizeof(uint32_t), GFP_KERNEL); + if (!new) { + ret = -ENOMEM; + goto error_free; + } ret = down_write_killable(&adev->reset_domain->sem); if (ret) goto error_free; swap(adev->reset_dump_reg_list, tmp); + swap(adev->reset_dump_reg_value, new); adev->num_regs = i; up_write(&adev->reset_domain->sem); ret = size; error_free: kfree(tmp); + kfree(new); return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 4831148342b7..c56b04e9ce9a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4666,15 +4666,15 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev) { - uint32_t reg_value; int i; lockdep_assert_held(&adev->reset_domain->sem); dump_stack(); for (i = 0; i < adev->num_regs; i++) { - reg_value = RREG32(adev->reset_dump_reg_list[i]); - trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i], reg_value); + adev->reset_dump_reg_value[i] = RREG32(adev->reset_dump_reg_list[i]); + trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i], + adev->reset_dump_reg_value[i]); } return 0; -- cgit v1.2.3 From 3d8785f6c04a953868384db455bb2fdd0b22c11c Mon Sep 17 00:00:00 2001 From: Somalapuram Amaranath Date: Thu, 2 Jun 2022 13:01:27 +0530 Subject: drm/amdgpu: adding device coredump support Added device coredump information: - Kernel version - Module - Time - VRAM status - Guilty process name and PID - GPU register dumps v1 -> v2: Variable name change v1 -> v2: NULL check v1 -> v2: Code alignment v1 -> v2: Adding dummy amdgpu_devcoredump_free v1 -> v2: memset reset_task_info to zero v2 -> v3: add CONFIG_DEV_COREDUMP for variables v2 -> v3: remove NULL check on amdgpu_devcoredump_read Signed-off-by: Somalapuram Amaranath Reviewed-by: Shashank Sharma Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 64 ++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 1525fa1d6798..c67069645a2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1046,6 +1046,11 @@ struct amdgpu_device { uint32_t *reset_dump_reg_list; uint32_t *reset_dump_reg_value; int num_regs; +#ifdef CONFIG_DEV_COREDUMP + struct amdgpu_task_info reset_task_info; + bool reset_vram_lost; + struct timespec64 reset_time; +#endif bool scpm_enabled; uint32_t scpm_status; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index c56b04e9ce9a..620afd75dae7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -32,6 +32,8 @@ #include #include #include +#include +#include #include #include @@ -4680,6 +4682,59 @@ static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev) return 0; } +#ifdef CONFIG_DEV_COREDUMP +static ssize_t amdgpu_devcoredump_read(char *buffer, loff_t offset, + size_t count, void *data, size_t datalen) +{ + struct drm_printer p; + struct amdgpu_device *adev = data; + struct drm_print_iterator iter; + int i; + + iter.data = buffer; + iter.offset = 0; + iter.start = offset; + iter.remain = count; + + p = drm_coredump_printer(&iter); + + drm_printf(&p, "**** AMDGPU Device Coredump ****\n"); + drm_printf(&p, "kernel: " UTS_RELEASE "\n"); + drm_printf(&p, "module: " KBUILD_MODNAME "\n"); + drm_printf(&p, "time: %lld.%09ld\n", adev->reset_time.tv_sec, adev->reset_time.tv_nsec); + if (adev->reset_task_info.pid) + drm_printf(&p, "process_name: %s PID: %d\n", + adev->reset_task_info.process_name, + adev->reset_task_info.pid); + + if (adev->reset_vram_lost) + drm_printf(&p, "VRAM is lost due to GPU reset!\n"); + if (adev->num_regs) { + drm_printf(&p, "AMDGPU register dumps:\nOffset: Value:\n"); + + for (i = 0; i < adev->num_regs; i++) + drm_printf(&p, "0x%08x: 0x%08x\n", + adev->reset_dump_reg_list[i], + adev->reset_dump_reg_value[i]); + } + + return count - iter.remain; +} + +static void amdgpu_devcoredump_free(void *data) +{ +} + +static void amdgpu_reset_capture_coredumpm(struct amdgpu_device *adev) +{ + struct drm_device *dev = adev_to_drm(adev); + + ktime_get_ts64(&adev->reset_time); + dev_coredumpm(dev->dev, THIS_MODULE, adev, 0, GFP_KERNEL, + amdgpu_devcoredump_read, amdgpu_devcoredump_free); +} +#endif + int amdgpu_do_asic_reset(struct list_head *device_list_handle, struct amdgpu_reset_context *reset_context) { @@ -4764,6 +4819,15 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, goto out; vram_lost = amdgpu_device_check_vram_lost(tmp_adev); +#ifdef CONFIG_DEV_COREDUMP + tmp_adev->reset_vram_lost = vram_lost; + memset(&tmp_adev->reset_task_info, 0, + sizeof(tmp_adev->reset_task_info)); + if (reset_context->job && reset_context->job->vm) + tmp_adev->reset_task_info = + reset_context->job->vm->task_info; + amdgpu_reset_capture_coredumpm(tmp_adev); +#endif if (vram_lost) { DRM_INFO("VRAM is lost due to GPU reset!\n"); amdgpu_inc_vram_lost(tmp_adev); -- cgit v1.2.3 From b07d1d73b09ef40e91ace51a2e167391676a8175 Mon Sep 17 00:00:00 2001 From: Arunpravin Paneer Selvam Date: Mon, 6 Jun 2022 13:06:30 +0530 Subject: drm/amd/amdgpu: Enable high priority gfx queue MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Starting from SIENNA CICHLID asic supports two gfx pipes, enabling two graphics queues, 1 on each pipe, pipe0 queue0 would be the normal piority queue and pipe1 queue0 would be the high priority queue Only one queue per pipe is visble to SPI, SPI looks at the priority value assigned to CP_GFX_HQD_QUEUE_PRIORITY from each of the queue's HQD/MQD. Create contexts applying AMDGPU_CTX_PRIORITY_HIGH which submits job to the high priority queue on GFX pipe1. There would be starvation of LP workload if HP workload is always available. v2: - remove unnecessary check(Nirmoy) - make pipe1 hardware support a separate patch(Nirmoy) - remove duplicate code(Shashank) - add CSA support for second gfx pipe(Alex) v3(Christian): - fix incorrect indentation - merge COMPUTE and GFX switch cases as both calls the same function. v4: - rebase w/ latest code base Signed-off-by: Arunpravin Paneer Selvam Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 7 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 55 +++++++++++++++++++++++++------- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 12 +++---- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 32 +++++++++++++++---- 5 files changed, 81 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index 7dc92ef36b2b..2ef5296216d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -110,7 +110,7 @@ static int amdgpu_ctx_priority_permit(struct drm_file *filp, return -EACCES; } -static enum amdgpu_gfx_pipe_priority amdgpu_ctx_prio_to_compute_prio(int32_t prio) +static enum amdgpu_gfx_pipe_priority amdgpu_ctx_prio_to_gfx_pipe_prio(int32_t prio) { switch (prio) { case AMDGPU_CTX_PRIORITY_HIGH: @@ -143,8 +143,9 @@ static unsigned int amdgpu_ctx_get_hw_prio(struct amdgpu_ctx *ctx, u32 hw_ip) ctx->init_priority : ctx->override_priority; switch (hw_ip) { + case AMDGPU_HW_IP_GFX: case AMDGPU_HW_IP_COMPUTE: - hw_prio = amdgpu_ctx_prio_to_compute_prio(ctx_prio); + hw_prio = amdgpu_ctx_prio_to_gfx_pipe_prio(ctx_prio); break; case AMDGPU_HW_IP_VCE: case AMDGPU_HW_IP_VCN_ENC: @@ -779,7 +780,7 @@ static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx, amdgpu_ctx_to_drm_sched_prio(priority)); /* set hw priority */ - if (hw_ip == AMDGPU_HW_IP_COMPUTE) { + if (hw_ip == AMDGPU_HW_IP_COMPUTE || hw_ip == AMDGPU_HW_IP_GFX) { hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip); hw_prio = array_index_nospec(hw_prio, AMDGPU_RING_PRIO_MAX); scheds = adev->gpu_sched[hw_ip][hw_prio].sched; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 16699158e00d..00c69f0a9f52 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -142,7 +142,12 @@ void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_s } } -static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev) +static bool amdgpu_gfx_is_graphics_multipipe_capable(struct amdgpu_device *adev) +{ + return amdgpu_async_gfx_ring && adev->gfx.me.num_pipe_per_me > 1; +} + +static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev) { if (amdgpu_compute_multipipe != -1) { DRM_INFO("amdgpu: forcing compute pipe policy %d\n", @@ -158,6 +163,28 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev) return adev->gfx.mec.num_mec > 1; } +bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev, + struct amdgpu_ring *ring) +{ + int queue = ring->queue; + int pipe = ring->pipe; + + /* Policy: use pipe1 queue0 as high priority graphics queue if we + * have more than one gfx pipe. + */ + if (amdgpu_gfx_is_graphics_multipipe_capable(adev) && + adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) { + int me = ring->me; + int bit; + + bit = amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue); + if (ring == &adev->gfx.gfx_ring[bit]) + return true; + } + + return false; +} + bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring) { @@ -174,7 +201,7 @@ bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev) { int i, queue, pipe; - bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev); + bool multipipe_policy = amdgpu_gfx_is_compute_multipipe_capable(adev); int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_queue_per_pipe, adev->gfx.num_compute_rings); @@ -200,18 +227,24 @@ void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev) void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev) { - int i, queue, me; - - for (i = 0; i < AMDGPU_MAX_GFX_QUEUES; ++i) { - queue = i % adev->gfx.me.num_queue_per_pipe; - me = (i / adev->gfx.me.num_queue_per_pipe) - / adev->gfx.me.num_pipe_per_me; + int i, queue, pipe; + bool multipipe_policy = amdgpu_gfx_is_graphics_multipipe_capable(adev); + int max_queues_per_me = adev->gfx.me.num_pipe_per_me * + adev->gfx.me.num_queue_per_pipe; - if (me >= adev->gfx.me.num_me) - break; + if (multipipe_policy) { /* policy: amdgpu owns the first queue per pipe at this stage * will extend to mulitple queues per pipe later */ - if (me == 0 && queue < 1) + for (i = 0; i < max_queues_per_me; i++) { + pipe = i % adev->gfx.me.num_pipe_per_me; + queue = (i / adev->gfx.me.num_pipe_per_me) % + adev->gfx.me.num_queue_per_pipe; + + set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue, + adev->gfx.me.queue_bitmap); + } + } else { + for (i = 0; i < max_queues_per_me; ++i) set_bit(i, adev->gfx.me.queue_bitmap); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 53526ffb2ce1..23a696d38390 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -396,6 +396,8 @@ bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec, int pipe, int queue); bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring); +bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev, + struct amdgpu_ring *ring); int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me, int pipe, int queue); void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 13db99d653bd..1fa9edf04022 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -543,12 +543,12 @@ static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring, */ prop->hqd_active = ring->funcs->type == AMDGPU_RING_TYPE_KIQ; - if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { - if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { - prop->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; - prop->hqd_queue_priority = - AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; - } + if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE && + amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) || + (ring->funcs->type == AMDGPU_RING_TYPE_GFX && + amdgpu_gfx_is_high_priority_graphics_queue(adev, ring))) { + prop->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; + prop->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; } } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index c5f46d264b23..6831d1eb18bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -53,7 +53,7 @@ * 2. Async ring */ #define GFX10_NUM_GFX_RINGS_NV1X 1 -#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1 +#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 #define GFX10_MEC_HPD_SIZE 2048 #define F32_CE_PROGRAM_RAM_SIZE 65536 @@ -4711,6 +4711,7 @@ static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, { struct amdgpu_ring *ring; unsigned int irq_type; + unsigned int hw_prio; ring = &adev->gfx.gfx_ring[ring_id]; @@ -4728,8 +4729,10 @@ static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; + hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? + AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, - AMDGPU_RING_PRIO_DEFAULT, NULL); + hw_prio, NULL); } static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, @@ -6581,6 +6584,24 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) } } +static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, + struct v10_gfx_mqd *mqd, + struct amdgpu_mqd_prop *prop) +{ + bool priority = 0; + u32 tmp; + + /* set up default queue priority level + * 0x0 = low priority, 0x1 = high priority + */ + if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) + priority = 1; + + tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); + tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); + mqd->cp_gfx_hqd_queue_priority = tmp; +} + static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, struct amdgpu_mqd_prop *prop) { @@ -6609,11 +6630,8 @@ static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); mqd->cp_gfx_hqd_vmid = 0; - /* set up default queue priority level - * 0x0 = low priority, 0x1 = high priority */ - tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); - tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); - mqd->cp_gfx_hqd_queue_priority = tmp; + /* set up gfx queue priority */ + gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop); /* set up time quantum */ tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); -- cgit v1.2.3 From 4c7631800e6bf0eced08dd7b4f793fcd972f597d Mon Sep 17 00:00:00 2001 From: Arunpravin Paneer Selvam Date: Mon, 6 Jun 2022 13:59:13 +0530 Subject: drm/amd/amdgpu: add pipe1 hardware support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable pipe1 support starting from SIENNA CICHLID asic Signed-off-by: Arunpravin Paneer Selvam Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 6831d1eb18bf..797e90e8ce28 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4794,7 +4794,7 @@ static int gfx_v10_0_sw_init(void *handle) case IP_VERSION(10, 3, 3): case IP_VERSION(10, 3, 7): adev->gfx.me.num_me = 1; - adev->gfx.me.num_pipe_per_me = 1; + adev->gfx.me.num_pipe_per_me = 2; adev->gfx.me.num_queue_per_pipe = 1; adev->gfx.mec.num_mec = 2; adev->gfx.mec.num_pipe_per_mec = 4; -- cgit v1.2.3 From a35806b36ea44724b21f7f110b38b5941fc9c393 Mon Sep 17 00:00:00 2001 From: David Zhang Date: Mon, 2 May 2022 11:21:25 -0400 Subject: drm/amd/display: Passing Y-granularity to dmub fw [Why] The Y-granularity panel parameter indicate the grid pattern granularity in the Y direction for PSRSU. [How] Send the Y-granularity data by PSR_COPY_SETTINGS dmub command. Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++++ drivers/gpu/drm/amd/display/dc/dc_types.h | 8 ++++++++ drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 97bb2d876426..dc1d75b204cd 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -3270,6 +3270,10 @@ bool dc_link_setup_psr(struct dc_link *link, DP_RECEIVER_ALPM_CONFIG, &alpm_configuration.raw, sizeof(alpm_configuration.raw)); + psr_context->su_granularity_required = + psr_config->su_granularity_required; + psr_context->su_y_granularity = + psr_config->su_y_granularity; } psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel; diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 2ba9f528c0fe..d61ea3e2bfbf 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -672,6 +672,10 @@ struct psr_config { unsigned int psr_sdp_transmit_line_num_deadline; bool allow_smu_optimizations; bool allow_multi_disp_optimizations; + /* Panel self refresh 2 selective update granularity required */ + bool su_granularity_required; + /* psr2 selective update y granularity capability */ + uint8_t su_y_granularity; }; union dmcu_psr_level { @@ -775,6 +779,10 @@ struct psr_context { unsigned int frame_delay; bool allow_smu_optimizations; bool allow_multi_disp_optimizations; + /* Panel self refresh 2 selective update granularity required */ + bool su_granularity_required; + /* psr2 selective update y granularity capability */ + uint8_t su_y_granularity; }; struct colorspace_transform { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index f1411a22cf1e..6883dd5b80d6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -333,6 +333,12 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->debug.u32All = 0; copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR; copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1; + + if (psr_context->su_granularity_required == 0) + copy_settings_data->su_y_granularity = 0; + else + copy_settings_data->su_y_granularity = psr_context->su_y_granularity; + copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled); copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us; copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; -- cgit v1.2.3 From 65657d98754c581ad66b56680d3c9ed679890071 Mon Sep 17 00:00:00 2001 From: David Zhang Date: Mon, 2 May 2022 11:48:22 -0400 Subject: drm/amd/display: Set default value of line_capture_indication [Why & how] We only support line capture indication as 0 for PSRSU Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index 6883dd5b80d6..bc4943205bce 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -339,6 +339,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, else copy_settings_data->su_y_granularity = psr_context->su_y_granularity; + copy_settings_data->line_capture_indication = 0; copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled); copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us; copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; -- cgit v1.2.3 From 32c453f18dccd93a27d6f026ca690167c8cc9639 Mon Sep 17 00:00:00 2001 From: David Zhang Date: Mon, 2 May 2022 11:59:58 -0400 Subject: drm/amd/display: add vline time in micro sec to PSR context [why] The current PSR SU programming margin is fixed base on FHD 60HZ panel. If the resolution and refresh rate become higher, the time of current margin might not cover the programming SU time. [how] Notice that the programming SU time is the same among different panels. Instead of fixing the margin with target line number, change the margin unit to micro second which indicate the time needed for programming SU. Then FW set the margin line number base on the line time and margin time. Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 ++ drivers/gpu/drm/amd/display/dc/dc_types.h | 2 ++ drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 + 3 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index dc1d75b204cd..68e9fc6b510c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -3274,6 +3274,8 @@ bool dc_link_setup_psr(struct dc_link *link, psr_config->su_granularity_required; psr_context->su_y_granularity = psr_config->su_y_granularity; + psr_context->line_time_in_us = + psr_config->line_time_in_us; } psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel; diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index d61ea3e2bfbf..119ce8b7a555 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -676,6 +676,7 @@ struct psr_config { bool su_granularity_required; /* psr2 selective update y granularity capability */ uint8_t su_y_granularity; + unsigned int line_time_in_us; }; union dmcu_psr_level { @@ -783,6 +784,7 @@ struct psr_context { bool su_granularity_required; /* psr2 selective update y granularity capability */ uint8_t su_y_granularity; + unsigned int line_time_in_us; }; struct colorspace_transform { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index bc4943205bce..c2d65756ce5d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -340,6 +340,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->su_y_granularity = psr_context->su_y_granularity; copy_settings_data->line_capture_indication = 0; + copy_settings_data->line_time_in_us = psr_context->line_time_in_us; copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled); copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us; copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; -- cgit v1.2.3 From 6cc5c77300afbb285c4f41e04f3435ae3c484c40 Mon Sep 17 00:00:00 2001 From: David Zhang Date: Tue, 3 May 2022 10:49:52 -0400 Subject: drm/amd/display: fix system hang when PSR exits [why] When DC driver send PSR exit dmub command to DMUB FW, it might not wait until PSR exit. Then it may hit the following deadlock situation. 1. DC driver send HW LOCK command to DMUB FW due to frame update 2. DMUB FW Set the HW lock 3. DMUB execute PSR exit sequence and stuck at polling DPG Pending register due to the HW Lock is set 4. DC driver ask DMUB FW to unlock HW lock, but DMUB FW is polling DPG pending register [how] The reason why DC driver doesn't wait until PSR exit is because some of the PSR state machine state is not update the dc driver. So when DC driver read back the PSR state, it take the state for PSR inactive. Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc_types.h | 7 +++++++ drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 16 ++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 119ce8b7a555..144c387010c2 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -657,10 +657,17 @@ enum dc_psr_state { PSR_STATE4b, PSR_STATE4c, PSR_STATE4d, + PSR_STATE4_FULL_FRAME, + PSR_STATE4a_FULL_FRAME, + PSR_STATE4b_FULL_FRAME, + PSR_STATE4c_FULL_FRAME, + PSR_STATE4_FULL_FRAME_POWERUP, PSR_STATE5, PSR_STATE5a, PSR_STATE5b, PSR_STATE5c, + PSR_STATE_HWLOCK_MGR, + PSR_STATE_POLLVUPDATE, PSR_STATE_INVALID = 0xFF }; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index c2d65756ce5d..e784002fe312 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -74,6 +74,22 @@ static enum dc_psr_state convert_psr_state(uint32_t raw_state) state = PSR_STATE5b; else if (raw_state == 0x53) state = PSR_STATE5c; + else if (raw_state == 0x4A) + state = PSR_STATE4_FULL_FRAME; + else if (raw_state == 0x4B) + state = PSR_STATE4a_FULL_FRAME; + else if (raw_state == 0x4C) + state = PSR_STATE4b_FULL_FRAME; + else if (raw_state == 0x4D) + state = PSR_STATE4c_FULL_FRAME; + else if (raw_state == 0x4E) + state = PSR_STATE4_FULL_FRAME_POWERUP; + else if (raw_state == 0x60) + state = PSR_STATE_HWLOCK_MGR; + else if (raw_state == 0x61) + state = PSR_STATE_POLLVUPDATE; + else + state = PSR_STATE_INVALID; return state; } -- cgit v1.2.3 From c7eac19eda0a82f0c1dd9455012754445772fd09 Mon Sep 17 00:00:00 2001 From: David Zhang Date: Tue, 3 May 2022 10:56:54 -0400 Subject: drm/amd/display: Set PSR level to enable ALPM by default [Why & How] While support ALPM, do ALPM state transition while PSR entry/exit. ALPM is needed for PSR-SU feature, and since the function is ready, we'd enable it by default. - Add psr level definition to enable/disable ALPM and set ALPM powerdone mode. - Enable ALPM by default Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++++ drivers/gpu/drm/amd/display/dc/dc_types.h | 4 +++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 68e9fc6b510c..31ffb961e18b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -3364,6 +3364,10 @@ bool dc_link_setup_psr(struct dc_link *link, */ psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1; + /* enable ALPM */ + psr_context->psr_level.bits.DISABLE_ALPM = 0; + psr_context->psr_level.bits.ALPM_DEFAULT_PD_MODE = 1; + /* Controls additional delay after remote frame capture before * continuing power down, default = 0 */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 144c387010c2..26b62f50ac4e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -698,7 +698,9 @@ union dmcu_psr_level { unsigned int SKIP_AUTO_STATE_ADVANCE:1; unsigned int DISABLE_PSR_ENTRY_ABORT:1; unsigned int SKIP_SINGLE_OTG_DISABLE:1; - unsigned int RESERVED:22; + unsigned int DISABLE_ALPM:1; + unsigned int ALPM_DEFAULT_PD_MODE:1; + unsigned int RESERVED:20; } bits; unsigned int u32all; }; -- cgit v1.2.3 From c2a050c5e07faf9ed2fa1daa1eb642d9da4a879d Mon Sep 17 00:00:00 2001 From: David Zhang Date: Tue, 3 May 2022 17:28:18 -0400 Subject: drm/amd/display: use HW lock mgr for PSR-SU [why] Feature requires synchronization of dig, pipe, and cursor locking between driver and DMUB fw for PSR-SU [how] return True if PSR-SU in the checker should_use_dmub_lock() Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c index b1b2e3c6f379..3f32e9c3fbaf 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c @@ -65,5 +65,7 @@ void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv, bool should_use_dmub_lock(struct dc_link *link) { + if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) + return true; return false; } -- cgit v1.2.3 From e61a048eabf9d1245f86e67ec4787d2f10e5a1e0 Mon Sep 17 00:00:00 2001 From: David Zhang Date: Tue, 3 May 2022 18:19:39 -0400 Subject: drm/amd/display: PSRSU+DSC WA for specific TCON [why] Some specific TCON chip has HW limitation to support PSRSU+DSC. [how] Force ffu mode when DSC enabled if we detect it is the specific model from sink OUI DPCD. And disable ABM update for this case. Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc_link.h | 1 + drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h index a3c37ee3f849..0bec986a6de8 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_link.h +++ b/drivers/gpu/drm/amd/display/dc/dc_link.h @@ -108,6 +108,7 @@ struct psr_settings { */ bool psr_frame_capture_indication_req; unsigned int psr_sdp_transmit_line_num_deadline; + uint8_t force_ffu_mode; unsigned int psr_power_opt; }; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index e784002fe312..9ca0cbb0af9b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -349,6 +349,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->debug.u32All = 0; copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR; copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1; + copy_settings_data->debug.bitfields.force_full_frame_update = 0; if (psr_context->su_granularity_required == 0) copy_settings_data->su_y_granularity = 0; @@ -363,6 +364,19 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->panel_inst = panel_inst; copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1); + /** + * WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update) + * Note that PSRSU+DSC is still under development. + */ + if (copy_settings_data->dsc_enable_status && + link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 && + !memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1, + sizeof(link->dpcd_caps.sink_dev_id_str))) + link->psr_settings.force_ffu_mode = 1; + else + link->psr_settings.force_ffu_mode = 0; + copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode; + if (link->fec_state == dc_link_fec_enabled && (!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1, sizeof(link->dpcd_caps.sink_dev_id_str)) || -- cgit v1.2.3 From 65e7a17499e15771339d85eaa1ba686ad2fe342c Mon Sep 17 00:00:00 2001 From: David Zhang Date: Mon, 25 Apr 2022 18:08:13 -0400 Subject: drm/amd/display: add shared helpers to update psr config fields to power module [why] Currently the amdgpu DM psr configuration parameters are hardcoded before feeding into the DC helper to setup PSR. We would define a helper which is to calculate parts of the psr config fields to avoid hard-coding. [how] To make helper shareable, declare and define the helper in the module_helper, to set/update below fields: - psr remote buffer setup time - sdp tx line number deadline - line time in us - su_y_granularity - su_granularity_required - psr_frame_capture_indication_req - psr_exit_link_training_required add another helper to check given the stream context, if there is only one stream and the output is eDP panel connected. changes in v2: ------------------ - add detailed comment for how psr setup time is calculated as per eDP 1.5 spec Cc: Chandan Vurdigerenataraj Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/modules/power/power_helpers.c | 84 ++++++++++++++++++++++ .../drm/amd/display/modules/power/power_helpers.h | 6 ++ 2 files changed, 90 insertions(+) diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c index 97928d4c3b9a..bc239d38c3c7 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c @@ -822,3 +822,87 @@ bool is_psr_su_specific_panel(struct dc_link *link) return false; } + +/** + * mod_power_calc_psr_configs() - calculate/update generic psr configuration fields. + * @psr_config: [output], psr configuration structure to be updated + * @link: [input] dc link pointer + * @stream: [input] dc stream state pointer + * + * calculate and update the psr configuration fields that are not DM specific, i.e. such + * fields which are based on DPCD caps or timing information. To setup PSR in DMUB FW, + * this helper is assumed to be called before the call of the DC helper dc_link_setup_psr(). + * + * PSR config fields to be updated within the helper: + * - psr_rfb_setup_time + * - psr_sdp_transmit_line_num_deadline + * - line_time_in_us + * - su_y_granularity + * - su_granularity_required + * - psr_frame_capture_indication_req + * - psr_exit_link_training_required + * + * PSR config fields that are DM specific and NOT updated within the helper: + * - allow_smu_optimizations + * - allow_multi_disp_optimizations + */ +void mod_power_calc_psr_configs(struct psr_config *psr_config, + struct dc_link *link, + const struct dc_stream_state *stream) +{ + unsigned int num_vblank_lines = 0; + unsigned int vblank_time_in_us = 0; + unsigned int sdp_tx_deadline_in_us = 0; + unsigned int line_time_in_us = 0; + struct dpcd_caps *dpcd_caps = &link->dpcd_caps; + const int psr_setup_time_step_in_us = 55; /* refer to eDP spec DPCD 0x071h */ + + /* timing parameters */ + num_vblank_lines = stream->timing.v_total - + stream->timing.v_addressable - + stream->timing.v_border_top - + stream->timing.v_border_bottom; + + vblank_time_in_us = (stream->timing.h_total * num_vblank_lines * 1000) / (stream->timing.pix_clk_100hz / 10); + + line_time_in_us = ((stream->timing.h_total * 1000) / (stream->timing.pix_clk_100hz / 10)) + 1; + + /** + * psr configuration fields + * + * as per eDP 1.5 pg. 377 of 459, DPCD 0x071h bits [3:1], psr setup time bits interpreted as below + * 000b <--> 330 us (default) + * 001b <--> 275 us + * 010b <--> 220 us + * 011b <--> 165 us + * 100b <--> 110 us + * 101b <--> 055 us + * 110b <--> 000 us + */ + psr_config->psr_rfb_setup_time = + (6 - dpcd_caps->psr_info.psr_dpcd_caps.bits.PSR_SETUP_TIME) * psr_setup_time_step_in_us; + + if (psr_config->psr_rfb_setup_time > vblank_time_in_us) { + link->psr_settings.psr_frame_capture_indication_req = true; + link->psr_settings.psr_sdp_transmit_line_num_deadline = num_vblank_lines; + } else { + sdp_tx_deadline_in_us = vblank_time_in_us - psr_config->psr_rfb_setup_time; + + /* Set the last possible line SDP may be transmitted without violating the RFB setup time */ + link->psr_settings.psr_frame_capture_indication_req = false; + link->psr_settings.psr_sdp_transmit_line_num_deadline = sdp_tx_deadline_in_us / line_time_in_us; + } + + psr_config->psr_sdp_transmit_line_num_deadline = link->psr_settings.psr_sdp_transmit_line_num_deadline; + psr_config->line_time_in_us = line_time_in_us; + psr_config->su_y_granularity = dpcd_caps->psr_info.psr2_su_y_granularity_cap; + psr_config->su_granularity_required = dpcd_caps->psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED; + psr_config->psr_frame_capture_indication_req = link->psr_settings.psr_frame_capture_indication_req; + psr_config->psr_exit_link_training_required = + !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.LINK_TRAINING_ON_EXIT_NOT_REQUIRED; +} + +bool mod_power_only_edp(const struct dc_state *context, const struct dc_stream_state *stream) +{ + return context && context->stream_count == 1 && dc_is_embedded_signal(stream->signal); +} diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h index 1a634d8c78c5..316452e9dbc9 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h @@ -27,6 +27,7 @@ #include "dc/inc/hw/dmcu.h" #include "dc/inc/hw/abm.h" +#include "dc/inc/core_types.h" struct resource_pool; @@ -53,4 +54,9 @@ bool dmub_init_abm_config(struct resource_pool *res_pool, unsigned int inst); bool is_psr_su_specific_panel(struct dc_link *link); +void mod_power_calc_psr_configs(struct psr_config *psr_config, + struct dc_link *link, + const struct dc_stream_state *stream); +bool mod_power_only_edp(const struct dc_state *context, + const struct dc_stream_state *stream); #endif /* MODULES_POWER_POWER_HELPERS_H_ */ -- cgit v1.2.3 From 381b590c307f29d0990c4b99ae3a2e02aff2a5b9 Mon Sep 17 00:00:00 2001 From: David Zhang Date: Tue, 26 Apr 2022 11:44:02 -0400 Subject: drm/amd/display: calculate psr config settings in runtime in DM [why] Currently the psr configuration parameters are hardcoded before feeding into the DC helper before passing to DMUB FW. We'd rework to call a shared helper to calculate/update generic psr config fields which are relying on the stream timing and eDP sink PSR caps to avoid hard-coding. [how] - drop part of hard-coded psr config fields by replacing w/ the call of helper from DM before feeding into DC link setup psr helper - For those DM specific psr config fields, e.g. allow smu opt, is not to be set/updated from the shared helper but to rely on the DC feature mask - for the psr version field in psr_config structure, since only the field psr_version of DC link psr_settings matters for that fed to DMUB FW, thus no need to set/update the psr_version field of psr_config structure. Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c index 141fd2721501..52508bdda8e9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c @@ -97,19 +97,24 @@ bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream) struct dc_link *link = NULL; struct psr_config psr_config = {0}; struct psr_context psr_context = {0}; + struct dc *dc = NULL; bool ret = false; if (stream == NULL) return false; link = stream->link; + dc = link->ctx->dc; if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) { - psr_config.psr_version = link->psr_settings.psr_version; - psr_config.psr_frame_capture_indication_req = 0; - psr_config.psr_rfb_setup_time = 0x37; - psr_config.psr_sdp_transmit_line_num_deadline = 0x20; - psr_config.allow_smu_optimizations = 0x0; + mod_power_calc_psr_configs(&psr_config, link, stream); + + /* linux DM specific updating for psr config fields */ + psr_config.allow_smu_optimizations = + (amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT) && + mod_power_only_edp(dc->current_state, stream); + psr_config.allow_multi_disp_optimizations = + (amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT); ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context); -- cgit v1.2.3 From 1b0da5a3e90d3920f6967e4303fdeaaec6f62208 Mon Sep 17 00:00:00 2001 From: David Zhang Date: Wed, 4 May 2022 12:30:24 -0400 Subject: drm/amd/display: update cursor position to DMUB FW [why] To involve the cursor position into dirty rectangle calculation. [how] - separate plane and cursor update by different DMUB command - send the cursor information while cursor updating, when updating cursor position/attribute, store cursor pos/attr to hubp, and notify dmub FW to exit psr before program cursor registers Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 2 + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 131 +++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 2 + drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 1 + 4 files changed, 136 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c index 3a7f76e2c598..564e061ccb58 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c @@ -1188,6 +1188,8 @@ void hubp1_cursor_set_position( uint32_t dst_x_offset; uint32_t cur_en = pos->enable ? 1 : 0; + hubp->curs_pos = *pos; + /* * Guard aganst cursor_set_position() from being called with invalid * attributes diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index e3a62873c0e7..351a923fbf73 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -51,6 +51,8 @@ #include "link_hwss.h" #include "dpcd_defs.h" #include "dsc.h" +#include "dce/dmub_psr.h" +#include "dc_dmub_srv.h" #include "dce/dmub_hw_lock_mgr.h" #include "dc_trace.h" #include "dce/dmub_outbox.h" @@ -3328,6 +3330,115 @@ static bool dcn10_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx) return false; } +static void dcn10_dmub_update_cursor_data( + struct pipe_ctx *pipe_ctx, + struct hubp *hubp, + const struct dc_cursor_mi_param *param, + const struct dc_cursor_position *cur_pos, + const struct dc_cursor_attributes *cur_attr) +{ + union dmub_rb_cmd cmd; + struct dmub_cmd_update_cursor_info_data *update_cursor_info; + const struct dc_cursor_position *pos; + const struct dc_cursor_attributes *attr; + int src_x_offset = 0; + int src_y_offset = 0; + int x_hotspot = 0; + int cursor_height = 0; + int cursor_width = 0; + uint32_t cur_en = 0; + unsigned int panel_inst = 0; + + struct dc_debug_options *debug = &hubp->ctx->dc->debug; + + if (!debug->enable_sw_cntl_psr && pipe_ctx->stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1) + return; + + if (pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED || + pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) + return; + + /** + * if cur_pos == NULL means the caller is from cursor_set_attribute + * then driver use previous cursor position data + * if cur_attr == NULL means the caller is from cursor_set_position + * then driver use previous cursor attribute + * if cur_pos or cur_attr is not NULL then update it + */ + if (cur_pos != NULL) + pos = cur_pos; + else + pos = &hubp->curs_pos; + + if (cur_attr != NULL) + attr = cur_attr; + else + attr = &hubp->curs_attr; + + if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, pipe_ctx->stream->link, &panel_inst)) + return; + + src_x_offset = pos->x - pos->x_hotspot - param->viewport.x; + src_y_offset = pos->y - pos->y_hotspot - param->viewport.y; + x_hotspot = pos->x_hotspot; + cursor_height = (int)attr->height; + cursor_width = (int)attr->width; + cur_en = pos->enable ? 1:0; + + // Rotated cursor width/height and hotspots tweaks for offset calculation + if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { + swap(cursor_height, cursor_width); + if (param->rotation == ROTATION_ANGLE_90) { + src_x_offset = pos->x - pos->y_hotspot - param->viewport.x; + src_y_offset = pos->y - pos->x_hotspot - param->viewport.y; + } + } else if (param->rotation == ROTATION_ANGLE_180) { + src_x_offset = pos->x - param->viewport.x; + src_y_offset = pos->y - param->viewport.y; + } + + if (param->mirror) { + x_hotspot = param->viewport.width - x_hotspot; + src_x_offset = param->viewport.x + param->viewport.width - src_x_offset; + } + + if (src_x_offset >= (int)param->viewport.width) + cur_en = 0; /* not visible beyond right edge*/ + + if (src_x_offset + cursor_width <= 0) + cur_en = 0; /* not visible beyond left edge*/ + + if (src_y_offset >= (int)param->viewport.height) + cur_en = 0; /* not visible beyond bottom edge*/ + + if (src_y_offset + cursor_height <= 0) + cur_en = 0; /* not visible beyond top edge*/ + + // Cursor bitmaps have different hotspot values + // There's a possibility that the above logic returns a negative value, so we clamp them to 0 + if (src_x_offset < 0) + src_x_offset = 0; + if (src_y_offset < 0) + src_y_offset = 0; + + memset(&cmd, 0x0, sizeof(cmd)); + cmd.update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; + cmd.update_cursor_info.header.payload_bytes = + sizeof(cmd.update_cursor_info.update_cursor_info_data); + update_cursor_info = &cmd.update_cursor_info.update_cursor_info_data; + update_cursor_info->cursor_rect.x = src_x_offset + param->viewport.x; + update_cursor_info->cursor_rect.y = src_y_offset + param->viewport.y; + update_cursor_info->cursor_rect.width = attr->width; + update_cursor_info->cursor_rect.height = attr->height; + update_cursor_info->enable = cur_en; + update_cursor_info->pipe_idx = pipe_ctx->pipe_idx; + update_cursor_info->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; + update_cursor_info->panel_inst = panel_inst; + dc_dmub_srv_cmd_queue(pipe_ctx->stream->ctx->dmub_srv, &cmd); + dc_dmub_srv_cmd_execute(pipe_ctx->stream->ctx->dmub_srv); + dc_dmub_srv_wait_idle(pipe_ctx->stream->ctx->dmub_srv); +} + void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) { struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; @@ -3526,6 +3637,7 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y; } + dcn10_dmub_update_cursor_data(pipe_ctx, hubp, ¶m, &pos_cpy, NULL); hubp->funcs->set_cursor_position(hubp, &pos_cpy, ¶m); dpp->funcs->set_cursor_position(dpp, &pos_cpy, ¶m, hubp->curs_attr.width, hubp->curs_attr.height); } @@ -3533,6 +3645,25 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx) { struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; + struct dc_cursor_mi_param param = { 0 }; + + /** + * If enter PSR without cursor attribute update + * the cursor attribute of dmub_restore_plane + * are initial value. call dmub to exit PSR and + * restore plane then update cursor attribute to + * avoid override with initial value + */ + if (pipe_ctx->plane_state != NULL) { + param.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10; + param.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz; + param.viewport = pipe_ctx->plane_res.scl_data.viewport; + param.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz; + param.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert; + param.rotation = pipe_ctx->plane_state->rotation; + param.mirror = pipe_ctx->plane_state->horizontal_mirror; + dcn10_dmub_update_cursor_data(pipe_ctx, pipe_ctx->plane_res.hubp, ¶m, NULL, attributes); + } pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes( pipe_ctx->plane_res.hubp, attributes); diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c index a665af19f201..9570c2118ccc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c @@ -967,6 +967,8 @@ void hubp2_cursor_set_position( uint32_t dst_x_offset; uint32_t cur_en = pos->enable ? 1 : 0; + hubp->curs_pos = *pos; + /* * Guard aganst cursor_set_position() from being called with invalid * attributes diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index b2cdb6bfc9b8..906818e792dd 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -63,6 +63,7 @@ struct hubp { int opp_id; int mpcc_id; struct dc_cursor_attributes curs_attr; + struct dc_cursor_position curs_pos; bool power_gated; }; -- cgit v1.2.3 From 7cc191ee7621b7145c6cc9c18a4e1929bb5f136e Mon Sep 17 00:00:00 2001 From: Leo Li Date: Wed, 30 Mar 2022 12:45:09 -0400 Subject: drm/amd/display: Implement MPO PSR SU [WHY] For additional power savings, PSR SU (also referred to as PSR2) can be enabled on eDP panels with PSR SU support. PSR2 saves more power compared to PSR1 by allowing more opportunities for the display hardware to be shut down. In comparison to PSR1, Shut down can now occur in-between frames, as well as in display regions where there is no visible update. In otherwords, it allows for some display hw components to be enabled only for a **selectively updated** region of the visible display. Hence PSR SU. [HOW] To define the SU region, support from the OS is required. OS needs to inform driver of damaged regions that need to be flushed to the eDP panel. Today, such support is lacking in most compositors. Therefore, an in-between solution is to implement PSR SU for MPO and cursor scenarios. The plane bounds can be used to define the damaged region to be flushed to panel. This is achieved by: * Leveraging dm_crtc_state->mpo_requested flag to identify when MPO is enabled. * If MPO is enabled, only add updated plane bounds to dirty region. Determine plane update by either: * Existence of drm damaged clips attached to the plane (added by a damage-aware compositor) * Change in fb id (flip) * Change in plane bounds (position and dimensions) * If cursor is enabled, the old_pos and new_pos of cursor plus cursor size is used as damaged regions(*). (*) Cursor updates follow a different code path through DC. PSR SU for cursor is already implemented in DC, and the only thing required to enable is to set DC_PSR_VERSION_SU_1 on the eDP link. See dcn10_dmub_update_cursor_data(). Signed-off-by: Leo Li Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 142 ++++++++++++++++++++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 6 +- 2 files changed, 144 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 872b7899b645..2bb316fa62b1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1265,10 +1265,20 @@ static void vblank_control_worker(struct work_struct *work) DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0); - /* Control PSR based on vblank requirements from OS */ + /* + * Control PSR based on vblank requirements from OS + * + * If panel supports PSR SU, there's no need to disable PSR when OS is + * submitting fast atomic commits (we infer this by whether the OS + * requests vblank events). Fast atomic commits will simply trigger a + * full-frame-update (FFU); a specific case of selective-update (SU) + * where the SU region is the full hactive*vactive region. See + * fill_dc_dirty_rects(). + */ if (vblank_work->stream && vblank_work->stream->link) { if (vblank_work->enable) { - if (vblank_work->stream->link->psr_settings.psr_allow_active) + if (vblank_work->stream->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && + vblank_work->stream->link->psr_settings.psr_allow_active) amdgpu_dm_psr_disable(vblank_work->stream); } else if (vblank_work->stream->link->psr_settings.psr_feature_enabled && !vblank_work->stream->link->psr_settings.psr_allow_active && @@ -5733,6 +5743,117 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, return 0; } +/** + * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates + * + * @plane: DRM plane containing dirty regions that need to be flushed to the eDP + * remote fb + * @old_plane_state: Old state of @plane + * @new_plane_state: New state of @plane + * @crtc_state: New state of CRTC connected to the @plane + * @flip_addrs: DC flip tracking struct, which also tracts dirty rects + * + * For PSR SU, DC informs the DMUB uController of dirty rectangle regions + * (referred to as "damage clips" in DRM nomenclature) that require updating on + * the eDP remote buffer. The responsibility of specifying the dirty regions is + * amdgpu_dm's. + * + * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the + * plane with regions that require flushing to the eDP remote buffer. In + * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - + * implicitly provide damage clips without any client support via the plane + * bounds. + * + * Today, amdgpu_dm only supports the MPO and cursor usecase. + * + * TODO: Also enable for FB_DAMAGE_CLIPS + */ +static void fill_dc_dirty_rects(struct drm_plane *plane, + struct drm_plane_state *old_plane_state, + struct drm_plane_state *new_plane_state, + struct drm_crtc_state *crtc_state, + struct dc_flip_addrs *flip_addrs) +{ + struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); + struct rect *dirty_rects = flip_addrs->dirty_rects; + uint32_t num_clips; + bool bb_changed; + bool fb_changed; + uint32_t i = 0; + + flip_addrs->dirty_rect_count = 0; + + /* + * Cursor plane has it's own dirty rect update interface. See + * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data + */ + if (plane->type == DRM_PLANE_TYPE_CURSOR) + return; + + /* + * Today, we only consider MPO use-case for PSR SU. If MPO not + * requested, and there is a plane update, do FFU. + */ + if (!dm_crtc_state->mpo_requested) { + dirty_rects[0].x = 0; + dirty_rects[0].y = 0; + dirty_rects[0].width = dm_crtc_state->base.mode.crtc_hdisplay; + dirty_rects[0].height = dm_crtc_state->base.mode.crtc_vdisplay; + flip_addrs->dirty_rect_count = 1; + DRM_DEBUG_DRIVER("[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", + new_plane_state->plane->base.id, + dm_crtc_state->base.mode.crtc_hdisplay, + dm_crtc_state->base.mode.crtc_vdisplay); + return; + } + + /* + * MPO is requested. Add entire plane bounding box to dirty rects if + * flipped to or damaged. + * + * If plane is moved or resized, also add old bounding box to dirty + * rects. + */ + num_clips = drm_plane_get_damage_clips_count(new_plane_state); + fb_changed = old_plane_state->fb->base.id != + new_plane_state->fb->base.id; + bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || + old_plane_state->crtc_y != new_plane_state->crtc_y || + old_plane_state->crtc_w != new_plane_state->crtc_w || + old_plane_state->crtc_h != new_plane_state->crtc_h); + + DRM_DEBUG_DRIVER("[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", + new_plane_state->plane->base.id, + bb_changed, fb_changed, num_clips); + + if (num_clips || fb_changed || bb_changed) { + dirty_rects[i].x = new_plane_state->crtc_x; + dirty_rects[i].y = new_plane_state->crtc_y; + dirty_rects[i].width = new_plane_state->crtc_w; + dirty_rects[i].height = new_plane_state->crtc_h; + DRM_DEBUG_DRIVER("[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)\n", + new_plane_state->plane->base.id, + dirty_rects[i].x, dirty_rects[i].y, + dirty_rects[i].width, dirty_rects[i].height); + i += 1; + } + + /* Add old plane bounding-box if plane is moved or resized */ + if (bb_changed) { + dirty_rects[i].x = old_plane_state->crtc_x; + dirty_rects[i].y = old_plane_state->crtc_y; + dirty_rects[i].width = old_plane_state->crtc_w; + dirty_rects[i].height = old_plane_state->crtc_h; + DRM_DEBUG_DRIVER("[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)\n", + old_plane_state->plane->base.id, + dirty_rects[i].x, dirty_rects[i].y, + dirty_rects[i].width, dirty_rects[i].height); + i += 1; + } + + flip_addrs->dirty_rect_count = i; +} + static void update_stream_scaling_settings(const struct drm_display_mode *mode, const struct dm_connector_state *dm_state, struct dc_stream_state *stream) @@ -6681,6 +6802,7 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc) state->cm_has_degamma = cur->cm_has_degamma; state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; state->force_dpms_off = cur->force_dpms_off; + state->mpo_requested = cur->mpo_requested; /* TODO Duplicate dc_stream after objects are stream object is flattened */ return &state->base; @@ -9328,6 +9450,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, bundle->surface_updates[planes_count].plane_info = &bundle->plane_infos[planes_count]; + fill_dc_dirty_rects(plane, old_plane_state, new_plane_state, + new_crtc_state, + &bundle->flip_addrs[planes_count]); + /* * Only allow immediate flips for fast updates that don't * change FB pitch, DCC state, rotation or mirroing. @@ -9523,6 +9649,18 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, /* Allow PSR when skip count is 0. */ acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count; + + /* + * If sink supports PSR SU, there is no need to rely on + * a vblank event disable request to enable PSR. PSR SU + * can be enabled immediately once OS demonstrates an + * adequate number of fast atomic commits to notify KMD + * of update events. See `vblank_control_worker()`. + */ + if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && + acrtc_attach->dm_irq_params.allow_psr_entry && + !acrtc_state->stream->link->psr_settings.psr_allow_active) + amdgpu_dm_psr_enable(acrtc_state->stream); } else { acrtc_attach->dm_irq_params.allow_psr_entry = false; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c index 52508bdda8e9..c8da18e45b0e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c @@ -79,10 +79,12 @@ void amdgpu_dm_set_psr_caps(struct dc_link *link) link->psr_settings.psr_feature_enabled = true; } - DRM_INFO("PSR support %d, DC PSR ver %d, sink PSR ver %d\n", + DRM_INFO("PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n", link->psr_settings.psr_feature_enabled, link->psr_settings.psr_version, - link->dpcd_caps.psr_info.psr_version); + link->dpcd_caps.psr_info.psr_version, + link->dpcd_caps.psr_info.psr_dpcd_caps.raw, + link->dpcd_caps.psr_info.psr2_su_y_granularity_cap); } -- cgit v1.2.3 From 84de5c2e92dccb2bcfd5ff68af44960b808fe6bb Mon Sep 17 00:00:00 2001 From: Gabe Teeger Date: Thu, 12 May 2022 12:47:23 -0400 Subject: drm/amd/display: Update optimized blank calc and programming [Why] The existing calculations in DCN3.1 were placeholder and need to be replaced with HW team approved calculations. [How] The new calculations add new parameters to the bounding box and pipe params - VblankNom and the bounding box default. The placeholder calculations are dropped from DCN3.1 in the meantime while we work out hardware approved replacements. Also fix a bug where we wipe out other register contents with a REG_SET instead of a REG_UPDATE for the register we were programming the min_dst_y_next_start_optimized. Reviewed-by: Nicholas Kazlauskas Acked-by: Hamza Mahfooz Signed-off-by: Gabe Teeger Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 1 - .../amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c | 16 ++-------------- .../gpu/drm/amd/display/dc/dml/display_mode_structs.h | 1 + drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 + 5 files changed, 5 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c index 197a5cae068b..84e1486f3d51 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c @@ -59,7 +59,7 @@ static void hubp31_program_extended_blank(struct hubp *hubp, { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - REG_SET(BLANK_OFFSET_1, 0, MIN_DST_Y_NEXT_START, min_dst_y_next_start_optimized); + REG_UPDATE(BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, min_dst_y_next_start_optimized); } static struct hubp_funcs dcn31_hubp_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c index 3d9f07d4770b..a67475251188 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c @@ -1651,7 +1651,6 @@ int dcn31_populate_dml_pipes_from_context( continue; pipe = &res_ctx->pipe_ctx[i]; timing = &pipe->stream->timing; - if (pipe->plane_state && (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height || pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width)) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c index 53d760e169e6..dd570689c095 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c @@ -1055,7 +1055,6 @@ static void dml_rq_dlg_get_dlg_params( float vba__refcyc_per_req_delivery_pre_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA float vba__refcyc_per_req_delivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - int blank_lines; memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs)); @@ -1079,20 +1078,9 @@ static void dml_rq_dlg_get_dlg_params( min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; - disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2)); - blank_lines = (dst->vblank_end + dst->vtotal_min - dst->vblank_start - dst->vstartup_start - 1); - if (blank_lines < 0) - blank_lines = 0; - if (blank_lines != 0) { - disp_dlg_regs->optimized_min_dst_y_next_start_us = - ((unsigned int) blank_lines * dst->hactive) / (unsigned int) dst->pixel_rate_mhz; - disp_dlg_regs->optimized_min_dst_y_next_start = - (unsigned int)(((double) (dlg_vblank_start + blank_lines)) * dml_pow(2, 2)); - } else { - // use unoptimized value - disp_dlg_regs->optimized_min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start; - } + disp_dlg_regs->optimized_min_dst_y_next_start_us = 0; + disp_dlg_regs->optimized_min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start; ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); dml_print("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, min_ttu_vblank); diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h index 967d3e1ce886..74afa10e70f8 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h @@ -329,6 +329,7 @@ struct _vcs_dpi_ip_params_st { unsigned int number_of_cursors; unsigned int max_num_dp2p0_outputs; unsigned int max_num_dp2p0_streams; + unsigned int VBlankNomDefaultUS; }; struct _vcs_dpi_display_xfc_params_st { diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h index ddf8b19c490e..43e327080552 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -465,6 +465,7 @@ struct vba_vars_st { unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX]; bool XFCEnabled[DC__NUM_DPP__MAX]; bool ScalerEnabled[DC__NUM_DPP__MAX]; + unsigned int VBlankNom[DC__NUM_DPP__MAX]; // Intermediates/Informational bool ImmediateFlipSupport; -- cgit v1.2.3 From 453b0016a054df0f442fda8a145b97a33816cab9 Mon Sep 17 00:00:00 2001 From: Wayne Lin Date: Wed, 20 Apr 2022 10:32:15 +0800 Subject: drm/amd/display: Detect dpcd_rev when hotplug mst monitor [Why] Once mst topology is constructed, later on new connected monitors are reported to source by CSN message. Within CSN, there is no carried info of DPCD_REV comparing to LINK_ADDRESS reply. As the result, we might leave some ports connected to DP but without DPCD revision number which will affect us determining the capability of the DP Rx. [How] Send out remote DPCD read when the port's dpcd_rev is 0x0 in detect_ctx(). Firstly, read out the value from DPCD 0x2200. If the return value is 0x0, it's likely the DP1.2 DP Rx then we reques revision from DPCD 0x0 again. Reviewed-by: Hersen Wu Acked-by: Hamza Mahfooz Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 38 +++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 9221b6690a4a..a6d551ff89d1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -344,12 +344,48 @@ dm_dp_mst_detect(struct drm_connector *connector, { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct amdgpu_dm_connector *master = aconnector->mst_port; + struct drm_dp_mst_port *port = aconnector->port; + int connection_status; if (drm_connector_is_unregistered(connector)) return connector_status_disconnected; - return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr, + connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr, aconnector->port); + + if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) { + uint8_t dpcd_rev; + int ret; + + ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev); + + if (ret == 1) { + port->dpcd_rev = dpcd_rev; + + /* Could be DP1.2 DP Rx case*/ + if (!dpcd_rev) { + ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev); + + if (ret == 1) + port->dpcd_rev = dpcd_rev; + } + + if (!dpcd_rev) + DRM_DEBUG_KMS("Can't decide DPCD revision number!"); + } + + /* + * Could be legacy sink, logical port etc on DP1.2. + * Will get Nack under these cases when issue remote + * DPCD read. + */ + if (ret != 1) + DRM_DEBUG_KMS("Can't access DPCD"); + } else if (port->pdt == DP_PEER_DEVICE_NONE) { + port->dpcd_rev = 0; + } + + return connection_status; } static int dm_dp_mst_atomic_check(struct drm_connector *connector, -- cgit v1.2.3 From 031ac4e419dfd8f099a0adba31f7f735013eb628 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 2 Jun 2022 12:06:12 -0400 Subject: drm/amdgpu/discovery: add comments about VCN instance handling Add comments to clarify code that is safe, but triggers and smatch warning. Link: https://lists.freedesktop.org/archives/amd-gfx/2022-June/079905.html Signed-off-by: Alex Deucher Cc: Dan Carpenter --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 91f21b725a43..b0811287f017 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1435,6 +1435,11 @@ static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) return -EINVAL; } + /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES + * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES + * but that may change in the future with new GPUs so keep this + * check for defensive purposes. + */ if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { dev_err(adev->dev, "invalid vcn instances\n"); return -EINVAL; @@ -1450,6 +1455,9 @@ static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) switch (le16_to_cpu(vcn_info->v1.header.version_major)) { case 1: + /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES + * so this won't overflow. + */ for (v = 0; v < adev->vcn.num_vcn_inst; v++) { adev->vcn.vcn_codec_disable_mask[v] = le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); -- cgit v1.2.3 From b94b02d72e2b979a32addc8f5099fcf1f6ce9e7b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 6 Jun 2022 09:59:52 -0400 Subject: drm/amdgpu/display: make some functions static Fixes "no previous prototype" warnings. Reviewed-by: Harry Wentland Reported-by: kernel test robot Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 8 ++++---- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 1db61029481b..ed70ae10bdb1 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -487,7 +487,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr_base->clks.dispclk_khz / 1000 / 7); } -void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr) +static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr) { struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; int ss_info_num = bp->funcs->get_ss_entry_number( diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c index 8eeb3b69b5b9..0faa1abd35ba 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c @@ -662,8 +662,8 @@ void dccg31_init(struct dccg *dccg) } } -void dccg31_otg_add_pixel(struct dccg *dccg, - uint32_t otg_inst) +static void dccg31_otg_add_pixel(struct dccg *dccg, + uint32_t otg_inst) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); @@ -671,8 +671,8 @@ void dccg31_otg_add_pixel(struct dccg *dccg, OTG_ADD_PIXEL[otg_inst], 1); } -void dccg31_otg_drop_pixel(struct dccg *dccg, - uint32_t otg_inst) +static void dccg31_otg_drop_pixel(struct dccg *dccg, + uint32_t otg_inst) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c index 08232d05d894..152a76ad7957 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c @@ -177,7 +177,7 @@ void dccg32_set_dtbclk_dto( } } -void dccg32_set_valid_pixel_rate( +static void dccg32_set_valid_pixel_rate( struct dccg *dccg, int ref_dtbclk_khz, int otg_inst, -- cgit v1.2.3 From d1b08baf93352bb3c88d637055dc21187a456646 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 6 Jun 2022 11:34:46 -0400 Subject: drm/amdgpu/display: fix DCN3.2 Makefiles for non-x86 Add proper handling for PPC64. Reviewed-by: Harry Wentland Reported-by: kernel test robot Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/Makefile | 9 ++++++++- drivers/gpu/drm/amd/display/dc/dcn321/Makefile | 9 ++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/Makefile b/drivers/gpu/drm/amd/display/dc/dcn32/Makefile index 6e0328060255..3d09db3070f4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn32/Makefile @@ -15,12 +15,19 @@ DCN32 = dcn32_resource.o dcn32_hubbub.o dcn32_hwseq.o dcn32_init.o \ dcn32_dio_stream_encoder.o dcn32_dio_link_encoder.o dcn32_hpo_dp_link_encoder.o \ dcn32_mpc.o -CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o := -mhard-float -msse +ifdef CONFIG_X86 +CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o := -msse +endif + +ifdef CONFIG_PPC64 +CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o := -mhard-float -maltivec +endif ifdef CONFIG_CC_IS_GCC ifeq ($(call cc-ifversion, -lt, 0701, y), y) IS_OLD_GCC = 1 endif +CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o += -mhard-float endif ifdef IS_OLD_GCC diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/Makefile b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile index 9b61d08700ca..5896ca303e39 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn321/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile @@ -12,12 +12,19 @@ DCN321 = dcn321_resource.o dcn321_dio_link_encoder.o -CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o := -mhard-float -msse +ifdef CONFIG_X86 +CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o := -msse +endif + +ifdef CONFIG_PPC64 +CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o := -mhard-float -maltivec +endif ifdef CONFIG_CC_IS_GCC ifeq ($(call cc-ifversion, -lt, 0701, y), y) IS_OLD_GCC = 1 endif +CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o += -mhard-float endif ifdef IS_OLD_GCC -- cgit v1.2.3 From 136f614931a2bb73616b292cf542da3a18daefd5 Mon Sep 17 00:00:00 2001 From: Alexey Kodanev Date: Mon, 6 Jun 2022 16:50:54 +0300 Subject: drm/radeon: fix potential buffer overflow in ni_set_mc_special_registers() The last case label can write two buffers 'mc_reg_address[j]' and 'mc_data[j]' with 'j' offset equal to SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE since there are no checks for this value in both case labels after the last 'j++'. Instead of changing '>' to '>=' there, add the bounds check at the start of the second 'case' (the first one already has it). Also, remove redundant last checks for 'j' index bigger than array size. The expression is always false. Moreover, before or after the patch 'table->last' can be equal to SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE and it seems it can be a valid value. Detected using the static analysis tool - Svace. Fixes: 69e0b57a91ad ("drm/radeon/kms: add dpm support for cayman (v5)") Signed-off-by: Alexey Kodanev Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/ni_dpm.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c index 769f666335ac..672d2239293e 100644 --- a/drivers/gpu/drm/radeon/ni_dpm.c +++ b/drivers/gpu/drm/radeon/ni_dpm.c @@ -2741,10 +2741,10 @@ static int ni_set_mc_special_registers(struct radeon_device *rdev, table->mc_reg_table_entry[k].mc_data[j] |= 0x100; } j++; - if (j > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE) - return -EINVAL; break; case MC_SEQ_RESERVE_M >> 2: + if (j >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE) + return -EINVAL; temp_reg = RREG32(MC_PMG_CMD_MRS1); table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; @@ -2753,8 +2753,6 @@ static int ni_set_mc_special_registers(struct radeon_device *rdev, (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); j++; - if (j > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE) - return -EINVAL; break; default: break; -- cgit v1.2.3 From ea64228d26fee9b766bc9615e92a319da5ef94ef Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 11 May 2022 17:31:27 -0400 Subject: drm/amdgpu/soc21: add mode2 asic reset for SMU IP v13.0.4 Set the default reset method to mode2 for SMU IP v13.0.4 Acked-by: Evan Quan Reviewed-by: Tim Huang Signed-off-by: Tim Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc21.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 09efef506e8f..57eaafb70d72 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -310,6 +310,7 @@ static enum amd_reset_method soc21_asic_reset_method(struct amdgpu_device *adev) { if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || + amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || amdgpu_reset_method == AMD_RESET_METHOD_BACO) return amdgpu_reset_method; @@ -320,6 +321,8 @@ soc21_asic_reset_method(struct amdgpu_device *adev) switch (adev->ip_versions[MP1_HWIP][0]) { case IP_VERSION(13, 0, 0): return AMD_RESET_METHOD_MODE1; + case IP_VERSION(13, 0, 4): + return AMD_RESET_METHOD_MODE2; default: if (amdgpu_dpm_is_baco_supported(adev)) return AMD_RESET_METHOD_BACO; @@ -341,6 +344,10 @@ static int soc21_asic_reset(struct amdgpu_device *adev) dev_info(adev->dev, "BACO reset\n"); ret = amdgpu_dpm_baco_reset(adev); break; + case AMD_RESET_METHOD_MODE2: + dev_info(adev->dev, "MODE2 reset\n"); + ret = amdgpu_dpm_mode2_reset(adev); + break; default: dev_info(adev->dev, "MODE1 reset\n"); ret = amdgpu_device_mode1_reset(adev); -- cgit v1.2.3 From ae204faa949d76eb89fa31f18c51c09ada5dad4f Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Mon, 6 Jun 2022 10:09:48 +0800 Subject: Revert "drm/amdgpu: Ensure the DMA engine is deactivated during set ups" This reverts commit b992a19085885c096b19625a85c674cb89829ca1. This causes regression in GPU reset related test. Cc: Alexander Deucher Cc: ricetons@gmail.com Signed-off-by: Guchun Chen Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 109 ++++++++++++++------------------- 1 file changed, 45 insertions(+), 64 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 06b2635b142a..83c6ccaaa9e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -469,6 +469,7 @@ static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se } } + /** * sdma_v5_2_gfx_stop - stop the gfx async dma engines * @@ -514,21 +515,17 @@ static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev) } /** - * sdma_v5_2_ctx_switch_enable_for_instance - start the async dma engines - * context switch for an instance + * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch * * @adev: amdgpu_device pointer - * @instance_idx: the index of the SDMA instance + * @enable: enable/disable the DMA MEs context switch. * - * Unhalt the async dma engines context switch. + * Halt or unhalt the async dma engines context switch. */ -static void sdma_v5_2_ctx_switch_enable_for_instance(struct amdgpu_device *adev, int instance_idx) +static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable) { u32 f32_cntl, phase_quantum = 0; - - if (WARN_ON(instance_idx >= adev->sdma.num_instances)) { - return; - } + int i; if (amdgpu_sdma_phase_quantum) { unsigned value = amdgpu_sdma_phase_quantum; @@ -552,68 +549,50 @@ static void sdma_v5_2_ctx_switch_enable_for_instance(struct amdgpu_device *adev, phase_quantum = value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; - - WREG32_SOC15_IP(GC, - sdma_v5_2_get_reg_offset(adev, instance_idx, mmSDMA0_PHASE0_QUANTUM), - phase_quantum); - WREG32_SOC15_IP(GC, - sdma_v5_2_get_reg_offset(adev, instance_idx, mmSDMA0_PHASE1_QUANTUM), - phase_quantum); - WREG32_SOC15_IP(GC, - sdma_v5_2_get_reg_offset(adev, instance_idx, mmSDMA0_PHASE2_QUANTUM), - phase_quantum); } - if (!amdgpu_sriov_vf(adev)) { - f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, instance_idx, mmSDMA0_CNTL)); - f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, - AUTO_CTXSW_ENABLE, 1); - WREG32(sdma_v5_2_get_reg_offset(adev, instance_idx, mmSDMA0_CNTL), f32_cntl); + for (i = 0; i < adev->sdma.num_instances; i++) { + if (enable && amdgpu_sdma_phase_quantum) { + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), + phase_quantum); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), + phase_quantum); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), + phase_quantum); + } + + if (!amdgpu_sriov_vf(adev)) { + f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); + f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, + AUTO_CTXSW_ENABLE, enable ? 1 : 0); + WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); + } } + } /** - * sdma_v5_2_ctx_switch_disable_all - stop the async dma engines context switch + * sdma_v5_2_enable - stop the async dma engines * * @adev: amdgpu_device pointer + * @enable: enable/disable the DMA MEs. * - * Halt the async dma engines context switch. + * Halt or unhalt the async dma engines. */ -static void sdma_v5_2_ctx_switch_disable_all(struct amdgpu_device *adev) +static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable) { u32 f32_cntl; int i; - if (amdgpu_sriov_vf(adev)) - return; - - for (i = 0; i < adev->sdma.num_instances; i++) { - f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); - f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, - AUTO_CTXSW_ENABLE, 0); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); + if (!enable) { + sdma_v5_2_gfx_stop(adev); + sdma_v5_2_rlc_stop(adev); } -} - -/** - * sdma_v5_2_halt - stop the async dma engines - * - * @adev: amdgpu_device pointer - * - * Halt the async dma engines. - */ -static void sdma_v5_2_halt(struct amdgpu_device *adev) -{ - int i; - u32 f32_cntl; - - sdma_v5_2_gfx_stop(adev); - sdma_v5_2_rlc_stop(adev); if (!amdgpu_sriov_vf(adev)) { for (i = 0; i < adev->sdma.num_instances; i++) { f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); - f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); + f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); } } @@ -625,9 +604,6 @@ static void sdma_v5_2_halt(struct amdgpu_device *adev) * @adev: amdgpu_device pointer * * Set up the gfx DMA ring buffers and enable them. - * It assumes that the dma engine is stopped for each instance. - * The function enables the engine and preemptions sequentially for each instance. - * * Returns 0 for success, error for failure. */ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) @@ -769,7 +745,10 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) ring->sched.ready = true; - sdma_v5_2_ctx_switch_enable_for_instance(adev, i); + if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ + sdma_v5_2_ctx_switch_enable(adev, true); + sdma_v5_2_enable(adev, true); + } r = amdgpu_ring_test_ring(ring); if (r) { @@ -813,7 +792,7 @@ static int sdma_v5_2_load_microcode(struct amdgpu_device *adev) int i, j; /* halt the MEs */ - sdma_v5_2_halt(adev); + sdma_v5_2_enable(adev, false); for (i = 0; i < adev->sdma.num_instances; i++) { if (!adev->sdma.instance[i].fw) @@ -885,8 +864,8 @@ static int sdma_v5_2_start(struct amdgpu_device *adev) int r = 0; if (amdgpu_sriov_vf(adev)) { - sdma_v5_2_ctx_switch_disable_all(adev); - sdma_v5_2_halt(adev); + sdma_v5_2_ctx_switch_enable(adev, false); + sdma_v5_2_enable(adev, false); /* set RB registers */ r = sdma_v5_2_gfx_resume(adev); @@ -910,10 +889,12 @@ static int sdma_v5_2_start(struct amdgpu_device *adev) amdgpu_gfx_off_ctrl(adev, false); sdma_v5_2_soft_reset(adev); + /* unhalt the MEs */ + sdma_v5_2_enable(adev, true); + /* enable sdma ring preemption */ + sdma_v5_2_ctx_switch_enable(adev, true); - /* Soft reset supposes to disable the dma engine and preemption. - * Now start the gfx rings and rlc compute queues. - */ + /* start the gfx rings and rlc compute queues */ r = sdma_v5_2_gfx_resume(adev); if (adev->in_s0ix) amdgpu_gfx_off_ctrl(adev, true); @@ -1447,8 +1428,8 @@ static int sdma_v5_2_hw_fini(void *handle) if (amdgpu_sriov_vf(adev)) return 0; - sdma_v5_2_ctx_switch_disable_all(adev); - sdma_v5_2_halt(adev); + sdma_v5_2_ctx_switch_enable(adev, false); + sdma_v5_2_enable(adev, false); return 0; } -- cgit v1.2.3 From 165ab7b4319d8ecbb689f3d68f0cd6bda4d82b1c Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Tue, 17 May 2022 10:12:27 -0400 Subject: Revert "drm/amd/display: Pass the new context into disable OTG WA" This reverts commit 8440f57532496d398a461887e56ca6f45089fbcf. Causes a hang when hotplugging DP, shutting down system, or enabling dual eDP. Reviewed-by: Dmytro Laktyushkin Acked-by: Hamza Mahfooz Signed-off-by: Nicholas Kazlauskas Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 8 ++++---- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 8 ++++---- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c index 6a81c1aea0be..bca5f01da763 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c @@ -99,13 +99,13 @@ static int dcn31_get_active_display_cnt_wa( return display_count; } -static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable) +static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable) { struct dc *dc = clk_mgr_base->ctx->dc; int i; for (i = 0; i < dc->res_pool->pipe_count; ++i) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; if (pipe->top_pipe || pipe->prev_odm_pipe) continue; @@ -211,11 +211,11 @@ void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, } if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { - dcn31_disable_otg_wa(clk_mgr_base, context, true); + dcn31_disable_otg_wa(clk_mgr_base, true); clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); - dcn31_disable_otg_wa(clk_mgr_base, context, false); + dcn31_disable_otg_wa(clk_mgr_base, false); update_dispclk = true; } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c index aa01a18df419..fb4ae800e919 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c @@ -79,13 +79,13 @@ static int dcn315_get_active_display_cnt_wa( return display_count; } -static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable) +static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable) { struct dc *dc = clk_mgr_base->ctx->dc; int i; for (i = 0; i < dc->res_pool->pipe_count; ++i) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; if (pipe->top_pipe || pipe->prev_odm_pipe) continue; @@ -173,11 +173,11 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, } if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { - dcn315_disable_otg_wa(clk_mgr_base, context, true); + dcn315_disable_otg_wa(clk_mgr_base, true); clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; dcn315_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); - dcn315_disable_otg_wa(clk_mgr_base, context, false); + dcn315_disable_otg_wa(clk_mgr_base, false); update_dispclk = true; } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c index 7192f30858eb..e4bb9c6193b5 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c @@ -112,13 +112,13 @@ static int dcn316_get_active_display_cnt_wa( return display_count; } -static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable) +static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable) { struct dc *dc = clk_mgr_base->ctx->dc; int i; for (i = 0; i < dc->res_pool->pipe_count; ++i) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; if (pipe->top_pipe || pipe->prev_odm_pipe) continue; @@ -221,11 +221,11 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base, } if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { - dcn316_disable_otg_wa(clk_mgr_base, context, true); + dcn316_disable_otg_wa(clk_mgr_base, true); clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); - dcn316_disable_otg_wa(clk_mgr_base, context, false); + dcn316_disable_otg_wa(clk_mgr_base, false); update_dispclk = true; } -- cgit v1.2.3 From 77361ed89a8b03c7e121f4b8c517d7be93ccd8df Mon Sep 17 00:00:00 2001 From: Jimmy Kizito Date: Thu, 24 Mar 2022 13:42:45 -0400 Subject: drm/amd/display: Avoid reading LTTPR caps in non-LTTPR mode. [Why] LTTPR capable devices on the DisplayPort path may assume that extended LTTPR AUX timeouts will be used after LTTPR capabilities are read. When DPTX operates in non-LTTPR mode, AUX timeouts are not extended and this can result in AUX transactions timing out. [How] Use shared helper function to determine LTTPR mode and do not read LTTPR capabilities in non-LTTPR mode. Reviewed-by: Mustapha Ghaddar Reviewed-by: Meenakshikumar Somasundaram Reviewed-by: Jun Lei Acked-by: Hamza Mahfooz Signed-off-by: Jimmy Kizito Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 44 +++++++++++++++++------- 1 file changed, 31 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 1ec81426498f..2d0e41761c32 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -5129,16 +5129,13 @@ static bool dpcd_read_sink_ext_caps(struct dc_link *link) return true; } -bool dp_retrieve_lttpr_cap(struct dc_link *link) +/* Logic to determine LTTPR mode */ +static void determine_lttpr_mode(struct dc_link *link) { - uint8_t lttpr_dpcd_data[8]; bool allow_lttpr_non_transparent_mode = 0; bool vbios_lttpr_enable = link->dc->caps.vbios_lttpr_enable; bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware; - enum dc_status status = DC_ERROR_UNEXPECTED; - bool is_lttpr_present = false; - memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data)); if ((link->dc->config.allow_lttpr_non_transparent_mode.bits.DP2_0 && link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED)) { @@ -5148,9 +5145,6 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link) allow_lttpr_non_transparent_mode = 1; } - /* - * Logic to determine LTTPR mode - */ link->lttpr_mode = LTTPR_MODE_NON_LTTPR; if (vbios_lttpr_enable && vbios_lttpr_interop) link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT; @@ -5172,6 +5166,18 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link) link->dc->debug.dpia_debug.bits.force_non_lttpr) link->lttpr_mode = LTTPR_MODE_NON_LTTPR; #endif +} + +bool dp_retrieve_lttpr_cap(struct dc_link *link) +{ + uint8_t lttpr_dpcd_data[8]; + enum dc_status status = DC_ERROR_UNEXPECTED; + bool is_lttpr_present = false; + + memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data)); + + /* Logic to determine LTTPR mode*/ + determine_lttpr_mode(link); if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) { /* By reading LTTPR capability, RX assumes that we will enable @@ -5287,11 +5293,23 @@ static enum dc_status wa_try_to_wake_dprx(struct dc_link *link, uint64_t timeout uint64_t time_taken_ms = 0; enum dc_connection_type type = dc_connection_none; - status = core_link_read_dpcd( - link, - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, - &dpcd_data, - sizeof(dpcd_data)); + determine_lttpr_mode(link); + + /* Issue an AUX read to test DPRX responsiveness. If LTTPR is supported the first read is expected to + * be to determine LTTPR capabilities. Otherwise trying to read power state should be an innocuous AUX read. + */ + if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) + status = core_link_read_dpcd( + link, + DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, + &dpcd_data, + sizeof(dpcd_data)); + else + status = core_link_read_dpcd( + link, + DP_SET_POWER, + &dpcd_data, + sizeof(dpcd_data)); if (status != DC_OK) { DC_LOG_WARNING("%s: Read DPCD LTTPR_CAP failed - try to toggle DPCD SET_POWER for %lld ms.", -- cgit v1.2.3 From 2d017189e2b39cf2fae63984215385401b77ea83 Mon Sep 17 00:00:00 2001 From: Duncan Ma Date: Thu, 12 May 2022 14:46:24 -0400 Subject: drm/amd/display: Blank eDP on enable drv if odm enabled [Why] For panels with pixel clock > 1200MHz that require ODM in pre-OS, when driver is disabled in OS, odm is enabled. Upon driver enablement, corruption is seen if odm was originally enabled. DP_PIXEL_COMBINE and pixelclk must be programmed prior to programming the optc-odm registers. However, eDP displays aren't blanked prior to initializing odm in this case. [How] Upon driver enablement, check whether odm is enabled, if so, blank eDP prior to programming optc-odm registers. Reviewed-by: Nicholas Kazlauskas Acked-by: Hamza Mahfooz Signed-off-by: Duncan Ma Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 20 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dc.h | 1 + drivers/gpu/drm/amd/display/dc/dc_link.h | 1 + drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 22 ++++++++++++++++++++++ 4 files changed, 44 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 31ffb961e18b..38a458141791 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -2126,6 +2126,26 @@ void dc_link_blank_all_dp_displays(struct dc *dc) } +void dc_link_blank_all_edp_displays(struct dc *dc) +{ + unsigned int i; + uint8_t dpcd_power_state = '\0'; + enum dc_status status = DC_ERROR_UNEXPECTED; + + for (i = 0; i < dc->link_count; i++) { + if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || + (!dc->links[i]->edp_sink_present)) + continue; + + /* if any of the displays are lit up turn them off */ + status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, + &dpcd_power_state, sizeof(dpcd_power_state)); + + if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) + dc_link_blank_dp_stream(dc->links[i], true); + } +} + void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init) { unsigned int j; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7bb67ab979e1..5a6c9a139e85 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -216,6 +216,7 @@ struct dc_caps { uint16_t subvp_pstate_allow_width_us; uint16_t subvp_vertical_int_margin_us; #endif + bool seamless_odm; }; struct dc_bug_wa { diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h index 0bec986a6de8..c4a42d758b4e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_link.h +++ b/drivers/gpu/drm/amd/display/dc/dc_link.h @@ -322,6 +322,7 @@ bool dc_link_setup_psr(struct dc_link *dc_link, void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency); void dc_link_blank_all_dp_displays(struct dc *dc); +void dc_link_blank_all_edp_displays(struct dc *dc); void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init); diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c index 531dd2c65007..55f2e30b8e5a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c @@ -213,6 +213,28 @@ void dcn31_init_hw(struct dc *dc) * everything down. */ if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { + + // we want to turn off edp displays if odm is enabled and no seamless boot + if (!dc->caps.seamless_odm) { + for (i = 0; i < dc->res_pool->timing_generator_count; i++) { + struct timing_generator *tg = dc->res_pool->timing_generators[i]; + uint32_t num_opps, opp_id_src0, opp_id_src1; + + num_opps = 1; + if (tg) { + if (tg->funcs->is_tg_enabled(tg) && tg->funcs->get_optc_source) { + tg->funcs->get_optc_source(tg, &num_opps, + &opp_id_src0, &opp_id_src1); + } + } + + if (num_opps > 1) { + dc_link_blank_all_edp_displays(dc); + break; + } + } + } + hws->funcs.init_pipes(dc, dc->current_state); if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, -- cgit v1.2.3 From 0c56705d8aae9696348cc320b71d531ede001b79 Mon Sep 17 00:00:00 2001 From: Duncan Ma Date: Tue, 17 May 2022 17:50:23 -0400 Subject: drm/amd/display: Correct min comp buffer size [Why] In 3-way mpo pipes, there is a case that we overbook the CRB buffer size. At rare instances, overbooking the crb will cause underflow. This only happens when det_size changes dynamically based on pipe_cnt. [How] Set min compbuff size to 1 segment when preparing BW. Reviewed-by: Dmytro Laktyushkin Acked-by: Hamza Mahfooz Signed-off-by: Duncan Ma Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c index 54db2eca9e6b..1b02f0ebe957 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c @@ -201,7 +201,7 @@ struct _vcs_dpi_ip_params_st dcn3_15_ip = { .hostvm_max_page_table_levels = 2, .rob_buffer_size_kbytes = 64, .det_buffer_size_kbytes = DCN3_15_DEFAULT_DET_SIZE, - .min_comp_buffer_size_kbytes = DCN3_15_MIN_COMPBUF_SIZE_KB, + .min_comp_buffer_size_kbytes = 64, .config_return_buffer_size_in_kbytes = 1024, .compressed_buffer_segment_size_in_kbytes = 64, .meta_fifo_size_in_kentries = 32, @@ -297,6 +297,7 @@ struct _vcs_dpi_ip_params_st dcn3_16_ip = { .hostvm_max_page_table_levels = 2, .rob_buffer_size_kbytes = 64, .det_buffer_size_kbytes = DCN3_16_DEFAULT_DET_SIZE, + .min_comp_buffer_size_kbytes = 64, .config_return_buffer_size_in_kbytes = 1024, .compressed_buffer_segment_size_in_kbytes = 64, .meta_fifo_size_in_kentries = 32, -- cgit v1.2.3 From e5309d7f66105011e0597fd55ff2ef7f636f52c6 Mon Sep 17 00:00:00 2001 From: Wenjing Liu Date: Fri, 13 May 2022 11:43:45 -0400 Subject: drm/amd/display: add DP sanity checks during enable stream [why] 1. When HPD deassertion is pulled in the middle of enabe stream link training, we will abort current training and turn off PHY. This causes current link settings to be zeroed this causes later stream enablement sequence to fail as we prefer to carry on enablement process despite of link training failure for SST. 2. When HPD is toggled after detection before before the enable stream sequence as a result. There could be a race condition where we could end up enable stream based on the previous link even though the link is updated after the HPD toggle. This causes an issue where our link bandwidth is no longer enough to accommodate the timing therefore causes us to oversubscribe MST payload time slots. As discussed we decided to add basic sanity check to make sure that our code can handle the oversubscription failure silently without system hang. [how] 1. Keep PHY powered on when HPD is deasserted during enable stream and wait for the detection sequence to power it off later. 2. Do not allocate payload if the required timeslot for current timing is greater than 64 timeslots. Reviewed-by: Aric Cyr Reviewed-by: George Shen Acked-by: Hamza Mahfooz Signed-off-by: Wenjing Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 2 ++ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 + drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 16 +++++++++++----- drivers/gpu/drm/amd/display/dc/inc/core_status.h | 2 +- 4 files changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 72376075db0c..283957dbdf93 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -422,6 +422,8 @@ char *dc_status_to_str(enum dc_status status) return "The value specified is not supported."; case DC_NO_LINK_ENC_RESOURCE: return "No link encoder resource"; + case DC_FAIL_DP_PAYLOAD_ALLOCATION: + return "Fail dp payload allocation"; case DC_ERROR_UNEXPECTED: return "Unexpected error"; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 38a458141791..ab9655d6e5c8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -3597,6 +3597,7 @@ static enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx, "allocation table for " "pipe idx: %d\n", pipe_ctx->pipe_idx); + return DC_FAIL_DP_PAYLOAD_ALLOCATION; } proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 2d0e41761c32..0496828e8673 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2875,10 +2875,13 @@ bool perform_link_training_with_retries( fail_count++; dp_trace_lt_fail_count_update(link, fail_count, false); - /* latest link training still fail, skip delay and keep PHY on - */ - if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY) - break; + if (link->ep_type == DISPLAY_ENDPOINT_PHY) { + /* latest link training still fail or link training is aborted + * skip delay and keep PHY on + */ + if (j == (attempts - 1) || (status == LINK_TRAINING_ABORT)) + break; + } DC_LOG_WARNING("%s: Link training attempt %u of %d failed @ rate(%d) x lane(%d)\n", __func__, (unsigned int)j + 1, attempts, cur_link_settings.link_rate, @@ -6890,6 +6893,10 @@ bool dpcd_write_128b_132b_sst_payload_allocation_table( if (allocate) { avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link); req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); + /// Validation should filter out modes that exceed link BW + ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); + if (req_slot_count > MAX_MTP_SLOT_COUNT) + return false; } else { /// Leave req_slot_count = 0 if allocate is false. } @@ -6917,7 +6924,6 @@ bool dpcd_write_128b_132b_sst_payload_allocation_table( &start_time_slot, 1); - ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); /// Validation should filter out modes that exceed link BW core_link_write_dpcd( link, DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h index 444182a97e6e..8eb8d4afa876 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h @@ -54,7 +54,7 @@ enum dc_status { DC_UNSUPPORTED_VALUE = 25, DC_NO_LINK_ENC_RESOURCE = 26, - + DC_FAIL_DP_PAYLOAD_ALLOCATION = 27, DC_ERROR_UNEXPECTED = -1 }; -- cgit v1.2.3 From d8791dc7f941f3dc78ef2c6aa71d7c752d5b529e Mon Sep 17 00:00:00 2001 From: Roman Li Date: Thu, 19 May 2022 14:41:16 -0400 Subject: drm/amd/display: Cap OLED brightness per max frame-average luminance [Why] For OLED eDP the Display Manager uses max_cll value as a limit for brightness control. max_cll defines the content light luminance for individual pixel. Whereas max_fall defines frame-average level luminance. The user may not observe the difference in brightness in between max_fall and max_cll. That negatively impacts the user experience. [How] Use max_fall value instead of max_cll as a limit for brightness control. Reviewed-by: Rodrigo Siqueira Acked-by: Hamza Mahfooz Signed-off-by: Roman Li Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2bb316fa62b1..e668bb1560da 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2843,7 +2843,7 @@ static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) { - u32 max_cll, min_cll, max, min, q, r; + u32 max_avg, min_cll, max, min, q, r; struct amdgpu_dm_backlight_caps *caps; struct amdgpu_display_manager *dm; struct drm_connector *conn_base; @@ -2873,7 +2873,7 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) caps = &dm->backlight_caps[i]; caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; caps->aux_support = false; - max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll; + max_avg = conn_base->hdr_sink_metadata.hdmi_type1.max_fall; min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll; if (caps->ext_caps->bits.oled == 1 /*|| @@ -2901,8 +2901,8 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) * The results of the above expressions can be verified at * pre_computed_values. */ - q = max_cll >> 5; - r = max_cll % 32; + q = max_avg >> 5; + r = max_avg % 32; max = (1 << q) * pre_computed_values[r]; // min luminance: maxLum * (CV/255)^2 / 100 -- cgit v1.2.3 From 8246370341e8e816ad22aaf8d8bfca850339ce0a Mon Sep 17 00:00:00 2001 From: Hansen Dsouza Date: Fri, 20 May 2022 16:39:29 -0400 Subject: drm/amd/display: Enable 3 plane MPO [why and how] 3 plane MPO is a new feature missing in a few resource files Enable 3 plane MPO by setting slave planes to 2 Reviewed-by: Krunoslav Kovac Reviewed-by: Aric Cyr Acked-by: Hamza Mahfooz Signed-off-by: Hansen Dsouza Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c | 6 +++--- drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c index 2b42af030b33..4f45753484fe 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c @@ -1762,9 +1762,9 @@ static bool dcn315_resource_construct( dc->caps.max_cursor_size = 256; dc->caps.min_horizontal_blanking_period = 80; dc->caps.dmdata_alloc_size = 2048; - dc->caps.max_slave_planes = 1; - dc->caps.max_slave_yuv_planes = 1; - dc->caps.max_slave_rgb_planes = 1; + dc->caps.max_slave_planes = 2; + dc->caps.max_slave_yuv_planes = 2; + dc->caps.max_slave_rgb_planes = 2; dc->caps.post_blend_color_processing = true; dc->caps.force_dp_tps4_for_cp2520 = true; dc->caps.dp_hpo = true; diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c index ef16260b7f3f..f9cee05aeccc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c @@ -1764,9 +1764,9 @@ static bool dcn316_resource_construct( dc->caps.max_cursor_size = 256; dc->caps.min_horizontal_blanking_period = 80; dc->caps.dmdata_alloc_size = 2048; - dc->caps.max_slave_planes = 1; - dc->caps.max_slave_yuv_planes = 1; - dc->caps.max_slave_rgb_planes = 1; + dc->caps.max_slave_planes = 2; + dc->caps.max_slave_yuv_planes = 2; + dc->caps.max_slave_rgb_planes = 2; dc->caps.post_blend_color_processing = true; dc->caps.force_dp_tps4_for_cp2520 = true; dc->caps.dp_hpo = true; -- cgit v1.2.3 From 874714feff3128dc691fc309ee8b9d479f541aa6 Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Sun, 22 May 2022 12:03:35 -0400 Subject: drm/amd/display: [FW Promotion] Release 0.0.119.0 Reviewed-by: Aric Cyr Acked-by: Hamza Mahfooz Signed-off-by: Anthony Koo Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index f6ad1b8c7034..bf6f017858a6 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -1427,6 +1427,7 @@ struct dmub_rb_cmd_dp_set_config_reply { struct dmub_cmd_hpd_state_query_data { uint8_t instance; /**< HPD instance or DPIA instance */ uint8_t result; /**< For returning HPD state */ + uint16_t pad; /** < Alignment */ enum aux_channel_type ch_type; /**< enum aux_channel_type */ enum aux_return_code_type status; /**< for returning the status of command */ }; -- cgit v1.2.3 From a0b9e4531b2eaf066a1ccb2986f4d2f9efa6c313 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Tue, 24 May 2022 09:29:28 -0400 Subject: drm/amd/display: 3.2.188 This version brings along the following: - Optimized blank calculations - More robust DP MST hotplug support - eDP bug fix relating to ODM - Revert a patch that caused a regression with DP - min comp buffer size fix - Make DP easier to debug - Calculate the maximum OLED brightness correctly - 3 plane MPO. Acked-by: Hamza Mahfooz Signed-off-by: Aric Cyr Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5a6c9a139e85..a1c965a84eba 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -47,7 +47,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.187" +#define DC_VER "3.2.188" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- cgit v1.2.3 From d4965c53b95d7533dfc2309d2fc25838bd33220e Mon Sep 17 00:00:00 2001 From: Duncan Ma Date: Wed, 25 May 2022 16:28:49 -0400 Subject: drm/amd/display: Fix dpp dto for disabled pipes [Why] When switching from 1 pipe to 4to1 mpc combine, DppDtoClk aren't enabled for the disabled pipes pior to programming the pipes. Upon optimizing bandwidth, DppDto are enabled causing intermittent underflow. [How] Update dppclk dto whenever pipe are flagged to enable. Reviewed-by: Dmytro Laktyushkin Reviewed-by: Nicholas Kazlauskas Reviewed-by: Hansen Dsouza Acked-by: Hamza Mahfooz Signed-off-by: Duncan Ma Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index aed8ab06b41d..facd4e01b7ac 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -1436,11 +1436,15 @@ static void dcn20_update_dchubp_dpp( struct hubp *hubp = pipe_ctx->plane_res.hubp; struct dpp *dpp = pipe_ctx->plane_res.dpp; struct dc_plane_state *plane_state = pipe_ctx->plane_state; + struct dccg *dccg = dc->res_pool->dccg; bool viewport_changed = false; if (pipe_ctx->update_flags.bits.dppclk) dpp->funcs->dpp_dppclk_control(dpp, false, true); + if (pipe_ctx->update_flags.bits.enable) + dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); + /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG -- cgit v1.2.3 From 6b6d12b6ff204cc224cd2369bda2b0580a80a5b3 Mon Sep 17 00:00:00 2001 From: Jimmy Kizito Date: Tue, 17 May 2022 13:31:03 -0400 Subject: drm/amd/display: Fix entry into transient encoder assignment mode. [Why] In some scenarios it is possible for the encoder assignment module to be set to "transient" mode even though there are no new encoder assignments. This can lead to incorrect results when querying encoder assignment, which in turn can cause incorrect displays to be manipulated. [How] Only allow encoder assignment to be in transient mode of operation when there are valid new encoder assignments. Reviewed-by: Meenakshikumar Somasundaram Reviewed-by: Jun Lei Acked-by: Hamza Mahfooz Signed-off-by: Jimmy Kizito Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 17 +++++--- .../gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c | 45 +++++++++++++++++++++- .../amd/display/dc/dcn31/dcn31_dio_link_encoder.c | 6 +++ drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h | 7 ++++ 5 files changed, 69 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 0496828e8673..c1207049dbc5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2812,8 +2812,8 @@ bool perform_link_training_with_retries( j = 0; while (j < attempts && fail_count < (attempts * 10)) { - DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d @ rate(%d) x lane(%d)\n", - __func__, (unsigned int)j + 1, attempts, cur_link_settings.link_rate, + DC_LOG_HW_LINK_TRAINING("%s: Beginning link(%d) training attempt %u of %d @ rate(%d) x lane(%d)\n", + __func__, link->link_index, (unsigned int)j + 1, attempts, cur_link_settings.link_rate, cur_link_settings.lane_count); dp_enable_link_phy( @@ -2883,8 +2883,8 @@ bool perform_link_training_with_retries( break; } - DC_LOG_WARNING("%s: Link training attempt %u of %d failed @ rate(%d) x lane(%d)\n", - __func__, (unsigned int)j + 1, attempts, cur_link_settings.link_rate, + DC_LOG_WARNING("%s: Link(%d) training attempt %u of %d failed @ rate(%d) x lane(%d)\n", + __func__, link->link_index, (unsigned int)j + 1, attempts, cur_link_settings.link_rate, cur_link_settings.lane_count); dp_disable_link_phy(link, &pipe_ctx->link_res, signal); @@ -2927,8 +2927,13 @@ bool perform_link_training_with_retries( */ req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing); link_bw = dc_link_bandwidth_kbps(link, &cur_link_settings); - if (req_bw > link_bw) - break; + is_link_bw_low = (req_bw > link_bw); + is_link_bw_min = ((cur_link_settings.link_rate <= LINK_RATE_LOW) && + (cur_link_settings.lane_count <= LANE_COUNT_ONE)); + if (is_link_bw_low) + DC_LOG_WARNING( + "%s: Link(%d) bandwidth too low after fallback req_bw(%d) > link_bw(%d)\n", + __func__, link->link_index, req_bw, link_bw); } msleep(delay_between_attempts); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c index 42da7f430113..639a0a276a08 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c @@ -26,6 +26,8 @@ #include "resource.h" #include "dc_link_dp.h" +#define DC_LOGGER dc->ctx->logger + /* Check whether stream is supported by DIG link encoders. */ static bool is_dig_link_enc_stream(struct dc_stream_state *stream) { @@ -383,6 +385,30 @@ void link_enc_cfg_link_encs_assign( state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i]; } + /* Log encoder assignments. */ + for (i = 0; i < MAX_PIPES; i++) { + struct link_enc_assignment assignment = + dc->current_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i]; + + if (assignment.valid) + DC_LOG_DEBUG("%s: CUR %s(%d) - enc_id(%d)\n", + __func__, + assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ? "PHY" : "DPIA", + assignment.ep_id.link_id.enum_id - 1, + assignment.eng_id); + } + for (i = 0; i < MAX_PIPES; i++) { + struct link_enc_assignment assignment = + state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i]; + + if (assignment.valid) + DC_LOG_DEBUG("%s: NEW %s(%d) - enc_id(%d)\n", + __func__, + assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ? "PHY" : "DPIA", + assignment.ep_id.link_id.enum_id - 1, + assignment.eng_id); + } + /* Current state mode will be set to steady once this state committed. */ state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY; } @@ -658,8 +684,25 @@ bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state) ((valid_uniqueness & 0x1) << 2) | ((valid_avail & 0x1) << 3) | ((valid_streams & 0x1) << 4); - dm_error("Invalid link encoder assignments: 0x%x\n", valid_bitmap); + DC_LOG_ERROR("%s: Invalid link encoder assignments - 0x%x\n", __func__, valid_bitmap); } return is_valid; } + +void link_enc_cfg_set_transient_mode(struct dc *dc, struct dc_state *current_state, struct dc_state *new_state) +{ + int i = 0; + int num_transient_assignments = 0; + + for (i = 0; i < MAX_PIPES; i++) { + if (current_state->res_ctx.link_enc_cfg_ctx.transient_assignments[i].valid) + num_transient_assignments++; + } + + /* Only enter transient mode if the new encoder assignments are valid. */ + if (new_state->stream_count == num_transient_assignments) { + current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_TRANSIENT; + DC_LOG_DEBUG("%s: current_state(%p) mode(%d)\n", __func__, current_state, LINK_ENC_CFG_TRANSIENT); + } +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c index 8b12b4111c88..a788d160953b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c @@ -458,6 +458,7 @@ void dcn31_link_encoder_enable_dp_output( /* Enable transmitter and encoder. */ if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) { + DC_LOG_DEBUG("%s: enc_id(%d)\n", __func__, enc->preferred_engine); dcn20_link_encoder_enable_dp_output(enc, link_settings, clock_source); } else { @@ -489,6 +490,7 @@ void dcn31_link_encoder_enable_dp_output( return; } + DC_LOG_DEBUG("%s: DPIA(%d) - enc_id(%d)\n", __func__, dpia_control.dpia_id, dpia_control.enc_id); link_dpia_control(enc->ctx, &dpia_control); } } @@ -503,6 +505,7 @@ void dcn31_link_encoder_enable_dp_mst_output( /* Enable transmitter and encoder. */ if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) { + DC_LOG_DEBUG("%s: enc_id(%d)\n", __func__, enc->preferred_engine); dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source); } else { @@ -534,6 +537,7 @@ void dcn31_link_encoder_enable_dp_mst_output( return; } + DC_LOG_DEBUG("%s: DPIA(%d) - enc_id(%d)\n", __func__, dpia_control.dpia_id, dpia_control.enc_id); link_dpia_control(enc->ctx, &dpia_control); } } @@ -547,6 +551,7 @@ void dcn31_link_encoder_disable_output( /* Disable transmitter and encoder. */ if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) { + DC_LOG_DEBUG("%s: enc_id(%d)\n", __func__, enc->preferred_engine); dcn10_link_encoder_disable_output(enc, signal); } else { @@ -578,6 +583,7 @@ void dcn31_link_encoder_disable_output( return; } + DC_LOG_DEBUG("%s: DPIA(%d) - enc_id(%d)\n", __func__, dpia_control.dpia_id, dpia_control.enc_id); link_dpia_control(enc->ctx, &dpia_control); link_encoder_disable(enc10); diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c index 55f2e30b8e5a..1ed1404e969d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c @@ -613,7 +613,7 @@ void dcn31_reset_hw_ctx_wrap( } /* New dc_state in the process of being applied to hardware. */ - dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_TRANSIENT; + link_enc_cfg_set_transient_mode(dc, dc->current_state, context); } void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable) diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h index c6f6baa6e677..7beb14169f92 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h @@ -110,4 +110,11 @@ bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, struct /* Returns true if encoder assignments in supplied state pass validity checks. */ bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state); +/* Set the link encoder assignment mode for the current_state to LINK_ENC_CFG_TRANSIENT mode. + * This indicates that a new_state is in the process of being applied to hardware. + * During this transition, old and new encoder assignments should be accessible from the old_state. + * Only allow transition into transient mode if new encoder assignments are valid. + */ +void link_enc_cfg_set_transient_mode(struct dc *dc, struct dc_state *current_state, struct dc_state *new_state); + #endif /* DC_INC_LINK_ENC_CFG_H_ */ -- cgit v1.2.3 From d445dd7b39c56a66872386a3ce0c8a862e59be46 Mon Sep 17 00:00:00 2001 From: "Lei, Jun" Date: Thu, 26 May 2022 16:58:25 -0400 Subject: drm/amd/display: Extend soc BB capabilitiy [why] Some parts are consuming dangerously close to maximum number of states supported when updating the BB (i.e. 8). [how] Change maximum stages from 9 to 20. Reviewed-by: Alvin Lee Acked-by: Hamza Mahfooz Signed-off-by: Jun Lei Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + drivers/gpu/drm/amd/display/dc/dml/dc_features.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index a1c965a84eba..7f80cec01b2e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -747,6 +747,7 @@ struct dc_debug_options { union aux_wake_wa_options aux_wake_wa; uint8_t psr_power_use_phy_fsm; enum dml_hostvm_override_opts dml_hostvm_override; + bool use_legacy_soc_bb_mechanism; }; struct gpu_info_soc_bounding_box_v1_0; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dc_features.h b/drivers/gpu/drm/amd/display/dc/dml/dc_features.h index 2a1983324629..74e86732e301 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dc_features.h +++ b/drivers/gpu/drm/amd/display/dc/dml/dc_features.h @@ -29,7 +29,7 @@ #define DC__PRESENT 1 #define DC__PRESENT__1 1 #define DC__NUM_DPP 4 -#define DC__VOLTAGE_STATES 9 +#define DC__VOLTAGE_STATES 20 #define DC__NUM_DPP__4 1 #define DC__NUM_DPP__0_PRESENT 1 #define DC__NUM_DPP__1_PRESENT 1 -- cgit v1.2.3 From 9d001360b47b792a475250bf7ef2bcfbd17ba09f Mon Sep 17 00:00:00 2001 From: Chris Park Date: Wed, 25 May 2022 23:22:11 -0400 Subject: drm/amd/display: Add HDMI member to DTO [Why] For Pixel Rate control, when on HDMI, HDMI DTO should be selected instead of DP DTO. [How] Add HDMI member to dtbclk_dto_params, so it can be used tell apart HDMI and DP DTO in the future. Reviewed-by: Alvin Lee Acked-by: Hamza Mahfooz Signed-off-by: Chris Park Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index 025169457cc8..c2d116cce119 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -80,6 +80,7 @@ struct dtbclk_dto_params { int req_audio_dtbclk_khz; int num_odm_segments; int ref_dtbclk_khz; + bool is_hdmi; }; struct dccg_funcs { -- cgit v1.2.3 From 44961f6ebce9a7dccb2ec3dca312c5dbf85920e5 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Sun, 29 May 2022 22:58:52 -0400 Subject: drm/amd/display: 3.2.189 This version brings along the following: - DPP DTO fix - Transient encoder fix - Restrict the reading of LTTPR capabilities in LTTPR mode - Increase maximum stages for BB - Distinguish HDMI DTO from DP DTO Acked-by: Hamza Mahfooz Signed-off-by: Aric Cyr Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7f80cec01b2e..76db013aac6e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -47,7 +47,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.188" +#define DC_VER "3.2.189" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- cgit v1.2.3 From 6bad4ff84cb57f548d42a41091159b750eed9ef9 Mon Sep 17 00:00:00 2001 From: David Zhang Date: Tue, 3 May 2022 17:53:44 -0400 Subject: drm/amd/display: expose AMD specific DPCD for PSR-SU-RC support [why & how] Expose vendor specific DPCD registers for rate controlling the eDP sink TCON's refresh rate during PSR active. When used in combination with PSR-SU and Freesync, it is called PSR-SU Rate Contorol, or PSR-SU-RC for short. v2: Add all DPCD registers required Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/include/ddc_service_types.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h index 20a3d4e23f66..05096c644a60 100644 --- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h +++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h @@ -41,6 +41,10 @@ #define DP_DEVICE_ID_38EC11 0x38EC11 #define DP_FORCE_PSRSU_CAPABILITY 0x40F +#define DP_SINK_PSR_ACTIVE_VTOTAL 0x373 +#define DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE 0x375 +#define DP_SOURCE_PSR_ACTIVE_VTOTAL 0x376 + enum ddc_result { DDC_RESULT_UNKNOWN = 0, DDC_RESULT_SUCESSFULL, -- cgit v1.2.3 From 6651875ad7796ed3cd84b3bafb3885d05bb543ff Mon Sep 17 00:00:00 2001 From: David Zhang Date: Tue, 3 May 2022 18:12:05 -0400 Subject: drm/amd/display: Add PSR-SU-RC support in DC [Why] PSR-SU Rate Control - or PSR-SU-RC - enables PSR-SU panels to work with variable refresh rate to allow for more power savings. Lowering the refresh rate can increase PSR residency by expanding the eDP main link shut down duration. It can also lower panel power consumption. There is a complication with PSR, since the eDP main link can be shut down. Therefore, the timing controller (TCON) on the eDP sink nees to be able to scan out its remote buffer independent of the main link. To allow the eDP source to specify the sink's refresh rate while the link is off, vendor-specific DPCD registers are used. This allows the eDP source to then "Rate Control" the panel during PSR active. [How] Add DC support to communicate with PSR-SU-RC supported eDP sinks. The sink will need to know the desired VTotal during PSR active. This change only adds support to DC, support in amdgpu_dm is still pending to enable this fully. Signed-off-by: David Zhang Signed-off-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 +++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dc_link.h | 3 +++ drivers/gpu/drm/amd/display/dc/dc_types.h | 2 ++ drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 23 ++++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h | 2 ++ .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 8 ++++++++ 6 files changed, 60 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index ab9655d6e5c8..7884530cc02b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1795,6 +1795,7 @@ static bool dc_link_construct_legacy(struct dc_link *link, */ program_hpd_filter(link); + link->psr_settings.psr_vtotal_control_support = false; link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__); @@ -3227,6 +3228,7 @@ bool dc_link_setup_psr(struct dc_link *link, /* updateSinkPsrDpcdConfig*/ union dpcd_psr_configuration psr_configuration; union dpcd_alpm_configuration alpm_configuration; + union dpcd_sink_active_vtotal_control_mode vtotal_control = {0}; psr_context->controllerId = CONTROLLER_ID_UNDEFINED; @@ -3296,6 +3298,13 @@ bool dc_link_setup_psr(struct dc_link *link, psr_config->su_y_granularity; psr_context->line_time_in_us = psr_config->line_time_in_us; + + if (link->psr_settings.psr_vtotal_control_support) { + psr_context->rate_control_caps = psr_config->rate_control_caps; + vtotal_control.bits.ENABLE = true; + core_link_write_dpcd(link, DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE, + &vtotal_control.raw, sizeof(vtotal_control.raw)); + } } psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel; @@ -3428,6 +3437,19 @@ void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency) *residency = 0; } +bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link, uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su) +{ + struct dc *dc = link->ctx->dc; + struct dmub_psr *psr = dc->res_pool->psr; + + if (psr == NULL || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support) + return false; + + psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su); + + return true; +} + const struct dc_link_status *dc_link_get_status(const struct dc_link *link) { return &link->link_status; diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h index c4a42d758b4e..29c0040a6dd4 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_link.h +++ b/drivers/gpu/drm/amd/display/dc/dc_link.h @@ -100,6 +100,7 @@ struct psr_settings { bool psr_feature_enabled; // PSR is supported by sink bool psr_allow_active; // PSR is currently active enum dc_psr_version psr_version; // Internal PSR version, determined based on DPCD + bool psr_vtotal_control_support; // Vtotal control is supported by sink /* These parameters are calculated in Driver, * based on display timing and Sink capabilities. @@ -325,6 +326,8 @@ void dc_link_blank_all_dp_displays(struct dc *dc); void dc_link_blank_all_edp_displays(struct dc *dc); void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init); +bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link, + uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su); /* Request DC to detect if there is a Panel connected. * boot - If this call is during initial boot. diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 26b62f50ac4e..fa735d5f730f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -684,6 +684,7 @@ struct psr_config { /* psr2 selective update y granularity capability */ uint8_t su_y_granularity; unsigned int line_time_in_us; + uint8_t rate_control_caps; }; union dmcu_psr_level { @@ -794,6 +795,7 @@ struct psr_context { /* psr2 selective update y granularity capability */ uint8_t su_y_granularity; unsigned int line_time_in_us; + uint8_t rate_control_caps; }; struct colorspace_transform { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index 9ca0cbb0af9b..0df06740ec39 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -250,6 +250,27 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_ dc_dmub_srv_wait_idle(dc->dmub_srv); } +/** + * Set PSR vtotal requirement for FreeSync PSR. + */ +static void dmub_psr_set_sink_vtotal_in_psr_active(struct dmub_psr *dmub, + uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su) +{ + union dmub_rb_cmd cmd; + struct dc_context *dc = dmub->ctx; + + memset(&cmd, 0, sizeof(cmd)); + cmd.psr_set_vtotal.header.type = DMUB_CMD__PSR; + cmd.psr_set_vtotal.header.sub_type = DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE; + cmd.psr_set_vtotal.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_vtotal_data); + cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_idle = psr_vtotal_idle; + cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_su = psr_vtotal_su; + + dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); + dc_dmub_srv_cmd_execute(dc->dmub_srv); + dc_dmub_srv_wait_idle(dc->dmub_srv); +} + /* * Set PSR power optimization flags. */ @@ -358,6 +379,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->line_capture_indication = 0; copy_settings_data->line_time_in_us = psr_context->line_time_in_us; + copy_settings_data->rate_control_caps = psr_context->rate_control_caps; copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled); copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us; copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; @@ -435,6 +457,7 @@ static const struct dmub_psr_funcs psr_funcs = { .psr_set_level = dmub_psr_set_level, .psr_force_static = dmub_psr_force_static, .psr_get_residency = dmub_psr_get_residency, + .psr_set_sink_vtotal_in_psr_active = dmub_psr_set_sink_vtotal_in_psr_active, .psr_set_power_opt = dmub_psr_set_power_opt, }; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h index 01acc01cc191..74005b9d352a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h @@ -46,6 +46,8 @@ struct dmub_psr_funcs { void (*psr_force_static)(struct dmub_psr *dmub, uint8_t panel_inst); void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency, uint8_t panel_inst); + void (*psr_set_sink_vtotal_in_psr_active)(struct dmub_psr *dmub, + uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su); void (*psr_set_power_opt)(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst); }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 6e6bd007babc..ec572a9e4054 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -101,6 +101,14 @@ union dpcd_alpm_configuration { unsigned char raw; }; +union dpcd_sink_active_vtotal_control_mode { + struct { + unsigned char ENABLE : 1; + unsigned char RESERVED : 7; + } bits; + unsigned char raw; +}; + union psr_error_status { struct { unsigned char LINK_CRC_ERROR :1; -- cgit v1.2.3 From f9f4daf15398c3aa0aa2dcd05ed4ea2544bcc62c Mon Sep 17 00:00:00 2001 From: David Zhang Date: Wed, 11 May 2022 13:29:54 -0400 Subject: drm/amd/display: pass panel instance in DMUB dirty rect command [Why] In cases where there are multiple eDP instances, DMUB needs to know which instance the command is for. Today, the field for specifying the panel_inst exists in both dmub_cmd_update_dirty_rect_data and dmub_cmd_update_cursor_info_data. For cursor updates, we already specify the panel_inst, but that's not the case for dirty_rect updates. Today, a value of '0' is used (due to initial memsetting of the cmd struct to 0) [how] In dc_dmub_update_dirty_rect(), Call dc_get_edp_link_panel_inst() to get the panel_inst, and fill it in the DMUB cmd struct. v2: Update commit message for clarity. Signed-off-by: Mikita Lipski Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index d4173be11903..31d83297bcb5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2837,10 +2837,14 @@ void dc_dmub_update_dirty_rect(struct dc *dc, struct dc_context *dc_ctx = dc->ctx; struct dmub_cmd_update_dirty_rect_data *update_dirty_rect; unsigned int i, j; + unsigned int panel_inst = 0; if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1) return; + if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) + return; + memset(&cmd, 0x0, sizeof(cmd)); cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT; cmd.update_dirty_rect.header.sub_type = 0; @@ -2869,6 +2873,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc, if (pipe_ctx->plane_state != plane_state) continue; + update_dirty_rect->panel_inst = panel_inst; update_dirty_rect->pipe_idx = j; dc_dmub_srv_cmd_queue(dc_ctx->dmub_srv, &cmd); dc_dmub_srv_cmd_execute(dc_ctx->dmub_srv); -- cgit v1.2.3 From 2ff6a14b20298db0763772b62cd4fb030e6d7f75 Mon Sep 17 00:00:00 2001 From: Robin Chen Date: Fri, 22 Apr 2022 17:25:38 +0800 Subject: drm/amd/display: refactor dirty rect dmub command decision [Why] To wrap the decision logic of sending dirty rect dmub command for both frame update and cursor update path. Signed-off-by: Robin Chen Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 14 ++++++++++++- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 24 ++++++++++++++++------ 2 files changed, 31 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 31d83297bcb5..645ec5bc3a7d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2827,6 +2827,18 @@ static void commit_planes_do_stream_update(struct dc *dc, } } +static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_state *stream) +{ + if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) + return true; + + if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1 && + dc->debug.enable_sw_cntl_psr) + return true; + + return false; +} + void dc_dmub_update_dirty_rect(struct dc *dc, int surface_count, struct dc_stream_state *stream, @@ -2839,7 +2851,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc, unsigned int i, j; unsigned int panel_inst = 0; - if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1) + if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream)) return; if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 351a923fbf73..573d5be9e302 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -3330,6 +3330,23 @@ static bool dcn10_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx) return false; } +static bool dcn10_dmub_should_update_cursor_data( + struct pipe_ctx *pipe_ctx, + struct dc_debug_options *debug) +{ + if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) + return false; + + if (pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) + return true; + + if (pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1 && + debug->enable_sw_cntl_psr) + return true; + + return false; +} + static void dcn10_dmub_update_cursor_data( struct pipe_ctx *pipe_ctx, struct hubp *hubp, @@ -3351,13 +3368,8 @@ static void dcn10_dmub_update_cursor_data( struct dc_debug_options *debug = &hubp->ctx->dc->debug; - if (!debug->enable_sw_cntl_psr && pipe_ctx->stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1) + if (!dcn10_dmub_should_update_cursor_data(pipe_ctx, debug)) return; - - if (pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED || - pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) - return; - /** * if cur_pos == NULL means the caller is from cursor_set_attribute * then driver use previous cursor position data -- cgit v1.2.3 From 68e355c00f2d58ba0426cf9a4d9df77077493018 Mon Sep 17 00:00:00 2001 From: Jesse Zhang Date: Tue, 7 Jun 2022 10:44:57 +0800 Subject: drm/amdkfd:Fix fw version for 10.3.6 fix fw error when loading fw for 10.3.6 Signed-off-by: Jesse Zhang Reviewed-by: Alex Deucher Reviewed-by: Mario Limonciello Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index f8635e768513..bf4200457772 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -182,7 +182,9 @@ static void kfd_device_info_init(struct kfd_dev *kfd, if (gc_version < IP_VERSION(11, 0, 0)) { /* Navi2x+, Navi1x+ */ - if (gc_version >= IP_VERSION(10, 3, 0)) + if (gc_version == IP_VERSION(10, 3, 6)) + kfd->device_info.no_atomic_fw_version = 14; + else if (gc_version >= IP_VERSION(10, 3, 0)) kfd->device_info.no_atomic_fw_version = 92; else if (gc_version >= IP_VERSION(10, 1, 1)) kfd->device_info.no_atomic_fw_version = 145; -- cgit v1.2.3 From 61243c173cd26fc8c6bea74d6d47a37ab520dacc Mon Sep 17 00:00:00 2001 From: Arunpravin Paneer Selvam Date: Tue, 7 Jun 2022 12:06:21 +0530 Subject: drm/amd/amdgpu: Fix alignment issue MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix alignment problems reported by zuul for the commit b07d1d73b09e ("drm/amd/amdgpu: Enable high priority gfx queue") Fixes: b07d1d73b09e ("drm/amd/amdgpu: Enable high priority gfx queue") Signed-off-by: Arunpravin Paneer Selvam Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 00c69f0a9f52..b697353e5a7a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -241,7 +241,7 @@ void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev) adev->gfx.me.num_queue_per_pipe; set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue, - adev->gfx.me.queue_bitmap); + adev->gfx.me.queue_bitmap); } } else { for (i = 0; i < max_queues_per_me; ++i) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 1fa9edf04022..d3558c34d406 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -544,9 +544,9 @@ static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring, prop->hqd_active = ring->funcs->type == AMDGPU_RING_TYPE_KIQ; if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE && - amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) || + amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) || (ring->funcs->type == AMDGPU_RING_TYPE_GFX && - amdgpu_gfx_is_high_priority_graphics_queue(adev, ring))) { + amdgpu_gfx_is_high_priority_graphics_queue(adev, ring))) { prop->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; prop->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; } -- cgit v1.2.3 From 143fee0ccc97284e6ece1cf86b7d50721b522448 Mon Sep 17 00:00:00 2001 From: Joseph Greathouse Date: Mon, 6 Jun 2022 16:09:25 -0500 Subject: drm/amdgpu: Add MODE register to wave debug info in gfx11 All other chips, from gfx6-gfx10, now include the MODE register at the end of the wave debug state. This appears to have been missed in gfx11, so this patch adds in MODE to the debug state for gfx11. Signed-off-by: Joseph Greathouse Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index ca37289c644f..05359df6c354 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -1096,6 +1096,7 @@ static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); + dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); } static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, -- cgit v1.2.3 From 0dc662318d36e060268751fbd3309660acd3c5aa Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Fri, 3 Jun 2022 11:58:35 -0400 Subject: drm/amd/display: Remove duplicated macro Reviewed-by: Harry Wentland Reviewed-by: Alex Deucher Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/include/dal_asic_id.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index 11391eead954..a0dffe30b394 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -221,10 +221,6 @@ enum { #ifndef ASICREV_IS_VANGOGH #define ASICREV_IS_VANGOGH(eChipRev) ((eChipRev >= VANGOGH_A0) && (eChipRev < VANGOGH_UNKNOWN)) #endif -#define GREEN_SARDINE_A0 0xA1 -#ifndef ASICREV_IS_GREEN_SARDINE -#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF)) -#endif #define FAMILY_YELLOW_CARP 146 #define YELLOW_CARP_A0 0x01 @@ -288,6 +284,4 @@ enum { #define FAMILY_UNKNOWN 0xFF - - #endif /* __DAL_ASIC_ID_H__ */ -- cgit v1.2.3 From c55300ad4a1814bac9191a4d2c7b0d74273aec7c Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 1 Jun 2022 10:26:54 -0400 Subject: drm/amd/display: Reduce frame size in the bouding box for DCN20 GCC throw warnings for the function dcn20_update_bounding_box due to its frame size that looks like this: error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] This commit fixes this issue by eliminating an intermediary variable that creates a large array. Cc: Stephen Rothwell Cc: Hamza Mahfooz Cc: Aurabindo Pillai Reviewed-by: Harry Wentland Reviewed-by: Alex Deucher Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 38 ++++++++++------------ 1 file changed, 18 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index eeec40f6fd0a..d9cc178f6980 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -1456,21 +1456,20 @@ void dcn20_calculate_wm( void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) { - struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES]; - int i; int num_calculated_states = 0; int min_dcfclk = 0; + int i; dc_assert_fp_enabled(); if (num_states == 0) return; - memset(calculated_states, 0, sizeof(calculated_states)); + memset(bb->clock_limits, 0, sizeof(bb->clock_limits)); - if (dc->bb_overrides.min_dcfclk_mhz > 0) + if (dc->bb_overrides.min_dcfclk_mhz > 0) { min_dcfclk = dc->bb_overrides.min_dcfclk_mhz; - else { + } else { if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) min_dcfclk = 310; else @@ -1481,36 +1480,35 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s for (i = 0; i < num_states; i++) { int min_fclk_required_by_uclk; - calculated_states[i].state = i; - calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; + bb->clock_limits[i].state = i; + bb->clock_limits[i].dram_speed_mts = uclk_states[i] * 16 / 1000; // FCLK:UCLK ratio is 1.08 min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080, 1000000); - calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? + bb->clock_limits[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? min_dcfclk : min_fclk_required_by_uclk; - calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ? - max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; + bb->clock_limits[i].socclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ? + max_clocks->socClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz; - calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ? - max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; + bb->clock_limits[i].dcfclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ? + max_clocks->dcfClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz; - calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000; - calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000; - calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3); + bb->clock_limits[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000; + bb->clock_limits[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000; + bb->clock_limits[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3); - calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000; + bb->clock_limits[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000; num_calculated_states++; } - calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000; - calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000; - calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000; + bb->clock_limits[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000; + bb->clock_limits[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000; + bb->clock_limits[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000; - memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits)); bb->num_states = num_calculated_states; // Duplicate the last state, DML always an extra state identical to max state to work -- cgit v1.2.3 From 6fbfc3a23c98bdcda679161c4f4e31368008af8a Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Thu, 26 May 2022 11:51:08 -0500 Subject: drm/amdkfd: Define config HSA_AMD_P2P to support peer-to-peer Extend current kernel config requirements of amdgpu by adding config HSA_AMD_P2P. Enabling HSA_AMD_P2P is REQUIRED to support peer-to-peer communication between AMD GPU devices over PCIe bus Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/Kconfig | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig b/drivers/gpu/drm/amd/amdkfd/Kconfig index 8cc0a76ddf9f..93bd4eda0d94 100644 --- a/drivers/gpu/drm/amd/amdkfd/Kconfig +++ b/drivers/gpu/drm/amd/amdkfd/Kconfig @@ -25,3 +25,17 @@ config HSA_AMD_SVM preemptions and one based on page faults. To enable page fault based memory management on most GFXv9 GPUs, set the module parameter amdgpu.noretry=0. + +config HSA_AMD_P2P + bool "HSA kernel driver support for peer-to-peer for AMD GPU devices" + depends on HSA_AMD && PCI_P2PDMA && DMABUF_MOVE_NOTIFY + help + Enable peer-to-peer (P2P) communication between AMD GPUs over + the PCIe bus. This can improve performance of multi-GPU compute + applications and libraries by enabling GPUs to access data directly + in peer GPUs' memory without intermediate copies in system memory. + + This P2P feature is only enabled on compatible chipsets, and between + GPUs with large memory BARs that expose the entire VRAM in PCIe bus + address space within the physical address limits of the GPUs. + -- cgit v1.2.3 From 08a2fd23c6c21e5ef24248a9c1b09e929655eb3b Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Thu, 26 May 2022 12:24:23 -0500 Subject: drm/amdgpu: Add peer-to-peer support among PCIe connected AMD GPUs Add support for peer-to-peer communication among AMD GPUs over PCIe bus. Support REQUIRES enablement of config HSA_AMD_P2P. Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 300 ++++++++++++++++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 31 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 10 + 5 files changed, 283 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index c67069645a2c..47bcf86cd0f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -223,6 +223,9 @@ static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; static const bool __maybe_unused debug_evictions; /* = false */ static const bool __maybe_unused no_system_mem_limit; #endif +#ifdef CONFIG_HSA_AMD_P2P +extern bool pcie_p2p; +#endif extern int amdgpu_tmz; extern int amdgpu_reset_method; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index f8b9f27adcf5..5c00ea1df21c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -48,6 +48,7 @@ enum kfd_mem_attachment_type { KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */ KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */ KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */ + KFD_MEM_ATT_SG /* Tag to DMA map SG BOs */ }; struct kfd_mem_attachment { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 6b6d46e29e6e..979855190031 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -241,6 +241,42 @@ void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) kfree(bo->kfd_bo); } +/** + * @create_dmamap_sg_bo: Creates a amdgpu_bo object to reflect information + * about USERPTR or DOOREBELL or MMIO BO. + * @adev: Device for which dmamap BO is being created + * @mem: BO of peer device that is being DMA mapped. Provides parameters + * in building the dmamap BO + * @bo_out: Output parameter updated with handle of dmamap BO + */ +static int +create_dmamap_sg_bo(struct amdgpu_device *adev, + struct kgd_mem *mem, struct amdgpu_bo **bo_out) +{ + struct drm_gem_object *gem_obj; + int ret, align; + + ret = amdgpu_bo_reserve(mem->bo, false); + if (ret) + return ret; + + align = 1; + ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, align, + AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE, + ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj); + + amdgpu_bo_unreserve(mem->bo); + + if (ret) { + pr_err("Error in creating DMA mappable SG BO on domain: %d\n", ret); + return -EINVAL; + } + + *bo_out = gem_to_amdgpu_bo(gem_obj); + (*bo_out)->parent = amdgpu_bo_ref(mem->bo); + return ret; +} + /* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's * reservation object. * @@ -446,6 +482,38 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem) return pte_flags; } +/** + * create_sg_table() - Create an sg_table for a contiguous DMA addr range + * @addr: The starting address to point to + * @size: Size of memory area in bytes being pointed to + * + * Allocates an instance of sg_table and initializes it to point to memory + * area specified by input parameters. The address used to build is assumed + * to be DMA mapped, if needed. + * + * DOORBELL or MMIO BOs use only one scatterlist node in their sg_table + * because they are physically contiguous. + * + * Return: Initialized instance of SG Table or NULL + */ +static struct sg_table *create_sg_table(uint64_t addr, uint32_t size) +{ + struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL); + + if (!sg) + return NULL; + if (sg_alloc_table(sg, 1, GFP_KERNEL)) { + kfree(sg); + return NULL; + } + sg_dma_address(sg->sgl) = addr; + sg->sgl->length = size; +#ifdef CONFIG_NEED_SG_DMA_LENGTH + sg->sgl->dma_length = size; +#endif + return sg; +} + static int kfd_mem_dmamap_userptr(struct kgd_mem *mem, struct kfd_mem_attachment *attachment) @@ -510,6 +578,87 @@ kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment) return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); } +/** + * kfd_mem_dmamap_sg_bo() - Create DMA mapped sg_table to access DOORBELL or MMIO BO + * @mem: SG BO of the DOORBELL or MMIO resource on the owning device + * @attachment: Virtual address attachment of the BO on accessing device + * + * An access request from the device that owns DOORBELL does not require DMA mapping. + * This is because the request doesn't go through PCIe root complex i.e. it instead + * loops back. The need to DMA map arises only when accessing peer device's DOORBELL + * + * In contrast, all access requests for MMIO need to be DMA mapped without regard to + * device ownership. This is because access requests for MMIO go through PCIe root + * complex. + * + * This is accomplished in two steps: + * - Obtain DMA mapped address of DOORBELL or MMIO memory that could be used + * in updating requesting device's page table + * - Signal TTM to mark memory pointed to by requesting device's BO as GPU + * accessible. This allows an update of requesting device's page table + * with entries associated with DOOREBELL or MMIO memory + * + * This method is invoked in the following contexts: + * - Mapping of DOORBELL or MMIO BO of same or peer device + * - Validating an evicted DOOREBELL or MMIO BO on device seeking access + * + * Return: ZERO if successful, NON-ZERO otherwise + */ +static int +kfd_mem_dmamap_sg_bo(struct kgd_mem *mem, + struct kfd_mem_attachment *attachment) +{ + struct ttm_operation_ctx ctx = {.interruptible = true}; + struct amdgpu_bo *bo = attachment->bo_va->base.bo; + struct amdgpu_device *adev = attachment->adev; + struct ttm_tt *ttm = bo->tbo.ttm; + enum dma_data_direction dir; + dma_addr_t dma_addr; + bool mmio; + int ret; + + /* Expect SG Table of dmapmap BO to be NULL */ + mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); + if (unlikely(ttm->sg)) { + pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio); + return -EINVAL; + } + + dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? + DMA_BIDIRECTIONAL : DMA_TO_DEVICE; + dma_addr = mem->bo->tbo.sg->sgl->dma_address; + pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length); + pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr); + dma_addr = dma_map_resource(adev->dev, dma_addr, + mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC); + ret = dma_mapping_error(adev->dev, dma_addr); + if (unlikely(ret)) + return ret; + pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr); + + ttm->sg = create_sg_table(dma_addr, mem->bo->tbo.sg->sgl->length); + if (unlikely(!ttm->sg)) { + ret = -ENOMEM; + goto unmap_sg; + } + + amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); + ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); + if (unlikely(ret)) + goto free_sg; + + return ret; + +free_sg: + sg_free_table(ttm->sg); + kfree(ttm->sg); + ttm->sg = NULL; +unmap_sg: + dma_unmap_resource(adev->dev, dma_addr, mem->bo->tbo.sg->sgl->length, + dir, DMA_ATTR_SKIP_CPU_SYNC); + return ret; +} + static int kfd_mem_dmamap_attachment(struct kgd_mem *mem, struct kfd_mem_attachment *attachment) @@ -521,6 +670,8 @@ kfd_mem_dmamap_attachment(struct kgd_mem *mem, return kfd_mem_dmamap_userptr(mem, attachment); case KFD_MEM_ATT_DMABUF: return kfd_mem_dmamap_dmabuf(attachment); + case KFD_MEM_ATT_SG: + return kfd_mem_dmamap_sg_bo(mem, attachment); default: WARN_ON_ONCE(1); } @@ -561,6 +712,50 @@ kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment) ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); } +/** + * kfd_mem_dmaunmap_sg_bo() - Free DMA mapped sg_table of DOORBELL or MMIO BO + * @mem: SG BO of the DOORBELL or MMIO resource on the owning device + * @attachment: Virtual address attachment of the BO on accessing device + * + * The method performs following steps: + * - Signal TTM to mark memory pointed to by BO as GPU inaccessible + * - Free SG Table that is used to encapsulate DMA mapped memory of + * peer device's DOORBELL or MMIO memory + * + * This method is invoked in the following contexts: + * UNMapping of DOORBELL or MMIO BO on a device having access to its memory + * Eviction of DOOREBELL or MMIO BO on device having access to its memory + * + * Return: void + */ +static void +kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem, + struct kfd_mem_attachment *attachment) +{ + struct ttm_operation_ctx ctx = {.interruptible = true}; + struct amdgpu_bo *bo = attachment->bo_va->base.bo; + struct amdgpu_device *adev = attachment->adev; + struct ttm_tt *ttm = bo->tbo.ttm; + enum dma_data_direction dir; + + if (unlikely(!ttm->sg)) { + pr_err("SG Table of BO is UNEXPECTEDLY NULL"); + return; + } + + amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); + ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); + + dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? + DMA_BIDIRECTIONAL : DMA_TO_DEVICE; + dma_unmap_resource(adev->dev, ttm->sg->sgl->dma_address, + ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC); + sg_free_table(ttm->sg); + kfree(ttm->sg); + ttm->sg = NULL; + bo->tbo.sg = NULL; +} + static void kfd_mem_dmaunmap_attachment(struct kgd_mem *mem, struct kfd_mem_attachment *attachment) @@ -574,38 +769,14 @@ kfd_mem_dmaunmap_attachment(struct kgd_mem *mem, case KFD_MEM_ATT_DMABUF: kfd_mem_dmaunmap_dmabuf(attachment); break; + case KFD_MEM_ATT_SG: + kfd_mem_dmaunmap_sg_bo(mem, attachment); + break; default: WARN_ON_ONCE(1); } } -static int -kfd_mem_attach_userptr(struct amdgpu_device *adev, struct kgd_mem *mem, - struct amdgpu_bo **bo) -{ - unsigned long bo_size = mem->bo->tbo.base.size; - struct drm_gem_object *gobj; - int ret; - - ret = amdgpu_bo_reserve(mem->bo, false); - if (ret) - return ret; - - ret = amdgpu_gem_object_create(adev, bo_size, 1, - AMDGPU_GEM_DOMAIN_CPU, - AMDGPU_GEM_CREATE_PREEMPTIBLE, - ttm_bo_type_sg, mem->bo->tbo.base.resv, - &gobj); - amdgpu_bo_unreserve(mem->bo); - if (ret) - return ret; - - *bo = gem_to_amdgpu_bo(gobj); - (*bo)->parent = amdgpu_bo_ref(mem->bo); - - return 0; -} - static int kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, struct amdgpu_bo **bo) @@ -656,6 +827,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, uint64_t va = mem->va; struct kfd_mem_attachment *attachment[2] = {NULL, NULL}; struct amdgpu_bo *bo[2] = {NULL, NULL}; + bool same_hive = false; int i, ret; if (!va) { @@ -663,6 +835,24 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, return -EINVAL; } + /* Determine access to VRAM, MMIO and DOORBELL BOs of peer devices + * + * The access path of MMIO and DOORBELL BOs of is always over PCIe. + * In contrast the access path of VRAM BOs depens upon the type of + * link that connects the peer device. Access over PCIe is allowed + * if peer device has large BAR. In contrast, access over xGMI is + * allowed for both small and large BAR configurations of peer device + */ + if ((adev != bo_adev) && + ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) || + (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) || + (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { + if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM) + same_hive = amdgpu_xgmi_same_hive(adev, bo_adev); + if (!same_hive && !amdgpu_device_is_peer_accessible(bo_adev, adev)) + return -EINVAL; + } + for (i = 0; i <= is_aql; i++) { attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL); if (unlikely(!attachment[i])) { @@ -673,9 +863,9 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va, va + bo_size, vm); - if (adev == bo_adev || - (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && adev->ram_is_direct_mapped) || - (mem->domain == AMDGPU_GEM_DOMAIN_VRAM && amdgpu_xgmi_same_hive(adev, bo_adev))) { + if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) || + (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && adev->ram_is_direct_mapped) || + same_hive) { /* Mappings on the local GPU, or VRAM mappings in the * local hive, or userptr mapping IOMMU direct map mode * share the original BO @@ -691,26 +881,30 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) { /* Create an SG BO to DMA-map userptrs on other GPUs */ attachment[i]->type = KFD_MEM_ATT_USERPTR; - ret = kfd_mem_attach_userptr(adev, mem, &bo[i]); + ret = create_dmamap_sg_bo(adev, mem, &bo[i]); if (ret) goto unwind; - } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT && - mem->bo->tbo.type != ttm_bo_type_sg) { - /* GTT BOs use DMA-mapping ability of dynamic-attach - * DMA bufs. TODO: The same should work for VRAM on - * large-BAR GPUs. - */ + /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */ + } else if (mem->bo->tbo.type == ttm_bo_type_sg) { + WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL || + mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP), + "Handing invalid SG BO in ATTACH request"); + attachment[i]->type = KFD_MEM_ATT_SG; + ret = create_dmamap_sg_bo(adev, mem, &bo[i]); + if (ret) + goto unwind; + /* Enable acces to GTT and VRAM BOs of peer devices */ + } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT || + mem->domain == AMDGPU_GEM_DOMAIN_VRAM) { attachment[i]->type = KFD_MEM_ATT_DMABUF; ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]); if (ret) goto unwind; + pr_debug("Employ DMABUF mechanim to enable peer GPU access\n"); } else { - /* FIXME: Need to DMA-map other BO types: - * large-BAR VRAM, doorbells, MMIO remap - */ - attachment[i]->type = KFD_MEM_ATT_SHARED; - bo[i] = mem->bo; - drm_gem_object_get(&bo[i]->tbo.base); + WARN_ONCE(true, "Handling invalid ATTACH request"); + ret = -EINVAL; + goto unwind; } /* Add BO to VM internal data structures */ @@ -1111,24 +1305,6 @@ update_gpuvm_pte_failed: return ret; } -static struct sg_table *create_doorbell_sg(uint64_t addr, uint32_t size) -{ - struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL); - - if (!sg) - return NULL; - if (sg_alloc_table(sg, 1, GFP_KERNEL)) { - kfree(sg); - return NULL; - } - sg->sgl->dma_address = addr; - sg->sgl->length = size; -#ifdef CONFIG_NEED_SG_DMA_LENGTH - sg->sgl->dma_length = size; -#endif - return sg; -} - static int process_validate_vms(struct amdkfd_process_info *process_info) { struct amdgpu_vm *peer_vm; @@ -1497,7 +1673,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( bo_type = ttm_bo_type_sg; if (size > UINT_MAX) return -EINVAL; - sg = create_doorbell_sg(*offset, size); + sg = create_sg_table(*offset, size); if (!sg) return -ENOMEM; } else { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 620afd75dae7..b9d50cb6c236 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include @@ -5499,6 +5500,36 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) } } +/** + * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR + * + * @adev: amdgpu_device pointer + * @peer_adev: amdgpu_device pointer for peer device trying to access @adev + * + * Return true if @peer_adev can access (DMA) @adev through the PCIe + * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of + * @peer_adev. + */ +bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, + struct amdgpu_device *peer_adev) +{ +#ifdef CONFIG_HSA_AMD_P2P + uint64_t address_mask = peer_adev->dev->dma_mask ? + ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1); + resource_size_t aper_limit = + adev->gmc.aper_base + adev->gmc.aper_size - 1; + bool p2p_access = !(pci_p2pdma_distance_many(adev->pdev, + &peer_adev->dev, 1, true) < 0); + + return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size && + adev->gmc.real_vram_size == adev->gmc.visible_vram_size && + !(adev->gmc.aper_base & address_mask || + aper_limit & address_mask)); +#else + return false; +#endif +} + int amdgpu_device_baco_enter(struct drm_device *dev) { struct amdgpu_device *adev = drm_to_adev(dev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 8890300766a5..e3d139708160 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -802,6 +802,16 @@ MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault ( module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); #endif +/** + * DOC: pcie_p2p (bool) + * Enable PCIe P2P (requires large-BAR). Default value: true (on) + */ +#ifdef CONFIG_HSA_AMD_P2P +bool pcie_p2p = true; +module_param(pcie_p2p, bool, 0444); +MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); +#endif + /** * DOC: dcfeaturemask (uint) * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. -- cgit v1.2.3 From 136788cc74cbd9fabc2922b77bfdd38a53eb7155 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Tue, 7 Jun 2022 09:43:02 -0400 Subject: drm/amd/display: fix null pointer deref error [Why] 0 was passed in place of a pointer which triggered null pointer dereference. Causes a backtrace like: [ 41.159466] RIP: 0010:dccg31_set_audio_dtbclk_dto+0x10/0x120 [amdgpu] [ 41.159928] Code: c0 00 00 00 6a 01 8b 92 84 01 00 00 52 0f b6 40 61 e9 30 ff ff ff 0f 1f 40 00 0f 1f 44 00 00 55 48 89 e5 41 56 41 55 41 54 53 <44> 8b 66 18 48 89 fb 48 8b 47 30 48 8b 3f 45 85 e4 74 09 4c 63 6e [ 41.159932] RSP: 0018:ffffaee54055afd0 EFLAGS: 00010246 [ 41.159936] RAX: 0000000000000000 RBX: 0000000000000000 RCX: ffff917445901800 [ 41.159939] RDX: ffffffffc15e6ca0 RSI: 0000000000000000 RDI: ffff91744dbd8c60 [ 41.159941] RBP: ffffaee54055aff0 R08: 0000000000000100 R09: ffffaee54055afe8 [ 41.159944] R10: 0000000000000001 R11: 0000000000000009 R12: ffff91747ca201f0 [ 41.159946] R13: ffff91747ca20000 R14: ffff917448720438 R15: ffff91747ca20000 [ 41.159948] FS: 00007f5e13e5f740(0000) GS:ffff91775ca40000(0000) knlGS:0000000000000000 [ 41.159951] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 41.159954] CR2: 0000000000000018 CR3: 000000010fea0000 CR4: 00000000003506e0 [ 41.159956] Call Trace: [ 41.159959] [ 41.159964] dce110_setup_audio_dto.isra.0+0xd8/0x1f0 [amdgpu] [ 41.160411] dce110_apply_ctx_to_hw+0x1aa/0x780 [amdgpu] [ 41.160842] ? __free_pages+0x88/0xb0 [ 41.160850] ? kfree+0x360/0x3e0 [ 41.160857] dc_commit_state+0x337/0xac0 [amdgpu] [ 41.161135] amdgpu_dm_atomic_commit_tail+0x5e3/0x2680 [amdgpu] [How] Pass in a pointer that contains nullified parameters instead of null pointer. Fixes: 405bb9eea36a ("drm/amd/display: Implement DTBCLK ref switching on dcn32") Signed-off-by: Aurabindo Pillai Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 631a8a2f9fc3..e7944c881148 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2191,15 +2191,18 @@ static void dce110_setup_audio_dto( build_audio_output(context, pipe_ctx, &audio_output); if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { - /* disable audio DTBCLK DTO */ - dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( - dc->res_pool->dccg, 0); + struct dtbclk_dto_params dto_params = {0}; pipe_ctx->stream_res.audio->funcs->wall_dto_setup( pipe_ctx->stream_res.audio, pipe_ctx->stream->signal, &audio_output.crtc_info, &audio_output.pll_info); + + /* disable audio DTBCLK DTO */ + dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( + dc->res_pool->dccg, &dto_params); + } else pipe_ctx->stream_res.audio->funcs->wall_dto_setup( pipe_ctx->stream_res.audio, -- cgit v1.2.3 From 87d6b28e4a753f4a0572a695fcee094510dc6519 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 1 Jun 2022 10:39:37 -0400 Subject: drm/amd/display: Reduce frame size in the bouding box for DCN301 GCC throw warnings for the function dcn301_fpu_update_bw_bounding_box due to its frame size that looks like this: error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] For fixing this issue I dropped an intermadiate variable. Cc: Stephen Rothwell Cc: Hamza Mahfooz Cc: Aurabindo Pillai Reviewed-by: Harry Wentland Reviewed-by: Alex Deucher Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c | 30 ++++++++++------------ 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c index 0a7a33864973..62cf283d9f41 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c @@ -249,7 +249,6 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param { struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool); struct clk_limit_table *clk_table = &bw_params->clk_table; - struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; unsigned int i, closest_clk_lvl; int j; @@ -271,24 +270,21 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param } } - clock_limits[i].state = i; - clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; - clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; - clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; - clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; - - clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz; - clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz; - clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; - clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz; - clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; - clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; - clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz; + dcn3_01_soc.clock_limits[i].state = i; + dcn3_01_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; + dcn3_01_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; + dcn3_01_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; + dcn3_01_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; + + dcn3_01_soc.clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz; + dcn3_01_soc.clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz; + dcn3_01_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; + dcn3_01_soc.clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz; + dcn3_01_soc.clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; + dcn3_01_soc.clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; + dcn3_01_soc.clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz; } - for (i = 0; i < clk_table->num_entries; i++) - dcn3_01_soc.clock_limits[i] = clock_limits[i]; - if (clk_table->num_entries) { dcn3_01_soc.num_states = clk_table->num_entries; /* duplicate last level */ -- cgit v1.2.3 From 284498206f31e655fb61b1e08d0506dccbffe55f Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 1 Jun 2022 10:52:06 -0400 Subject: drm/amd/display: Reduce frame size in the bouding box for DCN31/316 GCC throw warnings for the function dcn31_update_bw_bounding_box and dcn316_update_bw_bounding_box due to its frame size that looks like this: error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] For fixing this issue I dropped an intermadiate variable. Cc: Stephen Rothwell Cc: Hamza Mahfooz Cc: Aurabindo Pillai Reviewed-by: Harry Wentland Reviewed-by: Alex Deucher Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 58 ++++++++++------------ 1 file changed, 26 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c index 1b02f0ebe957..6da702923226 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c @@ -575,7 +575,6 @@ void dcn31_calculate_wm_and_dlg_fp( void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) { struct clk_limit_table *clk_table = &bw_params->clk_table; - struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; unsigned int i, closest_clk_lvl; int j; @@ -608,29 +607,27 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params } } - clock_limits[i].state = i; + dcn3_1_soc.clock_limits[i].state = i; /* Clocks dependent on voltage level. */ - clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; - clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; - clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; - clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; + dcn3_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; + dcn3_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; + dcn3_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; + dcn3_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; /* Clocks independent of voltage level. */ - clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : + dcn3_1_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; - clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : + dcn3_1_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; - clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; - clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; - clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; - clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; - clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; + dcn3_1_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; + dcn3_1_soc.clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; + dcn3_1_soc.clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; + dcn3_1_soc.clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; + dcn3_1_soc.clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; } - for (i = 0; i < clk_table->num_entries; i++) - dcn3_1_soc.clock_limits[i] = clock_limits[i]; if (clk_table->num_entries) { dcn3_1_soc.num_states = clk_table->num_entries; } @@ -702,7 +699,6 @@ void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) { struct clk_limit_table *clk_table = &bw_params->clk_table; - struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; unsigned int i, closest_clk_lvl; int max_dispclk_mhz = 0, max_dppclk_mhz = 0; int j; @@ -740,34 +736,32 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param closest_clk_lvl = dcn3_16_soc.num_states - 1; } - clock_limits[i].state = i; + dcn3_16_soc.clock_limits[i].state = i; /* Clocks dependent on voltage level. */ - clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; + dcn3_16_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; if (clk_table->num_entries == 1 && - clock_limits[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { + dcn3_16_soc.clock_limits[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { /*SMU fix not released yet*/ - clock_limits[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; + dcn3_16_soc.clock_limits[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; } - clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; - clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; - clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; + dcn3_16_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; + dcn3_16_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; + dcn3_16_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; /* Clocks independent of voltage level. */ - clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : + dcn3_16_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : dcn3_16_soc.clock_limits[closest_clk_lvl].dispclk_mhz; - clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : + dcn3_16_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : dcn3_16_soc.clock_limits[closest_clk_lvl].dppclk_mhz; - clock_limits[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; - clock_limits[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz; - clock_limits[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; - clock_limits[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; - clock_limits[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz; + dcn3_16_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; + dcn3_16_soc.clock_limits[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz; + dcn3_16_soc.clock_limits[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; + dcn3_16_soc.clock_limits[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; + dcn3_16_soc.clock_limits[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz; } - for (i = 0; i < clk_table->num_entries; i++) - dcn3_16_soc.clock_limits[i] = clock_limits[i]; if (clk_table->num_entries) { dcn3_16_soc.num_states = clk_table->num_entries; } -- cgit v1.2.3 From c4d7738c9efc81a4f0364da1e673ab1b1cf91735 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 24 May 2022 09:57:49 -0400 Subject: drm/amdgpu: simplify amdgpu_ucode_get_load_type() This is the same as the default case, so drop the extra logic. Reviewed-by: Guchun Chen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index ffa4c0d207db..c312577df596 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -486,26 +486,6 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) case CHIP_POLARIS12: case CHIP_VEGAM: return AMDGPU_FW_LOAD_SMU; - case CHIP_VEGA10: - case CHIP_RAVEN: - case CHIP_VEGA12: - case CHIP_VEGA20: - case CHIP_ARCTURUS: - case CHIP_RENOIR: - case CHIP_NAVI10: - case CHIP_NAVI14: - case CHIP_NAVI12: - case CHIP_SIENNA_CICHLID: - case CHIP_NAVY_FLOUNDER: - case CHIP_VANGOGH: - case CHIP_DIMGREY_CAVEFISH: - case CHIP_ALDEBARAN: - case CHIP_BEIGE_GOBY: - case CHIP_YELLOW_CARP: - if (!load_type) - return AMDGPU_FW_LOAD_DIRECT; - else - return AMDGPU_FW_LOAD_PSP; case CHIP_CYAN_SKILLFISH: if (!(load_type && adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)) -- cgit v1.2.3 From feb54650bae25f2a2adfc493e3e254e7c27a3fba Mon Sep 17 00:00:00 2001 From: Xiaohui Zhang Date: Tue, 7 Jun 2022 23:36:31 +0800 Subject: drm/radeon: integer overflow in radeon_mode_dumb_create() Similar to the handling of amdgpu_mode_dumb_create in commit 54ef0b5461c0 ("drm/amdgpu: integer overflow in amdgpu_mode_dumb_create()"), we thought a patch might be needed here as well. args->size is a u64. arg->pitch and args->height are u32. The multiplication will overflow instead of using the high 32 bits as intended. Signed-off-by: Xiaohui Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c index 8c01a7f0e027..84843b3b3aef 100644 --- a/drivers/gpu/drm/radeon/radeon_gem.c +++ b/drivers/gpu/drm/radeon/radeon_gem.c @@ -833,7 +833,7 @@ int radeon_mode_dumb_create(struct drm_file *file_priv, args->pitch = radeon_align_pitch(rdev, args->width, DIV_ROUND_UP(args->bpp, 8), 0); - args->size = args->pitch * args->height; + args->size = (u64)args->pitch * args->height; args->size = ALIGN(args->size, PAGE_SIZE); r = radeon_gem_object_create(rdev, args->size, 0, -- cgit v1.2.3 From 0f28cca87e9afc22280c44d378d2a6e249933977 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Thu, 26 May 2022 14:21:22 -0500 Subject: drm/amdkfd: Extend KFD device topology to surface peer-to-peer links Extend KFD device topology to surface peer-to-peer links among GPU devices connected over PCIe or xGMI. Enabling HSA_AMD_P2P is REQUIRED to surface peer-to-peer links. Prior to this KFD did not expose to user mode any P2P links or indirect links that go over two or more direct hops. Old versions of the Thunk used to make up their own P2P and indirect links without the information about peer-accessibility and chipset support available to the kernel mode driver. In this patch we expose P2P links in a new sysfs directory to provide more reliable P2P link information to user mode. Old versions of the Thunk will continue to work as before and ignore the new directory. This avoids conflicts between P2P links exposed by KFD and P2P links created by the Thunk itself. New versions of the Thunk will use only the P2P links provided in the new p2p_links directory, if it exists, or fall back to the old code path on older KFDs that don't expose p2p_links. Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 319 +++++++++++++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 3 + 2 files changed, 320 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 8d50d207cf66..3e240b22ec91 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -40,6 +40,7 @@ #include "kfd_svm.h" #include "amdgpu_amdkfd.h" #include "amdgpu_ras.h" +#include "amdgpu.h" /* topology_device_list - Master list of all topology devices */ static struct list_head topology_device_list; @@ -148,6 +149,7 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) struct kfd_mem_properties *mem; struct kfd_cache_properties *cache; struct kfd_iolink_properties *iolink; + struct kfd_iolink_properties *p2plink; struct kfd_perf_properties *perf; list_del(&dev->list); @@ -173,6 +175,13 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) kfree(iolink); } + while (dev->p2p_link_props.next != &dev->p2p_link_props) { + p2plink = container_of(dev->p2p_link_props.next, + struct kfd_iolink_properties, list); + list_del(&p2plink->list); + kfree(p2plink); + } + while (dev->perf_props.next != &dev->perf_props) { perf = container_of(dev->perf_props.next, struct kfd_perf_properties, list); @@ -214,6 +223,7 @@ struct kfd_topology_device *kfd_create_topology_device( INIT_LIST_HEAD(&dev->mem_props); INIT_LIST_HEAD(&dev->cache_props); INIT_LIST_HEAD(&dev->io_link_props); + INIT_LIST_HEAD(&dev->p2p_link_props); INIT_LIST_HEAD(&dev->perf_props); list_add_tail(&dev->list, device_list); @@ -465,6 +475,8 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr, dev->node_props.caches_count); sysfs_show_32bit_prop(buffer, offs, "io_links_count", dev->node_props.io_links_count); + sysfs_show_32bit_prop(buffer, offs, "p2p_links_count", + dev->node_props.p2p_links_count); sysfs_show_32bit_prop(buffer, offs, "cpu_core_id_base", dev->node_props.cpu_core_id_base); sysfs_show_32bit_prop(buffer, offs, "simd_id_base", @@ -568,6 +580,7 @@ static void kfd_remove_sysfs_file(struct kobject *kobj, struct attribute *attr) static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) { + struct kfd_iolink_properties *p2plink; struct kfd_iolink_properties *iolink; struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; @@ -585,6 +598,18 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) dev->kobj_iolink = NULL; } + if (dev->kobj_p2plink) { + list_for_each_entry(p2plink, &dev->p2p_link_props, list) + if (p2plink->kobj) { + kfd_remove_sysfs_file(p2plink->kobj, + &p2plink->attr); + p2plink->kobj = NULL; + } + kobject_del(dev->kobj_p2plink); + kobject_put(dev->kobj_p2plink); + dev->kobj_p2plink = NULL; + } + if (dev->kobj_cache) { list_for_each_entry(cache, &dev->cache_props, list) if (cache->kobj) { @@ -631,6 +656,7 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, uint32_t id) { + struct kfd_iolink_properties *p2plink; struct kfd_iolink_properties *iolink; struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; @@ -668,6 +694,10 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, if (!dev->kobj_iolink) return -ENOMEM; + dev->kobj_p2plink = kobject_create_and_add("p2p_links", dev->kobj_node); + if (!dev->kobj_p2plink) + return -ENOMEM; + dev->kobj_perf = kobject_create_and_add("perf", dev->kobj_node); if (!dev->kobj_perf) return -ENOMEM; @@ -757,6 +787,27 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, i++; } + i = 0; + list_for_each_entry(p2plink, &dev->p2p_link_props, list) { + p2plink->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL); + if (!p2plink->kobj) + return -ENOMEM; + ret = kobject_init_and_add(p2plink->kobj, &iolink_type, + dev->kobj_p2plink, "%d", i); + if (ret < 0) { + kobject_put(p2plink->kobj); + return ret; + } + + p2plink->attr.name = "properties"; + p2plink->attr.mode = KFD_SYSFS_FILE_MODE; + sysfs_attr_init(&iolink->attr); + ret = sysfs_create_file(p2plink->kobj, &p2plink->attr); + if (ret < 0) + return ret; + i++; + } + /* All hardware blocks have the same number of attributes. */ num_attrs = ARRAY_SIZE(perf_attr_iommu); list_for_each_entry(perf, &dev->perf_props, list) { @@ -1145,6 +1196,7 @@ static struct kfd_topology_device *kfd_assign_gpu(struct kfd_dev *gpu) struct kfd_mem_properties *mem; struct kfd_cache_properties *cache; struct kfd_iolink_properties *iolink; + struct kfd_iolink_properties *p2plink; down_write(&topology_lock); list_for_each_entry(dev, &topology_device_list, list) { @@ -1165,6 +1217,8 @@ static struct kfd_topology_device *kfd_assign_gpu(struct kfd_dev *gpu) cache->gpu = dev->gpu; list_for_each_entry(iolink, &dev->io_link_props, list) iolink->gpu = dev->gpu; + list_for_each_entry(p2plink, &dev->p2p_link_props, list) + p2plink->gpu = dev->gpu; break; } } @@ -1287,6 +1341,250 @@ static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev) kfd_set_iolink_non_coherent(peer_dev, link, inbound_link); } } + + /* Create indirect links so apply flags setting to all */ + list_for_each_entry(link, &dev->p2p_link_props, list) { + link->flags = CRAT_IOLINK_FLAGS_ENABLED; + kfd_set_iolink_no_atomics(dev, NULL, link); + peer_dev = kfd_topology_device_by_proximity_domain( + link->node_to); + + if (!peer_dev) + continue; + + list_for_each_entry(inbound_link, &peer_dev->p2p_link_props, + list) { + if (inbound_link->node_to != link->node_from) + continue; + + inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED; + kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link); + kfd_set_iolink_non_coherent(peer_dev, link, inbound_link); + } + } +} + +static int kfd_build_p2p_node_entry(struct kfd_topology_device *dev, + struct kfd_iolink_properties *p2plink) +{ + int ret; + + p2plink->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL); + if (!p2plink->kobj) + return -ENOMEM; + + ret = kobject_init_and_add(p2plink->kobj, &iolink_type, + dev->kobj_p2plink, "%d", dev->node_props.p2p_links_count - 1); + if (ret < 0) { + kobject_put(p2plink->kobj); + return ret; + } + + p2plink->attr.name = "properties"; + p2plink->attr.mode = KFD_SYSFS_FILE_MODE; + sysfs_attr_init(&p2plink->attr); + ret = sysfs_create_file(p2plink->kobj, &p2plink->attr); + if (ret < 0) + return ret; + + return 0; +} + +static int kfd_create_indirect_link_prop(struct kfd_topology_device *kdev, int gpu_node) +{ + struct kfd_iolink_properties *props = NULL, *props2 = NULL; + struct kfd_iolink_properties *gpu_link, *cpu_link; + struct kfd_topology_device *cpu_dev; + int ret = 0; + int i, num_cpu; + + num_cpu = 0; + list_for_each_entry(cpu_dev, &topology_device_list, list) { + if (cpu_dev->gpu) + break; + num_cpu++; + } + + gpu_link = list_first_entry(&kdev->io_link_props, + struct kfd_iolink_properties, list); + if (!gpu_link) + return -ENOMEM; + + for (i = 0; i < num_cpu; i++) { + /* CPU <--> GPU */ + if (gpu_link->node_to == i) + continue; + + /* find CPU <--> CPU links */ + cpu_dev = kfd_topology_device_by_proximity_domain(i); + if (cpu_dev) { + list_for_each_entry(cpu_link, + &cpu_dev->io_link_props, list) { + if (cpu_link->node_to == gpu_link->node_to) + break; + } + } + + if (cpu_link->node_to != gpu_link->node_to) + return -ENOMEM; + + /* CPU <--> CPU <--> GPU, GPU node*/ + props = kfd_alloc_struct(props); + if (!props) + return -ENOMEM; + + memcpy(props, gpu_link, sizeof(struct kfd_iolink_properties)); + props->weight = gpu_link->weight + cpu_link->weight; + props->min_latency = gpu_link->min_latency + cpu_link->min_latency; + props->max_latency = gpu_link->max_latency + cpu_link->max_latency; + props->min_bandwidth = min(gpu_link->min_bandwidth, cpu_link->min_bandwidth); + props->max_bandwidth = min(gpu_link->max_bandwidth, cpu_link->max_bandwidth); + + props->node_from = gpu_node; + props->node_to = i; + kdev->node_props.p2p_links_count++; + list_add_tail(&props->list, &kdev->p2p_link_props); + ret = kfd_build_p2p_node_entry(kdev, props); + if (ret < 0) + return ret; + + /* for small Bar, no CPU --> GPU in-direct links */ + if (kfd_dev_is_large_bar(kdev->gpu)) { + /* CPU <--> CPU <--> GPU, CPU node*/ + props2 = kfd_alloc_struct(props2); + if (!props2) + return -ENOMEM; + + memcpy(props2, props, sizeof(struct kfd_iolink_properties)); + props2->node_from = i; + props2->node_to = gpu_node; + props2->kobj = NULL; + cpu_dev->node_props.p2p_links_count++; + list_add_tail(&props2->list, &cpu_dev->p2p_link_props); + ret = kfd_build_p2p_node_entry(cpu_dev, props2); + if (ret < 0) + return ret; + } + } + return ret; +} + +#if defined(CONFIG_HSA_AMD_P2P) +static int kfd_add_peer_prop(struct kfd_topology_device *kdev, + struct kfd_topology_device *peer, int from, int to) +{ + struct kfd_iolink_properties *props = NULL; + struct kfd_iolink_properties *iolink1, *iolink2, *iolink3; + struct kfd_topology_device *cpu_dev; + int ret = 0; + + if (!amdgpu_device_is_peer_accessible( + kdev->gpu->adev, + peer->gpu->adev)) + return ret; + + iolink1 = list_first_entry(&kdev->io_link_props, + struct kfd_iolink_properties, list); + if (!iolink1) + return -ENOMEM; + + iolink2 = list_first_entry(&peer->io_link_props, + struct kfd_iolink_properties, list); + if (!iolink2) + return -ENOMEM; + + props = kfd_alloc_struct(props); + if (!props) + return -ENOMEM; + + memcpy(props, iolink1, sizeof(struct kfd_iolink_properties)); + + props->weight = iolink1->weight + iolink2->weight; + props->min_latency = iolink1->min_latency + iolink2->min_latency; + props->max_latency = iolink1->max_latency + iolink2->max_latency; + props->min_bandwidth = min(iolink1->min_bandwidth, iolink2->min_bandwidth); + props->max_bandwidth = min(iolink2->max_bandwidth, iolink2->max_bandwidth); + + if (iolink1->node_to != iolink2->node_to) { + /* CPU->CPU link*/ + cpu_dev = kfd_topology_device_by_proximity_domain(iolink1->node_to); + if (cpu_dev) { + list_for_each_entry(iolink3, &cpu_dev->io_link_props, list) + if (iolink3->node_to == iolink2->node_to) + break; + + props->weight += iolink3->weight; + props->min_latency += iolink3->min_latency; + props->max_latency += iolink3->max_latency; + props->min_bandwidth = min(props->min_bandwidth, + iolink3->min_bandwidth); + props->max_bandwidth = min(props->max_bandwidth, + iolink3->max_bandwidth); + } else { + WARN(1, "CPU node not found"); + } + } + + props->node_from = from; + props->node_to = to; + peer->node_props.p2p_links_count++; + list_add_tail(&props->list, &peer->p2p_link_props); + ret = kfd_build_p2p_node_entry(peer, props); + + return ret; +} +#endif + +static int kfd_dev_create_p2p_links(void) +{ + struct kfd_topology_device *dev; + struct kfd_topology_device *new_dev; + uint32_t i, k; + int ret = 0; + + k = 0; + list_for_each_entry(dev, &topology_device_list, list) + k++; + if (k < 2) + return 0; + + new_dev = list_last_entry(&topology_device_list, struct kfd_topology_device, list); + if (WARN_ON(!new_dev->gpu)) + return 0; + + k--; + i = 0; + + /* create in-direct links */ + ret = kfd_create_indirect_link_prop(new_dev, k); + if (ret < 0) + goto out; + + /* create p2p links */ +#if defined(CONFIG_HSA_AMD_P2P) + list_for_each_entry(dev, &topology_device_list, list) { + if (dev == new_dev) + break; + if (!dev->gpu || !dev->gpu->adev || + (dev->gpu->hive_id && + dev->gpu->hive_id == new_dev->gpu->hive_id)) + goto next; + + /* check if node(s) is/are peer accessible in one direction or bi-direction */ + ret = kfd_add_peer_prop(new_dev, dev, i, k); + if (ret < 0) + goto out; + + ret = kfd_add_peer_prop(dev, new_dev, k, i); + if (ret < 0) + goto out; +next: + i++; + } +#endif + +out: + return ret; } int kfd_topology_add_device(struct kfd_dev *gpu) @@ -1305,7 +1603,6 @@ int kfd_topology_add_device(struct kfd_dev *gpu) INIT_LIST_HEAD(&temp_topology_device_list); gpu_id = kfd_generate_gpu_id(gpu); - pr_debug("Adding new GPU (ID: 0x%x) to topology\n", gpu_id); /* Check to see if this gpu device exists in the topology_device_list. @@ -1362,6 +1659,8 @@ int kfd_topology_add_device(struct kfd_dev *gpu) dev->gpu_id = gpu_id; gpu->id = gpu_id; + kfd_dev_create_p2p_links(); + /* TODO: Move the following lines to function * kfd_add_non_crat_information */ @@ -1507,7 +1806,7 @@ err: static void kfd_topology_update_io_links(int proximity_domain) { struct kfd_topology_device *dev; - struct kfd_iolink_properties *iolink, *tmp; + struct kfd_iolink_properties *iolink, *p2plink, *tmp; list_for_each_entry(dev, &topology_device_list, list) { if (dev->proximity_domain > proximity_domain) @@ -1529,6 +1828,22 @@ static void kfd_topology_update_io_links(int proximity_domain) iolink->node_to--; } } + + list_for_each_entry_safe(p2plink, tmp, &dev->p2p_link_props, list) { + /* + * If there is a p2p link to the dev being deleted + * then remove that p2p link also. + */ + if (p2plink->node_to == proximity_domain) { + list_del(&p2plink->list); + dev->node_props.p2p_links_count--; + } else { + if (p2plink->node_from > proximity_domain) + p2plink->node_from--; + if (p2plink->node_to > proximity_domain) + p2plink->node_to--; + } + } } } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index 4f80d2ea1000..2fb5664e1041 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -38,6 +38,7 @@ struct kfd_node_properties { uint32_t mem_banks_count; uint32_t caches_count; uint32_t io_links_count; + uint32_t p2p_links_count; uint32_t cpu_core_id_base; uint32_t simd_id_base; uint32_t capability; @@ -131,12 +132,14 @@ struct kfd_topology_device { struct list_head cache_props; uint32_t io_link_count; struct list_head io_link_props; + struct list_head p2p_link_props; struct list_head perf_props; struct kfd_dev *gpu; struct kobject *kobj_node; struct kobject *kobj_mem; struct kobject *kobj_cache; struct kobject *kobj_iolink; + struct kobject *kobj_p2plink; struct kobject *kobj_perf; struct attribute attr_gpuid; struct attribute attr_name; -- cgit v1.2.3 From cac3bfcaedbf4d5c93cabaa7882f243099afb8ab Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 1 Jun 2022 10:57:33 -0400 Subject: drm/amd/display: Reduce frame size in the bouding box for DCN21 GCC throw warnings for the function dcn21_update_bw_bounding_box and dcn316_update_bw_bounding_box due to its frame size that looks like this: error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] For fixing this issue I dropped an intermadiate variable. Cc: Stephen Rothwell Cc: Hamza Mahfooz Cc: Aurabindo Pillai Reviewed-by: Harry Wentland Reviewed-by: Alex Deucher Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 29 ++++++++++------------ 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index d9cc178f6980..c2fec0d85da4 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -2004,7 +2004,6 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params { struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); struct clk_limit_table *clk_table = &bw_params->clk_table; - struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; unsigned int i, closest_clk_lvl = 0, k = 0; int j; @@ -2017,7 +2016,7 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params ASSERT(clk_table->num_entries); /* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */ for (i = 0; i < dcn2_1_soc.num_states + 1; i++) { - clock_limits[i] = dcn2_1_soc.clock_limits[i]; + dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i]; } for (i = 0; i < clk_table->num_entries; i++) { @@ -2033,24 +2032,22 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params if (i == 1) k++; - clock_limits[k].state = k; - clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; - clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz; - clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz; - clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; + dcn2_1_soc.clock_limits[k].state = k; + dcn2_1_soc.clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; + dcn2_1_soc.clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz; + dcn2_1_soc.clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz; + dcn2_1_soc.clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; - clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; - clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; - clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; - clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; - clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; - clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; - clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; + dcn2_1_soc.clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; + dcn2_1_soc.clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; + dcn2_1_soc.clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; + dcn2_1_soc.clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; + dcn2_1_soc.clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; + dcn2_1_soc.clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; + dcn2_1_soc.clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; k++; } - for (i = 0; i < clk_table->num_entries + 1; i++) - dcn2_1_soc.clock_limits[i] = clock_limits[i]; if (clk_table->num_entries) { dcn2_1_soc.num_states = clk_table->num_entries + 1; /* fill in min DF PState */ -- cgit v1.2.3 From 4e2d10443580d934188f226f48eda7d650711e03 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 31 May 2022 10:35:53 -0400 Subject: drm/amdkfd: Document and fix GTT BO kmap API Removed an unused parameter from two functions and added kernel-doc comments. Signed-off-by: Felix Kuehling Reviewed-by: Philip Yang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 7 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 28 ++++++++++++++++++++---- drivers/gpu/drm/amd/amdkfd/kfd_events.c | 5 ++--- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 6 ++--- 4 files changed, 32 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 5c00ea1df21c..bbe7d81bb0df 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -280,10 +280,9 @@ int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv); int amdgpu_amdkfd_gpuvm_sync_memory( struct amdgpu_device *adev, struct kgd_mem *mem, bool intr); -int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct amdgpu_device *adev, - struct kgd_mem *mem, void **kptr, uint64_t *size); -void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct amdgpu_device *adev, - struct kgd_mem *mem); +int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem, + void **kptr, uint64_t *size); +void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem); int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info, struct dma_fence **ef); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 979855190031..f386b0d256d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2083,8 +2083,21 @@ int amdgpu_amdkfd_gpuvm_sync_memory( return ret; } -int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct amdgpu_device *adev, - struct kgd_mem *mem, void **kptr, uint64_t *size) +/** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access + * + * @mem: Buffer object to be mapped for CPU access + * @kptr[out]: pointer in kernel CPU address space + * @size[out]: size of the buffer + * + * Pins the BO and maps it for kernel CPU access. The eviction fence is removed + * from the BO, since pinned BOs cannot be evicted. The bo must remain on the + * validate_list, so the GPU mapping can be restored after a page table was + * evicted. + * + * Return: 0 on success, error code on failure + */ +int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem, + void **kptr, uint64_t *size) { int ret; struct amdgpu_bo *bo = mem->bo; @@ -2135,8 +2148,15 @@ bo_reserve_failed: return ret; } -void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct amdgpu_device *adev, - struct kgd_mem *mem) +/** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Unmap a GTT BO for kernel CPU access + * + * @mem: Buffer object to be unmapped for CPU access + * + * Removes the kernel CPU mapping and unpins the BO. It does not restore the + * eviction fence, so this function should only be used for cleanup before the + * BO is destroyed. + */ +void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem) { struct amdgpu_bo *bo = mem->bo; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index 4df9c36146ba..3942a56c28bb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -377,8 +377,7 @@ int kfd_kmap_event_page(struct kfd_process *p, uint64_t event_page_offset) return -EINVAL; } - err = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(kfd->adev, - mem, &kern_addr, &size); + err = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(mem, &kern_addr, &size); if (err) { pr_err("Failed to map event page to kernel\n"); return err; @@ -387,7 +386,7 @@ int kfd_kmap_event_page(struct kfd_process *p, uint64_t event_page_offset) err = kfd_event_page_set(p, kern_addr, size, event_page_offset); if (err) { pr_err("Failed to set event page\n"); - amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(kfd->adev, mem); + amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(mem); return err; } return err; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index e3d64ec8c353..a13e60d48b73 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -693,7 +693,7 @@ static void kfd_process_free_gpuvm(struct kgd_mem *mem, struct kfd_dev *dev = pdd->dev; if (kptr) { - amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(dev->adev, mem); + amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(mem); kptr = NULL; } @@ -733,7 +733,7 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, } if (kptr) { - err = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(kdev->adev, + err = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel( (struct kgd_mem *)*mem, kptr, NULL); if (err) { pr_debug("Map GTT BO to kernel failed\n"); @@ -999,7 +999,7 @@ static void kfd_process_kunmap_signal_bo(struct kfd_process *p) if (!mem) goto out; - amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(kdev->adev, mem); + amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(mem); out: mutex_unlock(&p->mutex); -- cgit v1.2.3 From 0381ac3ca2e727d4dfb7264d9416a8ba6bb6c18b Mon Sep 17 00:00:00 2001 From: Xiaohui Zhang Date: Tue, 7 Jun 2022 23:19:33 +0800 Subject: drm/radeon: Initialize fences array entries in radeon_sa_bo_next_hole Similar to the handling of amdgpu_sa_bo_next_hole in commit 6a15f3ff19a8 ("drm/amdgpu: Initialize fences array entries in amdgpu_sa_bo_next_hole"), we thought a patch might be needed here as well. The entries were only initialized once in radeon_sa_bo_new. If a fence wasn't signalled yet in the first radeon_sa_bo_next_hole call, but then got signalled before a later radeon_sa_bo_next_hole call, it could destroy the fence but leave its pointer in the array, resulting in use-after-free in radeon_sa_bo_new. Signed-off-by: Xiaohui Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_sa.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_sa.c b/drivers/gpu/drm/radeon/radeon_sa.c index 310c322c7112..0981948bd9ed 100644 --- a/drivers/gpu/drm/radeon/radeon_sa.c +++ b/drivers/gpu/drm/radeon/radeon_sa.c @@ -267,6 +267,8 @@ static bool radeon_sa_bo_next_hole(struct radeon_sa_manager *sa_manager, for (i = 0; i < RADEON_NUM_RINGS; ++i) { struct radeon_sa_bo *sa_bo; + fences[i] = NULL; + if (list_empty(&sa_manager->flist[i])) { continue; } @@ -332,10 +334,8 @@ int radeon_sa_bo_new(struct radeon_device *rdev, spin_lock(&sa_manager->wq.lock); do { - for (i = 0; i < RADEON_NUM_RINGS; ++i) { - fences[i] = NULL; + for (i = 0; i < RADEON_NUM_RINGS; ++i) tries[i] = 0; - } do { radeon_sa_bo_try_free(sa_manager); -- cgit v1.2.3 From 851dd8625320fb626b6ab6399b2402fd84abcdfb Mon Sep 17 00:00:00 2001 From: ZhenGuo Yin Date: Mon, 6 Jun 2022 10:36:13 +0800 Subject: drm/amdgpu: fix scratch register access method in SRIOV The scratch register should be accessed through MMIO instead of RLCG in SRIOV, since it being used in RLCG register access function. Fixes: d54762cc3e6a ("drm/amdgpu: nuke dynamic gfx scratch reg allocation") Signed-off-by: ZhenGuo Yin Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 797e90e8ce28..abf2bf7f1a79 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -3780,11 +3780,12 @@ static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; + uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); uint32_t tmp = 0; unsigned i; int r; - WREG32_SOC15(GC, 0, mmSCRATCH_REG0, 0xCAFEDEAD); + WREG32(scratch, 0xCAFEDEAD); r = amdgpu_ring_alloc(ring, 3); if (r) { DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", @@ -3793,13 +3794,13 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) } amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); - amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0) - + amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START); amdgpu_ring_write(ring, 0xDEADBEEF); amdgpu_ring_commit(ring); for (i = 0; i < adev->usec_timeout; i++) { - tmp = RREG32_SOC15(GC, 0, mmSCRATCH_REG0); + tmp = RREG32(scratch); if (tmp == 0xDEADBEEF) break; if (amdgpu_emu_mode == 1) -- cgit v1.2.3 From cde83d47482e2578432f9ce029748f4f0d029e9e Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Fri, 20 May 2022 16:18:07 +0800 Subject: drm/amd/pm: enable FW CTF feature for SMU 13.0.0 The new 78.40.0 PMFW has this feature supported. Signed-off-by: Evan Quan Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index 418480e0c077..2ee17b3e8ac3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -302,6 +302,8 @@ smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu, *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT); + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT); + return 0; } -- cgit v1.2.3 From bb50bba9c6c741f5e359f009dde3b25f12a84e3d Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Mon, 23 May 2022 11:37:58 +0800 Subject: drm/amd/pm: drop unneeded thermal_controller_type check As there is actually no direct dependence between them. Signed-off-by: Evan Quan Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 6db10e49db7e..0991c1ffe525 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -1076,10 +1076,7 @@ int smu_v13_0_set_power_limit(struct smu_context *smu, int smu_v13_0_enable_thermal_alert(struct smu_context *smu) { - if (smu->smu_table.thermal_controller_type) - return amdgpu_irq_get(smu->adev, &smu->irq_source, 0); - - return 0; + return amdgpu_irq_get(smu->adev, &smu->irq_source, 0); } int smu_v13_0_disable_thermal_alert(struct smu_context *smu) -- cgit v1.2.3 From 6f73d6762694c3e91c49e6708077a0de2a75f2f5 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Wed, 25 May 2022 16:51:47 +0800 Subject: drm/amd/pm: optimize the interface for dpm feature status query Drop extra CMN2ASIC_MAPPING_FEATURE transform. Also some cosmetic fixes for better readability. Signed-off-by: Evan Quan Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 26 ++++++++------------------ 1 file changed, 8 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 53cd62ccab5d..15e4298c7cc8 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -682,16 +682,13 @@ static const char *smu_get_feature_name(struct smu_context *smu, size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu, char *buf) { + int8_t sort_feature[max(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)]; uint64_t feature_mask; - int feature_index = 0; + int i, feature_index; uint32_t count = 0; - int8_t sort_feature[SMU_FEATURE_COUNT]; size_t size = 0; - int ret = 0, i; - int feature_id; - ret = __smu_get_enabled_features(smu, &feature_mask); - if (ret) + if (__smu_get_enabled_features(smu, &feature_mask)) return 0; size = sysfs_emit_at(buf, size, "features high: 0x%08x low: 0x%08x\n", @@ -712,22 +709,15 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu, size += sysfs_emit_at(buf, size, "%-2s. %-20s %-3s : %-s\n", "No", "Feature", "Bit", "State"); - for (i = 0; i < SMU_FEATURE_COUNT; i++) { - if (sort_feature[i] < 0) - continue; - - /* convert to asic spcific feature ID */ - feature_id = smu_cmn_to_asic_specific_index(smu, - CMN2ASIC_MAPPING_FEATURE, - sort_feature[i]); - if (feature_id < 0) + for (feature_index = 0; feature_index < SMU_FEATURE_MAX; feature_index++) { + if (sort_feature[feature_index] < 0) continue; size += sysfs_emit_at(buf, size, "%02d. %-20s (%2d) : %s\n", count++, - smu_get_feature_name(smu, sort_feature[i]), - i, - !!test_bit(feature_id, (unsigned long *)&feature_mask) ? + smu_get_feature_name(smu, sort_feature[feature_index]), + feature_index, + !!test_bit(feature_index, (unsigned long *)&feature_mask) ? "enabled" : "disabled"); } -- cgit v1.2.3 From 62f8f5c3bfc2968461b0a74f0e393325bec16c69 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Thu, 28 Apr 2022 16:51:04 +0800 Subject: drm/amdgpu: enable ASPM support for PCIE 7.4.0/7.6.0 Enable ASPM support for PCIE 7.4.0 and 7.6.0. Signed-off-by: Evan Quan Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c | 116 +++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/soc21.c | 7 +- .../amd/include/asic_reg/nbio/nbio_4_3_0_offset.h | 2 + .../amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h | 1 + 6 files changed, 125 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 47bcf86cd0f3..7971d9208ecf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -670,6 +670,7 @@ enum amd_hw_ip_block_type { RSMU_HWIP, XGMI_HWIP, DCI_HWIP, + PCIE_HWIP, MAX_HWIP }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index b0811287f017..1369a1b74929 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -194,6 +194,7 @@ static int hw_id_map[MAX_HWIP] = { [UMC_HWIP] = UMC_HWID, [XGMI_HWIP] = XGMI_HWID, [DCI_HWIP] = DCI_HWID, + [PCIE_HWIP] = PCIE_HWID, }; static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c index ed31d133f07a..233be735165a 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c @@ -344,6 +344,121 @@ static u32 nbio_v4_3_get_rom_offset(struct amdgpu_device *adev) return rom_offset; } +#ifdef CONFIG_PCIEASPM +static void nbio_v4_3_program_ltr(struct amdgpu_device *adev) +{ + uint32_t def, data; + + def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); + data = 0x35EB; + data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK; + data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK; + if (def != data) + WREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); + + def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2); + data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK; + if (def != data) + WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2, data); + + def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); + if (adev->pdev->ltr_path) + data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; + else + data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; + if (def != data) + WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); +} +#endif + +static void nbio_v4_3_program_aspm(struct amdgpu_device *adev) +{ +#ifdef CONFIG_PCIEASPM + uint32_t def, data; + + if (!(adev->ip_versions[PCIE_HWIP][0] == IP_VERSION(7, 4, 0)) && + !(adev->ip_versions[PCIE_HWIP][0] == IP_VERSION(7, 6, 0))) + return; + + def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL); + data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; + data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; + data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; + if (def != data) + WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL, data); + + def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL7); + data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK; + if (def != data) + WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL7, data); + + def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3); + data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; + if (def != data) + WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3, data); + + def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3); + data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK; + data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK; + if (def != data) + WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data); + + def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5); + data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK; + if (def != data) + WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data); + + def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); + data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; + if (def != data) + WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); + + WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001); + + def = data = RREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2); + data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | + PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; + data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK; + if (def != data) + WREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2, data); + + def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL4); + data |= PCIE_LC_CNTL4__LC_L1_POWERDOWN_MASK; + if (def != data) + WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL4, data); + + def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL); + data |= PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK; + if (def != data) + WREG32_SOC15(NBIO, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL, data); + + nbio_v4_3_program_ltr(adev); + + def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3); + data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; + data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; + if (def != data) + WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data); + + def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5); + data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT; + if (def != data) + WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data); + + def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL); + data |= 0x0 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT; + data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; + data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; + if (def != data) + WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL, data); + + def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3); + data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; + if (def != data) + WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3, data); +#endif +} + const struct amdgpu_nbio_funcs nbio_v4_3_funcs = { .get_hdp_flush_req_offset = nbio_v4_3_get_hdp_flush_req_offset, .get_hdp_flush_done_offset = nbio_v4_3_get_hdp_flush_done_offset, @@ -365,4 +480,5 @@ const struct amdgpu_nbio_funcs nbio_v4_3_funcs = { .init_registers = nbio_v4_3_init_registers, .remap_hdp_registers = nbio_v4_3_remap_hdp_registers, .get_rom_offset = nbio_v4_3_get_rom_offset, + .program_aspm = nbio_v4_3_program_aspm, }; diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 57eaafb70d72..495848515edf 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -386,11 +386,12 @@ static void soc21_pcie_gen3_enable(struct amdgpu_device *adev) static void soc21_program_aspm(struct amdgpu_device *adev) { - - if (amdgpu_aspm == 0) + if (!amdgpu_device_should_use_aspm(adev)) return; - /* todo */ + if (!(adev->flags & AMD_IS_APU) && + (adev->nbio.funcs->program_aspm)) + adev->nbio.funcs->program_aspm(adev); } static void soc21_enable_doorbell_aperture(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h index 53802d674e13..4b489d64deaa 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h @@ -6918,6 +6918,8 @@ #define regPSWUSCFG0_SSID_CAP 0x2880031 #define regPSWUSCFG0_SSID_CAP_BASE_IDX 5 +#define regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL 0x2890102 +#define regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp // base address: 0x10100000 diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h index f3cda48bfaeb..d038fd915351 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h @@ -82045,5 +82045,6 @@ #define BIF_CFG_DEV0_EPF3_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL #define BIF_CFG_DEV0_EPF3_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +#define PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK 0x00010000L #endif -- cgit v1.2.3 From 1b3aa89550a2ce4f4af41e11162c5cc0b0b07b4f Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Tue, 24 May 2022 16:15:06 +0800 Subject: drm/amdgpu: avoid to perform undesired clockgating operation Make sure the clockgating feature is supported before action. Otherwise, the feature may be disabled unexpectedly on enablement request. Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c index 233be735165a..982a89f841d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c @@ -240,8 +240,11 @@ static void nbio_v4_3_update_medium_grain_clock_gating(struct amdgpu_device *ade { uint32_t def, data; + if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) + return; + def = data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL); - if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) { + if (enable) { data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | @@ -266,9 +269,12 @@ static void nbio_v4_3_update_medium_grain_light_sleep(struct amdgpu_device *adev { uint32_t def, data; + if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) + return; + /* TODO: need update in future */ def = data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2); - if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { + if (enable) { data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK; } else { data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK; -- cgit v1.2.3 From d7053e631e891698f7532712066014ca140c8ff3 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Tue, 31 May 2022 14:52:20 +0800 Subject: drm/amd/pm: enable mode1 reset support for SMU 13.0.0 Fulfill the interfaces for mode1 reset related. Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 2 ++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 11 +++++++++++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 20 ++++++++++++++++++++ 3 files changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h index fe9c47c87abc..ba6adf09bfc3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h @@ -302,5 +302,7 @@ int smu_v13_0_od_edit_dpm_table(struct smu_context *smu, int smu_v13_0_set_default_dpm_tables(struct smu_context *smu); void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu); + +int smu_v13_0_mode1_reset(struct smu_context *smu); #endif #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 0991c1ffe525..f9c36d294448 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -2411,3 +2411,14 @@ void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu) smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); } + +int smu_v13_0_mode1_reset(struct smu_context *smu) +{ + int ret = 0; + + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); + if (!ret) + msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); + + return ret; +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index 2ee17b3e8ac3..26fb72a588e7 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -117,6 +117,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), + MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0), }; static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = { @@ -1580,6 +1581,23 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, NULL); } +static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + u32 smu_version; + + /* SRIOV does not support SMU mode1 reset */ + if (amdgpu_sriov_vf(adev)) + return false; + + /* PMFW support is available since 78.41 */ + smu_cmn_get_smc_version(smu, NULL, &smu_version); + if (smu_version < 0x004e2900) + return false; + + return true; +} + static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask, .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table, @@ -1642,6 +1660,8 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { .baco_set_state = smu_v13_0_baco_set_state, .baco_enter = smu_v13_0_baco_enter, .baco_exit = smu_v13_0_baco_exit, + .mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported, + .mode1_reset = smu_v13_0_mode1_reset, }; void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu) -- cgit v1.2.3 From da4d45b7da937dfbeb918b87c66a5bf9a3079ed8 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Tue, 31 May 2022 15:13:24 +0800 Subject: drm/amd/pm: drop redundant declarations Drop those redundant declarations in smu_v13_0.h. Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h index ba6adf09bfc3..a11d36db1b8a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h @@ -278,20 +278,6 @@ int smu_v13_0_run_btc(struct smu_context *smu); int smu_v13_0_deep_sleep_control(struct smu_context *smu, bool enablement); -int smu_v13_0_gfx_ulv_control(struct smu_context *smu, - bool enablement); - -bool smu_v13_0_baco_is_support(struct smu_context *smu); - -enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu); - -int smu_v13_0_baco_set_state(struct smu_context *smu, - enum smu_baco_state state); - -int smu_v13_0_baco_enter(struct smu_context *smu); - -int smu_v13_0_baco_exit(struct smu_context *smu); - int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu); int smu_v13_0_od_edit_dpm_table(struct smu_context *smu, -- cgit v1.2.3 From 26c763875e0c15921a0480e008e2be07665e7f56 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Thu, 2 Jun 2022 11:34:10 +0800 Subject: drm/amd/pm: drop unneeded dpm features disablement for SMU 13.0.0/7 PMFW will handle that properly. Driver involvement may cause some unexpected issues. Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index ae595ee544dc..fb04d82f66e6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -1407,6 +1407,18 @@ static int smu_disable_dpms(struct smu_context *smu) (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); + /* + * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) + * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. + */ + switch (adev->ip_versions[MP1_HWIP][0]) { + case IP_VERSION(13, 0, 0): + case IP_VERSION(13, 0, 7): + return 0; + default: + break; + } + /* * For custom pptable uploading, skip the DPM features * disable process on Navi1x ASICs. @@ -1444,7 +1456,6 @@ static int smu_disable_dpms(struct smu_context *smu) case IP_VERSION(11, 0, 0): case IP_VERSION(11, 0, 5): case IP_VERSION(11, 0, 9): - case IP_VERSION(13, 0, 0): return 0; default: break; -- cgit v1.2.3 From 8728df26dd24a63b24e4e5a6c847172add2fa149 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Fri, 3 Jun 2022 10:24:31 +0800 Subject: drm/amdgpu/mes: only invalid/prime icache when finish loading both pipe MES FWs. invalid/prime icahce operation takes effect both pipes cuconrrently, therefore CP_MES_IC_BASE_LO/HI and CP_MES_MDBASE_LO/HI both have to be set before prime icache. Otherwise MES hardware gets garbage data in above regsters and causes page fault [ 470.873200] amdgpu 0000:33:00.0: amdgpu: [gfxhub] page fault (src_id:0 ring:217 vmid:0 pasid:0, for process pid 0 thread pid 0) [ 470.873222] amdgpu 0000:33:00.0: amdgpu: in page starting at address 0x000092cb89b00000 from client 10 [ 470.873234] amdgpu 0000:33:00.0: amdgpu: GCVM_L2_PROTECTION_FAULT_STATUS:0x00000BB3 [ 470.873242] amdgpu 0000:33:00.0: amdgpu: Faulty UTCL2 client ID: CPC (0x5) [ 470.873247] amdgpu 0000:33:00.0: amdgpu: MORE_FAULTS: 0x1 [ 470.873251] amdgpu 0000:33:00.0: amdgpu: WALKER_ERROR: 0x1 [ 470.873256] amdgpu 0000:33:00.0: amdgpu: PERMISSION_FAULTS: 0xb [ 470.873260] amdgpu 0000:33:00.0: amdgpu: MAPPING_ERROR: 0x1 [ 470.873264] amdgpu 0000:33:00.0: amdgpu: RW: 0x0 Signed-off-by: Yifan Zhang Acked-by: Alex Deucher Reviewed-by: Tim Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 36 +++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index fcf51947bb18..7eee004cf3ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -541,7 +541,7 @@ static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) /* This function is for backdoor MES firmware */ static int mes_v11_0_load_microcode(struct amdgpu_device *adev, - enum admgpu_mes_pipe pipe) + enum admgpu_mes_pipe pipe, bool prime_icache) { int r; uint32_t data; @@ -593,16 +593,18 @@ static int mes_v11_0_load_microcode(struct amdgpu_device *adev, /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); - /* invalidate ICACHE */ - data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); - data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); - data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); - WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); - - /* prime the ICACHE. */ - data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); - data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); - WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); + if (prime_icache) { + /* invalidate ICACHE */ + data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); + data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); + data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); + WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); + + /* prime the ICACHE. */ + data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); + data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); + WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); + } soc21_grbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); @@ -1044,17 +1046,19 @@ static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) int r = 0; if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { - r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE); + + r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); if (r) { - DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); + DRM_ERROR("failed to load MES fw, r=%d\n", r); return r; } - r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE); + r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); if (r) { - DRM_ERROR("failed to load MES fw, r=%d\n", r); + DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); return r; } + } mes_v11_0_enable(adev, true); @@ -1086,7 +1090,7 @@ static int mes_v11_0_hw_init(void *handle) if (!adev->enable_mes_kiq) { if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { r = mes_v11_0_load_microcode(adev, - AMDGPU_MES_SCHED_PIPE); + AMDGPU_MES_SCHED_PIPE, true); if (r) { DRM_ERROR("failed to MES fw, r=%d\n", r); return r; -- cgit v1.2.3 From 5d88cb162c9d70f8cb98030624b412b0f6f1c081 Mon Sep 17 00:00:00 2001 From: Mohammad Zafar Ziya Date: Tue, 7 Jun 2022 11:38:16 +0800 Subject: drm/amdgpu/jpeg2: Add jpeg vmid update under IB submit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add jpeg vmid update under IB submit Signed-off-by: Mohammad Zafar Ziya Acked-by: Christian König Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 6 +++++- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c index d2722adabd1b..f3c1af5130ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c @@ -535,6 +535,10 @@ void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, { unsigned vmid = AMDGPU_JOB_GET_VMID(job); + amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET, + 0, 0, PACKETJ_TYPE0)); + amdgpu_ring_write(ring, (vmid << JPEG_IH_CTRL__IH_VMID__SHIFT)); + amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, 0, 0, PACKETJ_TYPE0)); amdgpu_ring_write(ring, (vmid | (vmid << 4))); @@ -768,7 +772,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = { 8 + /* jpeg_v2_0_dec_ring_emit_vm_flush */ 18 + 18 + /* jpeg_v2_0_dec_ring_emit_fence x2 vm fence */ 8 + 16, - .emit_ib_size = 22, /* jpeg_v2_0_dec_ring_emit_ib */ + .emit_ib_size = 24, /* jpeg_v2_0_dec_ring_emit_ib */ .emit_ib = jpeg_v2_0_dec_ring_emit_ib, .emit_fence = jpeg_v2_0_dec_ring_emit_fence, .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h index 1a03baa59755..654e43e83e2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h @@ -41,6 +41,7 @@ #define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET 0x4084 #define mmUVD_JRBC_STATUS_INTERNAL_OFFSET 0x4089 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f +#define mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET 0x4149 #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000 -- cgit v1.2.3 From 9e68c3841390c43521d4fde6c51e91fcb2d4131f Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Tue, 12 Apr 2022 18:46:22 +0800 Subject: drm/amd/pm: add interface to deallocate power_context for smu_v13_0_7 add interface to deallocate power_context for smu_v13_0_7 Signed-off-by: Kenneth Feng Reviewed-by: Yang Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index bdea7bca3805..7da42cae5d6e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -1541,6 +1541,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { .load_microcode = smu_v13_0_load_microcode, .init_smc_tables = smu_v13_0_7_init_smc_tables, .init_power = smu_v13_0_init_power, + .fini_power = smu_v13_0_fini_power, .check_fw_status = smu_v13_0_7_check_fw_status, .setup_pptable = smu_v13_0_7_setup_pptable, .check_fw_version = smu_v13_0_check_fw_version, -- cgit v1.2.3 From 5b644783396b2150eeccb9a079498cad5dff3c42 Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Wed, 8 Jun 2022 16:31:18 +0800 Subject: drm/amd/pm: enable BACO on smu_v13_0_7 enable BACO on smu_v13_0_7 Signed-off-by: Kenneth Feng Reviewed-by: Yang Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index fb04d82f66e6..f57710790b8c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -1456,6 +1456,7 @@ static int smu_disable_dpms(struct smu_context *smu) case IP_VERSION(11, 0, 0): case IP_VERSION(11, 0, 5): case IP_VERSION(11, 0, 9): + case IP_VERSION(13, 0, 7): return 0; default: break; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index 7da42cae5d6e..dc614befcdf5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -97,6 +97,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), + MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), @@ -281,6 +282,7 @@ smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu, *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT); *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT); *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT); + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT); if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT); @@ -1584,6 +1586,11 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { .set_tool_table_location = smu_v13_0_set_tool_table_location, .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, + .baco_is_support = smu_v13_0_baco_is_support, + .baco_get_state = smu_v13_0_baco_get_state, + .baco_set_state = smu_v13_0_baco_set_state, + .baco_enter = smu_v13_0_baco_enter, + .baco_exit = smu_v13_0_baco_exit, }; void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu) -- cgit v1.2.3 From 250195ff744f260c169f5427422b6f39c58cb883 Mon Sep 17 00:00:00 2001 From: Christian König Date: Fri, 3 Jun 2022 12:21:06 +0200 Subject: drm/amdgpu: fix limiting AV1 to the first instance on VCN3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The job is not yet initialized here. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2037 Reviewed-by: Alex Deucher Tested-by: Pierre-Eric Pelloux-Prayer Signed-off-by: Christian König Fixes: cdc7893fc93f ("drm/amdgpu: use job and ib structures directly in CS parsers") Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 3cabceee5f57..39405f0db824 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -1761,23 +1761,21 @@ static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, }; -static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p, - struct amdgpu_job *job) +static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p) { struct drm_gpu_scheduler **scheds; /* The create msg must be in the first IB submitted */ - if (atomic_read(&job->base.entity->fence_seq)) + if (atomic_read(&p->entity->fence_seq)) return -EINVAL; scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC] [AMDGPU_RING_PRIO_DEFAULT].sched; - drm_sched_entity_modify_sched(job->base.entity, scheds, 1); + drm_sched_entity_modify_sched(p->entity, scheds, 1); return 0; } -static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, - uint64_t addr) +static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr) { struct ttm_operation_ctx ctx = { false, false }; struct amdgpu_bo_va_mapping *map; @@ -1848,7 +1846,7 @@ static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) continue; - r = vcn_v3_0_limit_sched(p, job); + r = vcn_v3_0_limit_sched(p); if (r) goto out; } @@ -1862,7 +1860,7 @@ static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, struct amdgpu_job *job, struct amdgpu_ib *ib) { - struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched); + struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched); uint32_t msg_lo = 0, msg_hi = 0; unsigned i; int r; @@ -1881,8 +1879,7 @@ static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, msg_hi = val; } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) && val == 0) { - r = vcn_v3_0_dec_msg(p, job, - ((u64)msg_hi) << 32 | msg_lo); + r = vcn_v3_0_dec_msg(p, ((u64)msg_hi) << 32 | msg_lo); if (r) return r; } -- cgit v1.2.3 From 64f6516e60b0bbe6abfc9f1d9f1999012e0f11a6 Mon Sep 17 00:00:00 2001 From: Christian König Date: Fri, 3 Jun 2022 15:05:04 +0200 Subject: drm/amdgpu: always flush the TLB on gfx8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits are set. Fixes: 5255e146c99a ("drm/amdgpu: rework TLB flushing") Reviewed-by: Alex Deucher Tested-by: Michal Kubecek Signed-off-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 109d8dd71c11..dc76d2b3ce52 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -793,6 +793,11 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, flush_tlb |= adev->gmc.xgmi.num_physical_nodes && adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0); + /* + * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB + */ + flush_tlb |= adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 0); + memset(¶ms, 0, sizeof(params)); params.adev = adev; params.vm = vm; -- cgit v1.2.3 From ce19bbe46fcfb88e75a6c7f691df4753a72daa81 Mon Sep 17 00:00:00 2001 From: Chandan Vurdigere Nataraj Date: Tue, 7 Jun 2022 14:58:57 +0530 Subject: drm/amdgpu/display: Remove unnecessary typecasts and fix build issues [Why] Getting below errors: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1414:5: error: implicit conversion from enumeration type 'enum scan_direction_class' to different enumeration type 'enum dm_rotation_angle' [-Werror,-Wenum-conversion] mode_lib->vba.SourceScan[k], ^~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1744:22: error: implicit conversion from enumeration type 'enum scan_direction_class' to different enumeration type 'enum dm_rotation_angle' [-Werror,-Wenum-conversion] && (!(!IsVertical(mode_lib->vba.SourceScan[k])) || mode_lib->vba.DCCEnable[k] == true)) { ~~~~~~~~~~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~ 2 errors generated. drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c:5484:18: error: implicit conversion from enumeration type 'RequestType' to different enumeration type 'enum RequestType' [-Werror,-Wenum-conversion] RequestLuma = REQ_256Bytes; ~ ^~~~~~~~~~~~ 18 errors of similar kind [How] 1. Add typecast at relevant places 2. Move the enum RequestType definition ahead of declarations Signed-off-by: Chandan Vurdigere Nataraj Reviewed-by: Leo Li Signed-off-by: Alex Deucher --- .../amd/display/dc/dml/dcn32/display_mode_vba_32.c | 5 +++-- .../dc/dml/dcn32/display_mode_vba_util_32.c | 25 +++++++++++----------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index b77a1ae792d1..5828e60f291d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -1411,7 +1411,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->BytePerPixelC[k], v->BytePerPixelDETY[k], v->BytePerPixelDETC[k], - mode_lib->vba.SourceScan[k], + (enum dm_rotation_angle) mode_lib->vba.SourceScan[k], /* Output */ &v->DCCYMaxUncompressedBlock[k], &v->DCCCMaxUncompressedBlock[k], @@ -1741,7 +1741,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.SourceFormatPixelAndScanSupport = true; for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear - && (!(!IsVertical(mode_lib->vba.SourceScan[k])) || mode_lib->vba.DCCEnable[k] == true)) { + && (!(!IsVertical((enum dm_rotation_angle) mode_lib->vba.SourceScan[k])) + || mode_lib->vba.DCCEnable[k] == true)) { mode_lib->vba.SourceFormatPixelAndScanSupport = false; } } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c index 6509a84eeb64..07f3a85f8edf 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c @@ -5314,9 +5314,15 @@ void dml32_CalculateDCCConfiguration( unsigned int *IndependentBlockLuma, unsigned int *IndependentBlockChroma) { + typedef enum { + REQ_256Bytes, + REQ_128BytesNonContiguous, + REQ_128BytesContiguous, + REQ_NA + } RequestType; - enum RequestType RequestLuma; - enum RequestType RequestChroma; + RequestType RequestLuma; + RequestType RequestChroma; unsigned int segment_order_horz_contiguous_luma; unsigned int segment_order_horz_contiguous_chroma; @@ -5350,13 +5356,6 @@ void dml32_CalculateDCCConfiguration( double detile_buf_vp_horz_limit; double detile_buf_vp_vert_limit; - typedef enum { - REQ_256Bytes, - REQ_128BytesNonContiguous, - REQ_128BytesContiguous, - REQ_NA - } RequestType; - yuv420 = ((SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_420_12) ? 1 : 0); horz_div_l = 1; @@ -5527,11 +5526,11 @@ void dml32_CalculateDCCConfiguration( RequestChroma = REQ_128BytesContiguous; } - if (RequestLuma == (enum RequestType) REQ_256Bytes) { + if (RequestLuma == REQ_256Bytes) { *MaxUncompressedBlockLuma = 256; *MaxCompressedBlockLuma = 256; *IndependentBlockLuma = 0; - } else if (RequestLuma == (enum RequestType) REQ_128BytesContiguous) { + } else if (RequestLuma == REQ_128BytesContiguous) { *MaxUncompressedBlockLuma = 256; *MaxCompressedBlockLuma = 128; *IndependentBlockLuma = 128; @@ -5541,11 +5540,11 @@ void dml32_CalculateDCCConfiguration( *IndependentBlockLuma = 64; } - if (RequestChroma == (enum RequestType) REQ_256Bytes) { + if (RequestChroma == REQ_256Bytes) { *MaxUncompressedBlockChroma = 256; *MaxCompressedBlockChroma = 256; *IndependentBlockChroma = 0; - } else if (RequestChroma == (enum RequestType) REQ_128BytesContiguous) { + } else if (RequestChroma == REQ_128BytesContiguous) { *MaxUncompressedBlockChroma = 256; *MaxCompressedBlockChroma = 128; *IndependentBlockChroma = 128; -- cgit v1.2.3 From 7aade9ceeb88d8ca674141d2c245f0107032afb1 Mon Sep 17 00:00:00 2001 From: Chandan Vurdigere Nataraj Date: Tue, 7 Jun 2022 13:47:29 +0530 Subject: drm/amdgpu/display: Fix compilation issues [Why] Getting below build errors: drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:1419:3: error: unannotated fall-through between switch labels [-Werror,-Wimplicit-fallthrough] default: ^ drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:1535:2: error: unannotated fall-through between switch labels [-Werror,-Wimplicit-fallthrough] default: ^ drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:3276:20: error: variable 'v1_5' is uninitialized when used here [-Werror,-Wuninitialized] for (i = 0; i < v1_5->number_of_path; ++i) ^~~~ [How] Fix compilation issues Signed-off-by: Chandan Vurdigere Nataraj Reviewed-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c index 3540b46765fb..25791ed0559d 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c @@ -1415,7 +1415,7 @@ static enum bp_result bios_parser_get_lttpr_caps( case 5: result = get_disp_caps_v4_5(bp, dce_caps); *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); - + break; default: break; } @@ -1532,6 +1532,7 @@ static enum bp_result bios_parser_get_embedded_panel_info( default: break; } + break; default: break; } @@ -3251,7 +3252,7 @@ static enum bp_result get_bracket_layout_record( static enum bp_result result; struct object_info_table *tbl; struct display_object_info_table_v1_4 *v1_4; - struct display_object_info_table_v1_5 *v1_5; + struct display_object_info_table_v1_5 *v1_5; if (slot_layout_info == NULL) { DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n"); @@ -3259,6 +3260,7 @@ static enum bp_result get_bracket_layout_record( } tbl = &bp->object_info_tbl; v1_4 = tbl->v1_4; + v1_5 = tbl->v1_5; result = BP_RESULT_NORECORD; switch (bp->object_info_tbl.revision.minor) { -- cgit v1.2.3 From 4c59b571fce6cedefc1c8e5158f7548f05c05ed6 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Mon, 6 Jun 2022 06:04:37 -0500 Subject: drm/amdkfd: Remove field io_link_count from struct kfd_topology_device The field is redundant and does not serve any functional role Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 -- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 1 - drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 1 - 3 files changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index cbfb32b3d235..a5409531a2fd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -1040,7 +1040,6 @@ static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink, props->rec_transfer_size = iolink->recommended_transfer_size; - dev->io_link_count++; dev->node_props.io_links_count++; list_add_tail(&props->list, &dev->io_link_props); break; @@ -1067,7 +1066,6 @@ static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink, props2->node_from = id_to; props2->node_to = id_from; props2->kobj = NULL; - to_dev->io_link_count++; to_dev->node_props.io_links_count++; list_add_tail(&props2->list, &to_dev->io_link_props); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 3e240b22ec91..304322ac39e6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1819,7 +1819,6 @@ static void kfd_topology_update_io_links(int proximity_domain) */ if (iolink->node_to == proximity_domain) { list_del(&iolink->list); - dev->io_link_count--; dev->node_props.io_links_count--; } else { if (iolink->node_from > proximity_domain) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index 2fb5664e1041..9f6c949186c1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -130,7 +130,6 @@ struct kfd_topology_device { struct list_head mem_props; uint32_t cache_count; struct list_head cache_props; - uint32_t io_link_count; struct list_head io_link_props; struct list_head p2p_link_props; struct list_head perf_props; -- cgit v1.2.3 From 73b4b53276a1d6290cd4f47dbbc885b6e6e59ac6 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 19 May 2022 09:47:28 -0400 Subject: Revert "workqueue: remove unused cancel_work()" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 6417250d3f894e66a68ba1cd93676143f2376a6f. amdpgu need this function in order to prematurly stop pending reset works when another reset work already in progress. Acked-by: Tejun Heo Signed-off-by: Andrey Grodzovsky Reviewed-by: Lai Jiangshan Reviewed-by: Christian König Signed-off-by: Alex Deucher --- include/linux/workqueue.h | 1 + kernel/workqueue.c | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/include/linux/workqueue.h b/include/linux/workqueue.h index 7fee9b6cfede..9e41e1226193 100644 --- a/include/linux/workqueue.h +++ b/include/linux/workqueue.h @@ -453,6 +453,7 @@ extern int schedule_on_each_cpu(work_func_t func); int execute_in_process_context(work_func_t fn, struct execute_work *); extern bool flush_work(struct work_struct *work); +extern bool cancel_work(struct work_struct *work); extern bool cancel_work_sync(struct work_struct *work); extern bool flush_delayed_work(struct delayed_work *dwork); diff --git a/kernel/workqueue.c b/kernel/workqueue.c index 0d2514b4ff0d..20d226d5bbc2 100644 --- a/kernel/workqueue.c +++ b/kernel/workqueue.c @@ -3258,6 +3258,15 @@ static bool __cancel_work(struct work_struct *work, bool is_dwork) return ret; } +/* + * See cancel_delayed_work() + */ +bool cancel_work(struct work_struct *work) +{ + return __cancel_work(work, false); +} +EXPORT_SYMBOL(cancel_work); + /** * cancel_delayed_work - cancel a delayed work * @dwork: delayed_work to cancel -- cgit v1.2.3 From ab9a0b1f3661157d144fb744f3a197563e8e0ff4 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Tue, 17 May 2022 11:17:35 -0400 Subject: drm/amdgpu: Cache result of last reset at reset domain level. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Will be read by executors of async reset like debugfs. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 1 + 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index b9d50cb6c236..6abec88cb5a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5318,6 +5318,8 @@ skip_sched_resume: if (r) dev_info(adev->dev, "GPU reset end with ret = %d\n", r); + + atomic_set(&adev->reset_domain->reset_res, r); return r; } @@ -5332,7 +5334,7 @@ static void amdgpu_device_queue_gpu_recover_work(struct work_struct *work) { struct amdgpu_recover_work_struct *recover_work = container_of(work, struct amdgpu_recover_work_struct, base); - recover_work->ret = amdgpu_device_gpu_recover_imp(recover_work->adev, recover_work->job); + amdgpu_device_gpu_recover_imp(recover_work->adev, recover_work->job); } /* * Serialize gpu recover into reset domain single threaded wq @@ -5349,7 +5351,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, flush_work(&work.base); - return work.ret; + return atomic_read(&adev->reset_domain->reset_res); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c index c80af0889773..32c86a0b145c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c @@ -132,6 +132,7 @@ struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_d } atomic_set(&reset_domain->in_gpu_reset, 0); + atomic_set(&reset_domain->reset_res, 0); init_rwsem(&reset_domain->sem); return reset_domain; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h index 1949dbe28a86..9e55a5d7a825 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h @@ -82,6 +82,7 @@ struct amdgpu_reset_domain { enum amdgpu_reset_domain_type type; struct rw_semaphore sem; atomic_t in_gpu_reset; + atomic_t reset_res; }; -- cgit v1.2.3 From 25a2b22e4148b1ac91960e13f4f5de020ed04d05 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Tue, 17 May 2022 12:09:27 -0400 Subject: drm/admgpu: Serialize RAS recovery work directly into reset domain queue. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Save the extra usless work schedule. Signed-off-by: Andrey Grodzovsky Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index dac202ae864d..b3b5ebbae82f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -35,6 +35,8 @@ #include "amdgpu_xgmi.h" #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" #include "atom.h" +#include "amdgpu_reset.h" + #ifdef CONFIG_X86_MCE_AMD #include @@ -1937,7 +1939,7 @@ static void amdgpu_ras_do_recovery(struct work_struct *work) } if (amdgpu_device_should_recover_gpu(ras->adev)) - amdgpu_device_gpu_recover(ras->adev, NULL); + amdgpu_device_gpu_recover_imp(ras->adev, NULL); atomic_set(&ras->in_recovery, 0); } @@ -2946,7 +2948,7 @@ int amdgpu_ras_reset_gpu(struct amdgpu_device *adev) struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0) - schedule_work(&ras->recovery_work); + amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work); return 0; } -- cgit v1.2.3 From 2f83658ffc8c259f05e79dc632e34b26bb8b75c5 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Tue, 17 May 2022 14:14:19 -0400 Subject: drm/amdgpu: Add work_struct for GPU reset from debugfs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We need to have a work_struct to cancel this reset if another already in progress. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 19 +++++++++++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 7971d9208ecf..ddb36c33b4bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1058,6 +1058,8 @@ struct amdgpu_device { bool scpm_enabled; uint32_t scpm_status; + + struct work_struct reset_work; }; static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index d16c8c1f72db..b0498ffcf7c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -39,6 +39,7 @@ #include #include "amdgpu.h" #include "amdgpu_trace.h" +#include "amdgpu_reset.h" /* * Fences @@ -798,7 +799,10 @@ static int gpu_recover_get(void *data, u64 *val) return 0; } - *val = amdgpu_device_gpu_recover(adev, NULL); + if (amdgpu_reset_domain_schedule(adev->reset_domain, &adev->reset_work)) + flush_work(&adev->reset_work); + + *val = atomic_read(&adev->reset_domain->reset_res); pm_runtime_mark_last_busy(dev->dev); pm_runtime_put_autosuspend(dev->dev); @@ -810,6 +814,14 @@ DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_fence_info); DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gpu_recover_fops, gpu_recover_get, NULL, "%lld\n"); +static void amdgpu_debugfs_reset_work(struct work_struct *work) +{ + struct amdgpu_device *adev = container_of(work, struct amdgpu_device, + reset_work); + + amdgpu_device_gpu_recover_imp(adev, NULL); +} + #endif void amdgpu_debugfs_fence_init(struct amdgpu_device *adev) @@ -821,9 +833,12 @@ void amdgpu_debugfs_fence_init(struct amdgpu_device *adev) debugfs_create_file("amdgpu_fence_info", 0444, root, adev, &amdgpu_debugfs_fence_info_fops); - if (!amdgpu_sriov_vf(adev)) + if (!amdgpu_sriov_vf(adev)) { + + INIT_WORK(&adev->reset_work, amdgpu_debugfs_reset_work); debugfs_create_file("amdgpu_gpu_recover", 0444, root, adev, &amdgpu_debugfs_gpu_recover_fops); + } #endif } -- cgit v1.2.3 From b5fd0cf3ea377a7332721df8a8c8e7715f93c8d4 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Tue, 17 May 2022 14:25:20 -0400 Subject: drm/amdgpu: Add work_struct for GPU reset from kfd. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We need to have a work_struct to cancel this reset if another already in progress. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 15 ++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 31 ------------------------------ 3 files changed, 15 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 1f8161cd507f..a23abc0e86e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -33,6 +33,7 @@ #include #include "amdgpu_ras.h" #include "amdgpu_umc.h" +#include "amdgpu_reset.h" /* Total memory size in system memory and all GPU VRAM. Used to * estimate worst case amount of memory to reserve for page tables @@ -122,6 +123,15 @@ static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, } } + +static void amdgpu_amdkfd_reset_work(struct work_struct *work) +{ + struct amdgpu_device *adev = container_of(work, struct amdgpu_device, + kfd.reset_work); + + amdgpu_device_gpu_recover_imp(adev, NULL); +} + void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) { int i; @@ -180,6 +190,8 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, adev_to_drm(adev), &gpu_resources); + + INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work); } } @@ -247,7 +259,8 @@ int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) { if (amdgpu_device_should_recover_gpu(adev)) - amdgpu_device_gpu_recover(adev, NULL); + amdgpu_reset_domain_schedule(adev->reset_domain, + &adev->kfd.reset_work); } int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index bbe7d81bb0df..ffb2b7d9b9a5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -97,6 +97,7 @@ struct amdgpu_kfd_dev { struct kfd_dev *dev; uint64_t vram_used; bool init_complete; + struct work_struct reset_work; }; enum kgd_engine_type { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 6abec88cb5a8..2d490941e727 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5323,37 +5323,6 @@ skip_sched_resume: return r; } -struct amdgpu_recover_work_struct { - struct work_struct base; - struct amdgpu_device *adev; - struct amdgpu_job *job; - int ret; -}; - -static void amdgpu_device_queue_gpu_recover_work(struct work_struct *work) -{ - struct amdgpu_recover_work_struct *recover_work = container_of(work, struct amdgpu_recover_work_struct, base); - - amdgpu_device_gpu_recover_imp(recover_work->adev, recover_work->job); -} -/* - * Serialize gpu recover into reset domain single threaded wq - */ -int amdgpu_device_gpu_recover(struct amdgpu_device *adev, - struct amdgpu_job *job) -{ - struct amdgpu_recover_work_struct work = {.adev = adev, .job = job}; - - INIT_WORK(&work.base, amdgpu_device_queue_gpu_recover_work); - - if (!amdgpu_reset_domain_schedule(adev->reset_domain, &work.base)) - return -EAGAIN; - - flush_work(&work.base); - - return atomic_read(&adev->reset_domain->reset_res); -} - /** * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot * -- cgit v1.2.3 From cf727044144d47c3e8482b9a7775bd3f04a87341 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Tue, 17 May 2022 14:27:49 -0400 Subject: drm/amdgpu: Rename amdgpu_device_gpu_recover_imp back to amdgpu_device_gpu_recover MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We removed the wrapper that was queueing the recover function into reset domain queue who was using this name. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 2 +- drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 2 +- drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index ddb36c33b4bc..fb9399a999ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1254,7 +1254,7 @@ bool amdgpu_device_has_job_running(struct amdgpu_device *adev); bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); int amdgpu_device_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job); -int amdgpu_device_gpu_recover_imp(struct amdgpu_device *adev, +int amdgpu_device_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job); void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); int amdgpu_device_pci_reset(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index a23abc0e86e7..513c57f839d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -129,7 +129,7 @@ static void amdgpu_amdkfd_reset_work(struct work_struct *work) struct amdgpu_device *adev = container_of(work, struct amdgpu_device, kfd.reset_work); - amdgpu_device_gpu_recover_imp(adev, NULL); + amdgpu_device_gpu_recover(adev, NULL); } void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2d490941e727..2d5a623598b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5076,7 +5076,7 @@ retry: * Returns 0 for success or an error on failure. */ -int amdgpu_device_gpu_recover_imp(struct amdgpu_device *adev, +int amdgpu_device_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job) { struct list_head device_list, *device_list_handle = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index b0498ffcf7c3..957437a5558c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -819,7 +819,7 @@ static void amdgpu_debugfs_reset_work(struct work_struct *work) struct amdgpu_device *adev = container_of(work, struct amdgpu_device, reset_work); - amdgpu_device_gpu_recover_imp(adev, NULL); + amdgpu_device_gpu_recover(adev, NULL); } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 67f66f2f1809..26ede765eed8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -64,7 +64,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) ti.process_name, ti.tgid, ti.task_name, ti.pid); if (amdgpu_device_should_recover_gpu(ring->adev)) { - r = amdgpu_device_gpu_recover_imp(ring->adev, job); + r = amdgpu_device_gpu_recover(ring->adev, job); if (r) DRM_ERROR("GPU Recovery Failed: %d\n", r); } else { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index b3b5ebbae82f..285534bfc084 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1939,7 +1939,7 @@ static void amdgpu_ras_do_recovery(struct work_struct *work) } if (amdgpu_device_should_recover_gpu(ras->adev)) - amdgpu_device_gpu_recover_imp(ras->adev, NULL); + amdgpu_device_gpu_recover(ras->adev, NULL); atomic_set(&ras->in_recovery, 0); } diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c index b81acf59870c..7ec5b5cf4bb9 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -284,7 +284,7 @@ flr_done: if (amdgpu_device_should_recover_gpu(adev) && (!amdgpu_device_has_job_running(adev) || adev->sdma_timeout == MAX_SCHEDULE_TIMEOUT)) - amdgpu_device_gpu_recover_imp(adev, NULL); + amdgpu_device_gpu_recover(adev, NULL); } static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c index 22c10b97ea81..e18b75c8fde6 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c @@ -311,7 +311,7 @@ flr_done: adev->gfx_timeout == MAX_SCHEDULE_TIMEOUT || adev->compute_timeout == MAX_SCHEDULE_TIMEOUT || adev->video_timeout == MAX_SCHEDULE_TIMEOUT)) - amdgpu_device_gpu_recover_imp(adev, NULL); + amdgpu_device_gpu_recover(adev, NULL); } static int xgpu_nv_set_mailbox_rcv_irq(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c index 7b63d30b9b79..c5016a926331 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c @@ -523,7 +523,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct *work) /* Trigger recovery due to world switch failure */ if (amdgpu_device_should_recover_gpu(adev)) - amdgpu_device_gpu_recover_imp(adev, NULL); + amdgpu_device_gpu_recover(adev, NULL); } static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev, -- cgit v1.2.3 From 247c7b0dac3cf1141b8bf5520adf2fac1a797aa9 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Tue, 17 May 2022 14:56:34 -0400 Subject: drm/amdgpu: Stop any pending reset if another in progress. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We skip rest requests if another one is already in progress. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2d5a623598b8..45dc96aee39e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5065,6 +5065,27 @@ retry: } } +static inline void amdggpu_device_stop_pedning_resets(struct amdgpu_device *adev) +{ + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + +#if defined(CONFIG_DEBUG_FS) + if (!amdgpu_sriov_vf(adev)) + cancel_work(&adev->reset_work); +#endif + + if (adev->kfd.dev) + cancel_work(&adev->kfd.reset_work); + + if (amdgpu_sriov_vf(adev)) + cancel_work(&adev->virt.flr_work); + + if (con && adev->ras_enabled) + cancel_work(&con->recovery_work); + +} + + /** * amdgpu_device_gpu_recover_imp - reset the asic and recover scheduler * @@ -5220,6 +5241,12 @@ retry: /* Rest of adevs pre asic reset from XGMI hive. */ r, adev_to_drm(tmp_adev)->unique); tmp_adev->asic_reset_res = r; } + + /* + * Drop all pending non scheduler resets. Scheduler resets + * were already dropped during drm_sched_stop + */ + amdggpu_device_stop_pedning_resets(tmp_adev); } tmp_vram_lost_counter = atomic_read(&((adev)->vram_lost_counter)); -- cgit v1.2.3 From e3c60b4ef42d4db5b8d1434fa1741abd7f2fc850 Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Wed, 8 Jun 2022 16:40:14 +0800 Subject: drm/amd/pm: update the driver if header for smu_v13_0_7 update the driver if header for smu_v13_0_7 Signed-off-by: Kenneth Feng Reviewed-by: Yang Wang Signed-off-by: Alex Deucher --- .../pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h | 62 +++++++++++++++------- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 2 +- 2 files changed, 45 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h index d99b4b47d49d..132da684e379 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h @@ -25,10 +25,10 @@ // *** IMPORTANT *** // PMFW TEAM: Always increment the interface version on any change to this file -#define SMU13_DRIVER_IF_VERSION 0x28 +#define SMU13_DRIVER_IF_VERSION 0x2A //Increment this version if SkuTable_t or BoardTable_t change -#define PPTABLE_VERSION 0x1D +#define PPTABLE_VERSION 0x1E #define NUM_GFXCLK_DPM_LEVELS 16 #define NUM_SOCCLK_DPM_LEVELS 8 @@ -112,6 +112,22 @@ #define FEATURE_SPARE_63_BIT 63 #define NUM_FEATURES 64 +#define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL +#define ALLOWED_FEATURE_CTRL_SCPM (1 << FEATURE_DPM_GFXCLK_BIT) | \ + (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \ + (1 << FEATURE_DPM_UCLK_BIT) | \ + (1 << FEATURE_DPM_FCLK_BIT) | \ + (1 << FEATURE_DPM_SOCCLK_BIT) | \ + (1 << FEATURE_DPM_MP0CLK_BIT) | \ + (1 << FEATURE_DPM_LINK_BIT) | \ + (1 << FEATURE_DPM_DCN_BIT) | \ + (1 << FEATURE_DS_GFXCLK_BIT) | \ + (1 << FEATURE_DS_SOCCLK_BIT) | \ + (1 << FEATURE_DS_FCLK_BIT) | \ + (1 << FEATURE_DS_LCLK_BIT) | \ + (1 << FEATURE_DS_DCFCLK_BIT) | \ + (1 << FEATURE_DS_UCLK_BIT) + //For use with feature control messages typedef enum { FEATURE_PWR_ALL, @@ -662,7 +678,7 @@ typedef struct { #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1 -#define PP_OD_FEATURE_VF_CURVE_BIT 0 +#define PP_OD_FEATURE_GFX_VF_CURVE_BIT 0 #define PP_OD_FEATURE_VMAX_BIT 1 #define PP_OD_FEATURE_PPT_BIT 2 #define PP_OD_FEATURE_FAN_CURVE_BIT 3 @@ -671,6 +687,8 @@ typedef struct { #define PP_OD_FEATURE_TDC_BIT 6 #define PP_OD_FEATURE_GFXCLK_BIT 7 #define PP_OD_FEATURE_UCLK_BIT 8 +#define PP_OD_FEATURE_ZERO_FAN_BIT 9 +#define PP_OD_FEATURE_TEMPERATURE_BIT 10 typedef enum { PP_OD_POWER_FEATURE_ALWAYS_ENABLED, @@ -689,8 +707,8 @@ typedef struct { uint8_t RuntimePwrSavingFeaturesCtrl; //Frequency changes - uint16_t GfxclkFmin; // MHz - uint16_t GfxclkFmax; // MHz + int16_t GfxclkFmin; // MHz + int16_t GfxclkFmax; // MHz uint16_t UclkFmin; // MHz uint16_t UclkFmax; // MHz @@ -701,17 +719,17 @@ typedef struct { //Fan control uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; - uint16_t FanMaximumRpm; uint16_t FanMinimumPwm; - uint16_t FanAcousticLimitRpm; + uint16_t AcousticTargetRpmThreshold; + uint16_t AcousticLimitRpmThreshold; uint16_t FanTargetTemperature; // Degree Celcius uint8_t FanZeroRpmEnable; uint8_t FanZeroRpmStopTemp; uint8_t FanMode; - uint8_t Padding[1]; - + uint8_t MaxOpTemp; + uint8_t Padding[4]; - uint32_t Spare[13]; + uint32_t Spare[12]; uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround } OverDriveTable_t; @@ -740,17 +758,17 @@ typedef struct { uint8_t FanLinearPwmPoints; uint8_t FanLinearTempPoints; - uint16_t FanMaximumRpm; uint16_t FanMinimumPwm; - uint16_t FanAcousticLimitRpm; + uint16_t AcousticTargetRpmThreshold; + uint16_t AcousticLimitRpmThreshold; uint16_t FanTargetTemperature; // Degree Celcius uint8_t FanZeroRpmEnable; uint8_t FanZeroRpmStopTemp; uint8_t FanMode; - uint8_t Padding[1]; + uint8_t MaxOpTemp; + uint8_t Padding[4]; - - uint32_t Spare[13]; + uint32_t Spare[12]; } OverDriveLimits_t; @@ -1018,7 +1036,8 @@ typedef struct { uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms - uint32_t SpareVmin[12]; + QuadraticInt_t Vmin_droop; + uint32_t SpareVmin[9]; //SECTION: DPM Configuration 1 @@ -1307,7 +1326,6 @@ typedef struct { uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS - // SECTION: Board Reserved uint32_t BoardSpare[64]; @@ -1382,8 +1400,14 @@ typedef struct { uint16_t AverageDclk0Frequency ; uint16_t AverageVclk1Frequency ; uint16_t AverageDclk1Frequency ; + uint16_t PCIeBusy ; + uint16_t dGPU_W_MAX ; + uint16_t padding ; + + uint32_t MetricsCounter ; uint16_t AvgVoltage[SVI_PLANE_COUNT]; + uint16_t AvgCurrent[SVI_PLANE_COUNT]; uint16_t AverageGfxActivity ; uint16_t AverageUclkActivity ; @@ -1415,11 +1439,13 @@ typedef struct { uint16_t AverageUclkActivity_MAX; + uint32_t PublicSerialNumberLower; + uint32_t PublicSerialNumberUpper; } SmuMetrics_t; typedef struct { SmuMetrics_t SmuMetrics; - uint32_t Spare[32]; + uint32_t Spare[30]; // Padding - ignore uint32_t MmHubPadding[8]; // SMU internal use diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h index a11d36db1b8a..e3454a876cac 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h @@ -31,7 +31,7 @@ #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x04 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x29 -#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x28 +#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x2A #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms -- cgit v1.2.3 From 5d6ec040ab44d23953a2efebfe02e41337952be7 Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Wed, 8 Jun 2022 16:59:52 +0800 Subject: drm/amd/pm: enable gfxoff on smu_v13_0_7 enable gfxoff on smu_v13_0_7 Signed-off-by: Kenneth Feng Reviewed-by: Yang Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index dc614befcdf5..b635c2b4f81c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -249,6 +249,9 @@ smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu, *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); } + if (adev->pm.pp_feature & PP_GFXOFF_MASK) + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); + if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) { *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT); *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT); -- cgit v1.2.3 From 7fc83cd079bba8b96b0f46e31f26c8f31c814146 Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Wed, 1 Jun 2022 09:20:28 +0800 Subject: drm/amd/pm: support BAMACO reset on smu_v13_0_7 support BAMACO reset on smu_v13_0_7, take BAMACO as a subset of BACO for the low latency, and it only happens on specific platforms. Signed-off-by: Kenneth Feng Reviewed-by: Yang Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 1 + .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 57 +++++++++++++++++++++- 2 files changed, 56 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 6d51e4340aad..b81c657c7386 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -432,6 +432,7 @@ struct smu_baco_context { uint32_t state; bool platform_support; + bool maco_support; }; struct smu_freq_info { diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index b635c2b4f81c..a92ab3266091 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -303,6 +303,8 @@ static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu) struct smu_13_0_7_powerplay_table *powerplay_table = table_context->power_play_table; struct smu_baco_context *smu_baco = &smu->smu_baco; + PPTable_t *smc_pptable = table_context->driver_pptable; + BoardTable_t *BoardTable = &smc_pptable->BoardTable; if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC) smu->dc_controlled_by_gpio = true; @@ -311,6 +313,9 @@ static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu) powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO) smu_baco->platform_support = true; + if (smu_baco->platform_support && (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled)) + smu_baco->maco_support = true; + table_context->thermal_controller_type = powerplay_table->thermal_controller_type; @@ -1537,6 +1542,54 @@ static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp return ret; } +static int smu_v13_0_7_baco_set_state(struct smu_context *smu, + enum smu_baco_state state) +{ + struct smu_baco_context *smu_baco = &smu->smu_baco; + struct amdgpu_device *adev = smu->adev; + bool is_maco_support = smu_baco->maco_support; + int ret; + + if (smu_v13_0_baco_get_state(smu) == state) + return 0; + + if (state == SMU_BACO_STATE_ENTER) { + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_EnterBaco, + (is_maco_support ? 2 : 0), + NULL); + } else { + ret = smu_cmn_send_smc_msg(smu, + SMU_MSG_ExitBaco, + NULL); + if (ret) + return ret; + + /* clear vbios scratch 6 and 7 for coming asic reinit */ + WREG32(adev->bios_scratch_reg_offset + 6, 0); + WREG32(adev->bios_scratch_reg_offset + 7, 0); + } + + if (!ret) + smu_baco->state = state; + + return ret; +} + +static int smu_v13_0_7_baco_enter(struct smu_context *smu) +{ + int ret = 0; + + ret = smu_v13_0_7_baco_set_state(smu, + SMU_BACO_STATE_ENTER); + if (ret) + return ret; + + msleep(10); + + return ret; +} + static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { .get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask, .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table, @@ -1591,8 +1644,8 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, .baco_is_support = smu_v13_0_baco_is_support, .baco_get_state = smu_v13_0_baco_get_state, - .baco_set_state = smu_v13_0_baco_set_state, - .baco_enter = smu_v13_0_baco_enter, + .baco_set_state = smu_v13_0_7_baco_set_state, + .baco_enter = smu_v13_0_7_baco_enter, .baco_exit = smu_v13_0_baco_exit, }; -- cgit v1.2.3 From 72aeb6ee0c78fafc476c02d1b19b5b38defcb57f Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Thu, 9 Jun 2022 19:20:47 +0800 Subject: drm/amd/pm: fix driver reload SMC firmware fail issue for smu13 issue calltrace: [ 402.773695] [drm] failed to load ucode SMC(0x2C) [ 402.773754] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0x0) [ 402.773762] [drm:psp_load_smu_fw [amdgpu]] *ERROR* PSP load smu failed! [ 402.966758] [drm:psp_v13_0_ring_destroy [amdgpu]] *ERROR* Fail to stop psp ring [ 402.966949] [drm:psp_hw_init [amdgpu]] *ERROR* PSP firmware loading failed [ 402.967116] [drm:amdgpu_device_fw_loading [amdgpu]] *ERROR* hw_init of IP block failed -22 [ 402.967252] amdgpu 0000:03:00.0: amdgpu: amdgpu_device_ip_init failed [ 402.967255] amdgpu 0000:03:00.0: amdgpu: Fatal error during GPU init if not reset mp1 state during kernel driver unload, it will cause psp load pmfw fail at the second time. add PPSMC_MSG_PrepareMp1ForUnload support for smu_v13_0_0/smu_v13_0_7 Signed-off-by: Yang Wang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 7 +++++++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 2 ++ 3 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index f57710790b8c..3d269d1c2749 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -66,6 +66,7 @@ static int smu_set_fan_control_mode(void *handle, u32 value); static int smu_set_power_limit(void *handle, uint32_t limit); static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); +static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); static int smu_sys_get_pp_feature_mask(void *handle, char *buf) @@ -1414,6 +1415,12 @@ static int smu_disable_dpms(struct smu_context *smu) switch (adev->ip_versions[MP1_HWIP][0]) { case IP_VERSION(13, 0, 0): case IP_VERSION(13, 0, 7): + ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); + if (ret) { + dev_err(adev->dev, "Fail set mp1 state to UNLOAD!\n"); + return ret; + } + return 0; default: break; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index 26fb72a588e7..fda89e309b07 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -118,6 +118,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0), + MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), }; static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = { @@ -1662,6 +1663,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { .baco_exit = smu_v13_0_baco_exit, .mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported, .mode1_reset = smu_v13_0_mode1_reset, + .set_mp1_state = smu_cmn_set_mp1_state, }; void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index a92ab3266091..185058637f7d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -116,6 +116,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), + MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), }; static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = { @@ -1647,6 +1648,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { .baco_set_state = smu_v13_0_7_baco_set_state, .baco_enter = smu_v13_0_7_baco_enter, .baco_exit = smu_v13_0_baco_exit, + .set_mp1_state = smu_cmn_set_mp1_state, }; void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu) -- cgit v1.2.3 From 438eac25d033a1701d839bad16c6ad78f683a293 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 8 Jun 2022 18:29:33 +0800 Subject: drm/amdgpu/discovery: enable vcn/jpeg v4_0_2 Enable vcn/jpeg 4_0_2. Signed-off-by: Yifan Zhang Reviewed-by: Alex Deucher Reviewed-by: Tim Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 1369a1b74929..11bbd76c581c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1897,6 +1897,7 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); break; case IP_VERSION(4, 0, 0): + case IP_VERSION(4, 0, 2): case IP_VERSION(4, 0, 4): amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); -- cgit v1.2.3 From f2a5002541d0698509d4f3adfbfcc55a9c1e2dd1 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Thu, 9 Jun 2022 17:03:48 +0800 Subject: drm/amd: disable GPA mode in backdoor load GPA mode should be disabled in direct load. Signed-off-by: Yifan Zhang Reviewed-by: Tim Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 05359df6c354..942d41a65f2f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4563,6 +4563,9 @@ static int gfx_v11_0_hw_init(void *handle) if (adev->gfx.imu.funcs->start_imu) adev->gfx.imu.funcs->start_imu(adev); } + + /* disable gpa mode in backdoor loading */ + gfx_v11_0_disable_gpa_mode(adev); } } -- cgit v1.2.3 From 5089c4a8ebea3c3ad9eedf038dad7098ebc06131 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Tue, 7 Jun 2022 22:43:42 -0400 Subject: drm/amd/display: ignore modifiers when checking for format support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [Why&How] There are cases where swizzle modes are set but modifiers arent. For such a userspace, we need not check modifiers while checking compatibilty in the drm hook for checking plane format. Ignore checking modifiers but check the DCN generation for the supported swizzle mode. v2: squash in unused variable removal (Alex) Signed-off-by: Aurabindo Pillai Reviewed-by: Marek Olšák Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 53 ++++++++++++++++++++--- 1 file changed, 46 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e668bb1560da..4a90ee111aec 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4936,8 +4936,7 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane, { struct amdgpu_device *adev = drm_to_adev(plane->dev); const struct drm_format_info *info = drm_format_info(format); - int i; - + struct hw_asic_id asic_id = adev->dm.dc->ctx->asic_id; enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3; if (!info) @@ -4953,13 +4952,53 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane, return true; } - /* Check that the modifier is on the list of the plane's supported modifiers. */ - for (i = 0; i < plane->modifier_count; i++) { - if (modifier == plane->modifiers[i]) + /* check if swizzle mode is supported by this version of DCN */ + switch (asic_id.chip_family) { + case FAMILY_SI: + case FAMILY_CI: + case FAMILY_KV: + case FAMILY_CZ: + case FAMILY_VI: + /* asics before AI does not have modifier support */ + return false; + break; + case FAMILY_AI: + case FAMILY_RV: + case FAMILY_NV: + case FAMILY_VGH: + case FAMILY_YELLOW_CARP: + case AMDGPU_FAMILY_GC_10_3_6: + case AMDGPU_FAMILY_GC_10_3_7: + switch (AMD_FMT_MOD_GET(TILE, modifier)) { + case AMD_FMT_MOD_TILE_GFX9_64K_R_X: + case AMD_FMT_MOD_TILE_GFX9_64K_D_X: + case AMD_FMT_MOD_TILE_GFX9_64K_S_X: + case AMD_FMT_MOD_TILE_GFX9_64K_D: + return true; + break; + default: + return false; + break; + } + break; + case AMDGPU_FAMILY_GC_11_0_0: + switch (AMD_FMT_MOD_GET(TILE, modifier)) { + case AMD_FMT_MOD_TILE_GFX11_256K_R_X: + case AMD_FMT_MOD_TILE_GFX9_64K_R_X: + case AMD_FMT_MOD_TILE_GFX9_64K_D_X: + case AMD_FMT_MOD_TILE_GFX9_64K_S_X: + case AMD_FMT_MOD_TILE_GFX9_64K_D: + return true; + break; + default: + return false; + break; + } + break; + default: + ASSERT(0); /* Unknown asic */ break; } - if (i == plane->modifier_count) - return false; /* * For D swizzle the canonical modifier depends on the bpp, so check -- cgit v1.2.3 From d52ea3dc65a9d504afa7a03ff24e17866670bdac Mon Sep 17 00:00:00 2001 From: Tim Huang Date: Wed, 1 Jun 2022 18:12:08 +0800 Subject: drm/amdgpu/pm: correct the firmware flag address for SMU IP v13.0.4 For SMU IP v13.0.4, the smnMP1_FIRMWARE_FLAGS address is different, we need this to correct the reading address. Signed-off-by: Tim Huang Reviewed-by: Yifan Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 1 + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 12 ++++++++++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h index e3454a876cac..43de0a8d4bd9 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h @@ -43,6 +43,7 @@ /* address block */ #define smnMP1_FIRMWARE_FLAGS 0x3010024 +#define smnMP1_V13_0_4_FIRMWARE_FLAGS 0x3010028 #define smnMP0_FW_INTF 0x30101c0 #define smnMP1_PUB_CTRL 0x3010b14 diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index f9c36d294448..fba0b87d01fb 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -273,8 +273,16 @@ int smu_v13_0_check_fw_status(struct smu_context *smu) struct amdgpu_device *adev = smu->adev; uint32_t mp1_fw_flags; - mp1_fw_flags = RREG32_PCIE(MP1_Public | - (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); + switch (adev->ip_versions[MP1_HWIP][0]) { + case IP_VERSION(13, 0, 4): + mp1_fw_flags = RREG32_PCIE(MP1_Public | + (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff)); + break; + default: + mp1_fw_flags = RREG32_PCIE(MP1_Public | + (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); + break; + } if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) -- cgit v1.2.3 From 526e6ca5d1d5fd22c79033cf5a8eb07d98a11274 Mon Sep 17 00:00:00 2001 From: Tim Huang Date: Mon, 6 Jun 2022 16:27:06 +0800 Subject: drm/amdgpu/pm: remove the repeated EnableGfxImu message sending The EnableGfxImu message will be issued in the set_gfx_power_up_by_imu. Signed-off-by: Tim Huang Reviewed-by: Yifan Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c index 196670345552..82d3718d8324 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c @@ -219,15 +219,10 @@ static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en) { struct amdgpu_device *adev = smu->adev; int ret = 0; - /* SMU fw need this message to trigger IMU to complete the initialization */ - if (en) - ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxImu, NULL); - else { - if (!adev->in_s0ix) - ret = smu_cmn_send_smc_msg(smu, - SMU_MSG_PrepareMp1ForUnload, - NULL); - } + + if (!en && !adev->in_s0ix) + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL); + return ret; } -- cgit v1.2.3 From ea937ad6e925994b94d17555e4c2f2f9a99234e1 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Fri, 10 Jun 2022 15:54:26 +0200 Subject: drm/amdgpu: Fix GTT size reporting in amdgpu_ioctl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The commit below changed the TTM manager size unit from pages to bytes, but failed to adjust the corresponding calculations in amdgpu_ioctl. Fixes: dfa714b88eb0 ("drm/amdgpu: remove GTT accounting v2") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1930 Bug: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6642 Tested-by: Martin Roukala Tested-by: Mike Lothian Reviewed-by: Christian König Signed-off-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 801f6fa692e9..6de63ea6687e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -642,7 +642,6 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) atomic64_read(&adev->visible_pin_size), vram_gtt.vram_size); vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; - vram_gtt.gtt_size *= PAGE_SIZE; vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); return copy_to_user(out, &vram_gtt, min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; @@ -675,7 +674,6 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) mem.cpu_accessible_vram.usable_heap_size * 3 / 4; mem.gtt.total_heap_size = gtt_man->size; - mem.gtt.total_heap_size *= PAGE_SIZE; mem.gtt.usable_heap_size = mem.gtt.total_heap_size - atomic64_read(&adev->gart_pin_size); mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); -- cgit v1.2.3 From 1f474c8742fd53a048cc8cc4b20e20b2614397eb Mon Sep 17 00:00:00 2001 From: Leo Li Date: Wed, 8 Jun 2022 12:17:44 -0400 Subject: drm/amd/display: Use pre-allocated temp struct for bounding box update [Why] There is a theoretical problem in prior patches for reducing the stack size of *update_bw_bounding_box() functions. By modifying the soc.clock_limits[n] struct directly, this can cause unintended behavior as the for loop attempts to swap rows in clock_limits[n]. A temporary struct is still required to make sure we stay functinoally equivalent. [How] Add a temporary clock_limits table to the SOC struct, and use it when swapping rows. Signed-off-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 33 ++++++----- .../gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c | 36 +++++++----- .../gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 64 +++++++++++++--------- .../drm/amd/display/dc/dml/display_mode_structs.h | 5 ++ 4 files changed, 82 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index c2fec0d85da4..e247b2270b1d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -2015,9 +2015,8 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params ASSERT(clk_table->num_entries); /* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */ - for (i = 0; i < dcn2_1_soc.num_states + 1; i++) { - dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i]; - } + memcpy(&dcn2_1_soc._clock_tmp, &dcn2_1_soc.clock_limits, + sizeof(dcn2_1_soc.clock_limits)); for (i = 0; i < clk_table->num_entries; i++) { /* loop backwards*/ @@ -2032,22 +2031,26 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params if (i == 1) k++; - dcn2_1_soc.clock_limits[k].state = k; - dcn2_1_soc.clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; - dcn2_1_soc.clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz; - dcn2_1_soc.clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz; - dcn2_1_soc.clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; + dcn2_1_soc._clock_tmp[k].state = k; + dcn2_1_soc._clock_tmp[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; + dcn2_1_soc._clock_tmp[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz; + dcn2_1_soc._clock_tmp[k].socclk_mhz = clk_table->entries[i].socclk_mhz; + dcn2_1_soc._clock_tmp[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; - dcn2_1_soc.clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; - dcn2_1_soc.clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; - dcn2_1_soc.clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; - dcn2_1_soc.clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; - dcn2_1_soc.clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; - dcn2_1_soc.clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; - dcn2_1_soc.clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; + dcn2_1_soc._clock_tmp[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; + dcn2_1_soc._clock_tmp[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; + dcn2_1_soc._clock_tmp[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; + dcn2_1_soc._clock_tmp[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; + dcn2_1_soc._clock_tmp[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; + dcn2_1_soc._clock_tmp[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; + dcn2_1_soc._clock_tmp[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; k++; } + + memcpy(&dcn2_1_soc.clock_limits, &dcn2_1_soc._clock_tmp, + sizeof(dcn2_1_soc.clock_limits)); + if (clk_table->num_entries) { dcn2_1_soc.num_states = clk_table->num_entries + 1; /* fill in min DF PState */ diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c index 62cf283d9f41..e4863f0bf0f6 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c @@ -254,6 +254,9 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param dc_assert_fp_enabled(); + memcpy(&dcn3_01_soc._clock_tmp, &dcn3_01_soc.clock_limits, + sizeof(dcn3_01_soc.clock_limits)); + /* Default clock levels are used for diags, which may lead to overclocking. */ if (!IS_DIAG_DC(dc->ctx->dce_environment)) { dcn3_01_ip.max_num_otg = pool->base.res_cap->num_timing_generator; @@ -270,29 +273,32 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param } } - dcn3_01_soc.clock_limits[i].state = i; - dcn3_01_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; - dcn3_01_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; - dcn3_01_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; - dcn3_01_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; - - dcn3_01_soc.clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz; - dcn3_01_soc.clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz; - dcn3_01_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; - dcn3_01_soc.clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz; - dcn3_01_soc.clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; - dcn3_01_soc.clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; - dcn3_01_soc.clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz; + dcn3_01_soc._clock_tmp[i].state = i; + dcn3_01_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; + dcn3_01_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; + dcn3_01_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz; + dcn3_01_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; + + dcn3_01_soc._clock_tmp[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz; + dcn3_01_soc._clock_tmp[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz; + dcn3_01_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; + dcn3_01_soc._clock_tmp[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz; + dcn3_01_soc._clock_tmp[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; + dcn3_01_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; + dcn3_01_soc._clock_tmp[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz; } if (clk_table->num_entries) { dcn3_01_soc.num_states = clk_table->num_entries; /* duplicate last level */ - dcn3_01_soc.clock_limits[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1]; - dcn3_01_soc.clock_limits[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states; + dcn3_01_soc._clock_tmp[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1]; + dcn3_01_soc._clock_tmp[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states; } } + memcpy(&dcn3_01_soc.clock_limits, &dcn3_01_soc._clock_tmp, + sizeof(dcn3_01_soc.clock_limits)); + dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c index 6da702923226..7be3476989ce 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c @@ -580,6 +580,9 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params dc_assert_fp_enabled(); + memcpy(&dcn3_1_soc._clock_tmp, &dcn3_1_soc.clock_limits, + sizeof(dcn3_1_soc.clock_limits)); + // Default clock levels are used for diags, which may lead to overclocking. if (!IS_DIAG_DC(dc->ctx->dce_environment)) { int max_dispclk_mhz = 0, max_dppclk_mhz = 0; @@ -607,32 +610,35 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params } } - dcn3_1_soc.clock_limits[i].state = i; + dcn3_1_soc._clock_tmp[i].state = i; /* Clocks dependent on voltage level. */ - dcn3_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; - dcn3_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; - dcn3_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; - dcn3_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; + dcn3_1_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; + dcn3_1_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; + dcn3_1_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz; + dcn3_1_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; /* Clocks independent of voltage level. */ - dcn3_1_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : + dcn3_1_soc._clock_tmp[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; - dcn3_1_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : + dcn3_1_soc._clock_tmp[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; - dcn3_1_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; - dcn3_1_soc.clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; - dcn3_1_soc.clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; - dcn3_1_soc.clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; - dcn3_1_soc.clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; + dcn3_1_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; + dcn3_1_soc._clock_tmp[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; + dcn3_1_soc._clock_tmp[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; + dcn3_1_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; + dcn3_1_soc._clock_tmp[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; } if (clk_table->num_entries) { dcn3_1_soc.num_states = clk_table->num_entries; } } + memcpy(&dcn3_1_soc.clock_limits, &dcn3_1_soc._clock_tmp, + sizeof(dcn3_1_soc.clock_limits)); + dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; @@ -705,6 +711,9 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param dc_assert_fp_enabled(); + memcpy(&dcn3_16_soc._clock_tmp, &dcn3_16_soc.clock_limits, + sizeof(dcn3_16_soc.clock_limits)); + // Default clock levels are used for diags, which may lead to overclocking. if (!IS_DIAG_DC(dc->ctx->dce_environment)) { @@ -736,37 +745,40 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param closest_clk_lvl = dcn3_16_soc.num_states - 1; } - dcn3_16_soc.clock_limits[i].state = i; + dcn3_16_soc._clock_tmp[i].state = i; /* Clocks dependent on voltage level. */ - dcn3_16_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; + dcn3_16_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; if (clk_table->num_entries == 1 && - dcn3_16_soc.clock_limits[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { + dcn3_16_soc._clock_tmp[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { /*SMU fix not released yet*/ - dcn3_16_soc.clock_limits[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; + dcn3_16_soc._clock_tmp[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; } - dcn3_16_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; - dcn3_16_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; - dcn3_16_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; + dcn3_16_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; + dcn3_16_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz; + dcn3_16_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; /* Clocks independent of voltage level. */ - dcn3_16_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : + dcn3_16_soc._clock_tmp[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : dcn3_16_soc.clock_limits[closest_clk_lvl].dispclk_mhz; - dcn3_16_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : + dcn3_16_soc._clock_tmp[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : dcn3_16_soc.clock_limits[closest_clk_lvl].dppclk_mhz; - dcn3_16_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; - dcn3_16_soc.clock_limits[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz; - dcn3_16_soc.clock_limits[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; - dcn3_16_soc.clock_limits[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; - dcn3_16_soc.clock_limits[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz; + dcn3_16_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; + dcn3_16_soc._clock_tmp[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz; + dcn3_16_soc._clock_tmp[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; + dcn3_16_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; + dcn3_16_soc._clock_tmp[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz; } if (clk_table->num_entries) { dcn3_16_soc.num_states = clk_table->num_entries; } } + memcpy(&dcn3_16_soc.clock_limits, &dcn3_16_soc._clock_tmp, + sizeof(dcn3_16_soc.clock_limits)); + if (max_dispclk_mhz) { dcn3_16_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h index 74afa10e70f8..2bdf60846762 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h @@ -161,6 +161,11 @@ struct _vcs_dpi_voltage_scaling_st { struct _vcs_dpi_soc_bounding_box_st { struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; + /* + * This is a temporary stash for updating @clock_limits with the PMFW + * clock table. Do not use outside of *update_bw_boudning_box functions. + */ + struct _vcs_dpi_voltage_scaling_st _clock_tmp[DC__VOLTAGE_STATES]; unsigned int num_states; double sr_exit_time_us; double sr_enter_plus_exit_time_us; -- cgit v1.2.3 From d6aa8424bcac64b2608452589c9a09984251c01c Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Fri, 10 Jun 2022 13:13:31 -0400 Subject: drm/amd/display: dml: move some variables to heap [Why&How] To reduce stack usage, move some variables into heap in the DML function dml32_ModeSupportAndSystemConfigurationFull() Fixes: dda4fb85e433 ("drm/amd/display: DML changes for DCN32/321") Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 17 +++++++---------- drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 3 +++ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index 5828e60f291d..b9f5bfa67791 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -1675,9 +1675,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l bool FullFrameMALLPStateMethod; bool SubViewportMALLPStateMethod; bool PhantomPipeMALLPStateMethod; - double MaxTotalVActiveRDBandwidth; - double DSTYAfterScaler[DC__NUM_DPP__MAX]; - double DSTXAfterScaler[DC__NUM_DPP__MAX]; unsigned int MaximumMPCCombine; #ifdef __DML_VBA_DEBUG__ @@ -3095,10 +3092,10 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } //Vertical Active BW support check - MaxTotalVActiveRDBandwidth = 0; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaxTotalVActiveRDBandwidth = 0; for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { - MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + mode_lib->vba.ReadBandwidthLuma[k] + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaxTotalVActiveRDBandwidth += mode_lib->vba.ReadBandwidthLuma[k] + mode_lib->vba.ReadBandwidthChroma[k]; } @@ -3115,7 +3112,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l * mode_lib->vba.DRAMChannelWidth * (i < 2 ? mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE : mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation) / 100); - if (MaxTotalVActiveRDBandwidth + if (v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaxTotalVActiveRDBandwidth <= mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i][j]) { mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][j] = true; } else { @@ -3281,8 +3278,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.SwathHeightCThisState[k], mode_lib->vba.TWait, /* Output */ - &DSTXAfterScaler[k], - &DSTYAfterScaler[k], + &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k], + &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTYAfterScaler[k], &mode_lib->vba.LineTimesForPrefetch[k], &mode_lib->vba.PrefetchBW[k], &mode_lib->vba.LinesForMetaPTE[k], @@ -3579,8 +3576,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.NoOfDPPThisState, mode_lib->vba.BytePerPixelInDETY, mode_lib->vba.BytePerPixelInDETC, - DSTXAfterScaler, - DSTYAfterScaler, + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler, + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTYAfterScaler, mode_lib->vba.WritebackEnable, mode_lib->vba.WritebackPixelFormat, mode_lib->vba.WritebackDestinationWidth, diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 43e327080552..9ad49ad38814 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -204,6 +204,9 @@ struct dml32_ModeSupportAndSystemConfigurationFull { SOCParametersList mSOCParameters; unsigned int MaximumSwathWidthSupportLuma; unsigned int MaximumSwathWidthSupportChroma; + double DSTYAfterScaler[DC__NUM_DPP__MAX]; + double DSTXAfterScaler[DC__NUM_DPP__MAX]; + double MaxTotalVActiveRDBandwidth; }; struct dummy_vars { -- cgit v1.2.3 From d11737f26ffeae88350b835caa37c7449da22550 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Mon, 6 Jun 2022 11:21:07 +0800 Subject: drm/amd/pm: enable UCLK DS feature for SMU 13.0.0 The feature is ready with latest PMFW and IFWI. Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index fda89e309b07..495713e4ebd4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -306,6 +306,8 @@ smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu, *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT); + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_UCLK_BIT); + return 0; } -- cgit v1.2.3 From 272308add589bd46ddb5899685e25fc9f6a58b1e Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Tue, 7 Jun 2022 14:40:24 +0800 Subject: drm/amd/pm: enable MACO support for SMU 13.0.0 Enable BAMACO reset support for SMU 13.0.0. Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 +- .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 3 ++ .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 52 +--------------------- 3 files changed, 7 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index fba0b87d01fb..f18f9605e586 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -2271,7 +2271,8 @@ int smu_v13_0_baco_set_state(struct smu_context *smu, if (state == SMU_BACO_STATE_ENTER) { ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, - 0, + smu_baco->maco_support ? + BACO_SEQ_BAMACO : BACO_SEQ_BACO, NULL); } else { ret = smu_cmn_send_smc_msg(smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index 495713e4ebd4..6fb2b072a730 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -325,6 +325,9 @@ static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu) powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) smu_baco->platform_support = true; + if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) + smu_baco->maco_support = true; + table_context->thermal_controller_type = powerplay_table->thermal_controller_type; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index 185058637f7d..193222fdd1c4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -1543,54 +1543,6 @@ static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp return ret; } -static int smu_v13_0_7_baco_set_state(struct smu_context *smu, - enum smu_baco_state state) -{ - struct smu_baco_context *smu_baco = &smu->smu_baco; - struct amdgpu_device *adev = smu->adev; - bool is_maco_support = smu_baco->maco_support; - int ret; - - if (smu_v13_0_baco_get_state(smu) == state) - return 0; - - if (state == SMU_BACO_STATE_ENTER) { - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_EnterBaco, - (is_maco_support ? 2 : 0), - NULL); - } else { - ret = smu_cmn_send_smc_msg(smu, - SMU_MSG_ExitBaco, - NULL); - if (ret) - return ret; - - /* clear vbios scratch 6 and 7 for coming asic reinit */ - WREG32(adev->bios_scratch_reg_offset + 6, 0); - WREG32(adev->bios_scratch_reg_offset + 7, 0); - } - - if (!ret) - smu_baco->state = state; - - return ret; -} - -static int smu_v13_0_7_baco_enter(struct smu_context *smu) -{ - int ret = 0; - - ret = smu_v13_0_7_baco_set_state(smu, - SMU_BACO_STATE_ENTER); - if (ret) - return ret; - - msleep(10); - - return ret; -} - static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { .get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask, .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table, @@ -1645,8 +1597,8 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, .baco_is_support = smu_v13_0_baco_is_support, .baco_get_state = smu_v13_0_baco_get_state, - .baco_set_state = smu_v13_0_7_baco_set_state, - .baco_enter = smu_v13_0_7_baco_enter, + .baco_set_state = smu_v13_0_baco_set_state, + .baco_enter = smu_v13_0_baco_enter, .baco_exit = smu_v13_0_baco_exit, .set_mp1_state = smu_cmn_set_mp1_state, }; -- cgit v1.2.3 From 1a65327a84db5b9081a51ccb1c562083f59bfcec Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Mon, 13 Jun 2022 14:52:54 +0800 Subject: Revert "drm/amdgpu/gmc11: enable AGP aperture" This reverts commit 2cfe34e18970d26bff73c63f16c76dae22138d19. Enable AGP aperture cause SDMA page fault for gfx11.0.2, so temp disable AGP aperture until SDMA FW resolved this. Reviewed-by: Hawking Zhang Signed-off-by: Jack Gui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c | 7 +++---- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 1 - drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c | 6 +++--- 4 files changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c index f99d7641bb21..5eccaa2c7ca0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c @@ -154,11 +154,10 @@ static void gfxhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev) { uint64_t value; - /* Program the AGP BAR */ + /* Disable AGP. */ WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); - WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); - WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); - + WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, 0); + WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, 0x00FFFFFF); /* Program the system aperture low logical page number. */ WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 454a25cc0046..9c225553f5b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -611,7 +611,6 @@ static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, amdgpu_gmc_vram_location(adev, &adev->gmc, base); amdgpu_gmc_gart_location(adev, mc); - amdgpu_gmc_agp_location(adev, mc); /* base offset of vram pages */ adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c index 4926fa82c1c4..bc11b2de37ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c @@ -169,10 +169,10 @@ static void mmhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev) uint64_t value; uint32_t tmp; - /* Program the AGP BAR */ + /* Disable AGP. */ WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); - WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); - WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); + WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0); + WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF); if (!amdgpu_sriov_vf(adev)) { /* diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c index 5e5b884d8357..770be0a8f7ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c @@ -162,10 +162,10 @@ static void mmhub_v3_0_2_init_system_aperture_regs(struct amdgpu_device *adev) uint64_t value; uint32_t tmp; - /* Program the AGP BAR */ + /* Disable AGP. */ WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); - WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); - WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); + WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0); + WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF); if (!amdgpu_sriov_vf(adev)) { /* -- cgit v1.2.3 From 9731dd4cadc53251ef80b3655c8d841fed52fa3d Mon Sep 17 00:00:00 2001 From: Daniel Phillips Date: Mon, 30 May 2022 11:21:22 -0400 Subject: drm/amdkfd: Add available memory ioctl Add a new KFD ioctl to return the largest possible memory size that can be allocated as a buffer object using kfd_ioctl_alloc_memory_of_gpu. It attempts to use exactly the same accept/reject criteria as that function so that allocating a new buffer object of the size returned by this new ioctl is guaranteed to succeed, barring races with other allocating tasks. This IOCTL will be used by libhsakmt: https://www.mail-archive.com/amd-gfx@lists.freedesktop.org/msg75743.html Signed-off-by: Daniel Phillips Signed-off-by: David Yat Sin Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 38 +++++++++++++++++++++--- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 34 +++++++++++++++++++++ include/uapi/linux/kfd_ioctl.h | 14 +++++++-- 4 files changed, 81 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index ffb2b7d9b9a5..648c031942e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -268,6 +268,7 @@ int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev, void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev, void *drm_priv); uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv); +size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev); int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( struct amdgpu_device *adev, uint64_t va, uint64_t size, void *drm_priv, struct kgd_mem **mem, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index f386b0d256d2..8805bd1eed37 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -38,6 +38,12 @@ */ #define AMDGPU_USERPTR_RESTORE_DELAY_MS 1 +/* + * Align VRAM allocations to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB + * BO chunk + */ +#define VRAM_ALLOCATION_ALIGN (1 << 21) + /* Impose limit on how much memory KFD can use */ static struct { uint64_t max_system_mem_limit; @@ -108,7 +114,7 @@ void amdgpu_amdkfd_reserve_system_mem(uint64_t size) * compromise that should work in most cases without reserving too * much memory for page tables unnecessarily (factor 16K, >> 14). */ -#define ESTIMATE_PT_SIZE(mem_size) ((mem_size) >> 14) +#define ESTIMATE_PT_SIZE(mem_size) max(((mem_size) >> 14), AMDGPU_VM_RESERVED_VRAM) static size_t amdgpu_amdkfd_acc_size(uint64_t size) { @@ -148,7 +154,13 @@ static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { system_mem_needed = acc_size; ttm_mem_needed = acc_size; - vram_needed = size; + + /* + * Conservatively round up the allocation requirement to 2 MB + * to avoid fragmentation caused by 4K allocations in the tail + * 2M BO chunk. + */ + vram_needed = ALIGN(size, VRAM_ALLOCATION_ALIGN); } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { system_mem_needed = acc_size + size; ttm_mem_needed = acc_size; @@ -173,7 +185,9 @@ static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, (kfd_mem_limit.ttm_mem_used + ttm_mem_needed > kfd_mem_limit.max_ttm_mem_limit) || (adev->kfd.vram_used + vram_needed > - adev->gmc.real_vram_size - reserved_for_pt)) { + adev->gmc.real_vram_size - + atomic64_read(&adev->vram_pin_size) - + reserved_for_pt)) { ret = -ENOMEM; goto release; } @@ -205,7 +219,7 @@ static void unreserve_mem_limit(struct amdgpu_device *adev, } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { kfd_mem_limit.system_mem_used -= acc_size; kfd_mem_limit.ttm_mem_used -= acc_size; - adev->kfd.vram_used -= size; + adev->kfd.vram_used -= ALIGN(size, VRAM_ALLOCATION_ALIGN); } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { kfd_mem_limit.system_mem_used -= (acc_size + size); kfd_mem_limit.ttm_mem_used -= acc_size; @@ -1633,6 +1647,22 @@ out_unlock: return ret; } +size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev) +{ + uint64_t reserved_for_pt = + ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size); + size_t available; + + spin_lock(&kfd_mem_limit.mem_limit_lock); + available = adev->gmc.real_vram_size + - adev->kfd.vram_used + - atomic64_read(&adev->vram_pin_size) + - reserved_for_pt; + spin_unlock(&kfd_mem_limit.mem_limit_lock); + + return ALIGN_DOWN(available, VRAM_ALLOCATION_ALIGN); +} + int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( struct amdgpu_device *adev, uint64_t va, uint64_t size, void *drm_priv, struct kgd_mem **mem, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 1c7016958d6d..3bcf9bf29acb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -65,6 +65,25 @@ static int kfd_char_dev_major = -1; static struct class *kfd_class; struct device *kfd_device; +static inline struct kfd_process_device *kfd_lock_pdd_by_id(struct kfd_process *p, __u32 gpu_id) +{ + struct kfd_process_device *pdd; + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, gpu_id); + + if (pdd) + return pdd; + + mutex_unlock(&p->mutex); + return NULL; +} + +static inline void kfd_unlock_pdd(struct kfd_process_device *pdd) +{ + mutex_unlock(&pdd->process->mutex); +} + int kfd_chardev_init(void) { int err = 0; @@ -958,6 +977,19 @@ bool kfd_dev_is_large_bar(struct kfd_dev *dev) return false; } +static int kfd_ioctl_get_available_memory(struct file *filep, + struct kfd_process *p, void *data) +{ + struct kfd_ioctl_get_available_memory_args *args = data; + struct kfd_process_device *pdd = kfd_lock_pdd_by_id(p, args->gpu_id); + + if (!pdd) + return -EINVAL; + args->available = amdgpu_amdkfd_get_available_memory(pdd->dev->adev); + kfd_unlock_pdd(pdd); + return 0; +} + static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, struct kfd_process *p, void *data) { @@ -2648,6 +2680,8 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_CRIU_OP, kfd_ioctl_criu, KFD_IOC_FLAG_CHECKPOINT_RESTORE), + AMDKFD_IOCTL_DEF(AMDKFD_IOC_AVAILABLE_MEMORY, + kfd_ioctl_get_available_memory, 0), }; #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 42975e940758..231eb010b823 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -34,9 +34,10 @@ * - 1.6 - Query clear flags in SVM get_attr API * - 1.7 - Checkpoint Restore (CRIU) API * - 1.8 - CRIU - Support for SDMA transfers with GTT BOs + * - 1.9 - Add available memory ioctl */ #define KFD_IOCTL_MAJOR_VERSION 1 -#define KFD_IOCTL_MINOR_VERSION 8 +#define KFD_IOCTL_MINOR_VERSION 9 struct kfd_ioctl_get_version_args { __u32 major_version; /* from KFD */ @@ -100,6 +101,12 @@ struct kfd_ioctl_get_queue_wave_state_args { __u32 pad; }; +struct kfd_ioctl_get_available_memory_args { + __u64 available; /* from KFD */ + __u32 gpu_id; /* to KFD */ + __u32 pad; +}; + /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */ #define KFD_IOC_CACHE_POLICY_COHERENT 0 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1 @@ -826,7 +833,10 @@ struct kfd_ioctl_set_xnack_mode_args { #define AMDKFD_IOC_CRIU_OP \ AMDKFD_IOWR(0x22, struct kfd_ioctl_criu_args) +#define AMDKFD_IOC_AVAILABLE_MEMORY \ + AMDKFD_IOWR(0x23, struct kfd_ioctl_get_available_memory_args) + #define AMDKFD_COMMAND_START 0x01 -#define AMDKFD_COMMAND_END 0x23 +#define AMDKFD_COMMAND_END 0x24 #endif -- cgit v1.2.3 From c443514a7d6d648bc497efbe502e2a49738b94de Mon Sep 17 00:00:00 2001 From: Wenjing Liu Date: Thu, 26 May 2022 15:52:42 -0400 Subject: drm/amd/display: lower lane count first when CR done partially fails in EQ [why] According to DP specs, in EQ DONE phase of link training, we should lower lane count when at least one CR DONE bit is set to 1, while lower link rate when all CR DONE bits are 0s. However in our code, we will treat both cases as latter. This is not exactly correct based on the specs expectation. [how] Check lane0 CR DONE bit when it is still set but CR DONE fails, we treat it as a partial CR DONE failure in EQ DONE phase, we will follow the same fallback flow as when ED DONE fails in EQ DONE phase. Reviewed-by: George Shen Acked-by: Hamza Mahfooz Signed-off-by: Wenjing Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 13 +++++++------ drivers/gpu/drm/amd/display/include/link_service_types.h | 2 ++ 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index c1207049dbc5..f9c10d044da6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1326,7 +1326,9 @@ static enum link_training_result perform_channel_equalization_sequence( /* 5. check CR done*/ if (!dp_is_cr_done(lane_count, dpcd_lane_status)) - return LINK_TRAINING_EQ_FAIL_CR; + return dpcd_lane_status[0].bits.CR_DONE_0 ? + LINK_TRAINING_EQ_FAIL_CR_PARTIAL : + LINK_TRAINING_EQ_FAIL_CR; /* 6. check CHEQ done*/ if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && @@ -1882,6 +1884,9 @@ static void print_status_message( case LINK_TRAINING_EQ_FAIL_CR: lt_result = "CR failed in EQ"; break; + case LINK_TRAINING_EQ_FAIL_CR_PARTIAL: + lt_result = "CR failed in EQ partially"; + break; case LINK_TRAINING_EQ_FAIL_EQ: lt_result = "EQ failed"; break; @@ -3612,11 +3617,6 @@ static bool decide_fallback_link_setting( struct dc_link_settings *cur, enum link_training_result training_result) { - if (!cur) - return false; - if (!max) - return false; - if (dp_get_link_encoding_format(max) == DP_128b_132b_ENCODING || link->dc->debug.force_dp2_lt_fallback_method) return decide_fallback_link_setting_max_bw_policy(link, max, cur, @@ -3646,6 +3646,7 @@ static bool decide_fallback_link_setting( break; } case LINK_TRAINING_EQ_FAIL_EQ: + case LINK_TRAINING_EQ_FAIL_CR_PARTIAL: { if (!reached_minimum_lane_count(cur->lane_count)) { cur->lane_count = reduce_lane_count(cur->lane_count); diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h index 447a56286dd0..23f7d7354aaa 100644 --- a/drivers/gpu/drm/amd/display/include/link_service_types.h +++ b/drivers/gpu/drm/amd/display/include/link_service_types.h @@ -67,6 +67,8 @@ enum link_training_result { LINK_TRAINING_CR_FAIL_LANE23, /* CR DONE bit is cleared during EQ step */ LINK_TRAINING_EQ_FAIL_CR, + /* CR DONE bit is cleared but LANE0_CR_DONE is set during EQ step */ + LINK_TRAINING_EQ_FAIL_CR_PARTIAL, /* other failure during EQ step */ LINK_TRAINING_EQ_FAIL_EQ, LINK_TRAINING_LQA_FAIL, -- cgit v1.2.3 From b840b64bc8ed3fc46f6d6aa7f97c43862a33bea5 Mon Sep 17 00:00:00 2001 From: Shah Dharati Date: Tue, 31 May 2022 09:58:12 -0400 Subject: drm/amd/display: Fix monitor flash issue [Why & How] For a some specific monitors, when connected on boot or hot plug, monitor flash for 1/2 seconds can happen during first HDCP query operation. Ading some delay in the init sequence for these monitors fixes the issue, so it is implemented as monitor specific patch. Co-authored-by: Shah Dharati Reviewed-by: Hansen Dsouza Reviewed-by: Nicholas Kazlauskas Acked-by: Hamza Mahfooz Signed-off-by: Shah Dharati Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c index 1f4095b26409..c5f6c11de7e5 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c @@ -524,7 +524,7 @@ enum mod_hdcp_status mod_hdcp_hdcp2_dp_transition(struct mod_hdcp *hdcp, set_watchdog_in_ms(hdcp, 3000, output); set_state_id(hdcp, output, D2_A6_WAIT_FOR_RX_ID_LIST); } else { - callback_in_ms(0, output); + callback_in_ms(1, output); set_state_id(hdcp, output, D2_SEND_CONTENT_STREAM_TYPE); } break; -- cgit v1.2.3 From 71be4b16d39ac8b25a8a04eda66cb65581e1a03c Mon Sep 17 00:00:00 2001 From: hersen wu Date: Sun, 29 May 2022 10:54:30 -0400 Subject: drm/amd/display: dsc validate fail not pass to atomic check [Why] when 4k@144hz dp connect to dp1.4 dsc mst hub, requested bandwidth exceeds caps of dsc hub. but dsc bw valid functions, increase_dsc_bpp, try_disable_dsc, pre_validate_dsc, compute_mst_dsc_configs_for_state, do not return false to atomic check. this cause user mode initiate mode set to kernel, then cause kernel assert, system hang. [How] dsc bandwidth valid functions return pass or fail to atomic check. Reviewed-by: Wayne Lin Reviewed-by: Rodrigo Siqueira Acked-by: Hamza Mahfooz Signed-off-by: hersen wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 43 +++++++++++++++------- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.h | 2 +- 3 files changed, 35 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4a90ee111aec..60fb99b74713 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11255,7 +11255,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } } - pre_validate_dsc(state, &dm_state, vars); + if (!pre_validate_dsc(state, &dm_state, vars)) { + ret = -EINVAL; + goto fail; + } } #endif for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { @@ -11501,6 +11504,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, #if defined(CONFIG_DRM_AMD_DC_DCN) if (!compute_mst_dsc_configs_for_state(state, dm_state->context, vars)) { DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n"); + ret = -EINVAL; goto fail; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index a6d551ff89d1..7e246a798c8a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -670,7 +670,7 @@ static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn) return dsc_config.bits_per_pixel; } -static void increase_dsc_bpp(struct drm_atomic_state *state, +static bool increase_dsc_bpp(struct drm_atomic_state *state, struct dc_link *dc_link, struct dsc_mst_fairness_params *params, struct dsc_mst_fairness_vars *vars, @@ -730,7 +730,7 @@ static void increase_dsc_bpp(struct drm_atomic_state *state, params[next_index].port, vars[next_index].pbn, pbn_per_timeslot) < 0) - return; + return false; if (!drm_dp_mst_atomic_check(state)) { vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn); } else { @@ -740,7 +740,7 @@ static void increase_dsc_bpp(struct drm_atomic_state *state, params[next_index].port, vars[next_index].pbn, pbn_per_timeslot) < 0) - return; + return false; } } else { vars[next_index].pbn += initial_slack[next_index]; @@ -749,7 +749,7 @@ static void increase_dsc_bpp(struct drm_atomic_state *state, params[next_index].port, vars[next_index].pbn, pbn_per_timeslot) < 0) - return; + return false; if (!drm_dp_mst_atomic_check(state)) { vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16; } else { @@ -759,16 +759,17 @@ static void increase_dsc_bpp(struct drm_atomic_state *state, params[next_index].port, vars[next_index].pbn, pbn_per_timeslot) < 0) - return; + return false; } } bpp_increased[next_index] = true; remaining_to_increase--; } + return true; } -static void try_disable_dsc(struct drm_atomic_state *state, +static bool try_disable_dsc(struct drm_atomic_state *state, struct dc_link *dc_link, struct dsc_mst_fairness_params *params, struct dsc_mst_fairness_vars *vars, @@ -816,7 +817,7 @@ static void try_disable_dsc(struct drm_atomic_state *state, params[next_index].port, vars[next_index].pbn, dm_mst_get_pbn_divider(dc_link)) < 0) - return; + return false; if (!drm_dp_mst_atomic_check(state)) { vars[next_index].dsc_enabled = false; @@ -828,12 +829,13 @@ static void try_disable_dsc(struct drm_atomic_state *state, params[next_index].port, vars[next_index].pbn, dm_mst_get_pbn_divider(dc_link)) < 0) - return; + return false; } tried[next_index] = true; remaining_to_try--; } + return true; } static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, @@ -949,9 +951,11 @@ static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, return false; /* Optimize degree of compression */ - increase_dsc_bpp(state, dc_link, params, vars, count, k); + if (!increase_dsc_bpp(state, dc_link, params, vars, count, k)) + return false; - try_disable_dsc(state, dc_link, params, vars, count, k); + if (!try_disable_dsc(state, dc_link, params, vars, count, k)) + return false; set_dsc_configs_from_fairness_vars(params, vars, count, k); @@ -1223,21 +1227,22 @@ static bool is_dsc_precompute_needed(struct drm_atomic_state *state) return ret; } -void pre_validate_dsc(struct drm_atomic_state *state, +bool pre_validate_dsc(struct drm_atomic_state *state, struct dm_atomic_state **dm_state_ptr, struct dsc_mst_fairness_vars *vars) { int i; struct dm_atomic_state *dm_state; struct dc_state *local_dc_state = NULL; + int ret = 0; if (!is_dsc_precompute_needed(state)) { DRM_INFO_ONCE("DSC precompute is not needed.\n"); - return; + return true; } if (dm_atomic_get_state(state, dm_state_ptr)) { DRM_INFO_ONCE("dm_atomic_get_state() failed\n"); - return; + return false; } dm_state = *dm_state_ptr; @@ -1249,7 +1254,7 @@ void pre_validate_dsc(struct drm_atomic_state *state, local_dc_state = kmemdup(dm_state->context, sizeof(struct dc_state), GFP_KERNEL); if (!local_dc_state) - return; + return false; for (i = 0; i < local_dc_state->stream_count; i++) { struct dc_stream_state *stream = dm_state->context->streams[i]; @@ -1275,11 +1280,19 @@ void pre_validate_dsc(struct drm_atomic_state *state, &state->crtcs[ind].new_state->mode, dm_new_conn_state, dm_old_crtc_state->stream); + if (local_dc_state->streams[i] == NULL) { + ret = -EINVAL; + break; + } } } + if (ret != 0) + goto clean_exit; + if (!pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars)) { DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n"); + ret = -EINVAL; goto clean_exit; } @@ -1309,5 +1322,7 @@ clean_exit: } kfree(local_dc_state); + + return (ret == 0); } #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h index 85628ad59e6c..2e13027d9b88 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h @@ -59,7 +59,7 @@ bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, bool needs_dsc_aux_workaround(struct dc_link *link); -void pre_validate_dsc(struct drm_atomic_state *state, +bool pre_validate_dsc(struct drm_atomic_state *state, struct dm_atomic_state **dm_state_ptr, struct dsc_mst_fairness_vars *vars); -- cgit v1.2.3 From a141d2083b462505727e14d98db5fc3cd43d59c6 Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Fri, 3 Jun 2022 16:39:48 -0400 Subject: drm/amd/display: Add debug option for exiting idle optimizations on cursor updates [Description] - Have option to exit idle opt on cursor updates for debug and optimizations purposes Reviewed-by: Samson Tam Acked-by: Hamza Mahfooz Signed-off-by: Alvin Lee Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 5 +++-- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index de8b214132a2..167bb3310877 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -389,7 +389,7 @@ bool dc_stream_set_cursor_position( struct dc_stream_state *stream, const struct dc_cursor_position *position) { - struct dc *dc; + struct dc *dc = stream->ctx->dc; bool reset_idle_optimizations = false; if (NULL == stream) { @@ -406,7 +406,8 @@ bool dc_stream_set_cursor_position( dc_z10_restore(dc); /* disable idle optimizations if enabling cursor */ - if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) { + if (dc->idle_optimizations_allowed && (!stream->cursor_position.enable || dc->debug.exit_idle_opt_for_cursor_updates) + && position->enable) { dc_allow_idle_optimizations(dc, false); reset_idle_optimizations = true; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 76db013aac6e..7191fc48c2e7 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -748,6 +748,7 @@ struct dc_debug_options { uint8_t psr_power_use_phy_fsm; enum dml_hostvm_override_opts dml_hostvm_override; bool use_legacy_soc_bb_mechanism; + bool exit_idle_opt_for_cursor_updates; }; struct gpu_info_soc_bounding_box_v1_0; -- cgit v1.2.3 From f51d22b0d04aa33e94d663fb63aa61e4da168523 Mon Sep 17 00:00:00 2001 From: Qingqing Zhuo Date: Fri, 3 Jun 2022 14:44:58 -0400 Subject: drm/amd/display: update topology_update_input_v3 struct [Why] DIO parameters were missing in topology_update_intput_v3 struct. [How] Add DIO parameters in v3 struct and update in functions perspectively. Reviewed-by: Bhawanpreet Lakha Acked-by: Hamza Mahfooz Signed-off-by: Qingqing Zhuo Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 2 ++ drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 4 ++++ drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h | 11 +++++++++++ 3 files changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index 15c0e3f2a9c3..fcafe07ed908 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -476,6 +476,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1; display->stream_enc_idx = config->stream_enc_idx; link->link_enc_idx = config->link_enc_idx; + link->dio_output_id = config->dio_output_idx; link->phy_idx = config->phy_idx; if (sink) link_is_hdcp14 = dc_link_is_hdcp14(aconnector->dc_link, sink->sink_signal); @@ -483,6 +484,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw; link->dp.assr_enabled = config->assr_enabled; link->dp.mst_enabled = config->mst_enabled; + link->dp.usb4_enabled = config->usb4_enabled; display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION; link->adjust.auth_delay = 3; link->adjust.hdcp1.disable = 0; diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c index be61975f1470..ee67a35c2a8e 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c @@ -202,6 +202,10 @@ static enum mod_hdcp_status add_display_to_topology_v3( dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE; dtm_cmd->dtm_in_message.topology_update_v3.phy_id = link->phy_idx; dtm_cmd->dtm_in_message.topology_update_v3.link_hdcp_cap = link->hdcp_supported_informational; + dtm_cmd->dtm_in_message.topology_update_v3.dio_output_type = link->dp.usb4_enabled ? + TA_DTM_DIO_OUTPUT_TYPE__DPIA : + TA_DTM_DIO_OUTPUT_TYPE__DIRECT; + dtm_cmd->dtm_in_message.topology_update_v3.dio_output_id = link->dio_output_id; psp_dtm_invoke(psp, dtm_cmd->cmd_id); mutex_unlock(&psp->dtm_context.mutex); diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h index 2937b4b61461..5b71bc96b98c 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h @@ -94,6 +94,15 @@ enum ta_dtm_encoder_type { TA_DTM_ENCODER_TYPE__DIG = 0x10 }; +/* @enum ta_dtm_dio_output_type + * This enum defines software value for dio_output_type + */ +typedef enum { + TA_DTM_DIO_OUTPUT_TYPE__INVALID, + TA_DTM_DIO_OUTPUT_TYPE__DIRECT, + TA_DTM_DIO_OUTPUT_TYPE__DPIA +} ta_dtm_dio_output_type; + struct ta_dtm_topology_update_input_v3 { /* display handle is unique across the driver and is used to identify a display */ /* for all security interfaces which reference displays such as HDCP */ @@ -111,6 +120,8 @@ struct ta_dtm_topology_update_input_v3 { enum ta_dtm_encoder_type encoder_type; uint32_t phy_id; uint32_t link_hdcp_cap; + ta_dtm_dio_output_type dio_output_type; + uint32_t dio_output_id; }; struct ta_dtm_topology_assr_enable { -- cgit v1.2.3 From 5f034aef8479ac80e8732958dcb66b8eda650659 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Sun, 5 Jun 2022 22:50:30 -0400 Subject: drm/amd/display: 3.2.190 This version brings along the following: - DP fixes - Exiting idle optimizations on mouse updates Acked-by: Hamza Mahfooz Signed-off-by: Aric Cyr Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7191fc48c2e7..0549fa2c572a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -47,7 +47,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.189" +#define DC_VER "3.2.190" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- cgit v1.2.3 From 85ee819fd08eff7617c186775fd958e6258216db Mon Sep 17 00:00:00 2001 From: Oliver Logush Date: Fri, 13 Aug 2021 13:44:56 -0400 Subject: drm/amd/display: Drop unused privacy_mask setters and getters [Why and How] dwbc_funcs.set/get_privacy_mask isn't being used anymore, drop it Reviewed-by: Charlene Liu Acked-by: Alan Liu Signed-off-by: Oliver Logush Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h index fd6572ba3fb2..b982be64c792 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h @@ -219,12 +219,6 @@ struct dwbc_funcs { struct dwbc *dwbc, const struct dc_transfer_func *in_transfer_func_dwb_ogam); - void (*get_privacy_mask)( - struct dwbc *dwbc, uint32_t *mask_id); - - void (*set_privacy_mask)( - struct dwbc *dwbc, uint32_t mask_id); - //TODO: merge with output_transfer_func? bool (*dwb_ogam_set_input_transfer_func)( struct dwbc *dwbc, -- cgit v1.2.3 From f69e98a91a01fd7c5755dd710e94a17d6e9f583f Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Tue, 9 Mar 2021 17:23:10 -0500 Subject: drm/amd/display: Fix comments [Why & how] Fix format and typo of comments. Acked-by: Alan Liu Signed-off-by: Samson Tam Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 1 - drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 ++++++-- .../amd/display/dc/gpio/dcn20/hw_translate_dcn20.c | 17 ++++++++++------- .../amd/display/dc/gpio/dcn21/hw_translate_dcn21.c | 17 ++++++++++------- .../amd/display/dc/gpio/dcn30/hw_translate_dcn30.c | 19 +++++++++++-------- 5 files changed, 37 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index cac80ba69072..fb82e9f9738e 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -436,7 +436,6 @@ void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base) clk_mgr_base->clks.dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider; } - } void dcn2_get_clock(struct clk_mgr *clk_mgr, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 7884530cc02b..199868925fe4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1379,7 +1379,9 @@ bool dc_link_get_hpd_state(struct dc_link *dc_link) static enum hpd_source_id get_hpd_line(struct dc_link *link) { struct gpio *hpd; - enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN; + enum hpd_source_id hpd_id; + + hpd_id = HPD_SOURCEID_UNKNOWN; hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service); @@ -1418,7 +1420,9 @@ static enum hpd_source_id get_hpd_line(struct dc_link *link) static enum channel_id get_ddc_line(struct dc_link *link) { struct ddc *ddc; - enum channel_id channel = CHANNEL_ID_UNKNOWN; + enum channel_id channel; + + channel = CHANNEL_ID_UNKNOWN; ddc = dal_ddc_service_get_ddc_pin(link->ddc); diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c index 52ba62b3b5e4..3005ee7751a0 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c @@ -150,7 +150,8 @@ static bool offset_to_id( /* DDC */ /* we don't care about the GPIO_ID for DDC * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK - * directly in the create method */ + * directly in the create method + */ case REG(DC_GPIO_DDC1_A): *en = GPIO_DDC_LINE_DDC1; return true; @@ -173,14 +174,16 @@ static bool offset_to_id( *en = GPIO_DDC_LINE_DDC_VGA; return true; -// case REG(DC_GPIO_I2CPAD_A): not exit -// case REG(DC_GPIO_PWRSEQ_A): -// case REG(DC_GPIO_PAD_STRENGTH_1): -// case REG(DC_GPIO_PAD_STRENGTH_2): -// case REG(DC_GPIO_DEBUG): +/* + * case REG(DC_GPIO_I2CPAD_A): not exit + * case REG(DC_GPIO_PWRSEQ_A): + * case REG(DC_GPIO_PAD_STRENGTH_1): + * case REG(DC_GPIO_PAD_STRENGTH_2): + * case REG(DC_GPIO_DEBUG): + */ /* UNEXPECTED */ default: -// case REG(DC_GPIO_SYNCA_A): not exist +/* case REG(DC_GPIO_SYNCA_A): not exist */ ASSERT_CRITICAL(false); return false; } diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c index 291966efe63d..d734e3a134d1 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c @@ -153,7 +153,8 @@ static bool offset_to_id( /* DDC */ /* we don't care about the GPIO_ID for DDC * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK - * directly in the create method */ + * directly in the create method + */ case REG(DC_GPIO_DDC1_A): *en = GPIO_DDC_LINE_DDC1; return true; @@ -173,14 +174,16 @@ static bool offset_to_id( *en = GPIO_DDC_LINE_DDC_VGA; return true; -// case REG(DC_GPIO_I2CPAD_A): not exit -// case REG(DC_GPIO_PWRSEQ_A): -// case REG(DC_GPIO_PAD_STRENGTH_1): -// case REG(DC_GPIO_PAD_STRENGTH_2): -// case REG(DC_GPIO_DEBUG): +/* + * case REG(DC_GPIO_I2CPAD_A): not exit + * case REG(DC_GPIO_PWRSEQ_A): + * case REG(DC_GPIO_PAD_STRENGTH_1): + * case REG(DC_GPIO_PAD_STRENGTH_2): + * case REG(DC_GPIO_DEBUG): + */ /* UNEXPECTED */ default: -// case REG(DC_GPIO_SYNCA_A): not exist +/* case REG(DC_GPIO_SYNCA_A): not exista */ #ifdef PALLADIUM_SUPPORTED *id = GPIO_ID_HPD; *en = GPIO_DDC_LINE_DDC1; diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c index 3169c567475f..49d6250037a9 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c @@ -155,7 +155,8 @@ static bool offset_to_id( /* DDC */ /* we don't care about the GPIO_ID for DDC * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK - * directly in the create method */ + * directly in the create method + */ case REG(DC_GPIO_DDC1_A): *en = GPIO_DDC_LINE_DDC1; return true; @@ -178,14 +179,16 @@ static bool offset_to_id( *en = GPIO_DDC_LINE_DDC_VGA; return true; -// case REG(DC_GPIO_I2CPAD_A): not exit -// case REG(DC_GPIO_PWRSEQ_A): -// case REG(DC_GPIO_PAD_STRENGTH_1): -// case REG(DC_GPIO_PAD_STRENGTH_2): -// case REG(DC_GPIO_DEBUG): +/* + * case REG(DC_GPIO_I2CPAD_A): not exit + * case REG(DC_GPIO_PWRSEQ_A): + * case REG(DC_GPIO_PAD_STRENGTH_1): + * case REG(DC_GPIO_PAD_STRENGTH_2): + * case REG(DC_GPIO_DEBUG): + */ /* UNEXPECTED */ default: -// case REG(DC_GPIO_SYNCA_A): not exist +/* case REG(DC_GPIO_SYNCA_A): not exist */ ASSERT_CRITICAL(false); return false; } @@ -369,7 +372,7 @@ static const struct hw_translate_funcs funcs = { }; /* - * dal_hw_translate_dcn10_init + * dal_hw_translate_dcn30_init * * @brief * Initialize Hw translate function pointers. -- cgit v1.2.3 From a34136a3b3526369e1b3e678590e3760e7653f0f Mon Sep 17 00:00:00 2001 From: Ian Chen Date: Mon, 10 May 2021 12:17:26 +0800 Subject: drm/amd/display: DAL ACR, dc part, fix missing dcn30 [Why] - missing in dcn30 function - Fix a divide by 0 when ACR trigger [How] - Add IS_SMU_TIMEOUT() to dcn30_smu_send_msg_with_param - Add zero check in dcn20_update_clocks_update_dentist Acked-by: Alan Liu Signed-off-by: Ian Chen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 22 +++++++++++++++------- .../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c | 11 ++++++++++- 2 files changed, 25 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index fb82e9f9738e..0d30d1d9d67e 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -126,16 +126,24 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct dc_state *context) { - int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR - * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; - int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR - * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; - - uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider); - uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider); + int dpp_divider = 0; + int disp_divider = 0; + uint32_t dppclk_wdivider = 0; + uint32_t dispclk_wdivider = 0; uint32_t current_dispclk_wdivider; uint32_t i; + if (clk_mgr->base.clks.dppclk_khz == 0 || clk_mgr->base.clks.dispclk_khz == 0) + return; + + dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR + * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; + disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR + * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; + + dppclk_wdivider = dentist_get_did_from_divider(dpp_divider); + dispclk_wdivider = dentist_get_did_from_divider(disp_divider); + REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, ¤t_dispclk_wdivider); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c index bfc960579760..1fbf1c105dc1 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c @@ -28,6 +28,8 @@ #include "clk_mgr_internal.h" #include "reg_helper.h" +#include "dm_helpers.h" + #include "dalsmc.h" #include "dcn30_smu11_driver_if.h" @@ -74,6 +76,7 @@ static uint32_t dcn30_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, un static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out) { + uint32_t result; /* Wait for response register to be ready */ dcn30_smu_wait_for_response(clk_mgr, 10, 200000); @@ -86,8 +89,14 @@ static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint /* Trigger the message transaction by writing the message ID */ REG_WRITE(DAL_MSG_REG, msg_id); + result = dcn30_smu_wait_for_response(clk_mgr, 10, 200000); + + if (IS_SMU_TIMEOUT(result)) { + dm_helpers_smu_timeout(CTX, msg_id, param_in, 10 * 200000); + } + /* Wait for response */ - if (dcn30_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) { + if (result == DALSMC_Result_OK) { if (param_out) *param_out = REG_READ(DAL_ARG_REG); -- cgit v1.2.3 From c2fbe663ec4f991832d67f936d3941f781884156 Mon Sep 17 00:00:00 2001 From: Felipe Clark Date: Sun, 7 Mar 2021 13:27:30 -0500 Subject: drm/amd/display: Firmware assisted MCLK switch and FS [WHY] Memory clock switching has great potential for power savings. [HOW] The driver code was modified to notify the DMCUB firmware that it should stretch the vertical blank of frames when a memory clock switch is about to start so that no blackouts happen on the screen due to unavailability of the frame buffer. The driver logic to determine when such firmware assisted strategy can be initiated is also implemented and consists on checking prerequisites of the feature. Acked-by: Alan Liu Signed-off-by: Felipe Clark Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 8 ++++--- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 ++ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 5 +++- drivers/gpu/drm/amd/display/dc/dc_stream.h | 3 ++- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 - drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 1 - drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 28 +++++++++++++--------- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h | 11 ++++++--- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 1 + .../gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 1 + .../drm/amd/display/dc/inc/hw_sequencer_private.h | 1 + .../drm/amd/display/modules/freesync/freesync.c | 5 ++++ .../gpu/drm/amd/display/modules/inc/mod_freesync.h | 4 ++++ 14 files changed, 51 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 645ec5bc3a7d..cfa6c2d1fc69 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -397,7 +397,6 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, struct dc_crtc_timing_adjust *adjust) { int i; - bool ret = false; stream->adjust.v_total_max = adjust->v_total_max; stream->adjust.v_total_mid = adjust->v_total_mid; @@ -412,10 +411,10 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, 1, *adjust); - ret = true; + return true; } } - return ret; + return false; } /** @@ -2650,6 +2649,9 @@ static void copy_stream_update_to_stream(struct dc *dc, if (update->vrr_infopacket) stream->vrr_infopacket = *update->vrr_infopacket; + if (update->allow_freesync) + stream->allow_freesync = *update->allow_freesync; + if (update->crtc_timing_adjust) stream->adjust = *update->crtc_timing_adjust; diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index 11597bca966a..548c91ad1b82 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -27,6 +27,8 @@ #include "dc_dmub_srv.h" #include "../dmub/dmub_srv.h" #include "dm_helpers.h" +#include "dc_hw_types.h" +#include "core_types.h" #define CTX dc_dmub_srv->ctx #define DC_LOGGER CTX->logger diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h index 50e44b53f14c..52758ff1e405 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h @@ -31,6 +31,10 @@ struct dmub_srv; struct dc; +struct pipe_ctx; +struct dc_crtc_timing_adjust; +struct dc_crtc_timing; +struct dc_state; struct dc_reg_helper_state { bool gather_in_progress; @@ -69,7 +73,6 @@ bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_bu void dc_dmub_trace_event_control(struct dc *dc, bool enable); void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub); - void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv); void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv); void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data); diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index f8f66790d09b..68cf06a5a3e3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -205,6 +205,7 @@ struct dc_stream_state { bool use_vsc_sdp_for_colorimetry; bool ignore_msa_timing_param; + bool allow_freesync; bool freesync_on_desktop; bool converter_disable_audio; @@ -295,9 +296,9 @@ struct dc_stream_update { struct dc_info_packet *vrr_infopacket; struct dc_info_packet *vsc_infopacket; struct dc_info_packet *vsp_infopacket; - bool *dpms_off; bool integer_scaling_update; + bool *allow_freesync; struct colorspace_transform *gamut_remap; enum dc_color_space *output_color_space; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 573d5be9e302..fff724e94eed 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2613,7 +2613,6 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); ASSERT(new_mpcc != NULL); - hubp->opp_id = pipe_ctx->stream_res.opp->inst; hubp->mpcc_id = mpcc_id; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index facd4e01b7ac..76f8b40b2165 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -2446,7 +2446,6 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) NULL, hubp->inst, mpcc_id); - dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); ASSERT(new_mpcc != NULL); diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c index ecdc7c781217..08b8893ff145 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c @@ -48,6 +48,8 @@ #include "dc_dmub_srv.h" #include "link_hwss.h" #include "dpcd_defs.h" +#include "../dcn20/dcn20_hwseq.h" +#include "dcn30_resource.h" #include "inc/dc_link_dp.h" #include "inc/link_dpcd.h" @@ -344,17 +346,6 @@ void dcn30_enable_writeback( dwb->funcs->enable(dwb, &wb_info->dwb_params); } -void dcn30_prepare_bandwidth(struct dc *dc, - struct dc_state *context) -{ - if (dc->clk_mgr->dc_mode_softmax_enabled) - if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && - context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) - dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz); - - dcn20_prepare_bandwidth(dc, context); -} - void dcn30_disable_writeback( struct dc *dc, unsigned int dwb_pipe_inst) @@ -647,6 +638,9 @@ void dcn30_init_hw(struct dc *dc) if (dc->res_pool->hubbub->funcs->init_crb) dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); + // Get DMCUB capabilities + dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub); + dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; } void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) @@ -962,3 +956,15 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc, pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, color_space, color_depth, solid_color, width, height, offset); } + +void dcn30_prepare_bandwidth(struct dc *dc, + struct dc_state *context) +{ + if (dc->clk_mgr->dc_mode_softmax_enabled) + if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && + context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) + dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz); + + dcn20_prepare_bandwidth(dc, context); +} + diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h index 73e7b690e82c..a24a8e33a3d2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h @@ -47,9 +47,6 @@ void dcn30_disable_writeback( struct dc *dc, unsigned int dwb_pipe_inst); -void dcn30_prepare_bandwidth(struct dc *dc, - struct dc_state *context); - bool dcn30_mmhubbub_warmup( struct dc *dc, unsigned int num_dwb, @@ -83,4 +80,12 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc, const struct tg_color *solid_color, int width, int height, int offset); +void dcn30_set_hubp_blank(const struct dc *dc, + struct pipe_ctx *pipe_ctx, + bool blank_enable); + +void dcn30_prepare_bandwidth(struct dc *dc, + struct dc_state *context); + + #endif /* __DC_HWSS_DCN30_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c index bb347319de83..4c06e6e1ba4a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c @@ -59,7 +59,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = { .pipe_control_lock = dcn20_pipe_control_lock, .interdependent_update_lock = dcn10_lock_all_pipes, .cursor_lock = dcn10_cursor_lock, - .prepare_bandwidth = dcn20_prepare_bandwidth, + .prepare_bandwidth = dcn30_prepare_bandwidth, .optimize_bandwidth = dcn20_optimize_bandwidth, .update_bandwidth = dcn20_update_bandwidth, .set_drr = dcn10_set_drr, diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c index b604fb26f288..9a440ae8f865 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c @@ -27,6 +27,7 @@ #include "dcn30_optc.h" #include "dc.h" #include "dcn_calc_math.h" +#include "dc_dmub_srv.h" #include "dml/dcn30/dcn30_fpu.h" diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c index 1c1a67c4cec1..4cf9a6cff46e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c @@ -89,6 +89,7 @@ #include "vm_helper.h" #include "dcn20/dcn20_vmid.h" #include "amdgpu_socbb.h" +#include "dc_dmub_srv.h" #define DC_LOGGER_INIT(logger) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h index 62a62e4fc4a8..ded45f8f4b82 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h @@ -68,6 +68,7 @@ struct dce_hwseq; struct timing_generator; struct tg_color; struct output_pixel_processor; +struct mpcc_blnd_cfg; struct hwseq_private_funcs { diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 03fa63d56fa6..aa121d45d9b8 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -1374,6 +1374,11 @@ unsigned long long mod_freesync_calc_field_rate_from_timing( return field_rate_in_uhz; } +bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr, struct dc_stream_state *const pStream) +{ + return (pVrr->state != VRR_STATE_UNSUPPORTED) && (pVrr->state != VRR_STATE_DISABLED); +} + bool mod_freesync_is_valid_range(uint32_t min_refresh_cap_in_uhz, uint32_t max_refresh_cap_in_uhz, uint32_t nominal_field_rate_in_uhz) diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h index cf6bc9446244..62e326dd29a8 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h @@ -194,4 +194,8 @@ unsigned int mod_freesync_calc_v_total_from_refresh( const struct dc_stream_state *stream, unsigned int refresh_in_uhz); +// Returns true when FreeSync is supported and enabled (even if it is inactive) +bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr, + struct dc_stream_state *const pStream); + #endif -- cgit v1.2.3 From 2bbb54bbacd674c692306351d1be5a9b5e61a1e4 Mon Sep 17 00:00:00 2001 From: Ahmad Othman Date: Mon, 4 Feb 2019 16:11:44 -0500 Subject: drm/amd/display: Add support for HF-VSIF [Why] - Currently there is no support for HF-VSIF - The current support of VSIF is limited to H14b infoframe [How] - refactor VSIF - Added new builder for HF-VSIF - Added the HF-VSIF packet to DisplayTarget - Updates DC to apply HF-VSIF updates when updating streams Acked-by: Alan Liu Signed-off-by: Ahmad Othman Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 11 +++++++++++ drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 ++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 8 +++++--- 4 files changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index cfa6c2d1fc69..7d71fd61c0a5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2732,7 +2732,8 @@ static void commit_planes_do_stream_update(struct dc *dc, if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) || stream_update->vrr_infopacket || stream_update->vsc_infopacket || - stream_update->vsp_infopacket) { + stream_update->vsp_infopacket || + stream_update->hfvsif_infopacket) { resource_build_info_frame(pipe_ctx); dc->hwss.update_info_frame(pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 9bbdfcd6b3a4..9bb0ae0dc836 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -2806,6 +2806,15 @@ static void set_vsc_info_packet( *info_packet = stream->vsc_infopacket; } +static void set_hfvs_info_packet( + struct dc_info_packet *info_packet, + struct dc_stream_state *stream) +{ + if (!stream->hfvsif_infopacket.valid) + return; + + *info_packet = stream->hfvsif_infopacket; +} void dc_resource_state_destruct(struct dc_state *context) { @@ -2886,6 +2895,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) info->spd.valid = false; info->hdrsmd.valid = false; info->vsc.valid = false; + info->hfvsif.valid = false; signal = pipe_ctx->stream->signal; @@ -2894,6 +2904,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) set_avi_info_frame(&info->avi, pipe_ctx); set_vendor_info_packet(&info->vendor, pipe_ctx->stream); + set_hfvs_info_packet(&info->hfvsif, pipe_ctx->stream); set_spd_info_packet(&info->spd, pipe_ctx->stream); diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 68cf06a5a3e3..376dddf54ec1 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -180,6 +180,7 @@ struct dc_stream_state { struct dc_info_packet vrr_infopacket; struct dc_info_packet vsc_infopacket; struct dc_info_packet vsp_infopacket; + struct dc_info_packet hfvsif_infopacket; uint8_t dsc_packed_pps[128]; struct rect src; /* composition area */ struct rect dst; /* stream addressable area */ @@ -296,6 +297,7 @@ struct dc_stream_update { struct dc_info_packet *vrr_infopacket; struct dc_info_packet *vsc_infopacket; struct dc_info_packet *vsp_infopacket; + struct dc_info_packet *hfvsif_infopacket; bool *dpms_off; bool integer_scaling_update; bool *allow_freesync; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c index 7608187751c8..92f474e6a96b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c @@ -675,11 +675,13 @@ static void enc1_stream_encoder_update_hdmi_info_packets( /* for bring up, disable dp double TODO */ REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); + /*Always add mandatory packets first followed by optional ones*/ enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi); - enc1_update_hdmi_info_packet(enc1, 1, &info_frame->vendor); + enc1_update_hdmi_info_packet(enc1, 1, &info_frame->hfvsif); enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut); - enc1_update_hdmi_info_packet(enc1, 3, &info_frame->spd); - enc1_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd); + enc1_update_hdmi_info_packet(enc1, 3, &info_frame->vendor); + enc1_update_hdmi_info_packet(enc1, 4, &info_frame->spd); + enc1_update_hdmi_info_packet(enc1, 5, &info_frame->hdrsmd); } static void enc1_stream_encoder_stop_hdmi_info_packets( -- cgit v1.2.3 From 28fdd0c32daf9a50a606530d54784fcfa29d88b7 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Tue, 14 May 2019 09:19:01 -0400 Subject: drm/amd/display: Copy hfvsif_infopacket when stream update [Why & How] Miss to copy hfvsif_infopacket when copying stream updates. Check and copy it. Acked-by: Alan Liu Signed-off-by: Nicholas Kazlauskas Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 7d71fd61c0a5..400b37e393b7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2658,6 +2658,9 @@ static void copy_stream_update_to_stream(struct dc *dc, if (update->dpms_off) stream->dpms_off = *update->dpms_off; + if (update->hfvsif_infopacket) + stream->hfvsif_infopacket = *update->hfvsif_infopacket; + if (update->vsc_infopacket) stream->vsc_infopacket = *update->vsc_infopacket; -- cgit v1.2.3 From 9a4c9de4838fd8ccfcfcfdcd7bd472dddd11f264 Mon Sep 17 00:00:00 2001 From: Ahmad Othman Date: Thu, 1 Aug 2019 15:05:04 -0400 Subject: drm/amd/display: Adding VTEM to dc [Why] Video Timing Extended Metadata packet (VTEM) is required for features like VRR and FVA [How] Adding support for VTEM transmission to stream encoders in DCN20 and DCN30 as part of FVA support Acked-by: Alan Liu Signed-off-by: Ahmad Othman Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +++++- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 14 +++++++++++++- drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 ++ .../gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 1 + .../drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c | 1 + drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 1 + 6 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 400b37e393b7..7c2b65226131 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2661,6 +2661,9 @@ static void copy_stream_update_to_stream(struct dc *dc, if (update->hfvsif_infopacket) stream->hfvsif_infopacket = *update->hfvsif_infopacket; + if (update->vtem_infopacket) + stream->vtem_infopacket = *update->vtem_infopacket; + if (update->vsc_infopacket) stream->vsc_infopacket = *update->vsc_infopacket; @@ -2736,7 +2739,8 @@ static void commit_planes_do_stream_update(struct dc *dc, stream_update->vrr_infopacket || stream_update->vsc_infopacket || stream_update->vsp_infopacket || - stream_update->hfvsif_infopacket) { + stream_update->hfvsif_infopacket || + stream_update->vtem_infopacket) { resource_build_info_frame(pipe_ctx); dc->hwss.update_info_frame(pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 9bb0ae0dc836..463ff12adbc8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -2816,6 +2816,17 @@ static void set_hfvs_info_packet( *info_packet = stream->hfvsif_infopacket; } + +static void set_vtem_info_packet( + struct dc_info_packet *info_packet, + struct dc_stream_state *stream) +{ + if (!stream->vtem_infopacket.valid) + return; + + *info_packet = stream->vtem_infopacket; +} + void dc_resource_state_destruct(struct dc_state *context) { int i, j; @@ -2896,7 +2907,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) info->hdrsmd.valid = false; info->vsc.valid = false; info->hfvsif.valid = false; - + info->vtem.valid = false; signal = pipe_ctx->stream->signal; /* HDMi and DP have different info packets*/ @@ -2905,6 +2916,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) set_vendor_info_packet(&info->vendor, pipe_ctx->stream); set_hfvs_info_packet(&info->hfvsif, pipe_ctx->stream); + set_vtem_info_packet(&info->vtem, pipe_ctx->stream); set_spd_info_packet(&info->spd, pipe_ctx->stream); diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 376dddf54ec1..c76fac3c153d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -181,6 +181,7 @@ struct dc_stream_state { struct dc_info_packet vsc_infopacket; struct dc_info_packet vsp_infopacket; struct dc_info_packet hfvsif_infopacket; + struct dc_info_packet vtem_infopacket; uint8_t dsc_packed_pps[128]; struct rect src; /* composition area */ struct rect dst; /* stream addressable area */ @@ -298,6 +299,7 @@ struct dc_stream_update { struct dc_info_packet *vsc_infopacket; struct dc_info_packet *vsp_infopacket; struct dc_info_packet *hfvsif_infopacket; + struct dc_info_packet *vtem_infopacket; bool *dpms_off; bool integer_scaling_update; bool *allow_freesync; diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c index aab25ca8343a..e8f5c01688ec 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c @@ -159,6 +159,7 @@ static void enc2_stream_encoder_update_hdmi_info_packets( enc2_update_hdmi_info_packet(enc1, 3, &info_frame->vendor); enc2_update_hdmi_info_packet(enc1, 4, &info_frame->spd); enc2_update_hdmi_info_packet(enc1, 5, &info_frame->hdrsmd); + enc2_update_hdmi_info_packet(enc1, 6, &info_frame->vtem); } static void enc2_stream_encoder_stop_hdmi_info_packets( diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c index 1a26ce87c16e..25e5c3bc1be9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c @@ -212,6 +212,7 @@ void enc3_stream_encoder_update_hdmi_info_packets( enc3_update_hdmi_info_packet(enc1, 1, &info_frame->vendor); enc3_update_hdmi_info_packet(enc1, 3, &info_frame->spd); enc3_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd); + enc3_update_hdmi_info_packet(enc1, 6, &info_frame->vtem); } void enc3_stream_encoder_stop_hdmi_info_packets( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h index e5fe0f6adc86..e04a51a57c93 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -77,6 +77,7 @@ struct encoder_info_frame { struct dc_info_packet gamut; struct dc_info_packet vendor; struct dc_info_packet hfvsif; + struct dc_info_packet vtem; /* source product description */ struct dc_info_packet spd; /* video stream configuration */ -- cgit v1.2.3 From 3de58f22f544ec9c692993fb1f3bc77163d3d5d8 Mon Sep 17 00:00:00 2001 From: Felipe Clark Date: Fri, 26 Mar 2021 15:01:20 -0400 Subject: drm/amd/display: Pass vrr mode to dcn [WHY] New features will require knowing the vrr mode for their enablement. [HOW] Pass the state via a member of dc_stream. Acked-by: Alan Liu Signed-off-by: Felipe Clark Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc_stream.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index c76fac3c153d..ae9382ce82d3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -208,6 +208,7 @@ struct dc_stream_state { bool ignore_msa_timing_param; bool allow_freesync; + bool vrr_active_variable; bool freesync_on_desktop; bool converter_disable_audio; -- cgit v1.2.3 From ebfb15262af3bec6c3cc263ce04164e44eea4b30 Mon Sep 17 00:00:00 2001 From: Harry VanZyllDeJong Date: Mon, 10 May 2021 19:30:24 -0400 Subject: drm/amd/display: Add vrr_active_variable to dc_stream_update [WHY] The display driver on some OSes need to track it in order to perform memory clock switching decisions. [HOW] Propagate the vrr active state to dirty bit so that on mode set it disables dynamic memory clock switching. Acked-by: Alan Liu Signed-off-by: Harry VanZyllDeJong Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++ drivers/gpu/drm/amd/display/dc/dc_stream.h | 1 + drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 2 +- drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h | 3 +-- 4 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 7c2b65226131..49339c5c7230 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2652,6 +2652,9 @@ static void copy_stream_update_to_stream(struct dc *dc, if (update->allow_freesync) stream->allow_freesync = *update->allow_freesync; + if (update->vrr_active_variable) + stream->vrr_active_variable = *update->vrr_active_variable; + if (update->crtc_timing_adjust) stream->adjust = *update->crtc_timing_adjust; diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index ae9382ce82d3..5a894c19b0ea 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -304,6 +304,7 @@ struct dc_stream_update { bool *dpms_off; bool integer_scaling_update; bool *allow_freesync; + bool *vrr_active_variable; struct colorspace_transform *gamut_remap; enum dc_color_space *output_color_space; diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index aa121d45d9b8..0686223034de 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -1374,7 +1374,7 @@ unsigned long long mod_freesync_calc_field_rate_from_timing( return field_rate_in_uhz; } -bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr, struct dc_stream_state *const pStream) +bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr) { return (pVrr->state != VRR_STATE_UNSUPPORTED) && (pVrr->state != VRR_STATE_DISABLED); } diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h index 62e326dd29a8..afe1f6cce528 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h @@ -195,7 +195,6 @@ unsigned int mod_freesync_calc_v_total_from_refresh( unsigned int refresh_in_uhz); // Returns true when FreeSync is supported and enabled (even if it is inactive) -bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr, - struct dc_stream_state *const pStream); +bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr); #endif -- cgit v1.2.3 From ac31a24d9188a9599dfbce7664cb11e6292873a5 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Fri, 3 Apr 2020 21:06:53 -0400 Subject: drm/amd/display: FVA timing adjustment [why] need to add timing adjustment for fva. [how] add hook to optc and hwseq. Acked-by: Alan Liu Signed-off-by: Charlene Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c index b1671b00ce40..e1a9a45b03b6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c @@ -165,6 +165,7 @@ void optc1_program_timing( optc1->vupdate_width = vupdate_width; patched_crtc_timing = *dc_crtc_timing; apply_front_porch_workaround(&patched_crtc_timing); + optc1->orginal_patched_timing = patched_crtc_timing; /* Load horizontal timing */ -- cgit v1.2.3 From ac78fa502afa539cce3a285e50d7fefaf4d2115e Mon Sep 17 00:00:00 2001 From: Martin Leung Date: Wed, 30 Oct 2019 14:19:30 -0400 Subject: drm/amd/display: Add null check to dc_submit_i2c_oem [why] dc_submit_i2c_oem could be called with ddc null [how] add null check and fail the call instead Acked-by: Alan Liu Signed-off-by: Martin Leung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 49339c5c7230..258322c39e9a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3477,10 +3477,13 @@ bool dc_submit_i2c_oem( struct i2c_command *cmd) { struct ddc_service *ddc = dc->res_pool->oem_device; - return dce_i2c_submit_command( - dc->res_pool, - ddc->ddc_pin, - cmd); + if (ddc) + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + + return false; } static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink) -- cgit v1.2.3 From ba8b460445f8d19d530646729c29319c278dbb38 Mon Sep 17 00:00:00 2001 From: Joshua Aberback Date: Thu, 28 May 2020 11:11:34 -0400 Subject: drm/amd/display: Blank for uclk OC in dm instead of dc [Why] All displays need to be blanked during the uclk OC interface so that we can guarantee pstate switching support. If the display config doesn't support pstate switching, only using core_link_disable_stream will not enable it as the front-end is untouched. We need to go through the full plane removal sequence to properly program the pipe to allow pstate switching. [How] - guard clk_mgr functions with non-NULL checks Acked-by: Alan Liu Signed-off-by: Joshua Aberback Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 34 +++++++++++--------------------- drivers/gpu/drm/amd/display/dc/dc.h | 10 ++-------- 2 files changed, 14 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 258322c39e9a..48a14a5bda56 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3666,37 +3666,27 @@ void dc_allow_idle_optimizations(struct dc *dc, bool allow) dc->idle_optimizations_allowed = allow; } -/* - * blank all streams, and set min and max memory clock to - * lowest and highest DPM level, respectively - */ +/* set min and max memory clock to lowest and highest DPM level, respectively */ void dc_unlock_memory_clock_frequency(struct dc *dc) { - unsigned int i; - - for (i = 0; i < MAX_PIPES; i++) - if (dc->current_state->res_ctx.pipe_ctx[i].plane_state) - core_link_disable_stream(&dc->current_state->res_ctx.pipe_ctx[i]); + if (dc->clk_mgr->funcs->set_hard_min_memclk) + dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false); - dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false); - dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); + if (dc->clk_mgr->funcs->set_hard_max_memclk) + dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); } -/* - * set min memory clock to the min required for current mode, - * max to maxDPM, and unblank streams - */ +/* set min memory clock to the min required for current mode, max to maxDPM */ void dc_lock_memory_clock_frequency(struct dc *dc) { - unsigned int i; + if (dc->clk_mgr->funcs->get_memclk_states_from_smu) + dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr); - dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr); - dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true); - dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); + if (dc->clk_mgr->funcs->set_hard_min_memclk) + dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true); - for (i = 0; i < MAX_PIPES; i++) - if (dc->current_state->res_ctx.pipe_ctx[i].plane_state) - core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]); + if (dc->clk_mgr->funcs->set_hard_max_memclk) + dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); } static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 0549fa2c572a..ba57e03d3d9e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1437,16 +1437,10 @@ bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_ void dc_allow_idle_optimizations(struct dc *dc, bool allow); -/* - * blank all streams, and set min and max memory clock to - * lowest and highest DPM level, respectively - */ +/* set min and max memory clock to lowest and highest DPM level, respectively */ void dc_unlock_memory_clock_frequency(struct dc *dc); -/* - * set min memory clock to the min required for current mode, - * max to maxDPM, and unblank streams - */ +/* set min memory clock to the min required for current mode, max to maxDPM */ void dc_lock_memory_clock_frequency(struct dc *dc); /* set soft max for memclk, to be used for AC/DC switching clock limitations */ -- cgit v1.2.3 From 68ad7f90c790a178f47ef08408d97a81cbb71b37 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Sun, 12 Jun 2022 12:12:34 +0800 Subject: drm/amdgpu: remove redundant enable_mes and enable_mes_kiq enable_mes and enable_mes_kiq are set in both device init and MES IP init. Leave the ones in MES IP init, since it is a more accurate way to judge from GC IP version. Signed-off-by: Yifan Zhang Acked-by: Alex Deucher Reviewed-by: Jack Xiao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 45dc96aee39e..ea9a9d781d8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3615,14 +3615,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, if (amdgpu_mcbp) DRM_INFO("MCBP is enabled\n"); - if (adev->asic_type >= CHIP_NAVI10) { - if (amdgpu_mes || amdgpu_mes_kiq) - adev->enable_mes = true; - - if (amdgpu_mes_kiq) - adev->enable_mes_kiq = true; - } - /* * Reset domain needs to be present early, before XGMI hive discovered * (if any) and intitialized to use reset sem and in_gpu reset flag -- cgit v1.2.3 From 914da384ae9a77079314f07022c18063c7e77778 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 10 Jun 2022 11:38:05 -0400 Subject: drm/amdkfd: fix warning when CONFIG_HSA_AMD_P2P is not set MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:1542:11: warning: variable 'i' set but not used [-Wunused-but-set-variable] Reviewed-by: Felix Kuehling Acked-by: Christian König Reported-by: kernel test robot Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 304322ac39e6..25990bec600d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1539,7 +1539,10 @@ static int kfd_dev_create_p2p_links(void) { struct kfd_topology_device *dev; struct kfd_topology_device *new_dev; - uint32_t i, k; +#if defined(CONFIG_HSA_AMD_P2P) + uint32_t i; +#endif + uint32_t k; int ret = 0; k = 0; @@ -1553,7 +1556,6 @@ static int kfd_dev_create_p2p_links(void) return 0; k--; - i = 0; /* create in-direct links */ ret = kfd_create_indirect_link_prop(new_dev, k); @@ -1562,6 +1564,7 @@ static int kfd_dev_create_p2p_links(void) /* create p2p links */ #if defined(CONFIG_HSA_AMD_P2P) + i = 0; list_for_each_entry(dev, &topology_device_list, list) { if (dev == new_dev) break; -- cgit v1.2.3 From 4e1db0119c64fd81509005a961790d263e99b21b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 14 Jun 2022 09:57:26 -0400 Subject: Revert "drm/amdgpu/display: Protect some functions with CONFIG_DRM_AMD_DC_DCN" This reverts commit d8e4fb9112e88d8d87ffbc38fa511e7118042d4f. This is no longer necessary as newer patches require these functions without CONFIG_DRM_AMD_DC_DCN. Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 463ff12adbc8..31f0262fc930 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1801,7 +1801,6 @@ static inline void retain_hpo_dp_link_enc( res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]++; } -#if defined(CONFIG_DRM_AMD_DC_DCN) static inline void release_hpo_dp_link_enc( struct resource_context *res_ctx, int enc_index) @@ -1809,7 +1808,6 @@ static inline void release_hpo_dp_link_enc( ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0); res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]--; } -#endif static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx, const struct resource_pool *pool, @@ -1834,7 +1832,6 @@ static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx, return pipe_ctx->link_res.hpo_dp_link_enc != NULL; } -#if defined(CONFIG_DRM_AMD_DC_DCN) static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx, struct pipe_ctx *pipe_ctx, struct dc_stream_state *stream) @@ -1848,7 +1845,6 @@ static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx, pipe_ctx->link_res.hpo_dp_link_enc = NULL; } } -#endif /* TODO: release audio object */ void update_audio_usage( -- cgit v1.2.3 From 2595fe04a44d8ac7a56db27dbd1c54698d97fc0b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 10 Jun 2022 11:17:59 -0400 Subject: drm/amdgpu/display: make FP handling in Makefiles consistent Use the same pattern as the DML Makefile and while we are here add a missing x86 guard around the msse flags for DCN3.2.x. Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile | 3 +-- drivers/gpu/drm/amd/display/dc/dcn201/Makefile | 1 - drivers/gpu/drm/amd/display/dc/dcn30/Makefile | 6 ++---- drivers/gpu/drm/amd/display/dc/dcn302/Makefile | 8 +++++++- drivers/gpu/drm/amd/display/dc/dcn32/Makefile | 5 +++-- drivers/gpu/drm/amd/display/dc/dcn321/Makefile | 5 +++-- 6 files changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile index c935c10b5f4f..7b505e1e9308 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile @@ -180,7 +180,7 @@ CLK_MGR_DCN32 = dcn32_clk_mgr.o dcn32_clk_mgr_smu_msg.o AMD_DAL_CLK_MGR_DCN32 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn32/,$(CLK_MGR_DCN32)) ifdef CONFIG_X86 -CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -msse +CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mhard-float -msse endif ifdef CONFIG_PPC64 @@ -191,7 +191,6 @@ ifdef CONFIG_CC_IS_GCC ifeq ($(call cc-ifversion, -lt, 0701, y), y) IS_OLD_GCC = 1 endif -CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mhard-float endif ifdef CONFIG_X86 diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/Makefile b/drivers/gpu/drm/amd/display/dc/dcn201/Makefile index f68038ceb1b1..96cbd4ccd344 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn201/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn201/Makefile @@ -18,7 +18,6 @@ ifdef CONFIG_CC_IS_GCC ifeq ($(call cc-ifversion, -lt, 0701, y), y) IS_OLD_GCC = 1 endif -CFLAGS_$(AMDDALPATH)/dc/dcn201/dcn201_resource.o += -mhard-float endif ifdef CONFIG_X86 diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile index dfd77b3cc84d..c20331eb62e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile @@ -32,8 +32,8 @@ DCN30 = dcn30_init.o dcn30_hubbub.o dcn30_hubp.o dcn30_dpp.o dcn30_optc.o \ ifdef CONFIG_X86 -CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -msse -CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -msse +CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mhard-float -msse +CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -msse endif ifdef CONFIG_PPC64 @@ -45,8 +45,6 @@ ifdef CONFIG_CC_IS_GCC ifeq ($(call cc-ifversion, -lt, 0701, y), y) IS_OLD_GCC = 1 endif -CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o += -mhard-float -CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o += -mhard-float endif ifdef CONFIG_X86 diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/Makefile b/drivers/gpu/drm/amd/display/dc/dcn302/Makefile index f9561d7f97a1..e4b69ad0dde5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn302/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn302/Makefile @@ -8,7 +8,7 @@ DCN3_02 = dcn302_init.o dcn302_hwseq.o dcn302_resource.o ifdef CONFIG_X86 -CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -msse +CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -mhard-float -msse endif ifdef CONFIG_PPC64 @@ -16,6 +16,12 @@ CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -mhard-float -maltivec endif ifdef CONFIG_X86 +ifdef CONFIG_CC_IS_GCC +ifeq ($(call cc-ifversion, -lt, 0701, y), y) +IS_OLD_GCC = 1 +endif +endif + ifdef IS_OLD_GCC # Stack alignment mismatch, proceed with caution. # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/Makefile b/drivers/gpu/drm/amd/display/dc/dcn32/Makefile index 3d09db3070f4..34f2e37b6704 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn32/Makefile @@ -16,7 +16,7 @@ DCN32 = dcn32_resource.o dcn32_hubbub.o dcn32_hwseq.o dcn32_init.o \ dcn32_mpc.o ifdef CONFIG_X86 -CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o := -msse +CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o := -mhard-float -msse endif ifdef CONFIG_PPC64 @@ -27,9 +27,9 @@ ifdef CONFIG_CC_IS_GCC ifeq ($(call cc-ifversion, -lt, 0701, y), y) IS_OLD_GCC = 1 endif -CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o += -mhard-float endif +ifdef CONFIG_X86 ifdef IS_OLD_GCC # Stack alignment mismatch, proceed with caution. # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 @@ -38,6 +38,7 @@ CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o += -mpreferred-stack-boundary=4 else CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o += -msse2 endif +endif AMD_DAL_DCN32 = $(addprefix $(AMDDALPATH)/dc/dcn32/,$(DCN32)) diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/Makefile b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile index 5896ca303e39..e554fd6c16f2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn321/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile @@ -13,7 +13,7 @@ DCN321 = dcn321_resource.o dcn321_dio_link_encoder.o ifdef CONFIG_X86 -CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o := -msse +CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o := -mhard-float -msse endif ifdef CONFIG_PPC64 @@ -24,9 +24,9 @@ ifdef CONFIG_CC_IS_GCC ifeq ($(call cc-ifversion, -lt, 0701, y), y) IS_OLD_GCC = 1 endif -CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o += -mhard-float endif +ifdef CONFIG_X86 ifdef IS_OLD_GCC # Stack alignment mismatch, proceed with caution. # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 @@ -35,6 +35,7 @@ CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o += -mpreferred-stack-boundary=4 else CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o += -msse2 endif +endif AMD_DAL_DCN321 = $(addprefix $(AMDDALPATH)/dc/dcn321/,$(DCN321)) -- cgit v1.2.3 From c435f61d0eb334dc8367164a125aea45d9dd9508 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Thu, 19 May 2022 13:51:42 -0400 Subject: drm/amd/display: Drop unnecessary guard from DC resource Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 31f0262fc930..28803ca9e3f2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1998,7 +1998,6 @@ enum dc_status dc_remove_stream_from_ctx( if (dc->res_pool->funcs->link_enc_unassign) dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream); -#if defined(CONFIG_DRM_AMD_DC_DCN) if (is_dp_128b_132b_signal(del_pipe)) { update_hpo_dp_stream_engine_usage( &new_ctx->res_ctx, dc->res_pool, @@ -2006,7 +2005,6 @@ enum dc_status dc_remove_stream_from_ctx( false); remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream); } -#endif if (del_pipe->stream_res.audio) update_audio_usage( -- cgit v1.2.3 From 4ed49c954e35559cb4a34ba049a15f54ec7fccf6 Mon Sep 17 00:00:00 2001 From: Ruijing Dong Date: Tue, 31 May 2022 14:18:25 -0400 Subject: drm/amdgpu/vcn: add unified queue ib test - add unified queue headers - add unified queue ib tests Acked-by: Leo Liu Signed-off-by: Ruijing Dong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 102 +++++++++++++++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 1 + 2 files changed, 100 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index aa7acfabf360..e62ff7db4736 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -329,6 +329,18 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) return 0; } +/* from vcn4 and above, only unified queue is used */ +bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + bool ret = false; + + if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)) + ret = true; + + return ret; +} + bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) { bool ret = false; @@ -718,19 +730,55 @@ error: return r; } +static uint32_t * amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib, + uint32_t ib_pack_in_dw, bool enc) +{ + uint32_t *ib_checksum; + + ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */ + ib->ptr[ib->length_dw++] = 0x30000002; + ib_checksum = &ib->ptr[ib->length_dw++]; + ib->ptr[ib->length_dw++] = ib_pack_in_dw; + + ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */ + ib->ptr[ib->length_dw++] = 0x30000001; + ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3; + ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t); + + return ib_checksum; +} + +static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum, + uint32_t ib_pack_in_dw) +{ + uint32_t i; + uint32_t checksum = 0; + + for (i = 0; i < ib_pack_in_dw; i++) + checksum += *(*ib_checksum + 2 + i); + + **ib_checksum = checksum; +} + static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, struct amdgpu_ib *ib_msg, struct dma_fence **fence) { struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; - const unsigned int ib_size_dw = 64; + unsigned int ib_size_dw = 64; struct amdgpu_device *adev = ring->adev; struct dma_fence *f = NULL; struct amdgpu_job *job; struct amdgpu_ib *ib; uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); + bool sq = amdgpu_vcn_using_unified_queue(ring); + uint32_t *ib_checksum; + uint32_t ib_pack_in_dw; int i, r; + if (sq) + ib_size_dw += 8; + r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, &job); if (r) @@ -739,6 +787,13 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, ib = &job->ibs[0]; ib->length_dw = 0; + /* single queue headers */ + if (sq) { + ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t) + + 4 + 2; /* engine info + decoding ib in dw */ + ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false); + } + ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); @@ -752,6 +807,9 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, for (i = ib->length_dw; i < ib_size_dw; ++i) ib->ptr[i] = 0x0; + if (sq) + amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw); + r = amdgpu_job_submit_direct(job, ring, &f); if (r) goto err_free; @@ -838,13 +896,18 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand struct amdgpu_ib *ib_msg, struct dma_fence **fence) { - const unsigned ib_size_dw = 16; + unsigned ib_size_dw = 16; struct amdgpu_job *job; struct amdgpu_ib *ib; struct dma_fence *f = NULL; + uint32_t *ib_checksum = NULL; uint64_t addr; + bool sq = amdgpu_vcn_using_unified_queue(ring); int i, r; + if (sq) + ib_size_dw += 8; + r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, &job); if (r) @@ -854,6 +917,10 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); ib->length_dw = 0; + + if (sq) + ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); + ib->ptr[ib->length_dw++] = 0x00000018; ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ ib->ptr[ib->length_dw++] = handle; @@ -873,6 +940,9 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand for (i = ib->length_dw; i < ib_size_dw; ++i) ib->ptr[i] = 0x0; + if (sq) + amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); + r = amdgpu_job_submit_direct(job, ring, &f); if (r) goto err; @@ -892,13 +962,18 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han struct amdgpu_ib *ib_msg, struct dma_fence **fence) { - const unsigned ib_size_dw = 16; + unsigned ib_size_dw = 16; struct amdgpu_job *job; struct amdgpu_ib *ib; struct dma_fence *f = NULL; + uint32_t *ib_checksum = NULL; uint64_t addr; + bool sq = amdgpu_vcn_using_unified_queue(ring); int i, r; + if (sq) + ib_size_dw += 8; + r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, &job); if (r) @@ -908,6 +983,10 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); ib->length_dw = 0; + + if (sq) + ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); + ib->ptr[ib->length_dw++] = 0x00000018; ib->ptr[ib->length_dw++] = 0x00000001; ib->ptr[ib->length_dw++] = handle; @@ -927,6 +1006,9 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han for (i = ib->length_dw; i < ib_size_dw; ++i) ib->ptr[i] = 0x0; + if (sq) + amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); + r = amdgpu_job_submit_direct(job, ring, &f); if (r) goto err; @@ -977,6 +1059,20 @@ error: return r; } +int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout) +{ + long r; + + r = amdgpu_vcn_enc_ring_test_ib(ring, timeout); + if (r) + goto error; + + r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout); + +error: + return r; +} + enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) { switch(ring) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index 6f90fcee0f9c..60c608144480 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -364,6 +364,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring); int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout); int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring); int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout); +int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout); int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring); int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout); -- cgit v1.2.3 From bb4f196b47b6554ba89f02ec60246f0c643a4bf8 Mon Sep 17 00:00:00 2001 From: Ruijing Dong Date: Tue, 31 May 2022 14:20:42 -0400 Subject: drm/amdgpu/vcn: support unified queue only in vcn4 - remove multiple queue support - add unified queue related functions Acked-by: Leo Liu Signed-off-by: Ruijing Dong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 563 +++++++++------------------------- 1 file changed, 140 insertions(+), 423 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 9119e966ffff..d6f134ef9633 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -29,7 +29,6 @@ #include "soc15d.h" #include "soc15_hw_ip.h" #include "vcn_v2_0.h" -#include "vcn_sw_ring.h" #include "vcn/vcn_4_0_0_offset.h" #include "vcn/vcn_4_0_0_sh_mask.h" @@ -45,15 +44,12 @@ #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 -bool unifiedQ_enabled = false; - static int amdgpu_ih_clientid_vcns[] = { SOC15_IH_CLIENTID_VCN, SOC15_IH_CLIENTID_VCN1 }; -static void vcn_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev); -static void vcn_v4_0_set_enc_ring_funcs(struct amdgpu_device *adev); +static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev); static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev); static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state); @@ -71,36 +67,15 @@ static int vcn_v4_0_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (unifiedQ_enabled) { - adev->vcn.num_vcn_inst = 1; - adev->vcn.num_enc_rings = 1; - } else { - adev->vcn.num_enc_rings = 2; - } - - if (!unifiedQ_enabled) - vcn_v4_0_set_dec_ring_funcs(adev); + /* re-use enc ring as unified ring */ + adev->vcn.num_enc_rings = 1; - vcn_v4_0_set_enc_ring_funcs(adev); + vcn_v4_0_set_unified_ring_funcs(adev); vcn_v4_0_set_irq_funcs(adev); return 0; } -static void amdgpu_vcn_setup_unified_queue_ucode(struct amdgpu_device *adev) -{ - if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { - const struct common_firmware_header *hdr; - - hdr = (const struct common_firmware_header *)adev->vcn.fw->data; - adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; - adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; - adev->firmware.fw_size += - ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); - DRM_INFO("PSP loading VCN firmware\n"); - } -} - /** * vcn_v4_0_sw_init - sw init for VCN block * @@ -111,17 +86,14 @@ static void amdgpu_vcn_setup_unified_queue_ucode(struct amdgpu_device *adev) static int vcn_v4_0_sw_init(void *handle) { struct amdgpu_ring *ring; - int i, j, r; struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i, r; r = amdgpu_vcn_sw_init(adev); if (r) return r; - if (unifiedQ_enabled) - amdgpu_vcn_setup_unified_queue_ucode(adev); - else - amdgpu_vcn_setup_ucode(adev); + amdgpu_vcn_setup_ucode(adev); r = amdgpu_vcn_resume(adev); if (r) @@ -129,81 +101,40 @@ static int vcn_v4_0_sw_init(void *handle) for (i = 0; i < adev->vcn.num_vcn_inst; i++) { volatile struct amdgpu_vcn4_fw_shared *fw_shared; + if (adev->vcn.harvest_config & (1 << i)) continue; - /* VCN DEC TRAP */ + + atomic_set(&adev->vcn.inst[i].sched_score, 0); + + /* VCN UNIFIED TRAP */ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], - VCN_4_0__SRCID__UVD_TRAP, &adev->vcn.inst[i].irq); + VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); if (r) return r; - atomic_set(&adev->vcn.inst[i].sched_score, 0); - if (!unifiedQ_enabled) { - ring = &adev->vcn.inst[i].ring_dec; - ring->use_doorbell = true; - - /* VCN4 doorbell layout - * 1: VCN_JPEG_DB_CTRL UVD_JRBC_RB_WPTR; (jpeg) - * 2: VCN_RB1_DB_CTRL UVD_RB_WPTR; (decode/encode for unified queue) - * 3: VCN_RB2_DB_CTRL UVD_RB_WPTR2; (encode only for swqueue) - * 4: VCN_RB3_DB_CTRL UVD_RB_WPTR3; (Reserved) - * 5: VCN_RB4_DB_CTRL UVD_RB_WPTR4; (decode only for swqueue) - */ - - ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) - + 5 + 8 * i; - - sprintf(ring->name, "vcn_dec_%d", i); - r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, - AMDGPU_RING_PRIO_DEFAULT, - &adev->vcn.inst[i].sched_score); - if (r) - return r; - } - for (j = 0; j < adev->vcn.num_enc_rings; ++j) { - /* VCN ENC TRAP */ - r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], - j + VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); - if (r) - return r; - - ring = &adev->vcn.inst[i].ring_enc[j]; - ring->use_doorbell = true; - - ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; - - if (unifiedQ_enabled) { - sprintf(ring->name, "vcn_unified%d", i); - r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, - AMDGPU_RING_PRIO_DEFAULT, NULL); - } else { - enum amdgpu_ring_priority_level hw_prio; + ring = &adev->vcn.inst[i].ring_enc[0]; + ring->use_doorbell = true; + ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; - hw_prio = amdgpu_vcn_get_enc_ring_prio(j); - sprintf(ring->name, "vcn_enc_%d.%d", i, j); - r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, - hw_prio, &adev->vcn.inst[i].sched_score); - } - if (r) - return r; - } + sprintf(ring->name, "vcn_unified_%d", i); - fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; - fw_shared->present_flag_0 = 0; + r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, + AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); + if (r) + return r; - if (unifiedQ_enabled) { - fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); - fw_shared->sq.is_enabled = 1; - } + fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; + fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); + fw_shared->sq.is_enabled = 1; if (amdgpu_vcnfw_log) amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); } - if (!unifiedQ_enabled) { - if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) - adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode; - } + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) + adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode; + return 0; } @@ -220,19 +151,19 @@ static int vcn_v4_0_sw_fini(void *handle) int i, r, idx; if (drm_dev_enter(&adev->ddev, &idx)) { - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - volatile struct amdgpu_vcn4_fw_shared *fw_shared; + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + volatile struct amdgpu_vcn4_fw_shared *fw_shared; - if (adev->vcn.harvest_config & (1 << i)) - continue; + if (adev->vcn.harvest_config & (1 << i)) + continue; - fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; - fw_shared->present_flag_0 = 0; - fw_shared->sq.is_enabled = 0; - } + fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; + fw_shared->present_flag_0 = 0; + fw_shared->sq.is_enabled = 0; + } - drm_dev_exit(idx); - } + drm_dev_exit(idx); + } r = amdgpu_vcn_suspend(adev); if (r) @@ -254,15 +185,13 @@ static int vcn_v4_0_hw_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_ring *ring; - int i, j, r; + int i, r; for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { if (adev->vcn.harvest_config & (1 << i)) continue; - if (unifiedQ_enabled) - ring = &adev->vcn.inst[i].ring_enc[0]; - else - ring = &adev->vcn.inst[i].ring_dec; + + ring = &adev->vcn.inst[i].ring_enc[0]; adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); @@ -270,13 +199,6 @@ static int vcn_v4_0_hw_init(void *handle) r = amdgpu_ring_test_helper(ring); if (r) goto done; - - for (j = 0; j < adev->vcn.num_enc_rings; ++j) { - ring = &adev->vcn.inst[i].ring_enc[j]; - r = amdgpu_ring_test_helper(ring); - if (r) - goto done; - } } done: @@ -464,7 +386,6 @@ static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); - } if (!indirect) @@ -888,7 +809,6 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; struct amdgpu_ring *ring; uint32_t tmp; - int i; /* disable register anti-hang mechanism */ WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, @@ -974,74 +894,32 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); - if (unifiedQ_enabled) { - ring = &adev->vcn.inst[inst_idx].ring_enc[0]; - fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; - } else - ring = &adev->vcn.inst[inst_idx].ring_dec; - - WREG32_SOC15(VCN, inst_idx, regVCN_RB4_DB_CTRL, - ring->doorbell_index << VCN_RB4_DB_CTRL__OFFSET__SHIFT | - VCN_RB4_DB_CTRL__EN_MASK); - - /* program the RB_BASE for ring buffer */ - WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO4, - lower_32_bits(ring->gpu_addr)); - WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI4, - upper_32_bits(ring->gpu_addr)); + ring = &adev->vcn.inst[inst_idx].ring_enc[0]; - WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE4, ring->ring_size / sizeof(uint32_t)); + WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); + WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); - /* reseting ring, fw should not check RB ring */ tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); - tmp &= ~(VCN_RB_ENABLE__RB4_EN_MASK); + tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); + fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; + WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); + WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); - /* Initialize the ring buffer's read and write pointers */ - tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR4); - WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR4, tmp); - ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR4); + tmp= RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); + WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); + ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); - tmp |= VCN_RB_ENABLE__RB4_EN_MASK; + tmp |= VCN_RB_ENABLE__RB1_EN_MASK; WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); + fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); - WREG32_SOC15(VCN, inst_idx, regUVD_SCRATCH2, 0); - - if (unifiedQ_enabled) - fw_shared->sq.queue_mode &= ~FW_QUEUE_RING_RESET; - - for (i = 0; i < adev->vcn.num_enc_rings; i++) { - ring = &adev->vcn.inst[inst_idx].ring_enc[i]; - - if (i) { - ring = &adev->vcn.inst[inst_idx].ring_enc[1]; - - WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO2, ring->gpu_addr); - WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); - WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE2, ring->ring_size / 4); - tmp= RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR2); - WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR2, tmp); - ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR2); - - WREG32_SOC15(VCN, inst_idx, regVCN_RB2_DB_CTRL, - ring->doorbell_index << VCN_RB2_DB_CTRL__OFFSET__SHIFT | - VCN_RB2_DB_CTRL__EN_MASK); - } else { - ring = &adev->vcn.inst[inst_idx].ring_enc[0]; - - WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); - WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); - WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); - tmp= RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); - WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); - ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); + WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, + ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | + VCN_RB1_DB_CTRL__EN_MASK); - WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, - ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | - VCN_RB1_DB_CTRL__EN_MASK); - } - } return 0; } @@ -1064,6 +942,8 @@ static int vcn_v4_0_start(struct amdgpu_device *adev) amdgpu_dpm_enable_uvd(adev, true); for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); continue; @@ -1081,15 +961,15 @@ static int vcn_v4_0_start(struct amdgpu_device *adev) /* enable VCPU clock */ WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), - UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); + UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); /* disable master interrupt */ WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, - ~UVD_MASTINT_EN__VCPU_EN_MASK); + ~UVD_MASTINT_EN__VCPU_EN_MASK); /* enable LMI MC and UMC channels */ WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, - ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); + ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; @@ -1099,10 +979,10 @@ static int vcn_v4_0_start(struct amdgpu_device *adev) /* setup regUVD_LMI_CTRL */ tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | - UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | - UVD_LMI_CTRL__MASK_MC_URGENT_MASK | - UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | - UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); + UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | + UVD_LMI_CTRL__MASK_MC_URGENT_MASK | + UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | + UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); /* setup regUVD_MPC_CNTL */ tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); @@ -1112,37 +992,37 @@ static int vcn_v4_0_start(struct amdgpu_device *adev) /* setup UVD_MPC_SET_MUXA0 */ WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, - ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | - (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | - (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | - (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); + ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | + (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | + (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | + (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); /* setup UVD_MPC_SET_MUXB0 */ WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, - ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | - (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | - (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | - (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); + ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | + (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | + (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | + (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); /* setup UVD_MPC_SET_MUX */ WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, - ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | - (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | - (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); + ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | + (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | + (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); vcn_v4_0_mc_resume(adev, i); /* VCN global tiling registers */ WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, - adev->gfx.config.gb_addr_config); + adev->gfx.config.gb_addr_config); /* unblock VCPU register access */ WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, - ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); + ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); /* release VCPU reset to boot */ WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, - ~UVD_VCPU_CNTL__BLK_RST_MASK); + ~UVD_VCPU_CNTL__BLK_RST_MASK); for (j = 0; j < 10; ++j) { uint32_t status; @@ -1166,13 +1046,13 @@ static int vcn_v4_0_start(struct amdgpu_device *adev) if (status & 2) break; - dev_err(adev->dev, "VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i); - WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), - UVD_VCPU_CNTL__BLK_RST_MASK, - ~UVD_VCPU_CNTL__BLK_RST_MASK); + dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); + WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), + UVD_VCPU_CNTL__BLK_RST_MASK, + ~UVD_VCPU_CNTL__BLK_RST_MASK); mdelay(10); WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, - ~UVD_VCPU_CNTL__BLK_RST_MASK); + ~UVD_VCPU_CNTL__BLK_RST_MASK); mdelay(10); r = -1; @@ -1180,78 +1060,43 @@ static int vcn_v4_0_start(struct amdgpu_device *adev) } if (r) { - dev_err(adev->dev, "VCN[%d] decode not responding, giving up!!!\n", i); + dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); return r; } /* enable master interrupt */ WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), - UVD_MASTINT_EN__VCPU_EN_MASK, - ~UVD_MASTINT_EN__VCPU_EN_MASK); + UVD_MASTINT_EN__VCPU_EN_MASK, + ~UVD_MASTINT_EN__VCPU_EN_MASK); /* clear the busy bit of VCN_STATUS */ WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, - ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); - - fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; - if (unifiedQ_enabled) { - ring = &adev->vcn.inst[i].ring_enc[0]; - fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; - } else { - ring = &adev->vcn.inst[i].ring_dec; + ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); - WREG32_SOC15(VCN, i, regVCN_RB4_DB_CTRL, - ring->doorbell_index << VCN_RB4_DB_CTRL__OFFSET__SHIFT | - VCN_RB4_DB_CTRL__EN_MASK); - - /* program the RB_BASE for ring buffer */ - WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO4, - lower_32_bits(ring->gpu_addr)); - WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI4, - upper_32_bits(ring->gpu_addr)); - - WREG32_SOC15(VCN, i, regUVD_RB_SIZE4, ring->ring_size / sizeof(uint32_t)); - - /* resetting ring, fw should not check RB ring */ - tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); - tmp &= ~(VCN_RB_ENABLE__RB4_EN_MASK); - WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); + ring = &adev->vcn.inst[i].ring_enc[0]; + WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, + ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | + VCN_RB1_DB_CTRL__EN_MASK); - /* Initialize the ring buffer's read and write pointers */ - tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR4); - WREG32_SOC15(VCN, i, regUVD_RB_WPTR4, tmp); - ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR4); + WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); + WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); - tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); - tmp |= VCN_RB_ENABLE__RB4_EN_MASK; - WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); + tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); + tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); + WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); + fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; + WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); + WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); - ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_RPTR4); - } - ring = &adev->vcn.inst[i].ring_enc[0]; - WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, - ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | - VCN_RB1_DB_CTRL__EN_MASK); tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); - WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); - WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); - WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); - if (unifiedQ_enabled) - fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); - else { - ring = &adev->vcn.inst[i].ring_enc[1]; - WREG32_SOC15(VCN, i, regVCN_RB2_DB_CTRL, - ring->doorbell_index << VCN_RB2_DB_CTRL__OFFSET__SHIFT | - VCN_RB2_DB_CTRL__EN_MASK); - tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR2); - WREG32_SOC15(VCN, i, regUVD_RB_WPTR2, tmp); - ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR2); - WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO2, ring->gpu_addr); - WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); - WREG32_SOC15(VCN, i, regUVD_RB_SIZE2, ring->ring_size / 4); - } + + tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); + tmp |= VCN_RB_ENABLE__RB1_EN_MASK; + WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); + fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); } return 0; @@ -1277,12 +1122,6 @@ static int vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); - tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR2); - SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR2, tmp, 0xFFFFFFFF); - - tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR4); - SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR4, tmp, 0xFFFFFFFF); - SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); @@ -1301,10 +1140,14 @@ static int vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) */ static int vcn_v4_0_stop(struct amdgpu_device *adev) { + volatile struct amdgpu_vcn4_fw_shared *fw_shared; uint32_t tmp; int i, r = 0; for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; + fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { r = vcn_v4_0_stop_dpg_mode(adev, i); continue; @@ -1414,8 +1257,6 @@ static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, /* unpause dpg, no need to wait */ reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); - SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); } adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; } @@ -1424,165 +1265,72 @@ static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, } /** - * vcn_v4_0_dec_ring_get_rptr - get read pointer + * vcn_v4_0_unified_ring_get_rptr - get unified read pointer * * @ring: amdgpu_ring pointer * - * Returns the current hardware read pointer + * Returns the current hardware unified read pointer */ -static uint64_t vcn_v4_0_dec_ring_get_rptr(struct amdgpu_ring *ring) +static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR4); + if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) + DRM_ERROR("wrong ring id is identified in %s", __func__); + + return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); } /** - * vcn_v4_0_dec_ring_get_wptr - get write pointer + * vcn_v4_0_unified_ring_get_wptr - get unified write pointer * * @ring: amdgpu_ring pointer * - * Returns the current hardware write pointer + * Returns the current hardware unified write pointer */ -static uint64_t vcn_v4_0_dec_ring_get_wptr(struct amdgpu_ring *ring) +static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; + if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) + DRM_ERROR("wrong ring id is identified in %s", __func__); + if (ring->use_doorbell) return *ring->wptr_cpu_addr; else - return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR4); + return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); } /** - * vcn_v4_0_dec_ring_set_wptr - set write pointer + * vcn_v4_0_unified_ring_set_wptr - set enc write pointer * * @ring: amdgpu_ring pointer * - * Commits the write pointer to the hardware + * Commits the enc write pointer to the hardware */ -static void vcn_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring) +static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { - WREG32_SOC15(VCN, ring->me, regUVD_SCRATCH2, - lower_32_bits(ring->wptr)); - } + if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) + DRM_ERROR("wrong ring id is identified in %s", __func__); if (ring->use_doorbell) { *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); } else { - WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR4, lower_32_bits(ring->wptr)); - } -} - -static const struct amdgpu_ring_funcs vcn_v4_0_dec_sw_ring_vm_funcs = { - .type = AMDGPU_RING_TYPE_VCN_DEC, - .align_mask = 0x3f, - .nop = VCN_DEC_SW_CMD_NO_OP, - .vmhub = AMDGPU_MMHUB_0, - .get_rptr = vcn_v4_0_dec_ring_get_rptr, - .get_wptr = vcn_v4_0_dec_ring_get_wptr, - .set_wptr = vcn_v4_0_dec_ring_set_wptr, - .emit_frame_size = - SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + - SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + - VCN_SW_RING_EMIT_FRAME_SIZE, - .emit_ib_size = 5, /* vcn_dec_sw_ring_emit_ib */ - .emit_ib = vcn_dec_sw_ring_emit_ib, - .emit_fence = vcn_dec_sw_ring_emit_fence, - .emit_vm_flush = vcn_dec_sw_ring_emit_vm_flush, - .test_ring = amdgpu_vcn_dec_sw_ring_test_ring, - .test_ib = amdgpu_vcn_dec_sw_ring_test_ib, - .insert_nop = amdgpu_ring_insert_nop, - .insert_end = vcn_dec_sw_ring_insert_end, - .pad_ib = amdgpu_ring_generic_pad_ib, - .begin_use = amdgpu_vcn_ring_begin_use, - .end_use = amdgpu_vcn_ring_end_use, - .emit_wreg = vcn_dec_sw_ring_emit_wreg, - .emit_reg_wait = vcn_dec_sw_ring_emit_reg_wait, - .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, -}; - -/** - * vcn_v4_0_enc_ring_get_rptr - get enc read pointer - * - * @ring: amdgpu_ring pointer - * - * Returns the current hardware enc read pointer - */ -static uint64_t vcn_v4_0_enc_ring_get_rptr(struct amdgpu_ring *ring) -{ - struct amdgpu_device *adev = ring->adev; - - if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) - return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); - else - return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR2); -} - -/** - * vcn_v4_0_enc_ring_get_wptr - get enc write pointer - * - * @ring: amdgpu_ring pointer - * - * Returns the current hardware enc write pointer - */ -static uint64_t vcn_v4_0_enc_ring_get_wptr(struct amdgpu_ring *ring) -{ - struct amdgpu_device *adev = ring->adev; - - if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { - if (ring->use_doorbell) - return *ring->wptr_cpu_addr; - else - return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); - } else { - if (ring->use_doorbell) - return *ring->wptr_cpu_addr; - else - return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR2); - } -} - -/** - * vcn_v4_0_enc_ring_set_wptr - set enc write pointer - * - * @ring: amdgpu_ring pointer - * - * Commits the enc write pointer to the hardware - */ -static void vcn_v4_0_enc_ring_set_wptr(struct amdgpu_ring *ring) -{ - struct amdgpu_device *adev = ring->adev; - - if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { - if (ring->use_doorbell) { - *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); - WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); - } else { - WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); - } - } else { - if (ring->use_doorbell) { - *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); - WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); - } else { - WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR2, lower_32_bits(ring->wptr)); - } + WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); } } -static const struct amdgpu_ring_funcs vcn_v4_0_enc_ring_vm_funcs = { +static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, .vmhub = AMDGPU_MMHUB_0, - .get_rptr = vcn_v4_0_enc_ring_get_rptr, - .get_wptr = vcn_v4_0_enc_ring_get_wptr, - .set_wptr = vcn_v4_0_enc_ring_set_wptr, + .get_rptr = vcn_v4_0_unified_ring_get_rptr, + .get_wptr = vcn_v4_0_unified_ring_get_wptr, + .set_wptr = vcn_v4_0_unified_ring_set_wptr, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + @@ -1594,7 +1342,7 @@ static const struct amdgpu_ring_funcs vcn_v4_0_enc_ring_vm_funcs = { .emit_fence = vcn_v2_0_enc_ring_emit_fence, .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, .test_ring = amdgpu_vcn_enc_ring_test_ring, - .test_ib = amdgpu_vcn_enc_ring_test_ib, + .test_ib = amdgpu_vcn_unified_ring_test_ib, .insert_nop = amdgpu_ring_insert_nop, .insert_end = vcn_v2_0_enc_ring_insert_end, .pad_ib = amdgpu_ring_generic_pad_ib, @@ -1606,13 +1354,13 @@ static const struct amdgpu_ring_funcs vcn_v4_0_enc_ring_vm_funcs = { }; /** - * vcn_v4_0_set_dec_ring_funcs - set dec ring functions + * vcn_v4_0_set_unified_ring_funcs - set unified ring functions * * @adev: amdgpu_device pointer * - * Set decode ring functions + * Set unified ring functions */ -static void vcn_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev) +static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev) { int i; @@ -1620,32 +1368,10 @@ static void vcn_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev) if (adev->vcn.harvest_config & (1 << i)) continue; - adev->vcn.inst[i].ring_dec.funcs = &vcn_v4_0_dec_sw_ring_vm_funcs; - adev->vcn.inst[i].ring_dec.me = i; - DRM_INFO("VCN(%d) decode software ring is enabled in VM mode\n", i); - } -} - -/** - * vcn_v4_0_set_enc_ring_funcs - set enc ring functions - * - * @adev: amdgpu_device pointer - * - * Set encode ring functions - */ -static void vcn_v4_0_set_enc_ring_funcs(struct amdgpu_device *adev) -{ - int i, j; - - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { - if (adev->vcn.harvest_config & (1 << i)) - continue; + adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_unified_ring_vm_funcs; + adev->vcn.inst[i].ring_enc[0].me = i; - for (j = 0; j < adev->vcn.num_enc_rings; ++j) { - adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v4_0_enc_ring_vm_funcs; - adev->vcn.inst[i].ring_enc[j].me = i; - } - DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i); + DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i); } } @@ -1798,18 +1524,9 @@ static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_ DRM_DEBUG("IH: VCN TRAP\n"); switch (entry->src_id) { - case VCN_4_0__SRCID__UVD_TRAP: - if (!unifiedQ_enabled) { - amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); - break; - } - break; case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); break; - case VCN_4_0__SRCID__UVD_ENC_LOW_LATENCY: - amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); - break; default: DRM_ERROR("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); -- cgit v1.2.3 From e751e4be1eec4d427d91583f31ce56ccb5286a27 Mon Sep 17 00:00:00 2001 From: Ruijing Dong Date: Tue, 14 Jun 2022 22:42:54 -0400 Subject: drm/amdgpu/vcn: adjust unified queue code format MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixed some errors and warnings found by checkpatch.pl. Acked-by: Christian König Signed-off-by: Ruijing Dong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 12 ++++++------ drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 8 ++++---- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index e62ff7db4736..fea436023351 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -730,8 +730,8 @@ error: return r; } -static uint32_t * amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib, - uint32_t ib_pack_in_dw, bool enc) +static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib, + uint32_t ib_pack_in_dw, bool enc) { uint32_t *ib_checksum; @@ -749,7 +749,7 @@ static uint32_t * amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib, } static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum, - uint32_t ib_pack_in_dw) + uint32_t ib_pack_in_dw) { uint32_t i; uint32_t checksum = 0; @@ -790,7 +790,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, /* single queue headers */ if (sq) { ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t) - + 4 + 2; /* engine info + decoding ib in dw */ + + 4 + 2; /* engine info + decoding ib in dw */ ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false); } @@ -896,7 +896,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand struct amdgpu_ib *ib_msg, struct dma_fence **fence) { - unsigned ib_size_dw = 16; + unsigned int ib_size_dw = 16; struct amdgpu_job *job; struct amdgpu_ib *ib; struct dma_fence *f = NULL; @@ -962,7 +962,7 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han struct amdgpu_ib *ib_msg, struct dma_fence **fence) { - unsigned ib_size_dw = 16; + unsigned int ib_size_dw = 16; struct amdgpu_job *job; struct amdgpu_ib *ib; struct dma_fence *f = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index d6f134ef9633..84ac2401895a 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -120,7 +120,7 @@ static int vcn_v4_0_sw_init(void *handle) sprintf(ring->name, "vcn_unified_%d", i); r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, - AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); + AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); if (r) return r; @@ -907,7 +907,7 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); - tmp= RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); + tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); @@ -1048,8 +1048,8 @@ static int vcn_v4_0_start(struct amdgpu_device *adev) dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), - UVD_VCPU_CNTL__BLK_RST_MASK, - ~UVD_VCPU_CNTL__BLK_RST_MASK); + UVD_VCPU_CNTL__BLK_RST_MASK, + ~UVD_VCPU_CNTL__BLK_RST_MASK); mdelay(10); WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, ~UVD_VCPU_CNTL__BLK_RST_MASK); -- cgit v1.2.3 From b3e73cbf17a95a85e3a943d7500e9e477d6ab9c3 Mon Sep 17 00:00:00 2001 From: Graham Sider Date: Wed, 18 May 2022 14:44:01 -0400 Subject: drm/amdgpu: Remove break for VMID loop TLB flush on MES Loop through all VMIDs for gmc_v10_0_flush_gpu_tlb_pasid and gmc_v11_0_flush_gpu_tlb_pasid (only if using MES for gmc_v10). This is required for MES due to use_different_vmid_compute causing SDMA queues to be assigned different VMIDs than compute for the same PASID. Signed-off-by: Graham Sider Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 ++- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 1 - 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 9077dfccaf3c..25d5743ae91b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -456,7 +456,8 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, gmc_v10_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, flush_type); } - break; + if (!adev->enable_mes) + break; } } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 9c225553f5b5..ecf41d8a8c7e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -344,7 +344,6 @@ static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, gmc_v11_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, flush_type); } - break; } } -- cgit v1.2.3 From 1f43b8903f3aae4a26a603c36f6d5dd25d6edb51 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 15 Jun 2022 12:02:08 -0400 Subject: drm/radeon: fix incorrrect SPDX-License-Identifiers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit radeon is MIT. This were incorrectly changed in commit b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") and commit d198b34f3855 (".gitignore: add SPDX License Identifier") and: commit ec8f24b7faaf ("treewide: Add SPDX license identifier - Makefile/Kconfig") Fixes: d198b34f3855 (".gitignore: add SPDX License Identifier") Fixes: ec8f24b7faaf ("treewide: Add SPDX license identifier - Makefile/Kconfig") Fixes: b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2053 Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/.gitignore | 2 +- drivers/gpu/drm/radeon/Kconfig | 2 +- drivers/gpu/drm/radeon/Makefile | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/radeon/.gitignore b/drivers/gpu/drm/radeon/.gitignore index 9c1a94153983..d8777383a64a 100644 --- a/drivers/gpu/drm/radeon/.gitignore +++ b/drivers/gpu/drm/radeon/.gitignore @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-only +# SPDX-License-Identifier: MIT mkregtable *_reg_safe.h diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig index 6f60f4840cc5..52819e7f1fca 100644 --- a/drivers/gpu/drm/radeon/Kconfig +++ b/drivers/gpu/drm/radeon/Kconfig @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-only +# SPDX-License-Identifier: MIT config DRM_RADEON_USERPTR bool "Always enable userptr support" depends on DRM_RADEON diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index ea5380e24c3c..e3ab3aca1396 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT # # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -- cgit v1.2.3 From f7ba887f606b1895dabf718547cf7397924f0d3a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 19 May 2022 10:21:08 -0400 Subject: drm/amdgpu: Adjust logic around GTT size (v3) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Certain GL unit tests for large textures can cause problems with the OOM killer since there is no way to link this memory to a process. This was originally mitigated (but not necessarily eliminated) by limiting the GTT size. The problem is this limit is often too low for many modern games so just make the limit 1/2 of system memory. The OOM accounting needs to be addressed, but we shouldn't prevent common 3D applications from being usable just to potentially mitigate that corner case. Set default GTT size to max(3G, 1/2 of system ram) by default. v2: drop previous logic and default to 3/4 of ram v3: default to half of ram to align with ttm v4: fix spelling in comment (Kent) Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1942 Reviewed-by: Marek Olšák Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index be6f76a30ac6..3b4c19412625 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1798,18 +1798,26 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) DRM_INFO("amdgpu: %uM of VRAM memory ready\n", (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); - /* Compute GTT size, either bsaed on 3/4th the size of RAM size + /* Compute GTT size, either based on 1/2 the size of RAM size * or whatever the user passed on module init */ if (amdgpu_gtt_size == -1) { struct sysinfo si; si_meminfo(&si); - gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), - adev->gmc.mc_vram_size), - ((uint64_t)si.totalram * si.mem_unit * 3/4)); - } - else + /* Certain GL unit tests for large textures can cause problems + * with the OOM killer since there is no way to link this memory + * to a process. This was originally mitigated (but not necessarily + * eliminated) by limiting the GTT size. The problem is this limit + * is often too low for many modern games so just make the limit 1/2 + * of system memory which aligns with TTM. The OOM accounting needs + * to be addressed, but we shouldn't prevent common 3D applications + * from being usable just to potentially mitigate that corner case. + */ + gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), + (u64)si.totalram * si.mem_unit / 2); + } else { gtt_size = (uint64_t)amdgpu_gtt_size << 20; + } /* Initialize GTT memory pool */ r = amdgpu_gtt_mgr_init(adev, gtt_size); -- cgit v1.2.3 From 6626c5a4ea2ef1bba3e02f75f797523e168fe28e Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Wed, 15 Jun 2022 23:34:53 +0800 Subject: drm/amdgpu/pm: adjust EccInfo_t struct The EccInfo_t struct in driver_if.h is as below in official release verion 68.55.0 typedef struct { uint64_t mca_umc_status; uint64_t mca_umc_addr; uint16_t ce_count_lo_chip; uint16_t ce_count_hi_chip; uint32_t eccPadding; uint64_t mca_ceumc_addr; } EccInfo_t; It's different from the debug version druing develop print correctable error address, so adjust EccInfo_t struct. Signed-off-by: Stanley.Yang Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h index 6f92038470ec..7a6075daa7b2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h @@ -521,12 +521,13 @@ typedef struct { typedef struct { uint64_t mca_umc_status; uint64_t mca_umc_addr; - uint64_t mca_ceumc_addr; uint16_t ce_count_lo_chip; uint16_t ce_count_hi_chip; uint32_t eccPadding; + + uint64_t mca_ceumc_addr; } EccInfo_V2_t; typedef struct { -- cgit v1.2.3 From 8748de873fedf4d55bdd99bbb738ee7ddf329792 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Wed, 20 Apr 2022 13:08:28 +0800 Subject: drm/amdgpu/gmc11: avoid cpu accessing registers to flush VM Due to gfxoff on, cpu accessing registers is not expected. Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 51 +++++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index ecf41d8a8c7e..e098b69d6321 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -259,6 +259,12 @@ static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, uint32_t vmhub, uint32_t flush_type) { + struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; + struct dma_fence *fence; + struct amdgpu_job *job; + + int r; + if ((vmhub == AMDGPU_GFXHUB_0) && !adev->gfx.is_poweron) return; @@ -282,8 +288,51 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, } mutex_lock(&adev->mman.gtt_window_lock); - gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0); + + if (vmhub == AMDGPU_MMHUB_0) { + gmc_v11_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); + mutex_unlock(&adev->mman.gtt_window_lock); + return; + } + + BUG_ON(vmhub != AMDGPU_GFXHUB_0); + + if (!adev->mman.buffer_funcs_enabled || + !adev->ib_pool_ready || + amdgpu_in_reset(adev) || + ring->sched.ready == false) { + gmc_v11_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); + mutex_unlock(&adev->mman.gtt_window_lock); + return; + } + + r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, + &job); + if (r) + goto error_alloc; + + job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); + job->vm_needs_flush = true; + job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; + amdgpu_ring_pad_ib(ring, &job->ibs[0]); + r = amdgpu_job_submit(job, &adev->mman.entity, + AMDGPU_FENCE_OWNER_UNDEFINED, &fence); + if (r) + goto error_submit; + + mutex_unlock(&adev->mman.gtt_window_lock); + + dma_fence_wait(fence, false); + dma_fence_put(fence); + + return; + +error_submit: + amdgpu_job_free(job); + +error_alloc: mutex_unlock(&adev->mman.gtt_window_lock); + DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); return; } -- cgit v1.2.3 From 51c45e450fc8529495bc85c2d8e309816cdcf959 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Fri, 10 Jun 2022 11:48:04 +0800 Subject: drm/amd/pm: skip to set mp1 unload state in special case set mp1 unload state will cause the SMC FW can't accept any SMU message, skip to set mp1 unload state to avoid following case fail: - runtime pm case. - gpu reset case. Fixes: 72aeb6ee0c78 ("drm/amd/pm: fix driver reload SMC firmware fail issue for smu13") Signed-off-by: Yang Wang Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 3d269d1c2749..fd79b213fab4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -1415,12 +1415,13 @@ static int smu_disable_dpms(struct smu_context *smu) switch (adev->ip_versions[MP1_HWIP][0]) { case IP_VERSION(13, 0, 0): case IP_VERSION(13, 0, 7): - ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); - if (ret) { - dev_err(adev->dev, "Fail set mp1 state to UNLOAD!\n"); - return ret; + if (!(adev->in_runpm || amdgpu_in_reset(adev))) { + ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); + if (ret) { + dev_err(adev->dev, "Fail set mp1 state to UNLOAD!\n"); + return ret; + } } - return 0; default: break; -- cgit v1.2.3 From 1320d6c7b0deb7219701a55397e93e6c73d00366 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Mon, 13 Jun 2022 23:53:52 -0500 Subject: drm/amd: Don't show warning on reading vbios values for SMU13 3.1 Some APUs with SMU13 are showing the following message: `amdgpu 0000:63:00.0: amdgpu: Unexpected and unhandled version: 3.1` This warning isn't relevant for smu info 3.1, as no bootup information is present in the table. Fixes: 593a54f18031 ("drm/amd/pm: correct the way for retrieving bootup clocks") Signed-off-by: Mario Limonciello Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index f18f9605e586..0e59ab2192bf 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -731,6 +731,8 @@ int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu) smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz; smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz; smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz; + } else if ((frev == 3) && (crev == 1)) { + return 0; } else if ((frev == 4) && (crev == 0)) { smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header; -- cgit v1.2.3 From 262236b4f5a7d2fe31ed31d34669a9ea4f1c3272 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Thu, 16 Jun 2022 16:44:55 -0400 Subject: drm/amd/display: add missing reg defs for DCN3x HUBBUB [Why&How] The omitted register definition caused call traces like: [ 3.811215] WARNING: CPU: 7 PID: 794 at drivers/gpu/drm/amd/amdgpu/../display/dc/dc_helper.c:120 set_reg_field_values.constprop.0+0xc7/0xe0 [amdgpu] [ 3.811406] Modules linked in: amdgpu(+) drm_ttm_helper ttm iommu_v2 gpu_sched drm_kms_helper cfbfillrect syscopyarea cfbimgblt sysfillrect sysimgblt fb_sys_fops cfbcopyarea drm i2c_piix4 drm_panel_orientation_quirks [ 3.811419] CPU: 7 PID: 794 Comm: systemd-udevd Not tainted 5.16.0-kfd+ #132 [ 3.811422] Hardware name: System manufacturer System Product Name/ROG STRIX B450-F GAMING, BIOS 3003 12/09/2019 [ 3.811425] RIP: 0010:set_reg_field_values.constprop.0+0xc7/0xe0 [amdgpu] [ 3.811615] Code: 08 49 89 51 08 8b 08 48 8d 42 08 49 89 41 08 44 8b 02 48 8d 50 08 0f b6 c9 49 89 51 08 8b 00 45 85 c0 75 b3 0f 0b eb af 5d c3 <0f> 0b e9 48 ff ff ff 49 8b 51 08 eb d0 49 8b 41 08 eb d5 66 0f 1f [ 3.811619] RSP: 0018:ffffb8c1c04cf640 EFLAGS: 00010246 [ 3.811621] RAX: 0000000000000000 RBX: ffff96f2100d8800 RCX: 0000000000000000 [ 3.811623] RDX: 0000000000000000 RSI: 0000000000000001 RDI: ffffb8c1c04cf650 [ 3.811625] RBP: ffffb8c1c04cf640 R08: 000000000000047f R09: ffffb8c1c04cf658 [ 3.811627] R10: ffff96f5161ff000 R11: ffff96f5161ff000 R12: ffff96f204afb9c0 [ 3.811629] R13: 0000000000000000 R14: ffff96f202b94c00 R15: ffffb8c1c04cf718 [ 3.811631] FS: 00007fe07c2e2880(0000) GS:ffff96f5059c0000(0000) knlGS:0000000000000000 [ 3.811634] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 3.811636] CR2: 0000559634ab57b8 CR3: 0000000120674000 CR4: 00000000003506e0 [ 3.811637] Call Trace: [ 3.811640] [ 3.811642] generic_reg_update_ex+0x69/0x200 [amdgpu] [ 3.811831] ? _printk+0x58/0x6f [ 3.811836] dcn32_init_crb+0x18f/0x1b0 [amdgpu] [ 3.812031] dcn32_init_hw+0x379/0x6a0 [amdgpu] [ 3.812223] dc_hardware_init+0xba/0x100 [amdgpu] [ 3.812415] amdgpu_dm_init.isra.0.cold+0x166/0x1867 [amdgpu] [ 3.812616] ? dev_vprintk_emit+0x139/0x15d [ 3.812621] ? dev_printk_emit+0x4e/0x65 [ 3.812624] dm_hw_init+0x12/0x30 [amdgpu] [ 3.812820] amdgpu_device_init.cold+0x130d/0x178c [amdgpu] [ 3.813017] ? pci_read_config_word+0x25/0x40 [ 3.813021] amdgpu_driver_load_kms+0x1a/0x130 [amdgpu] [ 3.813178] amdgpu_pci_probe+0x130/0x330 [amdgpu] Fixes: 4f29f9cf092b ("drm/amd: add register headers for DCN32/321") Signed-off-by: Aurabindo Pillai Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h | 2 ++ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h | 2 ++ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h | 3 +++ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h | 2 ++ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h | 4 ++++ 5 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h index 8d3ea8ee5b3b..3bae6e558971 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h @@ -65,6 +65,7 @@ SR(DCHUBBUB_DET3_CTRL),\ SR(DCHUBBUB_COMPBUF_CTRL),\ SR(COMPBUF_RESERVED_SPACE),\ + SR(DCHUBBUB_DEBUG_CTRL_0),\ SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL),\ SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A),\ SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B),\ @@ -118,6 +119,7 @@ HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \ HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \ HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, mask_sh),\ HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE, mask_sh),\ HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, mask_sh),\ HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE, mask_sh),\ diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h index 6f84ea5c006f..14c29ce4c7b3 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h @@ -1807,6 +1807,8 @@ #define regDCHUBBUB_DET2_CTRL_BASE_IDX 2 #define regDCHUBBUB_DET3_CTRL 0x04be #define regDCHUBBUB_DET3_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DEBUG_CTRL_0 0x04c5 +#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 #define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04c0 #define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2 #define regCOMPBUF_MEM_PWR_CTRL_1 0x04c1 diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h index d42f91560bb9..0691e328d0f0 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h @@ -6348,6 +6348,9 @@ #define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK 0x00000FFFL #define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS_MASK 0x0FFF0000L +//DCHUBBUB_DEBUG_CTRL_0 +#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 +#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x07FF0000L // addressBlock: dcn_dc_dchubbubl_hubbub_vmrq_if_dispdec //DCN_VM_CONTEXT0_CNTL diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h index e40a924c02ce..3bd8792fd7b3 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h @@ -1817,6 +1817,8 @@ #define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 #define regCOMPBUF_RESERVED_SPACE 0x04c4 #define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2 +#define regDCHUBBUB_DEBUG_CTRL_0 0x04c5 +#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 // addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h index 23faa628cd59..e82dffc2b9b0 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h @@ -6350,6 +6350,10 @@ #define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK 0x00000FFFL #define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS_MASK 0x0FFF0000L +//DCHUBBUB_DEBUG_CTRL_0 +#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 +#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x07FF0000L + // addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec //DCN_VM_CONTEXT0_CNTL -- cgit v1.2.3 From 0081bc072837b66587904e6988aea1e0845b0294 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Mon, 20 Jun 2022 19:32:33 +0800 Subject: drm/amdgpu: add LSDMA block for LSDMA v6.0.1 This patch adds LSDMA ip block for LSDMA v6.0.1. Signed-off-by: Yifan Zhang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 11bbd76c581c..37234c2998d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -2333,6 +2333,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) switch (adev->ip_versions[LSDMA_HWIP][0]) { case IP_VERSION(6, 0, 0): + case IP_VERSION(6, 0, 1): case IP_VERSION(6, 0, 2): adev->lsdma.funcs = &lsdma_v6_0_funcs; break; -- cgit v1.2.3 From 5d763a9955f0fbf2681a2f1fa87c416056bd0c89 Mon Sep 17 00:00:00 2001 From: Cruise Hung Date: Mon, 6 Jun 2022 22:12:39 +0800 Subject: drm/amd/display: Remove compiler warning Tested-by: Daniel Wheeler Reviewed-by: Aric Cyr Acked-by: Rodrigo Siqueira Signed-off-by: Cruise Hung Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/include/fixed31_32.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h index 22053d7ea6ce..ece97ae0e826 100644 --- a/drivers/gpu/drm/amd/display/include/fixed31_32.h +++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h @@ -322,7 +322,7 @@ struct fixed31_32 dc_fixpt_sqr(struct fixed31_32 arg); */ static inline struct fixed31_32 dc_fixpt_div_int(struct fixed31_32 arg1, long long arg2) { - return dc_fixpt_from_fraction(arg1.value, dc_fixpt_from_int(arg2).value); + return dc_fixpt_from_fraction(arg1.value, dc_fixpt_from_int((int)arg2).value); } /* -- cgit v1.2.3 From 4dd905fd9429626937107ca13770aa836c8a7e6e Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Wed, 15 Jun 2022 17:30:05 -0500 Subject: drm/amd: Revert "drm/amd/display: keep eDP Vdd on when eDP stream is already enabled" A variety of Lenovo machines with Rembrandt APUs and OLED panels have stopped showing the display at login. This behavior clears up after leaving it idle and moving the mouse or touching keyboard. It was bisected to be caused by commit 559e2655220d ("drm/amd/display: keep eDP Vdd on when eDP stream is already enabled"). Revert this commit to fix the issue. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2047 Reported-by: Aaron Ma Fixes: 559e2655220d ("drm/amd/display: keep eDP Vdd on when eDP stream is already enabled") Signed-off-by: Mario Limonciello Tested-by: Mark Pearson Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 24 ++-------------------- 1 file changed, 2 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index e7944c881148..8662703f306c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1776,29 +1776,9 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) break; } } - - /* - * TO-DO: So far the code logic below only addresses single eDP case. - * For dual eDP case, there are a few things that need to be - * implemented first: - * - * 1. Change the fastboot logic above, so eDP link[0 or 1]'s - * stream[0 or 1] will all be checked. - * - * 2. Change keep_edp_vdd_on to an array, and maintain keep_edp_vdd_on - * for each eDP. - * - * Once above 2 things are completed, we can then change the logic below - * correspondingly, so dual eDP case will be fully covered. - */ - - // We are trying to enable eDP, don't power down VDD if eDP stream is existing - if ((edp_stream_num == 1 && edp_streams[0] != NULL) || can_apply_edp_fast_boot) { + // We are trying to enable eDP, don't power down VDD + if (can_apply_edp_fast_boot) keep_edp_vdd_on = true; - DC_LOG_EVENT_LINK_TRAINING("Keep eDP Vdd on\n"); - } else { - DC_LOG_EVENT_LINK_TRAINING("No eDP stream enabled, turn eDP Vdd off\n"); - } } // Check seamless boot support -- cgit v1.2.3 From 10a36226157035e84aaa58e1699a32b3de2755af Mon Sep 17 00:00:00 2001 From: Wayne Lin Date: Wed, 13 Apr 2022 15:52:48 +0800 Subject: drm/amd/display: Revert "drm/amd/display: Add flag to detect dpms force off during HPD" This reverts commit 035f54969bb2c1a5ced52f43e4ef393e0c0f6bfa. The reverted commit was trying to fix side effect brought by commit 3c4d55c9b9be ("drm/amd/display: turn DPMS off on connector unplug") However, * This reverted commit will have mst case never call dm_set_dpms_off() which conflicts the idea of original commit 3c4d55c9b9be ("drm/amd/display: turn DPMS off on connector unplug") That's due to dm_crtc_state is always null since the input parameter aconnector is the root device (source) of mst topology. It's not an end stream sink within the mst topology. * Setting dpms off should be triggered by usermode. Besdies, it seems usermode does release relevant resource for mst & non-mst case when unplug connecotr now. Which means we no longer need both commits now: commit 3c4d55c9b9be ("drm/amd/display: turn DPMS off on connector unplug") commit 035f54969bb2 ("drm/amd/display: Add flag to detect dpms force off during HPD") Tested-by: Daniel Wheeler Reviewed-by: Aurabindo Jayamohanan Pillai Acked-by: Rodrigo Siqueira Acked-by: Lyude Paul Signed-off-by: Wayne Lin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 ++++++------------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 -- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 15 +++++---------- 3 files changed, 11 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 60fb99b74713..6c3288980e1e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2583,7 +2583,7 @@ cleanup: return; } -static void dm_set_dpms_off(struct dc_link *link, struct dm_crtc_state *acrtc_state) +static void dm_set_dpms_off(struct dc_link *link) { struct dc_stream_state *stream_state; struct amdgpu_dm_connector *aconnector = link->priv; @@ -2604,7 +2604,6 @@ static void dm_set_dpms_off(struct dc_link *link, struct dm_crtc_state *acrtc_st } stream_update.stream = stream_state; - acrtc_state->force_dpms_off = true; dc_commit_updates_for_stream(stream_state->ctx->dc, NULL, 0, stream_state, &stream_update, stream_state->ctx->dc->current_state); @@ -3061,16 +3060,13 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) struct drm_device *dev = connector->dev; enum dc_connection_type new_connection_type = dc_connection_none; struct amdgpu_device *adev = drm_to_adev(dev); +#ifdef CONFIG_DRM_AMD_DC_HDCP struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); - struct dm_crtc_state *dm_crtc_state = NULL; +#endif if (adev->dm.disable_hpd_irq) return; - if (dm_con_state->base.state && dm_con_state->base.crtc) - dm_crtc_state = to_dm_crtc_state(drm_atomic_get_crtc_state( - dm_con_state->base.state, - dm_con_state->base.crtc)); /* * In case of failure or MST no need to update connector status or notify the OS * since (for MST case) MST does this in its own context. @@ -3101,9 +3097,8 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { if (new_connection_type == dc_connection_none && - aconnector->dc_link->type == dc_connection_none && - dm_crtc_state) - dm_set_dpms_off(aconnector->dc_link, dm_crtc_state); + aconnector->dc_link->type == dc_connection_none) + dm_set_dpms_off(aconnector->dc_link); amdgpu_dm_update_connector_after_detect(aconnector); @@ -6840,7 +6835,6 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc) state->freesync_config = cur->freesync_config; state->cm_has_degamma = cur->cm_has_degamma; state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; - state->force_dpms_off = cur->force_dpms_off; state->mpo_requested = cur->mpo_requested; /* TODO Duplicate dc_stream after objects are stream object is flattened */ @@ -9579,8 +9573,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, * and rely on sending it from software. */ if (acrtc_attach->base.state->event && - acrtc_state->active_planes > 0 && - !acrtc_state->force_dpms_off) { + acrtc_state->active_planes > 0) { drm_crtc_vblank_get(pcrtc); spin_lock_irqsave(&pcrtc->dev->event_lock, flags); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index aa34c0068f41..2e351204cc2d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -639,8 +639,6 @@ struct dm_crtc_state { bool dsc_force_changed; bool vrr_supported; - - bool force_dpms_off; struct mod_freesync_config freesync_config; struct dc_info_packet vrr_infopacket; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index fcafe07ed908..a4191b2b4c65 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -448,7 +448,6 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) struct mod_hdcp_display *display = &hdcp_work[link_index].display; struct mod_hdcp_link *link = &hdcp_work[link_index].link; struct drm_connector_state *conn_state; - struct dc_sink *sink = NULL; bool link_is_hdcp14 = false; if (config->dpms_off) { @@ -462,13 +461,8 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) display->index = aconnector->base.index; display->state = MOD_HDCP_DISPLAY_ACTIVE; - if (aconnector->dc_sink) - sink = aconnector->dc_sink; - else if (aconnector->dc_em_sink) - sink = aconnector->dc_em_sink; - - if (sink != NULL) - link->mode = mod_hdcp_signal_type_to_operation_mode(sink->sink_signal); + if (aconnector->dc_sink != NULL) + link->mode = mod_hdcp_signal_type_to_operation_mode(aconnector->dc_sink->sink_signal); display->controller = CONTROLLER_ID_D0 + config->otg_inst; display->dig_fe = config->dig_fe; @@ -478,8 +472,9 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) link->link_enc_idx = config->link_enc_idx; link->dio_output_id = config->dio_output_idx; link->phy_idx = config->phy_idx; - if (sink) - link_is_hdcp14 = dc_link_is_hdcp14(aconnector->dc_link, sink->sink_signal); + + link->hdcp_supported_informational = dc_link_is_hdcp14(aconnector->dc_link, + aconnector->dc_sink->sink_signal) ? 1 : 0; link->hdcp_supported_informational = link_is_hdcp14; link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw; link->dp.assr_enabled = config->assr_enabled; -- cgit v1.2.3 From 052eaf6af846e59073a842e9b9517ba9d3f76d4a Mon Sep 17 00:00:00 2001 From: Wayne Lin Date: Wed, 13 Apr 2022 15:53:29 +0800 Subject: drm/amd/display: Revert "drm/amd/display: turn DPMS off on connector unplug" This reverts commit 3c4d55c9b9becedd8d31a7c96783a364533713ab. Revert the commit because: - It's incomplete of the function dm_set_dpms_off() for mst case. For stream sinks whithin the same mst topology, they share the same dc_link. dm_set_dpms_off() tries to update one mst stream only which is incomplete. - Setting dpms off should be triggered by usermode. Besdies, it seems usermode does release relevant resource for mst & non-mst case when unplug connecotr now. Tested-by: Daniel Wheeler Reviewed-by: Aurabindo Jayamohanan Pillai Acked-by: Rodrigo Siqueira Acked-by: Lyude Paul Signed-off-by: Wayne Lin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 31 ----------------------- drivers/gpu/drm/amd/display/dc/core/dc.c | 13 ---------- drivers/gpu/drm/amd/display/dc/dc_stream.h | 1 - 3 files changed, 45 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6c3288980e1e..986aeaf78ac0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2583,33 +2583,6 @@ cleanup: return; } -static void dm_set_dpms_off(struct dc_link *link) -{ - struct dc_stream_state *stream_state; - struct amdgpu_dm_connector *aconnector = link->priv; - struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); - struct dc_stream_update stream_update; - bool dpms_off = true; - - memset(&stream_update, 0, sizeof(stream_update)); - stream_update.dpms_off = &dpms_off; - - mutex_lock(&adev->dm.dc_lock); - stream_state = dc_stream_find_from_link(link); - - if (stream_state == NULL) { - DRM_DEBUG_DRIVER("Error finding stream state associated with link!\n"); - mutex_unlock(&adev->dm.dc_lock); - return; - } - - stream_update.stream = stream_state; - dc_commit_updates_for_stream(stream_state->ctx->dc, NULL, 0, - stream_state, &stream_update, - stream_state->ctx->dc->current_state); - mutex_unlock(&adev->dm.dc_lock); -} - static int dm_resume(void *handle) { struct amdgpu_device *adev = handle; @@ -3096,10 +3069,6 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) drm_kms_helper_connector_hotplug_event(connector); } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { - if (new_connection_type == dc_connection_none && - aconnector->dc_link->type == dc_connection_none) - dm_set_dpms_off(aconnector->dc_link); - amdgpu_dm_update_connector_after_detect(aconnector); drm_modeset_lock_all(dev); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 48a14a5bda56..146fd4b864b2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3325,19 +3325,6 @@ struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i) return NULL; } -struct dc_stream_state *dc_stream_find_from_link(const struct dc_link *link) -{ - uint8_t i; - struct dc_context *ctx = link->ctx; - - for (i = 0; i < ctx->dc->current_state->stream_count; i++) { - if (ctx->dc->current_state->streams[i]->link == link) - return ctx->dc->current_state->streams[i]; - } - - return NULL; -} - enum dc_irq_source dc_interrupt_to_irq_source( struct dc *dc, uint32_t src_id, diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 5a894c19b0ea..6f79327e0035 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -351,7 +351,6 @@ void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream); uint8_t dc_get_current_stream_count(struct dc *dc); struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i); -struct dc_stream_state *dc_stream_find_from_link(const struct dc_link *link); /* * Return the current frame counter. -- cgit v1.2.3 From 84a8b3908285d007db49532fd4b51d4b183d1242 Mon Sep 17 00:00:00 2001 From: Wayne Lin Date: Tue, 12 Apr 2022 21:18:00 +0800 Subject: drm/amd/display: Release remote dc_sink under mst scenario [Why] Observe that we have several problems while releasing remote dc_sink under mst cases. - When unplug mst branch device from the source, we now try to free all remote dc_sinks in dm_helpers_dp_mst_stop_top_mgr(). However, there are bugs while we're releasing dc_sinks here. First of all, link->remote_sinks[] array get shuffled within dc_link_remove_remote_sink(). As the result, increasing the array index within the releasing loop is wrong. Secondly, it tries to call dc_sink_release() to release the dc_sink of the same aconnector every time in the loop. Which can't release dc_sink of all aconnector in the mst topology. - There is no code path for us to release remote dc_sink for disconnected sst monitor which unplug event is notified by CSN sideband message. Which means we'll use stale dc_sink data to represent later on connected monitor. Also, has chance to break the maximum remote dc_sink number constraint. [How] Distinguish unplug event of mst scenario into 2 cases. * Unplug sst/legacy stream sink off the mst topology - Release related remote dc_sink in detec_ctx(). * Unplug mst branch device off the mst topology - Release related remote dc_sink in early_unregister() Tested-by: Daniel Wheeler Reviewed-by: Aurabindo Jayamohanan Pillai Acked-by: Rodrigo Siqueira Acked-by: Lyude Paul Signed-off-by: Wayne Lin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 ++-- .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 18 +----------- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 34 ++++++++++++++++++++-- 3 files changed, 35 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 986aeaf78ac0..9039c2fbabe2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2201,7 +2201,8 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend) } else { ret = drm_dp_mst_topology_mgr_resume(mgr, true); if (ret < 0) { - drm_dp_mst_topology_mgr_set_mst(mgr, false); + dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, + aconnector->dc_link); need_hotplug = true; } } @@ -10606,7 +10607,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, * added MST connectors not found in existing crtc_state in the chained mode * TODO: need to dig out the root cause of that */ - if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port)) + if (!aconnector) goto skip_modeset; if (modereset_required(new_crtc_state)) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 7c799ddc1d27..137645d40b72 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -451,7 +451,6 @@ bool dm_helpers_dp_mst_stop_top_mgr( struct dc_link *link) { struct amdgpu_dm_connector *aconnector = link->priv; - uint8_t i; if (!aconnector) { DRM_ERROR("Failed to find connector for link!"); @@ -463,22 +462,7 @@ bool dm_helpers_dp_mst_stop_top_mgr( if (aconnector->mst_mgr.mst_state == true) { drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false); - - for (i = 0; i < MAX_SINKS_PER_LINK; i++) { - if (link->remote_sinks[i] == NULL) - continue; - - if (link->remote_sinks[i]->sink_signal == - SIGNAL_TYPE_DISPLAY_PORT_MST) { - dc_link_remove_remote_sink(link, link->remote_sinks[i]); - - if (aconnector->dc_sink) { - dc_sink_release(aconnector->dc_sink); - aconnector->dc_sink = NULL; - aconnector->dc_link->cur_link_settings.lane_count = 0; - } - } - } + link->cur_link_settings.lane_count = 0; } return false; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 7e246a798c8a..26f733b2faa0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -140,11 +140,28 @@ amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) static void amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) { - struct amdgpu_dm_connector *amdgpu_dm_connector = + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); - struct drm_dp_mst_port *port = amdgpu_dm_connector->port; + struct drm_dp_mst_port *port = aconnector->port; + struct amdgpu_dm_connector *root = aconnector->mst_port; + struct dc_link *dc_link = aconnector->dc_link; + struct dc_sink *dc_sink = aconnector->dc_sink; drm_dp_mst_connector_early_unregister(connector, port); + + /* + * Release dc_sink for connector which its attached port is + * no longer in the mst topology + */ + drm_modeset_lock(&root->mst_mgr.base.lock, NULL); + if (dc_sink) { + if (dc_link->sink_count) + dc_link_remove_remote_sink(dc_link, dc_sink); + + dc_sink_release(dc_sink); + aconnector->dc_sink = NULL; + } + drm_modeset_unlock(&root->mst_mgr.base.lock); } static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { @@ -351,7 +368,7 @@ dm_dp_mst_detect(struct drm_connector *connector, return connector_status_disconnected; connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr, - aconnector->port); + aconnector->port); if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) { uint8_t dpcd_rev; @@ -385,6 +402,17 @@ dm_dp_mst_detect(struct drm_connector *connector, port->dpcd_rev = 0; } + /* + * Release dc_sink for connector which unplug event is notified by CSN msg + */ + if (connection_status == connector_status_disconnected && aconnector->dc_sink) { + if (aconnector->dc_link->sink_count) + dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink); + + dc_sink_release(aconnector->dc_sink); + aconnector->dc_sink = NULL; + } + return connection_status; } -- cgit v1.2.3 From 4d31819a3746b1f33a915546a4b1aa19374d1544 Mon Sep 17 00:00:00 2001 From: Wayne Lin Date: Tue, 31 May 2022 18:14:41 +0800 Subject: drm/amd/display: Take emulated dc_sink into account for HDCP [Why] While updating the config of hdcp, we use the sink_singal type of the dc_sink to decide the HDCP operation mode. However, it doesn't consider the case when the sink is a emulated one. [How] Take dc_em_sink into account while updating HDCP config. Tested-by: Daniel Wheeler Reviewed-by: Aurabindo Jayamohanan Pillai Acked-by: Rodrigo Siqueira Signed-off-by: Wayne Lin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index a4191b2b4c65..d7c41c133e2c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -448,6 +448,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) struct mod_hdcp_display *display = &hdcp_work[link_index].display; struct mod_hdcp_link *link = &hdcp_work[link_index].link; struct drm_connector_state *conn_state; + struct dc_sink *sink = NULL; bool link_is_hdcp14 = false; if (config->dpms_off) { @@ -461,8 +462,13 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) display->index = aconnector->base.index; display->state = MOD_HDCP_DISPLAY_ACTIVE; - if (aconnector->dc_sink != NULL) - link->mode = mod_hdcp_signal_type_to_operation_mode(aconnector->dc_sink->sink_signal); + if (aconnector->dc_sink) + sink = aconnector->dc_sink; + else if (aconnector->dc_em_sink) + sink = aconnector->dc_em_sink; + + if (sink != NULL) + link->mode = mod_hdcp_signal_type_to_operation_mode(sink->sink_signal); display->controller = CONTROLLER_ID_D0 + config->otg_inst; display->dig_fe = config->dig_fe; @@ -473,8 +479,8 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) link->dio_output_id = config->dio_output_idx; link->phy_idx = config->phy_idx; - link->hdcp_supported_informational = dc_link_is_hdcp14(aconnector->dc_link, - aconnector->dc_sink->sink_signal) ? 1 : 0; + if (sink) + link_is_hdcp14 = dc_link_is_hdcp14(aconnector->dc_link, sink->sink_signal); link->hdcp_supported_informational = link_is_hdcp14; link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw; link->dp.assr_enabled = config->assr_enabled; -- cgit v1.2.3 From ec457f8378901d673b841e81d289b0165286db7f Mon Sep 17 00:00:00 2001 From: Ian Chen Date: Mon, 16 May 2022 15:35:34 +0800 Subject: drm/amd/display: Drop unnecessary detect link code Delete unnecessary codes in detect_link_and_local_sink. We already have correct stop logic in dc_link_detect. Tested-by: Daniel Wheeler Reviewed-by: Wenjing Liu Acked-by: Rodrigo Siqueira Signed-off-by: Ian Chen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 199868925fe4..fac27b45230f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1142,11 +1142,6 @@ static bool detect_link_and_local_sink(struct dc_link *link, (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)) converter_disable_audio = true; - - // link switch from MST to non-MST stop topology manager - if (pre_connection_type == dc_connection_mst_branch && - link->type != dc_connection_mst_branch) - dm_helpers_dp_mst_stop_top_mgr(link->ctx, link); break; } -- cgit v1.2.3 From f04d275d94e164d24516c32437c988a323018f63 Mon Sep 17 00:00:00 2001 From: hersen wu Date: Sun, 29 May 2022 12:12:32 -0400 Subject: drm/amd/display: add mst port output bw check [Why] when connect one 4k@144hz dp to dsc mst hub, 4k@144hz mode is in valid mode list. but some mst hub port output bandwidth does not support 4k@144hz. [How] add mst port output bandwidth checks, include full_pbn, branch max throughput mps. Tested-by: Daniel Wheeler Reviewed-by: Jerry Zuo Acked-by: Rodrigo Siqueira Signed-off-by: hersen wu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++-- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 3 +- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 36 ++++++++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.h | 4 +++ 4 files changed, 48 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9039c2fbabe2..b3ab2a3ea29c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7260,7 +7260,11 @@ create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, break; } - dc_result = dc_validate_stream(adev->dm.dc, stream); + if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) + dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); + + if (dc_result == DC_OK) + dc_result = dc_validate_stream(adev->dm.dc, stream); if (dc_result != DC_OK) { DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n", @@ -7560,7 +7564,7 @@ static void dm_encoder_helper_disable(struct drm_encoder *encoder) } -static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth) +int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) { switch (display_color_depth) { case COLOR_DEPTH_666: diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 2e351204cc2d..547fc1547977 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -583,7 +583,6 @@ struct amdgpu_dm_connector { struct drm_dp_mst_port *port; struct amdgpu_dm_connector *mst_port; struct drm_dp_aux *dsc_aux; - /* TODO see if we can merge with ddc_bus or make a dm_connector */ struct amdgpu_i2c_adapter *i2c; @@ -747,4 +746,6 @@ int dm_atomic_get_state(struct drm_atomic_state *state, struct amdgpu_dm_connector * amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, struct drm_crtc *crtc); + +int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); #endif /* __AMDGPU_DM_H__ */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 26f733b2faa0..f3ce37664143 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1353,4 +1353,40 @@ clean_exit: return (ret == 0); } + #endif + +enum dc_status dm_dp_mst_is_port_support_mode( + struct amdgpu_dm_connector *aconnector, + struct dc_stream_state *stream) +{ + int bpp, pbn, branch_max_throughput_mps = 0; + + /* check if mode could be supported within fUll_pbn */ + bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3; + pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false); + if (pbn > aconnector->port->full_pbn) + return DC_FAIL_BANDWIDTH_VALIDATE; + + /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */ + switch (stream->timing.pixel_encoding) { + case PIXEL_ENCODING_RGB: + case PIXEL_ENCODING_YCBCR444: + branch_max_throughput_mps = + aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps; + break; + case PIXEL_ENCODING_YCBCR422: + case PIXEL_ENCODING_YCBCR420: + branch_max_throughput_mps = + aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps; + break; + default: + break; + } + + if (branch_max_throughput_mps != 0 && + ((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000)) + return DC_FAIL_BANDWIDTH_VALIDATE; + + return DC_OK; +} diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h index 2e13027d9b88..b92a7c5671aa 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h @@ -63,4 +63,8 @@ bool pre_validate_dsc(struct drm_atomic_state *state, struct dm_atomic_state **dm_state_ptr, struct dsc_mst_fairness_vars *vars); +enum dc_status dm_dp_mst_is_port_support_mode( + struct amdgpu_dm_connector *aconnector, + struct dc_stream_state *stream); + #endif -- cgit v1.2.3 From 06f2f7772dc7ff2e3734e654cb2d0b588076860d Mon Sep 17 00:00:00 2001 From: Sung Joon Kim Date: Tue, 7 Jun 2022 11:36:29 -0400 Subject: drm/amd/display: Fix eDP not light up on resume [why] Only on VG, if external display is disconnected during S3 suspend, the internal panel doesn't light up on resume because we set the power state using an unsupported DPCD register SET_POWER. To check the register is supported, we need to check SET_POWER_CAPABLE first which is eDP-specific DPCD register field. [how] Check the SET_POWER_CAPABLE register field and decide the control of the eDP power state based on the read register value. Tested-by: Daniel Wheeler Reviewed-by: Agustin Gutierrez Acked-by: Rodrigo Siqueira Signed-off-by: Sung Joon Kim Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +++++- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7 +++++++ drivers/gpu/drm/amd/display/dc/dc.h | 1 + 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index fac27b45230f..82b74ee5f0c3 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1104,9 +1104,13 @@ static bool detect_link_and_local_sink(struct dc_link *link, dc_ctx->dce_version == DCN_VERSION_3_01 && link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 && memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580, - sizeof(link->dpcd_caps.branch_dev_name)) == 0) + sizeof(link->dpcd_caps.branch_dev_name)) == 0) { dc->config.edp_no_power_sequencing = true; + if (!link->dpcd_caps.set_power_state_capable_edp) + link->wa_flags.dp_keep_receiver_powered = true; + } + sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; sink_caps.signal = SIGNAL_TYPE_EDP; break; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index f9c10d044da6..fd95bd51988b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -5832,6 +5832,7 @@ void detect_edp_sink_caps(struct dc_link *link) uint32_t link_rate_in_khz; enum dc_link_rate link_rate = LINK_RATE_UNKNOWN; uint8_t backlight_adj_cap; + uint8_t general_edp_cap; retrieve_link_cap(link); link->dpcd_caps.edp_supported_link_rates_count = 0; @@ -5870,6 +5871,12 @@ void detect_edp_sink_caps(struct dc_link *link) link->dpcd_caps.dynamic_backlight_capable_edp = (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false; + core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_1, + &general_edp_cap, sizeof(general_edp_cap)); + + link->dpcd_caps.set_power_state_capable_edp = + (general_edp_cap & DP_EDP_SET_POWER_CAP) ? true:false; + dc_link_set_default_brightness_aux(link); core_link_read_dpcd(link, DP_EDP_DPCD_REV, diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index ba57e03d3d9e..51f5d75bf9e3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1245,6 +1245,7 @@ struct dpcd_caps { bool panel_mode_edp; bool dpcd_display_control_capable; bool ext_receiver_cap_field_present; + bool set_power_state_capable_edp; bool dynamic_backlight_capable_edp; union dpcd_fec_capability fec_cap; struct dpcd_dsc_capabilities dsc_caps; -- cgit v1.2.3 From 3ab55e3a1ebc22c1e0b7c72261a8c9fe78a3a09a Mon Sep 17 00:00:00 2001 From: Sung Joon Kim Date: Tue, 7 Jun 2022 14:15:06 -0400 Subject: drm/amd/display: Turn off internal backlight when plugging external monitor [why] For VG, we want to turn off power/backlight of the intenral panel when plugging in external monitor and going to "external monitor only" mode. [how] For turning off power of the internal panel, ignore the config flag whic bypasses power sequencing for eDP panels. Tested-by: Daniel Wheeler Reviewed-by: Charlene Liu Acked-by: Rodrigo Siqueira Signed-off-by: Sung Joon Kim Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index fd95bd51988b..ef771471aa39 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -7275,8 +7275,7 @@ void dp_disable_link_phy(struct dc_link *link, const struct link_resource *link_ link->dc->hwss.edp_backlight_control(link, false); if (link_hwss->ext.disable_dp_link_output) link_hwss->ext.disable_dp_link_output(link, link_res, signal); - if (!link->dc->config.edp_no_power_sequencing) - link->dc->hwss.edp_power_control(link, false); + link->dc->hwss.edp_power_control(link, false); } else { if (dmcu != NULL && dmcu->funcs->lock_phy) dmcu->funcs->lock_phy(dmcu); -- cgit v1.2.3 From 4b33b5ffcf68de3a43e7dddc91c5dc86e6ed8587 Mon Sep 17 00:00:00 2001 From: Saaem Rizvi Date: Thu, 9 Jun 2022 15:34:43 -0400 Subject: drm/amd/display: Add SMU logging code [WHY] Logging for SMU response value after the wait allows us to know immediately what the response value was. Makes it easier to debug should the value be anything other than OK. [HOW] Using the the already available DC SMU logging functions. Tested-by: Daniel Wheeler Reviewed-by: Charlene Liu Acked-by: Rodrigo Siqueira Signed-off-by: Saaem Rizvi Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 12 ++++++++++++ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c | 12 ++++++++++++ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c | 8 ++++++++ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c | 8 ++++++++ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c | 8 ++++++++ 5 files changed, 48 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c index 30c6f9cd717f..4137394a6ace 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c @@ -41,6 +41,12 @@ #define FN(reg_name, field) \ FD(reg_name##__##field) +#include "logger_types.h" +#undef DC_LOGGER +#define DC_LOGGER \ + CTX->logger +#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } + #define VBIOSSMC_MSG_TestMessage 0x1 #define VBIOSSMC_MSG_GetSmuVersion 0x2 #define VBIOSSMC_MSG_PowerUpGfx 0x3 @@ -97,6 +103,12 @@ static int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, result = rn_smu_wait_for_response(clk_mgr, 10, 200000); ASSERT(result == VBIOSSMC_Result_OK); + smu_print("SMU response after wait: %d\n", result); + + if (result == VBIOSSMC_Status_BUSY) { + return -1; + } + /* First clear response register */ REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c index 1cae01a91a69..d8f03328558b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c @@ -41,6 +41,12 @@ #define FN(reg_name, field) \ FD(reg_name##__##field) +#include "logger_types.h" +#undef DC_LOGGER +#define DC_LOGGER \ + CTX->logger +#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } + #define VBIOSSMC_MSG_GetSmuVersion 0x2 #define VBIOSSMC_MSG_SetDispclkFreq 0x4 #define VBIOSSMC_MSG_SetDprefclkFreq 0x5 @@ -96,6 +102,12 @@ static int dcn301_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000); + smu_print("SMU response after wait: %d\n", result); + + if (result == VBIOSSMC_Status_BUSY) { + return -1; + } + /* First clear response register */ REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c index c5d7d075026f..6a17f7ed4d01 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c @@ -40,6 +40,12 @@ #define FN(reg_name, field) \ FD(reg_name##__##field) +#include "logger_types.h" +#undef DC_LOGGER +#define DC_LOGGER \ + CTX->logger +#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } + #define VBIOSSMC_MSG_TestMessage 0x1 #define VBIOSSMC_MSG_GetSmuVersion 0x2 #define VBIOSSMC_MSG_PowerUpGfx 0x3 @@ -104,6 +110,8 @@ static int dcn31_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000); ASSERT(result == VBIOSSMC_Result_OK); + smu_print("SMU response after wait: %d\n", result); + if (result == VBIOSSMC_Status_BUSY) { return -1; } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c index 2600313fea57..74a78fda62fb 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c @@ -70,6 +70,12 @@ static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D #define REG_NBIO(reg_name) \ (NBIO_BASE.instance[0].segment[regBIF_BX_PF2_ ## reg_name ## _BASE_IDX] + regBIF_BX_PF2_ ## reg_name) +#include "logger_types.h" +#undef DC_LOGGER +#define DC_LOGGER \ + CTX->logger +#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } + #define mmMP1_C2PMSG_3 0x3B1050C #define VBIOSSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team @@ -132,6 +138,8 @@ static int dcn315_smu_send_msg_with_param( result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000); ASSERT(result == VBIOSSMC_Result_OK); + smu_print("SMU response after wait: %d\n", result); + if (result == VBIOSSMC_Status_BUSY) { return -1; } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c index dceec4b96052..b2d1f24cfb80 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c @@ -58,6 +58,12 @@ static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E0000 #define FN(reg_name, field) \ FD(reg_name##__##field) +#include "logger_types.h" +#undef DC_LOGGER +#define DC_LOGGER \ + CTX->logger +#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } + #define VBIOSSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team #define VBIOSSMC_MSG_GetPmfwVersion 0x02 ///< Get PMFW version #define VBIOSSMC_MSG_Spare0 0x03 ///< Spare0 @@ -120,6 +126,8 @@ static int dcn316_smu_send_msg_with_param( result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000); ASSERT(result == VBIOSSMC_Result_OK); + smu_print("SMU response after wait: %d\n", result); + if (result == VBIOSSMC_Status_BUSY) { return -1; } -- cgit v1.2.3 From f173fbe5b042e1c87593e3b06e85cae0094dd867 Mon Sep 17 00:00:00 2001 From: Qingqing Zhuo Date: Fri, 10 Jun 2022 10:43:53 -0400 Subject: drm/amd/display: Fix DC warning at driver load [Why] Wrong index was checked for dcfclk_mhz, causing false warning. [How] Fix the assertion index. Tested-by: Daniel Wheeler Reviewed-by: Dmytro Laktyushkin Acked-by: Rodrigo Siqueira Signed-off-by: Qingqing Zhuo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c index fb4ae800e919..f4381725b210 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c @@ -550,7 +550,7 @@ static void dcn315_clk_mgr_helper_populate_bw_params( if (!bw_params->clk_table.entries[i].dtbclk_mhz) bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz; } - ASSERT(bw_params->clk_table.entries[i].dcfclk_mhz); + ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz); bw_params->vram_type = bios_info->memory_type; bw_params->num_channels = bios_info->ma_channel_number; if (!bw_params->num_channels) -- cgit v1.2.3 From 98dd398aa3e021896adb7f2b1d0f6b2d3784610c Mon Sep 17 00:00:00 2001 From: "JinZe.Xu" Date: Tue, 21 Jul 2020 17:52:41 +0800 Subject: drm/amd/display: Change HDMI judgement condition. [Why & How] Use dc_is_hdmi_signal to determine signal type. Tested-by: Daniel Wheeler Acked-by: Alan Liu Signed-off-by: JinZe.Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 82b74ee5f0c3..fb6ffcb0bc6b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -4374,7 +4374,7 @@ void core_link_enable_stream( dp_set_dsc_enable(pipe_ctx, true); } - if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { + if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { core_link_set_avmute(pipe_ctx, false); } } -- cgit v1.2.3 From f18368b686a86477a79bc240a3a1c655d88a2348 Mon Sep 17 00:00:00 2001 From: Wenjing Liu Date: Tue, 6 Oct 2020 16:22:40 -0400 Subject: drm/amd/display: Enrich the log in MST payload update [Why & How] Enrich the log to provide more informatio in MST payload update. Tested-by: Daniel Wheeler Reviewed-by: Ariel Bernstein Acked-by: Alan Liu Signed-off-by: Wenjing Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index fb6ffcb0bc6b..43b55bc6e2db 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -3831,11 +3831,14 @@ enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw for (i = 0; i < MAX_CONTROLLER_NUM; i++) { DC_LOG_MST("stream_enc[%d]: %p " + "stream[%d].hpo_dp_stream_enc: %p " "stream[%d].vcp_id: %d " "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, i, + (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, + i, link->mst_stream_alloc_table.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table.stream_allocations[i].slot_count); @@ -3896,11 +3899,14 @@ enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t for (i = 0; i < MAX_CONTROLLER_NUM; i++) { DC_LOG_MST("stream_enc[%d]: %p " + "stream[%d].hpo_dp_stream_enc: %p " "stream[%d].vcp_id: %d " "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, i, + (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, + i, link->mst_stream_alloc_table.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table.stream_allocations[i].slot_count); -- cgit v1.2.3 From 95133f41b090b09ba9163b4469cda1d5ee230cd3 Mon Sep 17 00:00:00 2001 From: George Shen Date: Wed, 6 Oct 2021 15:47:37 -0400 Subject: drm/amd/display: Fix in overriding DP drive settings [Why & How] Check always_match_dpcd_with_hw_lane_settings bit before overriding the DP drive settings Tested-by: Daniel Wheeler Reviewed-by: Wenjing Liu Acked-by: Alan Liu Signed-off-by: George Shen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index ef771471aa39..9f873d2cdcad 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1674,8 +1674,9 @@ static void override_training_settings( : POST_CURSOR2_DISABLED; } - dp_hw_to_dpcd_lane_settings(lt_settings, - lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); + if (lt_settings->always_match_dpcd_with_hw_lane_settings) + dp_hw_to_dpcd_lane_settings(lt_settings, + lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); /* Initialize training timings */ if (overrides->cr_pattern_time != NULL) -- cgit v1.2.3 From 2b96b036a6a5767b84f87edc2c0a1c70c91ebac0 Mon Sep 17 00:00:00 2001 From: Wenjing Liu Date: Sat, 11 Sep 2021 23:06:31 -0400 Subject: drm/amd/display: rename lane_settings to hw_lane_settings [why] This is one of the major steps to decouple hw lane settings from dpcd lane settings. Tested-by: Daniel Wheeler Reviewed-by: Jun Lei Acked-by: Alan Liu Signed-off-by: Wenjing Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 ++++---- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 10 +++++----- drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c | 10 +++++----- drivers/gpu/drm/amd/display/include/link_service_types.h | 1 - 4 files changed, 14 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index c7a592d68feb..4d5824edafaa 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -540,11 +540,11 @@ static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, /* apply phy settings from user */ for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { - link_lane_settings.lane_settings[r].VOLTAGE_SWING = + link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING = (enum dc_voltage_swing) (param[0]); - link_lane_settings.lane_settings[r].PRE_EMPHASIS = + link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS = (enum dc_pre_emphasis) (param[1]); - link_lane_settings.lane_settings[r].POST_CURSOR2 = + link_lane_settings.hw_lane_settings[r].POST_CURSOR2 = (enum dc_post_cursor2) (param[2]); } @@ -738,7 +738,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us } for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) - link_training_settings.lane_settings[i] = link->cur_lane_setting[i]; + link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i]; dc_link_set_test_pattern( link, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 9f873d2cdcad..dfee3ba8b234 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1660,15 +1660,15 @@ static void override_training_settings( lt_settings->always_match_dpcd_with_hw_lane_settings = false; } for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { - lt_settings->lane_settings[lane].VOLTAGE_SWING = + lt_settings->hw_lane_settings[lane].VOLTAGE_SWING = lt_settings->voltage_swing != NULL ? *lt_settings->voltage_swing : VOLTAGE_SWING_LEVEL0; - lt_settings->lane_settings[lane].PRE_EMPHASIS = + lt_settings->hw_lane_settings[lane].PRE_EMPHASIS = lt_settings->pre_emphasis != NULL ? *lt_settings->pre_emphasis : PRE_EMPHASIS_DISABLED; - lt_settings->lane_settings[lane].POST_CURSOR2 = + lt_settings->hw_lane_settings[lane].POST_CURSOR2 = lt_settings->post_cursor2 != NULL ? *lt_settings->post_cursor2 : POST_CURSOR2_DISABLED; @@ -1935,8 +1935,8 @@ static void print_status_message( link_rate, lt_settings->link_settings.lane_count, lt_result, - lt_settings->lane_settings[0].VOLTAGE_SWING, - lt_settings->lane_settings[0].PRE_EMPHASIS, + lt_settings->hw_lane_settings[0].VOLTAGE_SWING, + lt_settings->hw_lane_settings[0].PRE_EMPHASIS, lt_spread); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c index 1b7a8774b0c9..a29ebd9dbbcd 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c @@ -177,13 +177,13 @@ static uint8_t dpia_build_set_config_data(enum dpia_set_config_type type, break; case DPIA_SET_CFG_SET_VSPE: /* Assume all lanes have same drive settings. */ - data.set_vspe.swing = lt_settings->lane_settings[0].VOLTAGE_SWING; - data.set_vspe.pre_emph = lt_settings->lane_settings[0].PRE_EMPHASIS; + data.set_vspe.swing = lt_settings->hw_lane_settings[0].VOLTAGE_SWING; + data.set_vspe.pre_emph = lt_settings->hw_lane_settings[0].PRE_EMPHASIS; data.set_vspe.max_swing_reached = - lt_settings->lane_settings[0].VOLTAGE_SWING == + lt_settings->hw_lane_settings[0].VOLTAGE_SWING == VOLTAGE_SWING_MAX_LEVEL ? 1 : 0; data.set_vspe.max_pre_emph_reached = - lt_settings->lane_settings[0].PRE_EMPHASIS == + lt_settings->hw_lane_settings[0].PRE_EMPHASIS == PRE_EMPHASIS_MAX_LEVEL ? 1 : 0; break; default: @@ -405,7 +405,7 @@ static enum link_training_result dpia_training_cr_non_transparent( /* Update VS/PE. */ dp_decide_lane_settings(lt_settings, dpcd_lane_adjust, - lt_settings->lane_settings, + lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); retry_count++; } diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h index 23f7d7354aaa..79fabc51c991 100644 --- a/drivers/gpu/drm/amd/display/include/link_service_types.h +++ b/drivers/gpu/drm/amd/display/include/link_service_types.h @@ -94,7 +94,6 @@ struct link_training_settings { /* TODO: turn lane settings below into mandatory fields * as initial lane configuration */ - struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]; enum dc_voltage_swing *voltage_swing; enum dc_pre_emphasis *pre_emphasis; enum dc_post_cursor2 *post_cursor2; -- cgit v1.2.3 From 6bad8e4a0ec8a950d10d91cb1846f3ef3e1f4ae0 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Sat, 2 Oct 2021 09:44:08 -0400 Subject: drm/amd/display: Change initializer to single brace [Why & How] Change struct initializer from multiple brace to single brace. Tested-by: Daniel Wheeler Acked-by: Alan Liu Signed-off-by: Aric Cyr Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++-- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 6 ++--- drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c | 28 +++++++++++----------- 3 files changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 43b55bc6e2db..fd053d6bdf73 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1528,7 +1528,7 @@ static bool dc_link_construct_legacy(struct dc_link *link, const struct link_init_data *init_params) { uint8_t i; - struct ddc_service_init_data ddc_service_init_data = { { 0 } }; + struct ddc_service_init_data ddc_service_init_data = { 0 }; struct dc_context *dc_ctx = init_params->ctx; struct encoder_init_data enc_init_data = { 0 }; struct panel_cntl_init_data panel_cntl_init_data = { 0 }; @@ -1828,7 +1828,7 @@ create_fail: static bool dc_link_construct_dpia(struct dc_link *link, const struct link_init_data *init_params) { - struct ddc_service_init_data ddc_service_init_data = { { 0 } }; + struct ddc_service_init_data ddc_service_init_data = { 0 }; struct dc_context *dc_ctx = init_params->ctx; DC_LOGGER_INIT(dc_ctx->logger); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index dfee3ba8b234..76efac8300a9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -638,7 +638,7 @@ static void dpcd_set_lt_pattern_and_lane_settings( uint32_t dpcd_base_lt_offset; uint8_t dpcd_lt_buffer[5] = {0}; - union dpcd_training_pattern dpcd_pattern = { 0 }; + union dpcd_training_pattern dpcd_pattern = {0}; uint32_t size_in_bytes; bool edp_workaround = false; /* TODO link_prop.INTERNAL */ dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET; @@ -1369,7 +1369,7 @@ static enum link_training_result perform_clock_recovery_sequence( enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; union lane_align_status_updated dpcd_lane_status_updated; - union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } }; + union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; retries_cr = 0; retry_count = 0; @@ -2164,7 +2164,7 @@ static enum link_training_result dp_perform_128b_132b_cds_done_sequence( enum link_training_result result = LINK_TRAINING_SUCCESS; union lane_align_status_updated dpcd_lane_status_updated = {0}; union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; - union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } }; + union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; uint32_t wait_time = 0; /* initiate CDS done sequence */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c index a29ebd9dbbcd..03f7249df1ef 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c @@ -226,7 +226,7 @@ static enum dc_status dpcd_set_lt_pattern(struct dc_link *link, enum dc_dp_training_pattern pattern, uint32_t hop) { - union dpcd_training_pattern dpcd_pattern = { {0} }; + union dpcd_training_pattern dpcd_pattern = {0}; uint32_t dpcd_tps_offset = DP_TRAINING_PATTERN_SET; enum dc_status status; @@ -287,9 +287,9 @@ static enum link_training_result dpia_training_cr_non_transparent( /* From DP spec, CR read interval is always 100us. */ uint32_t wait_time_microsec = TRAINING_AUX_RD_INTERVAL; enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; - union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } }; - union lane_align_status_updated dpcd_lane_status_updated = { {0} }; - union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } }; + union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; + union lane_align_status_updated dpcd_lane_status_updated = {0}; + union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; uint8_t set_cfg_data; enum dpia_set_config_ts ts; @@ -445,9 +445,9 @@ static enum link_training_result dpia_training_cr_transparent( uint32_t retry_count = 0; uint32_t wait_time_microsec = lt_settings->cr_pattern_time; enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; - union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } }; - union lane_align_status_updated dpcd_lane_status_updated = { {0} }; - union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } }; + union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; + union lane_align_status_updated dpcd_lane_status_updated = {0}; + union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; /* Cap of LINK_TRAINING_MAX_CR_RETRY attempts at clock recovery. * Fix inherited from perform_clock_recovery_sequence() - @@ -599,9 +599,9 @@ static enum link_training_result dpia_training_eq_non_transparent( enum dc_dp_training_pattern tr_pattern; uint32_t wait_time_microsec; enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; - union lane_align_status_updated dpcd_lane_status_updated = { {0} }; - union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } }; - union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } }; + union lane_align_status_updated dpcd_lane_status_updated = {0}; + union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; + union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; uint8_t set_cfg_data; enum dpia_set_config_ts ts; @@ -738,9 +738,9 @@ static enum link_training_result dpia_training_eq_transparent( enum dc_dp_training_pattern tr_pattern = lt_settings->pattern_for_eq; uint32_t wait_time_microsec; enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; - union lane_align_status_updated dpcd_lane_status_updated = { {0} }; - union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } }; - union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } }; + union lane_align_status_updated dpcd_lane_status_updated = {0}; + union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; + union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; wait_time_microsec = dpia_get_eq_aux_rd_interval(link, lt_settings, DPRX); @@ -827,7 +827,7 @@ static enum link_training_result dpia_training_eq_phase( /* End training of specified hop in display path. */ static enum dc_status dpcd_clear_lt_pattern(struct dc_link *link, uint32_t hop) { - union dpcd_training_pattern dpcd_pattern = { {0} }; + union dpcd_training_pattern dpcd_pattern = {0}; uint32_t dpcd_tps_offset = DP_TRAINING_PATTERN_SET; enum dc_status status; -- cgit v1.2.3 From a3e731260b9325e2e87baf54f07619c6cb83931b Mon Sep 17 00:00:00 2001 From: George Shen Date: Thu, 7 Oct 2021 15:59:44 -0400 Subject: drm/amd/display: Fix typo in override_lane_settings [Why] The function currently skips overriding the drive settings of the first lane. [How] Change for loop to start at 0 instead of 1. Tested-by: Daniel Wheeler Reviewed-by: Wenjing Liu Acked-by: Alan Liu Signed-off-by: George Shen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 76efac8300a9..972dbbcc36da 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -944,7 +944,7 @@ static void override_lane_settings(const struct link_training_settings *lt_setti return; - for (lane = 1; lane < LANE_COUNT_DP_MAX; lane++) { + for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { if (lt_settings->voltage_swing) lane_settings[lane].VOLTAGE_SWING = *lt_settings->voltage_swing; if (lt_settings->pre_emphasis) -- cgit v1.2.3 From 0bbd1c7de319ca5a08359e5fc901a0317bf5c0d6 Mon Sep 17 00:00:00 2001 From: George Shen Date: Mon, 31 Jan 2022 14:31:14 -0500 Subject: drm/amd/display: Handle downstream LTTPR with fixed VS sequence [Why] Several issues were discovered that caused link training to fail when an LTTPR device is connected downstream for the fixed VS sequence. [How] The following were added: - workaround to configure AUX timeout for fixed VS sequence - additional delay before disabling fixed VS intercept - detection of fixed VS deadlock state and performing DPCD sequence to recover Tested-by: Daniel Wheeler Reviewed-by: Meenakshikumar Somasundaram Acked-by: Alan Liu Signed-off-by: George Shen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 43 +++++++++++++++++++--- drivers/gpu/drm/amd/display/dc/dc.h | 2 + .../gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 1 - 3 files changed, 40 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 972dbbcc36da..c993b428ca7e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2384,6 +2384,7 @@ static enum link_training_result dp_perform_fixed_vs_pe_training_sequence( link->dpcd_caps.lttpr_caps.phy_repeater_cnt); const uint8_t vendor_lttpr_write_data_intercept_en[4] = {0x1, 0x55, 0x63, 0x0}; const uint8_t vendor_lttpr_write_data_intercept_dis[4] = {0x1, 0x55, 0x63, 0x68}; + uint32_t pre_disable_intercept_delay_ms = link->dc->debug.fixed_vs_aux_delay_config_wa; uint8_t vendor_lttpr_write_data_vs[4] = {0x1, 0x51, 0x63, 0x0}; uint8_t vendor_lttpr_write_data_pe[4] = {0x1, 0x52, 0x63, 0x0}; uint32_t vendor_lttpr_write_address = 0xF004F; @@ -2406,6 +2407,10 @@ static enum link_training_result dp_perform_fixed_vs_pe_training_sequence( if (offset != 0xFF) { vendor_lttpr_write_address += ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1)); + + /* Certain display and cable configuration require extra delay */ + if (offset > 2) + pre_disable_intercept_delay_ms = link->dc->debug.fixed_vs_aux_delay_config_wa * 2; } /* Vendor specific: Reset lane settings */ @@ -2485,6 +2490,7 @@ static enum link_training_result dp_perform_fixed_vs_pe_training_sequence( /* Perform Clock Recovery Sequence */ if (status == LINK_TRAINING_SUCCESS) { + const uint8_t max_vendor_dpcd_retries = 10; uint32_t retries_cr; uint32_t retry_count; uint32_t wait_time_microsec; @@ -2492,6 +2498,8 @@ static enum link_training_result dp_perform_fixed_vs_pe_training_sequence( union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; union lane_align_status_updated dpcd_lane_status_updated; union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; + enum dc_status dpcd_status = DC_OK; + uint8_t i = 0; retries_cr = 0; retry_count = 0; @@ -2522,11 +2530,23 @@ static enum link_training_result dp_perform_fixed_vs_pe_training_sequence( lt_settings->pattern_for_cr, 0); /* Vendor specific: Disable intercept */ - core_link_write_dpcd( - link, - vendor_lttpr_write_address, - &vendor_lttpr_write_data_intercept_dis[0], - sizeof(vendor_lttpr_write_data_intercept_dis)); + for (i = 0; i < max_vendor_dpcd_retries; i++) { + msleep(pre_disable_intercept_delay_ms); + dpcd_status = core_link_write_dpcd( + link, + vendor_lttpr_write_address, + &vendor_lttpr_write_data_intercept_dis[0], + sizeof(vendor_lttpr_write_data_intercept_dis)); + + if (dpcd_status == DC_OK) + break; + + core_link_write_dpcd( + link, + vendor_lttpr_write_address, + &vendor_lttpr_write_data_intercept_en[0], + sizeof(vendor_lttpr_write_data_intercept_en)); + } } else { vendor_lttpr_write_data_vs[3] = 0; vendor_lttpr_write_data_pe[3] = 0; @@ -5190,6 +5210,19 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link) determine_lttpr_mode(link); if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) { + if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && + !link->dc->debug.disable_fixed_vs_aux_timeout_wa) { + /* Fixed VS workaround for AUX timeout */ + const uint32_t fixed_vs_address = 0xF004F; + const uint8_t fixed_vs_data[4] = {0x1, 0x22, 0x63, 0xc}; + + core_link_write_dpcd( + link, + fixed_vs_address, + fixed_vs_data, + sizeof(fixed_vs_data)); + } + /* By reading LTTPR capability, RX assumes that we will enable * LTTPR extended aux timeout if LTTPR is present. */ diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 51f5d75bf9e3..236a204d41ad 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -737,6 +737,8 @@ struct dc_debug_options { bool enable_z9_disable_interface; bool enable_sw_cntl_psr; union dpia_debug_options dpia_debug; + bool disable_fixed_vs_aux_timeout_wa; + uint32_t fixed_vs_aux_delay_config_wa; bool force_disable_subvp; bool force_subvp_mclk_switch; bool force_usr_allow; diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c index a67475251188..1a67d04cc017 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c @@ -890,7 +890,6 @@ static const struct dc_debug_options debug_defaults_drv = { .disable_z10 = true, .optimize_edp_link_rate = true, .enable_sw_cntl_psr = true, - .apply_vendor_specific_lttpr_wa = true, .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/ .dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE, }; -- cgit v1.2.3 From 20cb72174ddcc86596286784416adb947195e45c Mon Sep 17 00:00:00 2001 From: George Shen Date: Fri, 11 Feb 2022 14:13:01 -0500 Subject: drm/amd/display: Remove unused vendor specific w/a [Why & How] Old vendor specific w/a are no longer needed and unused. Clean up codebase by removing them. Tested-by: Daniel Wheeler Reviewed-by: Wenjing Liu Acked-by: Alan Liu Signed-off-by: George Shen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 133 +---------------------- drivers/gpu/drm/amd/display/dc/dc.h | 1 - 2 files changed, 4 insertions(+), 130 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index c993b428ca7e..76233db6876c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -329,51 +329,6 @@ static uint8_t get_dpcd_link_rate(const struct dc_link_settings *link_settings) return link_rate; } -static void vendor_specific_lttpr_wa_one_start(struct dc_link *link) -{ - const uint8_t vendor_lttpr_write_data[4] = {0x1, 0x50, 0x63, 0xff}; - const uint8_t offset = dp_convert_to_count( - link->dpcd_caps.lttpr_caps.phy_repeater_cnt); - uint32_t vendor_lttpr_write_address = 0xF004F; - - if (offset != 0xFF) - vendor_lttpr_write_address += - ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1)); - - /* W/A for certain LTTPR to reset their lane settings, part one of two */ - core_link_write_dpcd( - link, - vendor_lttpr_write_address, - &vendor_lttpr_write_data[0], - sizeof(vendor_lttpr_write_data)); -} - -static void vendor_specific_lttpr_wa_one_two( - struct dc_link *link, - const uint8_t rate) -{ - if (link->apply_vendor_specific_lttpr_link_rate_wa) { - uint8_t toggle_rate = 0x0; - - if (rate == 0x6) - toggle_rate = 0xA; - else - toggle_rate = 0x6; - - if (link->vendor_specific_lttpr_link_rate_wa == rate) { - /* W/A for certain LTTPR to reset internal state for link training */ - core_link_write_dpcd( - link, - DP_LINK_BW_SET, - &toggle_rate, - 1); - } - - /* Store the last attempted link rate for this link */ - link->vendor_specific_lttpr_link_rate_wa = rate; - } -} - static void dp_fixed_vs_pe_read_lane_adjust( struct dc_link *link, union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX]) @@ -423,51 +378,6 @@ static void dp_fixed_vs_pe_read_lane_adjust( } } -static void vendor_specific_lttpr_wa_four( - struct dc_link *link, - bool apply_wa) -{ - const uint8_t vendor_lttpr_write_data_one[4] = {0x1, 0x55, 0x63, 0x8}; - const uint8_t vendor_lttpr_write_data_two[4] = {0x1, 0x55, 0x63, 0x0}; - const uint8_t offset = dp_convert_to_count( - link->dpcd_caps.lttpr_caps.phy_repeater_cnt); - uint32_t vendor_lttpr_write_address = 0xF004F; - uint8_t sink_status = 0; - uint8_t i; - - if (offset != 0xFF) - vendor_lttpr_write_address += - ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1)); - - /* W/A to pass through DPCD write of TPS=0 to DPRX */ - if (apply_wa) { - core_link_write_dpcd( - link, - vendor_lttpr_write_address, - &vendor_lttpr_write_data_one[0], - sizeof(vendor_lttpr_write_data_one)); - } - - /* clear training pattern set */ - dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE); - - if (apply_wa) { - core_link_write_dpcd( - link, - vendor_lttpr_write_address, - &vendor_lttpr_write_data_two[0], - sizeof(vendor_lttpr_write_data_two)); - } - - /* poll for intra-hop disable */ - for (i = 0; i < 10; i++) { - if ((core_link_read_dpcd(link, DP_SINK_STATUS, &sink_status, 1) == DC_OK) && - (sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION) == 0) - break; - udelay(1000); - } -} - static void dp_fixed_vs_pe_set_retimer_lane_settings( struct dc_link *link, const union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX], @@ -561,14 +471,6 @@ enum dc_status dpcd_set_link_settings( <_settings->link_settings.link_rate_set, 1); } else { rate = get_dpcd_link_rate(<_settings->link_settings); - if (link->dc->debug.apply_vendor_specific_lttpr_wa && - (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && - link->lttpr_mode == LTTPR_MODE_TRANSPARENT) - vendor_specific_lttpr_wa_one_start(link); - - if (link->dc->debug.apply_vendor_specific_lttpr_wa && - (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)) - vendor_specific_lttpr_wa_one_two(link, rate); status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1); } @@ -1303,12 +1205,6 @@ static enum link_training_result perform_channel_equalization_sequence( dp_translate_training_aux_read_interval( link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]); - if (link->dc->debug.apply_vendor_specific_lttpr_wa && - (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && - link->lttpr_mode == LTTPR_MODE_TRANSPARENT) { - wait_time_microsec = 16000; - } - dp_wait_for_training_aux_rd_interval( link, wait_time_microsec); @@ -1415,11 +1311,6 @@ static enum link_training_result perform_clock_recovery_sequence( /* 3. wait receiver to lock-on*/ wait_time_microsec = lt_settings->cr_pattern_time; - if (link->dc->debug.apply_vendor_specific_lttpr_wa && - (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)) { - wait_time_microsec = 16000; - } - dp_wait_for_training_aux_rd_interval( link, wait_time_microsec); @@ -2752,14 +2643,7 @@ enum link_training_result dc_link_dp_perform_link_training( <_settings); /* reset previous training states */ - if (link->dc->debug.apply_vendor_specific_lttpr_wa && - (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && - link->lttpr_mode == LTTPR_MODE_TRANSPARENT) { - link->apply_vendor_specific_lttpr_link_rate_wa = true; - vendor_specific_lttpr_wa_four(link, true); - } else { - dpcd_exit_training_mode(link); - } + dpcd_exit_training_mode(link); /* configure link prior to entering training mode */ dpcd_configure_lttpr_mode(link, <_settings); @@ -2780,14 +2664,7 @@ enum link_training_result dc_link_dp_perform_link_training( ASSERT(0); /* exit training mode */ - if (link->dc->debug.apply_vendor_specific_lttpr_wa && - (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && - link->lttpr_mode == LTTPR_MODE_TRANSPARENT) { - link->apply_vendor_specific_lttpr_link_rate_wa = false; - vendor_specific_lttpr_wa_four(link, (status != LINK_TRAINING_SUCCESS)); - } else { - dpcd_exit_training_mode(link); - } + dpcd_exit_training_mode(link); /* switch to video idle */ if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) @@ -4227,8 +4104,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link) &dpcd_lane_adjustment[0].raw, sizeof(dpcd_lane_adjustment)); - if (link->dc->debug.apply_vendor_specific_lttpr_wa && - (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && + if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && link->lttpr_mode == LTTPR_MODE_TRANSPARENT) dp_fixed_vs_pe_read_lane_adjust( link, @@ -6198,8 +6074,7 @@ bool dc_link_dp_set_test_pattern( if (is_dp_phy_pattern(test_pattern)) { /* Set DPCD Lane Settings before running test pattern */ if (p_link_settings != NULL) { - if (link->dc->debug.apply_vendor_specific_lttpr_wa && - (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && + if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && link->lttpr_mode == LTTPR_MODE_TRANSPARENT) { dp_fixed_vs_pe_set_retimer_lane_settings( link, diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 236a204d41ad..81e308d59a97 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -744,7 +744,6 @@ struct dc_debug_options { bool force_usr_allow; /* uses value at boot and disables switch */ bool disable_dtb_ref_clk_switch; - bool apply_vendor_specific_lttpr_wa; bool extended_blank_optimization; union aux_wake_wa_options aux_wake_wa; uint8_t psr_power_use_phy_fsm; -- cgit v1.2.3 From 990cad0e4a9df4202cd482c192608caf6408e4b3 Mon Sep 17 00:00:00 2001 From: Wenjing Liu Date: Fri, 25 Mar 2022 16:12:14 -0400 Subject: drm/amd/display: extract update stream allocation to link_hwss [Why & How] Extract update stream allocation table into link hwss as part of the link hwss refactor work. Tested-by: Daniel Wheeler Reviewed-by: George Shen Acked-by: Alan Liu Signed-off-by: Wenjing Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 10 +++++++--- drivers/gpu/drm/amd/display/dc/inc/link_hwss.h | 6 +++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index fd053d6bdf73..1206a3dd746f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -3871,7 +3871,6 @@ enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t struct fixed31_32 avg_time_slots_per_mtp; struct fixed31_32 pbn; struct fixed31_32 pbn_per_slot; - struct link_encoder *link_encoder = link->link_enc; struct dp_mst_stream_allocation_table proposed_table = {0}; uint8_t i; enum act_return_status ret; @@ -3915,8 +3914,13 @@ enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t ASSERT(proposed_table.stream_count > 0); /* update mst stream allocation table hardware state */ - link_encoder->funcs->update_mst_stream_allocation_table( - link_encoder, + if (link_hwss->ext.update_stream_allocation_table == NULL || + dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { + DC_LOG_ERROR("Failure: unknown encoding format\n"); + return DC_ERROR_UNEXPECTED; + } + + link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, &link->mst_stream_alloc_table); /* poll for immediate branch device ACT handled */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h index e6c49ef8b584..3482a877b6af 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h +++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h @@ -62,9 +62,9 @@ struct link_hwss_ext { const struct link_resource *link_res, struct encoder_set_dp_phy_pattern_param *tp_params); void (*set_dp_lane_settings)(struct dc_link *link, - const struct link_resource *link_res, - const struct dc_link_settings *link_settings, - const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]); + const struct link_resource *link_res, + const struct dc_link_settings *link_settings, + const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]); void (*update_stream_allocation_table)(struct dc_link *link, const struct link_resource *link_res, const struct link_mst_stream_allocation_table *table); -- cgit v1.2.3 From a30e8c13e7affd6fe379c6bf213133b0f917d1bf Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Tue, 15 Jun 2021 15:11:31 -0400 Subject: drm/amd/display: Fix in dp link-training when updating payload allocation table [Why & How] Check if aux is not accessible before updating payload allocation table. Tested-by: Daniel Wheeler Acked-by: Alan Liu Signed-off-by: Dmytro Laktyushkin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 76233db6876c..4027f439a5a4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -6823,6 +6823,13 @@ bool dpcd_write_128b_132b_sst_payload_allocation_table( /// Leave req_slot_count = 0 if allocate is false. } + proposed_table->stream_count = 1; /// Always 1 stream for SST + proposed_table->stream_allocations[0].slot_count = req_slot_count; + proposed_table->stream_allocations[0].vcp_id = vc_id; + + if (link->aux_access_disabled) + return true; + /// Write DPCD 2C0 = 1 to start updating update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; core_link_write_dpcd( @@ -6890,10 +6897,6 @@ bool dpcd_write_128b_132b_sst_payload_allocation_table( // TODO - DP2.0 Payload: Read and log the payload table from downstream branch } - proposed_table->stream_count = 1; /// Always 1 stream for SST - proposed_table->stream_allocations[0].slot_count = req_slot_count; - proposed_table->stream_allocations[0].vcp_id = vc_id; - return result; } @@ -6909,6 +6912,8 @@ bool dpcd_poll_for_allocation_change_trigger(struct dc_link *link) union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; union lane_align_status_updated lane_status_updated; + if (link->aux_access_disabled) + return true; for (i = 0; i < act_retries; i++) { get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); -- cgit v1.2.3 From 074efb5cadcb3c9e40d536a730318bfab3384cad Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Tue, 14 Jun 2022 09:04:53 -0400 Subject: drm/amd/display: Check minimum disp_clk and dpp_clk debug option Our debug struct has the min_disp_clk_khz and min_dpp_clk_khz options, which we ignore in the DCN32. This commit introduces those checks and the necessary calculation. Tested-by: Daniel Wheeler Reviewed-by: Aurabindo Jayamohanan Pillai Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index ed70ae10bdb1..b32880afb3fb 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -265,6 +265,25 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, &num_levels); + if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) { + unsigned int i; + + for (i = 0; i < num_levels; i++) + if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz + < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz)) + clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz + = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz); + } + + if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) { + unsigned int i; + + for (i = 0; i < num_levels; i++) + if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz + < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz)) + clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz + = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz); + } /* Get UCLK, update bounding box */ clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base); -- cgit v1.2.3 From 04e6931a76e592e66e1014ffe4d13303ccac5d8b Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Fri, 6 May 2022 15:57:09 -0400 Subject: drm/amd/display: Update DPPCLK programming sequence [Description] - When lowering DPPCLK, we want to program the DPP DTO before updating the DPP refclk. - Also update DPPCLK to the exact frequency that will be set after clock divider has been programmed. This will prevent rounding errors when making the request to PMFW (we need DPP DTO to match exactly with the exact DPP refclk). Tested-by: Daniel Wheeler Acked-by: Rodrigo Siqueira Signed-off-by: Alvin Lee Signed-off-by: Alex Deucher --- .../amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 25 +++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index b32880afb3fb..bab85f3c9c67 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -325,6 +325,26 @@ static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, } } +/* Since DPPCLK request to PMFW needs to be exact (due to DPP DTO programming), + * update DPPCLK to be the exact frequency that will be set after the DPPCLK + * divider is updated. This will prevent rounding issues that could cause DPP + * refclk and DPP DTO to not match up. + */ +static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks) +{ + int dpp_divider = 0; + int disp_divider = 0; + + dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR + * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz; + disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR + * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz; + + // Divide back the previous result to round up to the actual clock value that will be set from divider + new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider; + new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider; +} + static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool safe_to_lower) @@ -448,13 +468,14 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, } } + dcn32_update_dppclk_dispclk_freq(clk_mgr, new_clocks); if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) { if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz) dpp_clock_lowered = true; clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; - if (clk_mgr->smu_present) + if (clk_mgr->smu_present && !dpp_clock_lowered) dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz)); update_dppclk = true; @@ -488,6 +509,8 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, /* if clock is being lowered, increase DTO before lowering refclk */ dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); dcn20_update_clocks_update_dentist(clk_mgr, context); + if (clk_mgr->smu_present) + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz)); } else { /* if clock is being raised, increase refclk before lowering DTO */ if (update_dppclk || update_dispclk) -- cgit v1.2.3 From a3a885878e74d3d81e4742f8dd84faa27c8863ad Mon Sep 17 00:00:00 2001 From: George Shen Date: Fri, 20 May 2022 11:55:10 -0400 Subject: drm/amd/display: Fix divide-by-zero in DPPCLK and DISPCLK calculation [Why] Certain use cases will pass in zero in the new_clocks parameter for all clocks. This results in a divide-by-zero error when attempting to round up the new clock. When new_clocks are zero, no rounding is required, so we can skip it. [How] Guard the division calculation with a check to make sure clocks are not zero. Tested-by: Daniel Wheeler Acked-by: Rodrigo Siqueira Signed-off-by: George Shen Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index bab85f3c9c67..8ece88ddfb5b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -335,14 +335,16 @@ static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, s int dpp_divider = 0; int disp_divider = 0; - dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR - * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz; - disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR - * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz; - - // Divide back the previous result to round up to the actual clock value that will be set from divider - new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider; - new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider; + if (new_clocks->dppclk_khz) { + dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR + * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz; + new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider; + } + if (new_clocks->dispclk_khz > 0) { + disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR + * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz; + new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider; + } } static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, -- cgit v1.2.3 From 32e8ab05ed81c995b92f12b590c12ef951ca1129 Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Wed, 25 May 2022 13:34:07 -0400 Subject: drm/amd/display: Update SW state correctly for FCLK FCLK not supported for DCN321, but still need to update the software state accordingly to prevent unneeded full updates in driver Tested-by: Daniel Wheeler Acked-by: Rodrigo Siqueira Signed-off-by: Alvin Lee Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 8ece88ddfb5b..90ba9576a6fb 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -431,12 +431,12 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); } - if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && - should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) { + if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) && + clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21) { clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support; /* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */ - if (!clk_mgr_base->clks.fclk_p_state_change_support) { + if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && !clk_mgr_base->clks.fclk_p_state_change_support) { /* Handle code for sending a message to PMFW that FCLK P-state change is not supported */ dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED); } -- cgit v1.2.3 From 3e838f7ccf64b0e33a2f6d1c66158cc5ab04c86f Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Tue, 14 Jun 2022 09:51:08 -0400 Subject: drm/amd/display: Get VCO frequency from registers Add support to get VCO frequency from registers. Tested-by: Daniel Wheeler Reviewed-by: Aurabindo Jayamohanan Pillai Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- .../amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 94 +++++++++++++++++++++- drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 3 + 2 files changed, 96 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 90ba9576a6fb..e3abadeca0a6 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -531,6 +531,96 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr_base->clks.dispclk_khz / 1000 / 7); } +static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) +{ + struct fixed31_32 pll_req; + uint32_t pll_req_reg = 0; + + /* get FbMult value */ + if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) + pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ); + else + pll_req_reg = REG_READ(CLK1_CLK_PLL_REQ); + + /* set up a fixed-point number + * this works because the int part is on the right edge of the register + * and the frac part is on the left edge + */ + pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int); + pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac; + + /* multiply by REFCLK period */ + pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); + + return dc_fixpt_floor(pll_req); +} + +static void dcn32_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, + struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + uint32_t dprefclk_did = 0; + uint32_t dcfclk_did = 0; + uint32_t dtbclk_did = 0; + uint32_t dispclk_did = 0; + uint32_t dppclk_did = 0; + uint32_t target_div = 0; + + if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) { + /* DFS Slice 0 is used for DISPCLK */ + dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL); + /* DFS Slice 1 is used for DPPCLK */ + dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL); + /* DFS Slice 2 is used for DPREFCLK */ + dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL); + /* DFS Slice 3 is used for DCFCLK */ + dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL); + /* DFS Slice 4 is used for DTBCLK */ + dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL); + } else { + /* DFS Slice 0 is used for DISPCLK */ + dispclk_did = REG_READ(CLK1_CLK0_DFS_CNTL); + /* DFS Slice 1 is used for DPPCLK */ + dppclk_did = REG_READ(CLK1_CLK1_DFS_CNTL); + /* DFS Slice 2 is used for DPREFCLK */ + dprefclk_did = REG_READ(CLK1_CLK2_DFS_CNTL); + /* DFS Slice 3 is used for DCFCLK */ + dcfclk_did = REG_READ(CLK1_CLK3_DFS_CNTL); + /* DFS Slice 4 is used for DTBCLK */ + dtbclk_did = REG_READ(CLK1_CLK4_DFS_CNTL); + } + + /* Convert DISPCLK DFS Slice DID to divider*/ + target_div = dentist_get_divider_from_did(dispclk_did); + //Get dispclk in khz + regs_and_bypass->dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR + * clk_mgr->base.dentist_vco_freq_khz) / target_div; + + /* Convert DISPCLK DFS Slice DID to divider*/ + target_div = dentist_get_divider_from_did(dppclk_did); + //Get dppclk in khz + regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR + * clk_mgr->base.dentist_vco_freq_khz) / target_div; + + /* Convert DPREFCLK DFS Slice DID to divider*/ + target_div = dentist_get_divider_from_did(dprefclk_did); + //Get dprefclk in khz + regs_and_bypass->dprefclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR + * clk_mgr->base.dentist_vco_freq_khz) / target_div; + + /* Convert DCFCLK DFS Slice DID to divider*/ + target_div = dentist_get_divider_from_did(dcfclk_did); + //Get dcfclk in khz + regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR + * clk_mgr->base.dentist_vco_freq_khz) / target_div; + + /* Convert DTBCLK DFS Slice DID to divider*/ + target_div = dentist_get_divider_from_did(dtbclk_did); + //Get dtbclk in khz + regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR + * clk_mgr->base.dentist_vco_freq_khz) / target_div; +} + static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr) { struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; @@ -680,6 +770,7 @@ static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base) static struct clk_mgr_funcs dcn32_funcs = { .get_dp_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, .update_clocks = dcn32_update_clocks, + .dump_clk_registers = dcn32_dump_clk_registers, .init_clocks = dcn32_init_clocks, .notify_wm_ranges = dcn32_notify_wm_ranges, .set_hard_min_memclk = dcn32_set_hard_min_memclk, @@ -730,7 +821,8 @@ void dcn32_clk_mgr_construct( } /* integer part is now VCO frequency in kHz */ - clk_mgr->base.dentist_vco_freq_khz = 4300000;//dcn32_get_vco_frequency_from_reg(clk_mgr); + clk_mgr->base.dentist_vco_freq_khz = dcn32_get_vco_frequency_from_reg(clk_mgr); + /* in case we don't get a value from the register, use default */ if (clk_mgr->base.dentist_vco_freq_khz == 0) clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index 4dd461e6c14b..9ae9439c8f7b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -245,6 +245,9 @@ struct clk_mgr_funcs { void (*init_clocks)(struct clk_mgr *clk_mgr); + void (*dump_clk_registers)(struct clk_state_registers_and_bypass *regs_and_bypass, + struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info); + void (*enable_pme_wa) (struct clk_mgr *clk_mgr); void (*get_clock)(struct clk_mgr *clk_mgr, struct dc_state *context, -- cgit v1.2.3 From aeb73c608c5b7fa6fad6d98694323e7629e93cce Mon Sep 17 00:00:00 2001 From: Chaitanya Dhere Date: Thu, 14 Apr 2022 13:24:11 -0400 Subject: drm/amd/display: Implement a pme workaround function [Why] For DCN32 we do not have a pme workaround function defined that sends a BacoAudio message. Default code had uses the DCN30 function for pme workaround. PMFW headers are inconsistent with their message ID definitions which cause ID's to clash leading to inconsistent system behaviour. There is a clash with FCLK message due to inconsitent PMFW headers. [How] Implement a new BacoAudio function to workaround the problem of inconsistent PMFW headers in order to avoid BacoAudio message clasing with FCLK Enable message. Tested-by: Daniel Wheeler Acked-by: Rodrigo Siqueira Signed-off-by: Chaitanya Dhere Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +- .../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c | 8 ++++++++ .../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h | 1 + 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index e3abadeca0a6..b31adf5238d0 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -757,7 +757,7 @@ static void dcn32_enable_pme_wa(struct clk_mgr *clk_mgr_base) if (!clk_mgr->smu_present) return; - dcn30_smu_set_pme_workaround(clk_mgr); + dcn32_smu_set_pme_workaround(clk_mgr); } static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c index d7c99e9179be..67ed8bf4510b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c @@ -115,6 +115,14 @@ void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL); } +void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr) +{ + smu_print("SMU Set PME workaround\n"); + + dcn32_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_BacoAudioD3PME, 0, NULL); +} + /* Returns the actual frequency that was set in MHz, 0 on failure */ unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz) { diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h index 352435edbd79..a68038a41972 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h @@ -39,6 +39,7 @@ void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable); void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); +void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr); void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways); void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz); -- cgit v1.2.3 From 2d7a1ef85d013699ef60068a9f37ab56ffb33c32 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Tue, 14 Jun 2022 10:11:47 -0400 Subject: drm/amd/display: Update hook dcn32_funcs In DCN32 clk hook functions, we are using the wrong reference for get_dp_ref_clk_frequency and missing the get_dtb_ref_clk_frequency reference. This commit adds those references. Tested-by: Daniel Wheeler Reviewed-by: Aurabindo Pillai Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index b31adf5238d0..113f93b3d3b2 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -768,7 +768,8 @@ static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base) static struct clk_mgr_funcs dcn32_funcs = { - .get_dp_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, + .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, + .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, .update_clocks = dcn32_update_clocks, .dump_clk_registers = dcn32_dump_clk_registers, .init_clocks = dcn32_init_clocks, -- cgit v1.2.3 From 2b2db1f9dbfbc61116fec83a51d16fd0cf49b61b Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Tue, 14 Jun 2022 10:18:27 -0400 Subject: drm/amd/display: Drop duplicate define We already have DALSMC_MSG_TransferTableDram2Smu in the file dalsmc.h; for this reason, we don't need this definition in the smu msg file. Tested-by: Daniel Wheeler Reviewed-by: Aurabindo Pillai Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c index 67ed8bf4510b..3137b987f0a0 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c @@ -34,8 +34,6 @@ #define mmDAL_ARG_REG 0x16273 #define mmDAL_RESP_REG 0x16274 -#define DALSMC_MSG_TransferTableDram2Smu 0x8 - #define REG(reg_name) \ mm ## reg_name -- cgit v1.2.3 From dc597268225b2e39bca0bc0c5394e3e6266be2e3 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Sun, 12 Jun 2022 20:06:32 -0400 Subject: drm/amd/display: 3.2.191 This DC patchset brings improvements in multiple areas. In summary, we highlight: - Remove unnecessary code; - Small fixes (compilation warnings, typos, etc); - Improvements in the DPMS code; - Fix eDP issues - Improvements in the MST code Tested-by: Daniel Wheeler Acked-by: Rodrigo Siqueira Signed-off-by: Aric Cyr Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 81e308d59a97..8292f27c1516 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -47,7 +47,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.190" +#define DC_VER "3.2.191" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- cgit v1.2.3 From 43af2220b3302bc04d72bdf07970ebc0fc46155b Mon Sep 17 00:00:00 2001 From: Joshua Ashton Date: Thu, 16 Jun 2022 01:21:27 +0000 Subject: amd/display/dc: Fix COLOR_ENCODING and COLOR_RANGE doing nothing for DCN20+ For DCN20 and above, the code that actually hooks up the provided input_color_space got lost at some point. Fixes COLOR_ENCODING and COLOR_RANGE doing nothing on DCN20+. Tested using Steam Remote Play Together + gamescope. Update other DCNs the same wasy DCN1.x was updates in commit a1e07ba89d49 ("drm/amd/display: Use plane->color_space for dpp if specified") Fixes: a1e07ba89d49 ("drm/amd/display: Use plane->color_space for dpp if specified") Signed-off-by: Joshua Ashton Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 3 +++ drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c | 3 +++ drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c | 3 +++ 3 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c index 970b65efeac1..eaa7032f0f1a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c @@ -212,6 +212,9 @@ static void dpp2_cnv_setup ( break; } + /* Set default color space based on format if none is given. */ + color_space = input_color_space ? input_color_space : color_space; + if (is_2bit == 1 && alpha_2bit_lut != NULL) { REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c index 8b6505b7dca8..f50ab961bc17 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c @@ -153,6 +153,9 @@ static void dpp201_cnv_setup( break; } + /* Set default color space based on format if none is given. */ + color_space = input_color_space ? input_color_space : color_space; + if (is_2bit == 1 && alpha_2bit_lut != NULL) { REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c index 9cca59bf2ae0..3c77949b8110 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c @@ -294,6 +294,9 @@ void dpp3_cnv_setup ( break; } + /* Set default color space based on format if none is given. */ + color_space = input_color_space ? input_color_space : color_space; + if (is_2bit == 1 && alpha_2bit_lut != NULL) { REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); -- cgit v1.2.3 From 83a3439ddb28e15afa66f52650cf3c1486ae6515 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 20 Jun 2022 11:43:35 +0200 Subject: drm/amdgpu: Drop CONFIG_BACKLIGHT_CLASS_DEVICE ifdefs The DRM_AMDGPU Kconfig code contains: select BACKLIGHT_CLASS_DEVICE So the condition these ifdefs test for is always true, drop them. Signed-off-by: Hans de Goede Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 6 ------ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 ---- drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 14 -------------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 +-------------- 4 files changed, 1 insertion(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index 98ac53ee6bb5..130060834b4e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -66,9 +66,7 @@ struct amdgpu_atif { struct amdgpu_atif_notifications notifications; struct amdgpu_atif_functions functions; struct amdgpu_atif_notification_cfg notification_cfg; -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) struct backlight_device *bd; -#endif struct amdgpu_dm_backlight_caps backlight_caps; }; @@ -436,7 +434,6 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev, DRM_DEBUG_DRIVER("ATIF: %d pending SBIOS requests\n", count); if (req.pending & ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST) { -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) if (atif->bd) { DRM_DEBUG_DRIVER("Changing brightness to %d\n", req.backlight_level); @@ -447,7 +444,6 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev, */ backlight_device_set_brightness(atif->bd, req.backlight_level); } -#endif } if (req.pending & ATIF_DGPU_DISPLAY_EVENT) { @@ -849,7 +845,6 @@ int amdgpu_acpi_init(struct amdgpu_device *adev) { struct amdgpu_atif *atif = &amdgpu_acpi_priv.atif; -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) if (atif->notifications.brightness_change) { if (amdgpu_device_has_dc_support(adev)) { #if defined(CONFIG_DRM_AMD_DC) @@ -876,7 +871,6 @@ int amdgpu_acpi_init(struct amdgpu_device *adev) } } } -#endif adev->acpi_nb.notifier_call = amdgpu_acpi_event; register_acpi_notifier(&adev->acpi_nb); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index f80b4838cea1..dbe2904e015b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -349,15 +349,11 @@ struct amdgpu_mode_info { #define AMDGPU_MAX_BL_LEVEL 0xFF -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) - struct amdgpu_backlight_privdata { struct amdgpu_encoder *encoder; uint8_t negative; }; -#endif - struct amdgpu_atom_ss { uint16_t percentage; uint16_t percentage_divider; diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index d4f5a584075d..fa7421afb9a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -118,8 +118,6 @@ amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder *amdgpu_encode } } -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) - static u8 amdgpu_atombios_encoder_backlight_level(struct backlight_device *bd) { u8 level; @@ -251,18 +249,6 @@ amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder *amdgpu_encoder) } } -#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ - -void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *encoder) -{ -} - -void amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder *encoder) -{ -} - -#endif - bool amdgpu_atombios_encoder_is_digital(struct drm_encoder *encoder) { struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b3ab2a3ea29c..beadd75ab93d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3862,9 +3862,6 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ - defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) - static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, int bl_idx) { @@ -4068,7 +4065,6 @@ amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) else DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); } -#endif static int initialize_plane(struct amdgpu_display_manager *dm, struct amdgpu_mode_info *mode_info, int plane_id, @@ -4114,9 +4110,6 @@ static int initialize_plane(struct amdgpu_display_manager *dm, static void register_backlight_device(struct amdgpu_display_manager *dm, struct dc_link *link) { -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ - defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) - if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && link->type != dc_connection_none) { /* @@ -4132,7 +4125,6 @@ static void register_backlight_device(struct amdgpu_display_manager *dm, dm->num_of_edps++; } } -#endif } @@ -7064,15 +7056,12 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector) if (aconnector->mst_mgr.dev) drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ - defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) for (i = 0; i < dm->num_of_edps; i++) { if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) { backlight_device_unregister(dm->backlight_dev[i]); dm->backlight_dev[i] = NULL; } } -#endif if (aconnector->dc_em_sink) dc_sink_release(aconnector->dc_em_sink); @@ -10155,15 +10144,13 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) /* Update audio instances for each connector. */ amdgpu_dm_commit_audio(dev, state); -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ - defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) /* restore the backlight level */ for (i = 0; i < dm->num_of_edps; i++) { if (dm->backlight_dev[i] && (dm->actual_brightness[i] != dm->brightness[i])) amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); } -#endif + /* * send vblank event on all events not handled in flip and * mark consumed event for drm_atomic_helper_commit_hw_done -- cgit v1.2.3 From efb4fd107cfd9748f777a4e9015d803d3c9db68b Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Mon, 20 Jun 2022 16:24:58 +0800 Subject: drm/amdkfd: correct sdma queue number of sdma 6.0.1 sdma 6.0.1 has 8 queues instead of 2. Fixes: 26776a7031c423 ("drm/amdkfd: add GC 11.0.1 KFD support") Signed-off-by: Yifan Zhang Acked-by: Alex Deucher Reviewed-by: Tim Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index bf4200457772..c8fee0dbfdcb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -75,7 +75,6 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ - case IP_VERSION(6, 0, 1): kfd->device_info.num_sdma_queues_per_engine = 2; break; case IP_VERSION(4, 2, 0):/* VEGA20 */ @@ -90,6 +89,7 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ case IP_VERSION(6, 0, 0): + case IP_VERSION(6, 0, 1): case IP_VERSION(6, 0, 2): kfd->device_info.num_sdma_queues_per_engine = 8; break; -- cgit v1.2.3 From cb4b7a23ff85740ed9e0a3aa4c3c0195654a89d5 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 20 Jun 2022 11:43:36 +0200 Subject: drm/radeon: Drop CONFIG_BACKLIGHT_CLASS_DEVICE ifdefs The DRM_RADEON Kconfig code contains: select BACKLIGHT_CLASS_DEVICE So the condition these ifdefs test for is always true, drop them. Signed-off-by: Hans de Goede Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/atombios_encoders.c | 14 -------------- drivers/gpu/drm/radeon/radeon_acpi.c | 2 -- drivers/gpu/drm/radeon/radeon_legacy_encoders.c | 15 --------------- drivers/gpu/drm/radeon/radeon_mode.h | 4 ---- 4 files changed, 35 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c index 70bd84b7ef2b..c93040e60d04 100644 --- a/drivers/gpu/drm/radeon/atombios_encoders.c +++ b/drivers/gpu/drm/radeon/atombios_encoders.c @@ -141,8 +141,6 @@ atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) } } -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) - static u8 radeon_atom_bl_level(struct backlight_device *bd) { u8 level; @@ -286,18 +284,6 @@ static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) } } -#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ - -void radeon_atom_backlight_init(struct radeon_encoder *encoder) -{ -} - -static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) -{ -} - -#endif - static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) diff --git a/drivers/gpu/drm/radeon/radeon_acpi.c b/drivers/gpu/drm/radeon/radeon_acpi.c index 1baef7b493de..b603c0b77075 100644 --- a/drivers/gpu/drm/radeon/radeon_acpi.c +++ b/drivers/gpu/drm/radeon/radeon_acpi.c @@ -391,7 +391,6 @@ static int radeon_atif_handler(struct radeon_device *rdev, radeon_set_backlight_level(rdev, enc, req.backlight_level); -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) if (rdev->is_atom_bios) { struct radeon_encoder_atom_dig *dig = enc->enc_priv; backlight_force_update(dig->bl_dev, @@ -401,7 +400,6 @@ static int radeon_atif_handler(struct radeon_device *rdev, backlight_force_update(dig->bl_dev, BACKLIGHT_UPDATE_HOTKEY); } -#endif } } if (req.pending & ATIF_DGPU_DISPLAY_EVENT) { diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c index 7fdb77d48d6a..1a66fb969ee7 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c @@ -318,8 +318,6 @@ radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 leve radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode); } -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) - static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd) { struct radeon_backlight_privdata *pdata = bl_get_data(bd); @@ -488,19 +486,6 @@ static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder) } } -#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ - -void radeon_legacy_backlight_init(struct radeon_encoder *encoder) -{ -} - -static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder) -{ -} - -#endif - - static void radeon_lvds_enc_destroy(struct drm_encoder *encoder) { struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 3485e7f142e9..b34cffc162e2 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -281,15 +281,11 @@ struct radeon_mode_info { #define RADEON_MAX_BL_LEVEL 0xFF -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) - struct radeon_backlight_privdata { struct radeon_encoder *encoder; uint8_t negative; }; -#endif - #define MAX_H_CODE_TIMING_LEN 32 #define MAX_V_CODE_TIMING_LEN 32 -- cgit v1.2.3 From 163d4cd26a18db7db68a98b4d1ca95d542ca72af Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Jun 2022 16:52:01 -0400 Subject: drm/amdgpu: fix adev variable used in amdgpu_device_gpu_recover() Use the correct adev variable for the drm_fb_helper in amdgpu_device_gpu_recover(). Noticed by inspection. Fixes: 087451f372bf ("drm/amdgpu: use generic fb helpers instead of setting up AMD own's.") Reviewed-by: Guchun Chen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index ea9a9d781d8c..f2a4c268ac72 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5187,7 +5187,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, */ amdgpu_unregister_gpu_instance(tmp_adev); - drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true); + drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true); /* disable ras on ALL IPs */ if (!need_emergency_restart && -- cgit v1.2.3 From fd6ae969cfa2b12c6082eb83bdfa648b15d9b3c7 Mon Sep 17 00:00:00 2001 From: Jiang Jian Date: Tue, 21 Jun 2022 21:10:41 +0800 Subject: drm/amdgpu: vm - drop unexpected word "the" in the comments there is an unexpected word "the" in the comments that need to be dropped file: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c line: 57 * the kernel tells the the ring what VMID to use for that command changed to * the kernel tells the ring what VMID to use for that command Signed-off-by: Jiang Jian Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index dc76d2b3ce52..8530befb2051 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -54,7 +54,7 @@ * (uncached system pages). * Each VM has an ID associated with it and there is a page table * associated with each VMID. When executing a command buffer, - * the kernel tells the the ring what VMID to use for that command + * the kernel tells the ring what VMID to use for that command * buffer. VMIDs are allocated dynamically as commands are submitted. * The userspace drivers maintain their own address space and the kernel * sets up their pages tables accordingly when they submit their -- cgit v1.2.3 From c85c623ab406188da7969180e53c4b61e8a982e0 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Tue, 21 Jun 2022 11:23:39 -0400 Subject: drm/amd/display: fix array index in DML MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [Why&How] When the a 3d array is used by indexing with only one dimension in an if condition, the addresses get compared instead of the intended value stored in the array. GCC 12.1 caught this error: drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/dcn32/display_mode_vba_32.c: In function ‘DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation’: drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/dcn32/display_mode_vba_32.c:1007:45: error: the comparison will always evaluate as ‘true’ for the address of ‘use_one_row_for_frame_flip’ will never be NULL [-Werror=address] 1007 | if (v->use_one_row_for_frame_flip[k]) { | ^ In file included from ./drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/display_mode_lib.h:32, from ./drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dc.h:45, from drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/dcn32/display_mode_vba_32.c:30: ./drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/display_mode_vba.h:605:14: note: ‘use_one_row_for_frame_flip’ declared here 605 | bool use_one_row_for_frame_flip[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; | Fix this by explicitly specifying the last two indices. Fixes: dda4fb85e433 ("drm/amd/display: DML changes for DCN32/321") Acked-by: Alex Deucher Signed-off-by: Aurabindo Pillai Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index b9f5bfa67791..c920d71fbd56 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -994,7 +994,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman + mode_lib->vba.DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k]); - if (v->use_one_row_for_frame_flip[k]) { + if (v->use_one_row_for_frame_flip[k][0][0]) { mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes + 2 * v->PixelPTEBytesPerRow[k]; -- cgit v1.2.3 From eec53143b7fe1ccaace434e03b5959c9117bf9c5 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Tue, 21 Jun 2022 11:23:40 -0400 Subject: drm/amd/display: fix incorrect comparison in DML MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [Why&How] GCC 12 catches the following incorrect comparison in the if arm drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/dcn32/display_mode_vba_32.c: In function ‘dml32_ModeSupportAndSystemConfigurationFull’: drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/dcn32/display_mode_vba_32.c:3740:33: error: the comparison will always evaluate as ‘true’ for the address of ‘USRRetrainingSupport’ will never be NULL [-Werror=address] 3740 | || &mode_lib->vba.USRRetrainingSupport[i][j])) { | ^~ In file included from ./drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/display_mode_lib.h:32, from ./drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dc.h:45, from drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/dcn32/display_mode_vba_32.c:30: ./drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/display_mode_vba.h:1175:14: note: ‘USRRetrainingSupport’ declared here 1175 | bool USRRetrainingSupport[DC__VOLTAGE_STATES][2]; | Fix this by remove preceding & so that value is compared instead of address Fixes: dda4fb85e433 ("drm/amd/display: DML changes for DCN32/321") Acked-by: Alex Deucher Signed-off-by: Aurabindo Pillai Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index c920d71fbd56..510b7a81ee12 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -3725,7 +3725,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l && (!mode_lib->vba.FCLKChangeRequirementFinal || i == v->soc.num_states - 1 || mode_lib->vba.FCLKChangeSupport[i][j] != dm_fclock_change_unsupported) && (!mode_lib->vba.USRRetrainingRequiredFinal - || &mode_lib->vba.USRRetrainingSupport[i][j])) { + || mode_lib->vba.USRRetrainingSupport[i][j])) { mode_lib->vba.ModeSupport[i][j] = true; } else { mode_lib->vba.ModeSupport[i][j] = false; -- cgit v1.2.3 From f4f9b827d76d2fa23c2a2359b4e9fb417deec61a Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Wed, 15 Jun 2022 16:26:35 -0400 Subject: drm/amdkfd: Add queue to MES if it becomes active We remove the user queue from MES scheduler to update queue properties. If the queue becomes active after updating, add the user queue to MES scheduler, to be able to handle command packet submission. v2: don't break pqm_set_gws Signed-off-by: Philip Yang Reviewed-by: Graham Sider Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index e1797657b04c..21aeb05b17db 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -811,7 +811,6 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q, struct mqd_manager *mqd_mgr; struct kfd_process_device *pdd; bool prev_active = false; - bool add_queue = false; dqm_lock(dqm); pdd = kfd_get_process_device_data(q->device, q->process); @@ -887,7 +886,7 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q, if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) { if (!dqm->dev->shared_resources.enable_mes) retval = map_queues_cpsch(dqm); - else if (add_queue) + else if (q->properties.is_active) retval = add_queue_mes(dqm, q, &pdd->qpd); } else if (q->properties.is_active && (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || -- cgit v1.2.3 From ab8529b0cdb271d9b222cbbddb2641f3fca5df8f Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Fri, 10 Jun 2022 20:15:29 -0400 Subject: drm/amdkfd: Free queue after unmap queue success After queue unmap or remove from MES successfully, free queue sysfs entries, doorbell and remove from queue list. Otherwise, application may destroy queue again, cause below kernel warning or crash backtrace. For outstanding queues, either application forget to destroy or failed to destroy, kfd_process_notifier_release will remove queue sysfs entries, kfd_process_wq_release will free queue doorbell. v2: decrement_queue_count for MES queue refcount_t: underflow; use-after-free. WARNING: CPU: 7 PID: 3053 at lib/refcount.c:28 Call Trace: kobject_put+0xd6/0x1a0 kfd_procfs_del_queue+0x27/0x30 [amdgpu] pqm_destroy_queue+0xeb/0x240 [amdgpu] kfd_ioctl_destroy_queue+0x32/0x70 [amdgpu] kfd_ioctl+0x27d/0x500 [amdgpu] do_syscall_64+0x35/0x80 WARNING: CPU: 2 PID: 3053 at drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.c:400 Call Trace: deallocate_doorbell.isra.0+0x39/0x40 [amdgpu] destroy_queue_cpsch+0xb3/0x270 [amdgpu] pqm_destroy_queue+0x108/0x240 [amdgpu] kfd_ioctl_destroy_queue+0x32/0x70 [amdgpu] kfd_ioctl+0x27d/0x500 [amdgpu] general protection fault, probably for non-canonical address 0xdead000000000108: Call Trace: pqm_destroy_queue+0xf0/0x200 [amdgpu] kfd_ioctl_destroy_queue+0x2f/0x60 [amdgpu] kfd_ioctl+0x19b/0x600 [amdgpu] Signed-off-by: Philip Yang Reviewed-by: Graham Sider Signed-off-by: Alex Deucher --- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 28 +++++++++++++--------- .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +- 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 21aeb05b17db..213246a5b4e4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -1872,6 +1872,22 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm, } + if (q->properties.is_active) { + if (!dqm->dev->shared_resources.enable_mes) { + retval = execute_queues_cpsch(dqm, + KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); + if (retval == -ETIME) + qpd->reset_wavefronts = true; + } else { + retval = remove_queue_mes(dqm, q, qpd); + } + + if (retval) + goto failed_unmap_queue; + + decrement_queue_count(dqm, qpd, q); + } + mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( q->properties.type)]; @@ -1885,17 +1901,6 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm, list_del(&q->list); qpd->queue_count--; - if (q->properties.is_active) { - if (!dqm->dev->shared_resources.enable_mes) { - decrement_queue_count(dqm, qpd, q); - retval = execute_queues_cpsch(dqm, - KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); - if (retval == -ETIME) - qpd->reset_wavefronts = true; - } else { - retval = remove_queue_mes(dqm, q, qpd); - } - } /* * Unconditionally decrement this counter, regardless of the queue's @@ -1912,6 +1917,7 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm, return retval; +failed_unmap_queue: failed_try_destroy_debugged_queue: dqm_unlock(dqm); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index dc00484ff484..99f2a6412201 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -419,7 +419,6 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) } if (pqn->q) { - kfd_procfs_del_queue(pqn->q); dqm = pqn->q->device->dqm; retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q); if (retval) { @@ -439,6 +438,7 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) if (dev->shared_resources.enable_mes) amdgpu_amdkfd_free_gtt_mem(dev->adev, pqn->q->gang_ctx_bo); + kfd_procfs_del_queue(pqn->q); uninit_queue(pqn->q); } -- cgit v1.2.3 From 543faf57ee0ef6feb1ef60122c0abb9097083ded Mon Sep 17 00:00:00 2001 From: Darren Powell Date: Fri, 29 Apr 2022 21:20:52 -0400 Subject: amdgpu/pm: Fix incorrect variable for size of clocks array [v2] No Changes, added RB [v1] Size of pp_clock_levels_with_latency is PP_MAX_CLOCK_LEVELS, not MAX_NUM_CLOCKS. Both are currently defined as 16, modifying in case one value is modified in future Changed code in both arcturus and aldabaran. Also removed unneeded var count, and used min_t function Signed-off-by: Darren Powell Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 9 +++++---- drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 9 +++++---- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c index bfabcd3c45aa..445005571f76 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c @@ -573,12 +573,13 @@ static int arcturus_get_clk_table(struct smu_context *smu, struct pp_clock_levels_with_latency *clocks, struct smu_11_0_dpm_table *dpm_table) { - int i, count; + uint32_t i; - count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; - clocks->num_levels = count; + clocks->num_levels = min_t(uint32_t, + dpm_table->count, + (uint32_t)PP_MAX_CLOCK_LEVELS); - for (i = 0; i < count; i++) { + for (i = 0; i < clocks->num_levels; i++) { clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000; clocks->data[i].latency_in_us = 0; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index 1133edd34e4d..cc96a5b11d51 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -555,12 +555,13 @@ static int aldebaran_get_clk_table(struct smu_context *smu, struct pp_clock_levels_with_latency *clocks, struct smu_13_0_dpm_table *dpm_table) { - int i, count; + uint32_t i; - count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; - clocks->num_levels = count; + clocks->num_levels = min_t(uint32_t, + dpm_table->count, + (uint32_t)PP_MAX_CLOCK_LEVELS); - for (i = 0; i < count; i++) { + for (i = 0; i < clocks->num_levels; i++) { clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000; clocks->data[i].latency_in_us = 0; -- cgit v1.2.3 From ceb180361e3851007547c55035cd1de03f108f75 Mon Sep 17 00:00:00 2001 From: Darren Powell Date: Wed, 11 May 2022 01:07:04 -0400 Subject: amdgpu/pm: Fix possible array out-of-bounds if SCLK levels != 2 [v2] simplified fix after Lijo's feedback removed clocks.num_levels from calculation of loop count removed unsafe accesses to shim table freq_values retained corner case output only min,now if clocks.num_levels == 1 && now > min [v1] added a check to populate and use SCLK shim table freq_values only if using dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL or AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM removed clocks.num_levels from calculation of shim table size removed unsafe accesses to shim table freq_values output gfx_table values if using other dpm levels added check for freq_match when using freq_values for when now == min_clk == Test == LOGFILE=aldebaran-sclk.test.log AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print $9}'` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" > $LOGFILE FILES="pp_od_clk_voltage pp_dpm_sclk" for f in $FILES do echo === $f === >> $LOGFILE cat $HWMON_DIR/device/$f >> $LOGFILE done cat $LOGFILE Signed-off-by: Darren Powell Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 34 ++++++++-------------- 1 file changed, 12 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index cc96a5b11d51..619aee51b123 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -746,7 +746,7 @@ static int aldebaran_print_clk_levels(struct smu_context *smu, struct smu_13_0_dpm_table *single_dpm_table; struct smu_dpm_context *smu_dpm = &smu->smu_dpm; struct smu_13_0_dpm_context *dpm_context = NULL; - uint32_t display_levels; + int display_levels; uint32_t freq_values[3] = {0}; uint32_t min_clk, max_clk; @@ -778,7 +778,7 @@ static int aldebaran_print_clk_levels(struct smu_context *smu, return ret; } - display_levels = clocks.num_levels; + display_levels = (clocks.num_levels == 1) ? 1 : 2; min_clk = pstate_table->gfxclk_pstate.curr.min; max_clk = pstate_table->gfxclk_pstate.curr.max; @@ -788,30 +788,20 @@ static int aldebaran_print_clk_levels(struct smu_context *smu, /* fine-grained dpm has only 2 levels */ if (now > min_clk && now < max_clk) { - display_levels = clocks.num_levels + 1; + display_levels++; freq_values[2] = max_clk; freq_values[1] = now; } - /* - * For DPM disabled case, there will be only one clock level. - * And it's safe to assume that is always the current clock. - */ - if (display_levels == clocks.num_levels) { - for (i = 0; i < clocks.num_levels; i++) - size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, - freq_values[i], - (clocks.num_levels == 1) ? - "*" : - (aldebaran_freqs_in_same_level( - freq_values[i], now) ? - "*" : - "")); - } else { - for (i = 0; i < display_levels; i++) - size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, - freq_values[i], i == 1 ? "*" : ""); - } + for (i = 0; i < display_levels; i++) + size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, + freq_values[i], + (display_levels == 1) ? + "*" : + (aldebaran_freqs_in_same_level( + freq_values[i], now) ? + "*" : + "")); break; -- cgit v1.2.3 From f12d07d6e9f22bbe65d158de1435ec515acfb50a Mon Sep 17 00:00:00 2001 From: Ruijing Dong Date: Wed, 22 Jun 2022 10:10:11 -0400 Subject: drm/amdgpu/vcn: fix no previous prototype warning Declare 'static', as the function is not intended to be used outside of this translation unit. Fixes: 4ed49c954e35 ("drm/amdgpu/vcn: add unified queue ib test") Reported-by: kernel test robot Reviewed-by: James Zhu Signed-off-by: Ruijing Dong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index fea436023351..1bfdfb9207ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -330,7 +330,7 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) } /* from vcn4 and above, only unified queue is used */ -bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring) +static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; bool ret = false; -- cgit v1.2.3 From 3d313f09f31490cec9d5251b59adeb6542c944cc Mon Sep 17 00:00:00 2001 From: Carlos Llamas Date: Tue, 21 Jun 2022 20:39:21 +0000 Subject: drm/fourcc: fix integer type usage in uapi header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Kernel uapi headers are supposed to use __[us]{8,16,32,64} types defined by as opposed to 'uint32_t' and similar. See [1] for the relevant discussion about this topic. In this particular case, the usage of 'uint64_t' escaped headers_check as these macros are not being called here. However, the following program triggers a compilation error: #include int main() { unsigned long x = AMD_FMT_MOD_CLEAR(RB); return 0; } gcc error: drm.c:5:27: error: ‘uint64_t’ undeclared (first use in this function) 5 | unsigned long x = AMD_FMT_MOD_CLEAR(RB); | ^~~~~~~~~~~~~~~~~ This patch changes AMD_FMT_MOD_{SET,CLEAR} macros to use the correct integer types, which fixes the above issue. [1] https://lkml.org/lkml/2019/6/5/18 Fixes: 8ba16d599374 ("drm/fourcc: Add AMD DRM modifiers.") Signed-off-by: Carlos Llamas Reviewed-by: Simon Ser Signed-off-by: Alex Deucher --- include/uapi/drm/drm_fourcc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 1d717c75e171..65af4a724b67 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -1446,11 +1446,11 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) #define AMD_FMT_MOD_PIPE_MASK 0x7 #define AMD_FMT_MOD_SET(field, value) \ - ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) + ((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT) #define AMD_FMT_MOD_GET(field, value) \ (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) #define AMD_FMT_MOD_CLEAR(field) \ - (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) + (~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) #if defined(__cplusplus) } -- cgit v1.2.3 From fa3dab48defe1ae2f5a5fb56df5f5931fb3e45c8 Mon Sep 17 00:00:00 2001 From: Jiang Jian Date: Wed, 22 Jun 2022 22:22:37 +0800 Subject: gpu/drm/radeon: Fix typo in comments Remove the repeated word 'and' from comments Signed-off-by: Jiang Jian Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/r300_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h index 60d5413bafa1..9d341cff63ee 100644 --- a/drivers/gpu/drm/radeon/r300_reg.h +++ b/drivers/gpu/drm/radeon/r300_reg.h @@ -1103,7 +1103,7 @@ * The destination register index is in FPI1 (color) and FPI3 (alpha) * together with enable bits. * There are separate enable bits for writing into temporary registers - * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_* + * (DSTC_REG_* /DSTA_REG) and program output registers (DSTC_OUTPUT_* * /DSTA_OUTPUT). You can write to both at once, or not write at all (the * same index must be used for both). * -- cgit v1.2.3 From 508f748b03949143ccda614b900e3f7d842251e5 Mon Sep 17 00:00:00 2001 From: Ruili Ji Date: Wed, 22 Jun 2022 14:20:22 +0800 Subject: drm/amdgpu: To flush tlb for MMHUB of RAVEN series amdgpu: [mmhub0] no-retry page fault (src_id:0 ring:40 vmid:8 pasid:32769, for process test_basic pid 3305 thread test_basic pid 3305) amdgpu: in page starting at address 0x00007ff990003000 from IH client 0x12 (VMC) amdgpu: VM_L2_PROTECTION_FAULT_STATUS:0x00840051 amdgpu: Faulty UTCL2 client ID: MP1 (0x0) amdgpu: MORE_FAULTS: 0x1 amdgpu: WALKER_ERROR: 0x0 amdgpu: PERMISSION_FAULTS: 0x5 amdgpu: MAPPING_ERROR: 0x0 amdgpu: RW: 0x1 When memory is allocated by kfd, no one triggers the tlb flush for MMHUB0. There is page fault from MMHUB0. v2:fix indentation v3:change subject and fix indentation Signed-off-by: Ruili Ji Reviewed-by: Philip Yang Reviewed-by: Aaron Liu Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 513c57f839d8..44da025502ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -727,7 +727,8 @@ int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev, { bool all_hub = false; - if (adev->family == AMDGPU_FAMILY_AI) + if (adev->family == AMDGPU_FAMILY_AI || + adev->family == AMDGPU_FAMILY_RV) all_hub = true; return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub); -- cgit v1.2.3 From ff83e6e7ab042e1f6f4345be1837d08c41b0a49d Mon Sep 17 00:00:00 2001 From: Graham Sider Date: Fri, 3 Jun 2022 09:53:54 -0400 Subject: drm/amdgpu: Fetch MES scheduler/KIQ versions Store MES scheduler and MES KIQ version numbers in amdgpu_mes for GFX11. Signed-off-by: Graham Sider Acked-by: Felix Kuehling Reviewed-by: Jack Xiao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 3 +++ drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 12 ++++++++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 25590b301f25..42f5a61dd2ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -65,6 +65,9 @@ struct amdgpu_mes { spinlock_t queue_id_lock; + uint32_t sched_version; + uint32_t kiq_version; + uint32_t total_max_queue; uint32_t doorbell_id_offset; uint32_t max_doorbell_slices; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 7eee004cf3ce..ead1860744d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -858,6 +858,18 @@ static int mes_v11_0_queue_init(struct amdgpu_device *adev, mes_v11_0_queue_init_register(ring); } + /* get MES scheduler/KIQ versions */ + mutex_lock(&adev->srbm_mutex); + soc21_grbm_select(adev, 3, pipe, 0, 0); + + if (pipe == AMDGPU_MES_SCHED_PIPE) + adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); + else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) + adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); + + soc21_grbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + return 0; } -- cgit v1.2.3 From e77a541f5dea0a2ff9d6a40dcda9b284e1e736fe Mon Sep 17 00:00:00 2001 From: Graham Sider Date: Wed, 11 May 2022 12:33:35 -0400 Subject: drm/amdkfd: Enable GFX11 usermode queue oversubscription MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Starting with GFX11, MES requires wptr BOs to be GTT allocated/mapped to GART for usermode queues in order to support oversubscription. In the case that work is submitted to an unmapped queue, MES must have a GART wptr address to determine whether the queue should be mapped. This change is accompanied with changes in MES and is applicable for MES_API_VERSION >= 2. v3: - Use amdgpu_vm_bo_lookup_mapping for wptr_bo mapping lookup - Move wptr_bo refcount increment to amdgpu_amdkfd_map_gtt_bo_to_gart - Remove list_del_init from amdgpu_amdkfd_map_gtt_bo_to_gart - Cleanup/fix create_queue wptr_bo error handling v4: - Add MES version shift/mask defines to amdgpu_mes.h - Change version check from MES_VERSION to MES_API_VERSION - Add check in kfd_ioctl_create_queue before wptr bo pin/GART map to ensure bo is a single page. Signed-off-by: Graham Sider Acked-by: Alex Deucher Acked-by: Christian König Reviewed-by: Philip Yang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 48 ++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 7 ++++ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 45 +++++++++++++++++++- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 9 +++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 2 + drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 ++ .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 17 +++++--- 8 files changed, 125 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 648c031942e9..b25b41f50213 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -286,6 +286,8 @@ int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem, void **kptr, uint64_t *size); void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem); +int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo); + int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info, struct dma_fence **ef); int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 8805bd1eed37..f3f9912fc51a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2113,6 +2113,54 @@ int amdgpu_amdkfd_gpuvm_sync_memory( return ret; } +/** + * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference count + * @adev: Device to which allocated BO belongs + * @bo: Buffer object to be mapped + * + * Before return, bo reference count is incremented. To release the reference and unpin/ + * unmap the BO, call amdgpu_amdkfd_free_gtt_mem. + */ +int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo) +{ + int ret; + + ret = amdgpu_bo_reserve(bo, true); + if (ret) { + pr_err("Failed to reserve bo. ret %d\n", ret); + goto err_reserve_bo_failed; + } + + ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); + if (ret) { + pr_err("Failed to pin bo. ret %d\n", ret); + goto err_pin_bo_failed; + } + + ret = amdgpu_ttm_alloc_gart(&bo->tbo); + if (ret) { + pr_err("Failed to bind bo to GART. ret %d\n", ret); + goto err_map_bo_gart_failed; + } + + amdgpu_amdkfd_remove_eviction_fence( + bo, bo->kfd_bo->process_info->eviction_fence); + + amdgpu_bo_unreserve(bo); + + bo = amdgpu_bo_ref(bo); + + return 0; + +err_map_bo_gart_failed: + amdgpu_bo_unpin(bo); +err_pin_bo_failed: + amdgpu_bo_unreserve(bo); +err_reserve_bo_failed: + + return ret; +} + /** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access * * @mem: Buffer object to be mapped for CPU access diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 42f5a61dd2ec..9c11219e925f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -33,6 +33,13 @@ #define AMDGPU_MES_MAX_GFX_PIPES 2 #define AMDGPU_MES_MAX_SDMA_PIPES 2 +#define AMDGPU_MES_API_VERSION_SHIFT 12 +#define AMDGPU_MES_FEAT_VERSION_SHIFT 24 + +#define AMDGPU_MES_VERSION_MASK 0x00000fff +#define AMDGPU_MES_API_VERSION_MASK 0x00fff000 +#define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 + enum amdgpu_mes_priority_level { AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 3bcf9bf29acb..d07588230ed6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -299,6 +299,7 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, struct kfd_process_device *pdd; struct queue_properties q_properties; uint32_t doorbell_offset_in_process = 0; + struct amdgpu_bo *wptr_bo = NULL; memset(&q_properties, 0, sizeof(struct queue_properties)); @@ -326,12 +327,49 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, goto err_bind_process; } + /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work + * on unmapped queues for usermode queue oversubscription (no aggregated doorbell) + */ + if (dev->shared_resources.enable_mes && + ((dev->adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) + >> AMDGPU_MES_API_VERSION_SHIFT) >= 2) { + struct amdgpu_bo_va_mapping *wptr_mapping; + struct amdgpu_vm *wptr_vm; + + wptr_vm = drm_priv_to_vm(pdd->drm_priv); + err = amdgpu_bo_reserve(wptr_vm->root.bo, false); + if (err) + goto err_wptr_map_gart; + + wptr_mapping = amdgpu_vm_bo_lookup_mapping( + wptr_vm, args->write_pointer_address >> PAGE_SHIFT); + amdgpu_bo_unreserve(wptr_vm->root.bo); + if (!wptr_mapping) { + pr_err("Failed to lookup wptr bo\n"); + err = -EINVAL; + goto err_wptr_map_gart; + } + + wptr_bo = wptr_mapping->bo_va->base.bo; + if (wptr_bo->tbo.base.size > PAGE_SIZE) { + pr_err("Requested GART mapping for wptr bo larger than one page\n"); + err = -EINVAL; + goto err_wptr_map_gart; + } + + err = amdgpu_amdkfd_map_gtt_bo_to_gart(dev->adev, wptr_bo); + if (err) { + pr_err("Failed to map wptr bo to GART\n"); + goto err_wptr_map_gart; + } + } + pr_debug("Creating queue for PASID 0x%x on gpu 0x%x\n", p->pasid, dev->id); - err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id, NULL, NULL, NULL, - &doorbell_offset_in_process); + err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id, wptr_bo, + NULL, NULL, NULL, &doorbell_offset_in_process); if (err != 0) goto err_create_queue; @@ -363,6 +401,9 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, return 0; err_create_queue: + if (wptr_bo) + amdgpu_amdkfd_free_gtt_mem(dev->adev, wptr_bo); +err_wptr_map_gart: err_bind_process: err_pdd: mutex_unlock(&p->mutex); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 213246a5b4e4..299927a4959b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -177,6 +177,7 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, struct kfd_process_device *pdd = qpd_to_pdd(qpd); struct mes_add_queue_input queue_input; int r, queue_type; + uint64_t wptr_addr_off; if (dqm->is_hws_hang) return -EIO; @@ -196,7 +197,13 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, AMDGPU_MES_PRIORITY_LEVEL_NORMAL; queue_input.doorbell_offset = q->properties.doorbell_off; queue_input.mqd_addr = q->gart_mqd_addr; - queue_input.wptr_addr = (uint64_t)q->properties.write_ptr; + + if (q->wptr_bo) { + wptr_addr_off = (uint64_t)q->properties.write_ptr - (uint64_t)q->wptr_bo->kfd_bo->va; + queue_input.wptr_addr = ((uint64_t)q->wptr_bo->tbo.resource->start << PAGE_SHIFT) + wptr_addr_off; + } else + queue_input.wptr_addr = (uint64_t)q->properties.write_ptr; + queue_input.paging = false; queue_input.tba_addr = qpd->tba_addr; queue_input.tma_addr = qpd->tma_addr; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c index 4e0387f591be..b8e14c2cc295 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -377,6 +377,8 @@ static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); + m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); + m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); m->sdmax_rlcx_doorbell_offset = q->doorbell_off << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 2585d6e61d42..4c4bbd493caa 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -571,6 +571,8 @@ struct queue { void *gang_ctx_bo; uint64_t gang_ctx_gpu_addr; void *gang_ctx_cpu_ptr; + + struct amdgpu_bo *wptr_bo; }; enum KFD_MQD_TYPE { @@ -1206,6 +1208,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, struct file *f, struct queue_properties *properties, unsigned int *qid, + struct amdgpu_bo *wptr_bo, const struct kfd_criu_queue_priv_data *q_data, const void *restore_mqd, const void *restore_ctl_stack, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 99f2a6412201..a46e2a37b4a6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -180,7 +180,8 @@ void pqm_uninit(struct process_queue_manager *pqm) static int init_user_queue(struct process_queue_manager *pqm, struct kfd_dev *dev, struct queue **q, struct queue_properties *q_properties, - struct file *f, unsigned int qid) + struct file *f, struct amdgpu_bo *wptr_bo, + unsigned int qid) { int retval; @@ -210,6 +211,7 @@ static int init_user_queue(struct process_queue_manager *pqm, goto cleanup; } memset((*q)->gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_CTX_SIZE); + (*q)->wptr_bo = wptr_bo; } pr_debug("PQM After init queue"); @@ -226,6 +228,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, struct file *f, struct queue_properties *properties, unsigned int *qid, + struct amdgpu_bo *wptr_bo, const struct kfd_criu_queue_priv_data *q_data, const void *restore_mqd, const void *restore_ctl_stack, @@ -288,7 +291,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, * allocate_sdma_queue() in create_queue() has the * corresponding check logic. */ - retval = init_user_queue(pqm, dev, &q, properties, f, *qid); + retval = init_user_queue(pqm, dev, &q, properties, f, wptr_bo, *qid); if (retval != 0) goto err_create_queue; pqn->q = q; @@ -309,7 +312,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, goto err_create_queue; } - retval = init_user_queue(pqm, dev, &q, properties, f, *qid); + retval = init_user_queue(pqm, dev, &q, properties, f, wptr_bo, *qid); if (retval != 0) goto err_create_queue; pqn->q = q; @@ -435,9 +438,13 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) pdd->qpd.num_gws = 0; } - if (dev->shared_resources.enable_mes) + if (dev->shared_resources.enable_mes) { amdgpu_amdkfd_free_gtt_mem(dev->adev, pqn->q->gang_ctx_bo); + if (pqn->q->wptr_bo) + amdgpu_amdkfd_free_gtt_mem(dev->adev, pqn->q->wptr_bo); + + } kfd_procfs_del_queue(pqn->q); uninit_queue(pqn->q); } @@ -844,7 +851,7 @@ int kfd_criu_restore_queue(struct kfd_process *p, print_queue_properties(&qp); - ret = pqm_create_queue(&p->pqm, pdd->dev, NULL, &qp, &queue_id, q_data, mqd, ctl_stack, + ret = pqm_create_queue(&p->pqm, pdd->dev, NULL, &qp, &queue_id, NULL, q_data, mqd, ctl_stack, NULL); if (ret) { pr_err("Failed to create new queue err:%d\n", ret); -- cgit v1.2.3 From a957995618a8afe3efa2b5746c0a954bbd450882 Mon Sep 17 00:00:00 2001 From: Graham Sider Date: Thu, 28 Apr 2022 10:16:16 -0400 Subject: drm/amdgpu: Update mes_v11_api_def.h Update MES API to support oversubscription without aggregated doorbell for usermode queues. v2: Change oversubscription_no_aggregated_en to is_kfd_process (align with MES) Signed-off-by: Graham Sider Acked-by: Felix Kuehling Reviewed-by: Jack Xiao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 1 + drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 ++ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 ++ drivers/gpu/drm/amd/include/mes_v11_api_def.h | 4 +++- 5 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 69a70a0aaed9..521e35d93d67 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -677,6 +677,7 @@ int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id, queue_input.wptr_addr = qprops->wptr_gpu_addr; queue_input.queue_type = qprops->queue_type; queue_input.paging = qprops->paging; + queue_input.is_kfd_process = 0; r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); if (r) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 9c11219e925f..85ebb5fdba0b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -214,6 +214,7 @@ struct mes_add_queue_input { uint32_t gws_size; uint64_t tba_addr; uint64_t tma_addr; + uint32_t is_kfd_process; }; struct mes_remove_queue_input { diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index ead1860744d8..7dfc6ea21397 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -165,6 +165,7 @@ static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, mes_add_queue_pkt.gws_size = input->gws_size; mes_add_queue_pkt.trap_handler_addr = input->tba_addr; mes_add_queue_pkt.tma_addr = input->tma_addr; + mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; mes_add_queue_pkt.api_status.api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; @@ -312,6 +313,7 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) mes_set_hw_res_pkt.disable_reset = 1; mes_set_hw_res_pkt.disable_mes_log = 1; mes_set_hw_res_pkt.use_different_vmid_compute = 1; + mes_set_hw_res_pkt.oversubscription_timer = 50; mes_set_hw_res_pkt.api_status.api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 299927a4959b..74a1f8a6f53f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -204,6 +204,8 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, } else queue_input.wptr_addr = (uint64_t)q->properties.write_ptr; + queue_input.is_kfd_process = 1; + queue_input.paging = false; queue_input.tba_addr = qpd->tba_addr; queue_input.tma_addr = qpd->tma_addr; diff --git a/drivers/gpu/drm/amd/include/mes_v11_api_def.h b/drivers/gpu/drm/amd/include/mes_v11_api_def.h index f9d02d7bdf77..fa1b9e0d299a 100644 --- a/drivers/gpu/drm/amd/include/mes_v11_api_def.h +++ b/drivers/gpu/drm/amd/include/mes_v11_api_def.h @@ -226,6 +226,7 @@ union MESAPI_SET_HW_RESOURCES { }; uint32_t uint32_t_all; }; + uint32_t oversubscription_timer; }; uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; @@ -265,7 +266,8 @@ union MESAPI__ADD_QUEUE { uint32_t is_gang_suspended : 1; uint32_t is_tmz_queue : 1; uint32_t map_kiq_utility_queue : 1; - uint32_t reserved : 23; + uint32_t is_kfd_process : 1; + uint32_t reserved : 22; }; struct MES_API_STATUS api_status; uint64_t tma_addr; -- cgit v1.2.3 From 10a9035c36d00586ad4bdb838f8800be951db8d2 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Thu, 23 Jun 2022 08:30:01 -0700 Subject: drm/amd/display: Fix indentation in dcn32_get_vco_frequency_from_reg() Clang warns: drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c:549:4: warning: misleading indentation; statement is not part of the previous 'else' [-Wmisleading-indentation] pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int); ^ drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c:542:3: note: previous statement is here else ^ 1 warning generated. Indent this statement to the left, as it was clearly intended to be called unconditionally, which will fix the warning. Link: https://github.com/ClangBuiltLinux/linux/issues/1655 Fixes: 3e838f7ccf64 ("drm/amd/display: Get VCO frequency from registers") Signed-off-by: Nathan Chancellor Reviewed-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 113f93b3d3b2..4e8059f20007 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -546,7 +546,7 @@ static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mg * this works because the int part is on the right edge of the register * and the frac part is on the left edge */ - pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int); + pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int); pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac; /* multiply by REFCLK period */ -- cgit v1.2.3 From 50ef0cacc43c5b01d5d1d65f08af33513b07e2c7 Mon Sep 17 00:00:00 2001 From: Jiang Jian Date: Thu, 23 Jun 2022 18:14:48 +0800 Subject: drm/amdgpu: drop unexpected word 'for' in comments there is an unexpected word 'for' in the comments that need to be dropped file - drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c line - 245 * position and also advance the position for for Vega10 changed to: * position and also advance the position for Vega10 Signed-off-by: Jiang Jian Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c index 3df146579ad9..1d5af50331e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c @@ -242,7 +242,7 @@ restart_ih: * @entry: IV entry * * Decodes the interrupt vector at the current rptr - * position and also advance the position for for Vega10 + * position and also advance the position for Vega10 * and later GPUs. */ void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev, -- cgit v1.2.3 From f64e6e0b6afe047cb0d34a5369597fe0d188e94d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 20 Jun 2022 18:29:39 -0400 Subject: Revert "drm/amdgpu/display: set vblank_disable_immediate for DC" This reverts commit 92020e81ddbeac351ea4a19bcf01743f32b9c800. This causes stuttering and timeouts with DMCUB for some users so revert it until we understand why and safely enable it to save power. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1887 Acked-by: Harry Wentland Signed-off-by: Alex Deucher Cc: Nicholas Kazlauskas --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 --- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index b4cf8717f554..89011bae7588 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -320,6 +320,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev) if (!amdgpu_device_has_dc_support(adev)) { if (!adev->enable_virtual_display) /* Disable vblank IRQs aggressively for power-saving */ + /* XXX: can this be enabled for DC? */ adev_to_drm(adev)->vblank_disable_immediate = true; r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index beadd75ab93d..2f7982fd7082 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4251,9 +4251,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) } } - /* Disable vblank IRQs aggressively for power-saving. */ - adev_to_drm(adev)->vblank_disable_immediate = true; - /* loops over all connectors on the board */ for (i = 0; i < link_cnt; i++) { struct dc_link *link = NULL; -- cgit v1.2.3 From 5027605aedec363b3209c17d382efe5e29211594 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Thu, 23 Jun 2022 13:14:18 -0400 Subject: drm/amdkfd: Fix spelling mistake "mechanim" -> "mechanism" There is a spelling mistake in a pr_debug message. Fix it. Signed-off-by: Colin Ian King Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index f3f9912fc51a..0036c9e405af 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -914,7 +914,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]); if (ret) goto unwind; - pr_debug("Employ DMABUF mechanim to enable peer GPU access\n"); + pr_debug("Employ DMABUF mechanism to enable peer GPU access\n"); } else { WARN_ONCE(true, "Handling invalid ATTACH request"); ret = -EINVAL; -- cgit v1.2.3 From 7fc494f9cf8ec7497d4aab26a3b19deceab0fe31 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Thu, 23 Jun 2022 13:19:04 -0400 Subject: drm/amdgpu/display: Fix spelling mistake "supporing" -> "supporting" There is a spelling mistake in a dml_print message. Fix it. Reviewed-by: Harry Wentland Signed-off-by: Colin Ian King Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index 510b7a81ee12..5bb6f4d8bf28 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -1098,7 +1098,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman if (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required && v->ImmediateFlipSupportedForPipe[k] == false) { v->ImmediateFlipSupported = false; #ifdef __DML_VBA_DEBUG__ - dml_print("DML::%s: Pipe %0d not supporing iflip\n", __func__, k); + dml_print("DML::%s: Pipe %0d not supporting iflip\n", __func__, k); #endif } } -- cgit v1.2.3 From 366e817e83e4d795fe3f6e7379bfe79d49cac89b Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Mon, 20 Jun 2022 02:37:20 +0200 Subject: Revert "drm/amd/display: ignore modifiers when checking for format support" This reverts commit 5089c4a8ebea3c3ad9eedf038dad7098ebc06131. This breaks validation and enumeration of display capable modifiers. The early return true means the rest of the validation code never gets executed, and we need that to enumerate the right modifiers to userspace for the format. The modifiers that are in the initial list generated for a plane are the superset for all formats and we need the proper checks in this function to filter some of them out for formats with which they're invalid to be used. Furthermore, the safety contract here is that we validate the incoming modifiers to ensure the kernel can handle them and the display hardware can handle them. This includes e.g. rejecting multi-plane images with DCC. Note that the legacy swizzle mechanism allows encoding more swizzles, and at fb creation time we convert them to modifiers and reject those with no corresponding modifiers. If we are seeing rejections I'm happy to help define modifiers that correspond to those, or if absolutely needed implement a fallback path to allow for less strict validation of the legacy path. However, I'd like to revert this patch, since any of these is going to be a significant rework of the patch, and I'd rather not the regression gets into a release or forgotten in the meantime. Reviewed-by: Aurabindo Pillai Signed-off-by: Bas Nieuwenhuizen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 53 +++-------------------- 1 file changed, 7 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2f7982fd7082..9195d6a8a51f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4890,7 +4890,8 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane, { struct amdgpu_device *adev = drm_to_adev(plane->dev); const struct drm_format_info *info = drm_format_info(format); - struct hw_asic_id asic_id = adev->dm.dc->ctx->asic_id; + int i; + enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3; if (!info) @@ -4906,53 +4907,13 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane, return true; } - /* check if swizzle mode is supported by this version of DCN */ - switch (asic_id.chip_family) { - case FAMILY_SI: - case FAMILY_CI: - case FAMILY_KV: - case FAMILY_CZ: - case FAMILY_VI: - /* asics before AI does not have modifier support */ - return false; - break; - case FAMILY_AI: - case FAMILY_RV: - case FAMILY_NV: - case FAMILY_VGH: - case FAMILY_YELLOW_CARP: - case AMDGPU_FAMILY_GC_10_3_6: - case AMDGPU_FAMILY_GC_10_3_7: - switch (AMD_FMT_MOD_GET(TILE, modifier)) { - case AMD_FMT_MOD_TILE_GFX9_64K_R_X: - case AMD_FMT_MOD_TILE_GFX9_64K_D_X: - case AMD_FMT_MOD_TILE_GFX9_64K_S_X: - case AMD_FMT_MOD_TILE_GFX9_64K_D: - return true; - break; - default: - return false; - break; - } - break; - case AMDGPU_FAMILY_GC_11_0_0: - switch (AMD_FMT_MOD_GET(TILE, modifier)) { - case AMD_FMT_MOD_TILE_GFX11_256K_R_X: - case AMD_FMT_MOD_TILE_GFX9_64K_R_X: - case AMD_FMT_MOD_TILE_GFX9_64K_D_X: - case AMD_FMT_MOD_TILE_GFX9_64K_S_X: - case AMD_FMT_MOD_TILE_GFX9_64K_D: - return true; - break; - default: - return false; - break; - } - break; - default: - ASSERT(0); /* Unknown asic */ + /* Check that the modifier is on the list of the plane's supported modifiers. */ + for (i = 0; i < plane->modifier_count; i++) { + if (modifier == plane->modifiers[i]) break; } + if (i == plane->modifier_count) + return false; /* * For D swizzle the canonical modifier depends on the bpp, so check -- cgit v1.2.3 From 01cf387b1c7f60527c91627528370f463bcb84f3 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 22 Jun 2022 10:36:58 -0400 Subject: drm/amdgpu/display: reduce stack size in dml32_ModeSupportAndSystemConfigurationFull() Move more stack variable in to dummy vars structure on the heap. Fixes stack frame size errors: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In function 'dml32_ModeSupportAndSystemConfigurationFull': drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:3833:1: error: the frame size of 2720 bytes is larger than 2048 bytes [-Werror=frame-larger-than=] 3833 | } // ModeSupportAndSystemConfigurationFull | ^ Fixes: dda4fb85e433 ("drm/amd/display: DML changes for DCN32/321") Cc: Stephen Rothwell Cc: Aurabindo Pillai Cc: Rodrigo Siqueira Jordao Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- .../amd/display/dc/dml/dcn32/display_mode_vba_32.c | 77 ++++++++++------------ .../gpu/drm/amd/display/dc/dml/display_mode_vba.h | 3 +- 2 files changed, 36 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index 5bb6f4d8bf28..7d536c2f4477 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -1660,8 +1660,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) { - bool dummy_boolean[2]; - unsigned int dummy_integer[1]; + unsigned int dummy_integer[4]; bool MPCCombineMethodAsNeededForPStateChangeAndVoltage; bool MPCCombineMethodAsPossible; enum odm_combine_mode dummy_odm_mode[DC__NUM_DPP__MAX]; @@ -1973,10 +1972,10 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[5], /* Long DETBufferSizeInKByte[] */ v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[6], /* Long DETBufferSizeY[] */ v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[7], /* Long DETBufferSizeC[] */ - &dummy_boolean[0], /* bool *UnboundedRequestEnabled */ - &dummy_integer[0], /* Long *CompressedBufferSizeInkByte */ + &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[0][0], /* bool *UnboundedRequestEnabled */ + &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[0][0], /* Long *CompressedBufferSizeInkByte */ mode_lib->vba.SingleDPPViewportSizeSupportPerSurface,/* bool ViewportSizeSupportPerSurface[] */ - &dummy_boolean[1]); /* bool *ViewportSizeSupport */ + &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[1][0]); /* bool *ViewportSizeSupport */ MPCCombineMethodAsNeededForPStateChangeAndVoltage = false; MPCCombineMethodAsPossible = false; @@ -2506,7 +2505,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l // for (i = 0; i < (int) v->soc.num_states; ++i) { for (j = 0; j <= 1; ++j) { - bool dummy_boolean_array[1][DC__NUM_DPP__MAX]; for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { mode_lib->vba.RequiredDPPCLKThisState[k] = mode_lib->vba.RequiredDPPCLK[i][j][k]; mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k]; @@ -2570,7 +2568,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.DETBufferSizeCThisState, &mode_lib->vba.UnboundedRequestEnabledThisState, &mode_lib->vba.CompressedBufferSizeInkByteThisState, - dummy_boolean_array[0], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[0], &mode_lib->vba.ViewportSizeSupport[i][j]); for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { @@ -2708,9 +2706,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } { - bool dummy_boolean_array[2][DC__NUM_DPP__MAX]; - unsigned int dummy_integer_array[22][DC__NUM_DPP__MAX]; - dml32_CalculateVMRowAndSwath( mode_lib->vba.NumberOfActiveSurfaces, v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters, @@ -2733,32 +2728,32 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l /* Output */ mode_lib->vba.PTEBufferSizeNotExceededPerState, mode_lib->vba.DCCMetaBufferSizeNotExceededPerState, - dummy_integer_array[0], - dummy_integer_array[1], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[0], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[1], mode_lib->vba.dpte_row_height, mode_lib->vba.dpte_row_height_chroma, - dummy_integer_array[2], - dummy_integer_array[3], - dummy_integer_array[4], - dummy_integer_array[5], - dummy_integer_array[6], - dummy_integer_array[7], - dummy_integer_array[8], - dummy_integer_array[9], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[2], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[3], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[4], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[5], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[6], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[7], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[8], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[9], mode_lib->vba.meta_row_height, mode_lib->vba.meta_row_height_chroma, - dummy_integer_array[10], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[10], mode_lib->vba.dpte_group_bytes, - dummy_integer_array[11], - dummy_integer_array[12], - dummy_integer_array[13], - dummy_integer_array[14], - dummy_integer_array[15], - dummy_integer_array[16], - dummy_integer_array[17], - dummy_integer_array[18], - dummy_integer_array[19], - dummy_integer_array[20], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[11], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[12], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[13], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[14], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[15], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[16], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[17], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[18], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[19], + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[20], mode_lib->vba.PrefetchLinesYThisState, mode_lib->vba.PrefetchLinesCThisState, mode_lib->vba.PrefillY, @@ -2772,9 +2767,9 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.MetaRowBytesThisState, mode_lib->vba.use_one_row_for_frame_this_state, mode_lib->vba.use_one_row_for_frame_flip_this_state, - dummy_boolean_array[0], // Boolean UsesMALLForStaticScreen[] - dummy_boolean_array[1], // Boolean PTE_BUFFER_MODE[] - dummy_integer_array[21]); // Long BIGK_FRAGMENT_SIZE[] + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[0], // Boolean UsesMALLForStaticScreen[] + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[1], // Boolean PTE_BUFFER_MODE[] + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[21]); // Long BIGK_FRAGMENT_SIZE[] } for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { @@ -3197,7 +3192,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { DmlPipe myPipe; - unsigned int dummy_integer; mode_lib->vba.TWait = dml32_CalculateTWait( mode_lib->vba.PrefetchModePerState[i][j], @@ -3294,7 +3288,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[0], // double *Tdmdl_vm &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[1], // double *Tdmdl &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[2], // double *TSetup - &dummy_integer, // unsigned int *VUpdateOffsetPix + &dummy_integer[0], // unsigned int *VUpdateOffsetPix &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[3], // unsigned int *VUpdateWidthPix &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[4]); // unsigned int *VReadyOffsetPix } @@ -3323,7 +3317,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } { - double dummy_single[2]; dml32_CalculatePrefetchBandwithSupport( mode_lib->vba.NumberOfActiveSurfaces, mode_lib->vba.ReturnBWPerState[i][j], @@ -3346,8 +3339,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.UrgentBurstFactorCursorPre, /* output */ - &dummy_single[0], // Single *PrefetchBandwidth - &dummy_single[1], // Single *FractionOfUrgentBandwidth + &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[0], // Single *PrefetchBandwidth + &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[1], // Single *FractionOfUrgentBandwidth &mode_lib->vba.PrefetchSupported[i][j]); } @@ -3457,7 +3450,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } { - double dummy_single[2]; dml32_CalculateImmediateFlipBandwithSupport(mode_lib->vba.NumberOfActiveSurfaces, mode_lib->vba.ReturnBWPerState[i][j], mode_lib->vba.ImmediateFlipRequirement, @@ -3480,8 +3472,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.UrgentBurstFactorCursorPre, /* output */ - &dummy_single[0], // Single *TotalBandwidth - &dummy_single[1], // Single *FractionOfUrgentBandwidth + &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[0], // Single *TotalBandwidth + &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[1], // Single *FractionOfUrgentBandwidth &mode_lib->vba.ImmediateFlipSupportedForState[i][j]); // Boolean *ImmediateFlipBandwidthSupport } @@ -3534,7 +3526,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SMNLatency = mode_lib->vba.SMNLatency; { - unsigned int dummy_integer[4]; dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( mode_lib->vba.USRRetrainingRequiredFinal, mode_lib->vba.UsesMALLForPStateChange, diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 9ad49ad38814..10ff536ef2a4 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -196,7 +196,7 @@ struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCal }; struct dml32_ModeSupportAndSystemConfigurationFull { - unsigned int dummy_integer_array[8][DC__NUM_DPP__MAX]; + unsigned int dummy_integer_array[22][DC__NUM_DPP__MAX]; double dummy_double_array[2][DC__NUM_DPP__MAX]; DmlPipe SurfParameters[DC__NUM_DPP__MAX]; double dummy_single[5]; @@ -207,6 +207,7 @@ struct dml32_ModeSupportAndSystemConfigurationFull { double DSTYAfterScaler[DC__NUM_DPP__MAX]; double DSTXAfterScaler[DC__NUM_DPP__MAX]; double MaxTotalVActiveRDBandwidth; + bool dummy_boolean_array[2][DC__NUM_DPP__MAX]; }; struct dummy_vars { -- cgit v1.2.3 From d7f0c8aff01340c2bed48f1e712a7f17c31b3db9 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Thu, 3 Mar 2022 14:39:22 +0800 Subject: drm/amdgpu: update GFX11 cs settings Update GFX11 cs related settings. Signed-off-by: Evan Quan Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/clearstate_gfx11.h | 307 +++++++++++++------------- 1 file changed, 158 insertions(+), 149 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx11.h b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx11.h index f3852b59b1d6..a8b29d33c464 100644 --- a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx11.h +++ b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx11.h @@ -39,7 +39,7 @@ static const unsigned int gfx11_SECT_CONTEXT_def_1[] = 0x00000000, // DB_DEPTH_CLEAR 0x00000000, // PA_SC_SCREEN_SCISSOR_TL 0x40004000, // PA_SC_SCREEN_SCISSOR_BR - 0x00000000, // DB_DFSM_CONTROL + 0, // HOLE 0x00000000, // DB_RESERVED_REG_2 0x00000000, // DB_Z_INFO 0x00000000, // DB_STENCIL_INFO @@ -50,7 +50,7 @@ static const unsigned int gfx11_SECT_CONTEXT_def_1[] = 0x00000000, // DB_RESERVED_REG_1 0x00000000, // DB_RESERVED_REG_3 0x00000000, // DB_SPI_VRS_CENTER_LOCATION - 0x00000000, // DB_VRS_OVERRIDE_CNTL + 0, // HOLE 0x00000000, // DB_Z_READ_BASE_HI 0x00000000, // DB_STENCIL_READ_BASE_HI 0x00000000, // DB_Z_WRITE_BASE_HI @@ -270,29 +270,29 @@ static const unsigned int gfx11_SECT_CONTEXT_def_2[] = 0x00000000, // PA_SC_FSR_EN 0x00000000, // PA_SC_FSR_FBW_RECURSIONS_X 0x00000000, // PA_SC_FSR_FBW_RECURSIONS_Y - 0x00000000, // PA_SC_VRS_RATE_FEEDBACK_VIEW + 0, // HOLE 0x00000000, // PA_SC_VRS_OVERRIDE_CNTL 0x00000000, // PA_SC_VRS_RATE_FEEDBACK_BASE 0x00000000, // PA_SC_VRS_RATE_FEEDBACK_BASE_EXT 0x00000000, // PA_SC_VRS_RATE_FEEDBACK_SIZE_XY 0x00000000, // PA_SC_BINNER_OUTPUT_TIMEOUT_CNTL - 0, // HOLE + 0x00000000, // PA_SC_VRS_RATE_CACHE_CNTL 0, // HOLE 0, // HOLE 0x00000000, // PA_SC_VRS_RATE_BASE 0x00000000, // PA_SC_VRS_RATE_BASE_EXT 0x00000000, // PA_SC_VRS_RATE_SIZE_XY - 0x00000000, // PA_SC_VRS_RATE_VIEW - 0xffffffff, // VGT_MAX_VTX_INDX - 0x00000000, // VGT_MIN_VTX_INDX - 0x00000000, // VGT_INDX_OFFSET + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE 0x00000000, // VGT_MULTI_PRIM_IB_RESET_INDX 0x00550055, // CB_RMI_GL2_CACHE_CONTROL 0x00000000, // CB_BLEND_RED 0x00000000, // CB_BLEND_GREEN 0x00000000, // CB_BLEND_BLUE 0x00000000, // CB_BLEND_ALPHA - 0x00000000, // CB_DCC_CONTROL + 0x00000000, // CB_FDCC_CONTROL 0x00000000, // CB_COVERAGE_OUT_CONTROL 0x00000000, // DB_STENCIL_CONTROL 0x01000000, // DB_STENCILREFMASK @@ -470,8 +470,8 @@ static const unsigned int gfx11_SECT_CONTEXT_def_2[] = 0x00000000, // SPI_BARYC_CNTL 0, // HOLE 0x00000000, // SPI_TMPRING_SIZE - 0, // HOLE - 0, // HOLE + 0x00000000, // SPI_GFX_SCRATCH_BASE_LO + 0x00000000, // SPI_GFX_SCRATCH_BASE_HI 0, // HOLE 0, // HOLE 0, // HOLE @@ -545,7 +545,7 @@ static const unsigned int gfx11_SECT_CONTEXT_def_4[] = 0x00000000, // PA_STEREO_CNTL 0x00000000, // PA_STATE_STEREO_X 0x00000000, // PA_CL_VRS_CNTL - 0x00000000, // PA_SIDEBAND_REQUEST_DELAYS + 0, // HOLE 0, // HOLE 0, // HOLE 0, // HOLE @@ -658,30 +658,30 @@ static const unsigned int gfx11_SECT_CONTEXT_def_4[] = 0x00000000, // PA_SU_POINT_MINMAX 0x00000000, // PA_SU_LINE_CNTL 0x00000000, // PA_SC_LINE_STIPPLE - 0x00000000, // VGT_OUTPUT_PATH_CNTL - 0x00000000, // VGT_HOS_CNTL + 0, // HOLE + 0, // HOLE 0x00000000, // VGT_HOS_MAX_TESS_LEVEL 0x00000000, // VGT_HOS_MIN_TESS_LEVEL - 0x00000000, // VGT_HOS_REUSE_DEPTH - 0x00000000, // VGT_GROUP_PRIM_TYPE - 0x00000000, // VGT_GROUP_FIRST_DECR - 0x00000000, // VGT_GROUP_DECR - 0x00000000, // VGT_GROUP_VECT_0_CNTL - 0x00000000, // VGT_GROUP_VECT_1_CNTL - 0x00000000, // VGT_GROUP_VECT_0_FMT_CNTL - 0x00000000, // VGT_GROUP_VECT_1_FMT_CNTL - 0x00000000, // VGT_GS_MODE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE 0x00000000, // VGT_GS_ONCHIP_CNTL 0x00000000, // PA_SC_MODE_CNTL_0 0x00000000, // PA_SC_MODE_CNTL_1 0x00000000, // VGT_ENHANCE - 0x00000100, // VGT_GS_PER_ES - 0x00000080, // VGT_ES_PER_GS - 0x00000002, // VGT_GS_PER_VS - 0x00000000, // VGT_GSVS_RING_OFFSET_1 - 0x00000000, // VGT_GSVS_RING_OFFSET_2 - 0x00000000, // VGT_GSVS_RING_OFFSET_3 - 0x00000000, // VGT_GS_OUT_PRIM_TYPE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE 0x00000000, // IA_ENHANCE }; static const unsigned int gfx11_SECT_CONTEXT_def_5[] = @@ -695,37 +695,36 @@ static const unsigned int gfx11_SECT_CONTEXT_def_6[] = }; static const unsigned int gfx11_SECT_CONTEXT_def_7[] = { - 0x00000000, // VGT_MULTI_PRIM_IB_RESET_EN 0x00000000, // VGT_DRAW_PAYLOAD_CNTL 0, // HOLE - 0x00000000, // VGT_INSTANCE_STEP_RATE_0 - 0x00000000, // VGT_INSTANCE_STEP_RATE_1 - 0x000000ff, // IA_MULTI_VGT_PARAM + 0, // HOLE + 0, // HOLE + 0, // HOLE 0x00000000, // VGT_ESGS_RING_ITEMSIZE - 0x00000000, // VGT_GSVS_RING_ITEMSIZE + 0, // HOLE 0x00000000, // VGT_REUSE_OFF - 0x00000000, // VGT_VTX_CNT_EN + 0, // HOLE 0x00000000, // DB_HTILE_SURFACE 0x00000000, // DB_SRESULTS_COMPARE_STATE0 0x00000000, // DB_SRESULTS_COMPARE_STATE1 0x00000000, // DB_PRELOAD_CONTROL 0, // HOLE - 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_0 - 0x00000000, // VGT_STRMOUT_VTX_STRIDE_0 0, // HOLE - 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_0 - 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_1 - 0x00000000, // VGT_STRMOUT_VTX_STRIDE_1 0, // HOLE - 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_1 - 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_2 - 0x00000000, // VGT_STRMOUT_VTX_STRIDE_2 0, // HOLE - 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_2 - 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_3 - 0x00000000, // VGT_STRMOUT_VTX_STRIDE_3 0, // HOLE - 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_3 + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE 0, // HOLE 0, // HOLE 0, // HOLE @@ -745,10 +744,10 @@ static const unsigned int gfx11_SECT_CONTEXT_def_7[] = 0x00000000, // VGT_TESS_DISTRIBUTION 0x00000000, // VGT_SHADER_STAGES_EN 0x00000000, // VGT_LS_HS_CONFIG - 0x00000000, // VGT_GS_VERT_ITEMSIZE - 0x00000000, // VGT_GS_VERT_ITEMSIZE_1 - 0x00000000, // VGT_GS_VERT_ITEMSIZE_2 - 0x00000000, // VGT_GS_VERT_ITEMSIZE_3 + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE 0x00000000, // VGT_TF_PARAM 0x00000000, // DB_ALPHA_TO_MASK 0, // HOLE @@ -759,11 +758,22 @@ static const unsigned int gfx11_SECT_CONTEXT_def_7[] = 0x00000000, // PA_SU_POLY_OFFSET_BACK_SCALE 0x00000000, // PA_SU_POLY_OFFSET_BACK_OFFSET 0x00000000, // VGT_GS_INSTANCE_CNT - 0x00000000, // VGT_STRMOUT_CONFIG - 0x00000000, // VGT_STRMOUT_BUFFER_CONFIG -}; -static const unsigned int gfx11_SECT_CONTEXT_def_8[] = -{ + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE 0x00000000, // PA_SC_CENTROID_PRIORITY_0 0x00000000, // PA_SC_CENTROID_PRIORITY_1 0x00001000, // PA_SC_LINE_CNTL @@ -797,126 +807,126 @@ static const unsigned int gfx11_SECT_CONTEXT_def_8[] = 0x00100000, // PA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x00000000, // PA_SC_NGG_MODE_CNTL 0x00000000, // PA_SC_BINNER_CNTL_2 - 0x0000001e, // VGT_VERTEX_REUSE_BLOCK_CNTL - 0x00000020, // VGT_OUT_DEALLOC_CNTL + 0, // HOLE + 0, // HOLE 0x00000000, // CB_COLOR0_BASE - 0x00000000, // CB_COLOR0_PITCH - 0x00000000, // CB_COLOR0_SLICE + 0, // HOLE + 0, // HOLE 0x00000000, // CB_COLOR0_VIEW 0x00000000, // CB_COLOR0_INFO 0x00000000, // CB_COLOR0_ATTRIB - 0x00000000, // CB_COLOR0_DCC_CONTROL - 0x00000000, // CB_COLOR0_CMASK - 0x00000000, // CB_COLOR0_CMASK_SLICE - 0x00000000, // CB_COLOR0_FMASK - 0x00000000, // CB_COLOR0_FMASK_SLICE - 0x00000000, // CB_COLOR0_CLEAR_WORD0 - 0x00000000, // CB_COLOR0_CLEAR_WORD1 + 0x00000000, // CB_COLOR0_FDCC_CONTROL + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE 0x00000000, // CB_COLOR0_DCC_BASE 0, // HOLE 0x00000000, // CB_COLOR1_BASE - 0x00000000, // CB_COLOR1_PITCH - 0x00000000, // CB_COLOR1_SLICE + 0, // HOLE + 0, // HOLE 0x00000000, // CB_COLOR1_VIEW 0x00000000, // CB_COLOR1_INFO 0x00000000, // CB_COLOR1_ATTRIB - 0x00000000, // CB_COLOR1_DCC_CONTROL - 0x00000000, // CB_COLOR1_CMASK - 0x00000000, // CB_COLOR1_CMASK_SLICE - 0x00000000, // CB_COLOR1_FMASK - 0x00000000, // CB_COLOR1_FMASK_SLICE - 0x00000000, // CB_COLOR1_CLEAR_WORD0 - 0x00000000, // CB_COLOR1_CLEAR_WORD1 + 0x00000000, // CB_COLOR1_FDCC_CONTROL + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE 0x00000000, // CB_COLOR1_DCC_BASE 0, // HOLE 0x00000000, // CB_COLOR2_BASE - 0x00000000, // CB_COLOR2_PITCH - 0x00000000, // CB_COLOR2_SLICE + 0, // HOLE + 0, // HOLE 0x00000000, // CB_COLOR2_VIEW 0x00000000, // CB_COLOR2_INFO 0x00000000, // CB_COLOR2_ATTRIB - 0x00000000, // CB_COLOR2_DCC_CONTROL - 0x00000000, // CB_COLOR2_CMASK - 0x00000000, // CB_COLOR2_CMASK_SLICE - 0x00000000, // CB_COLOR2_FMASK - 0x00000000, // CB_COLOR2_FMASK_SLICE - 0x00000000, // CB_COLOR2_CLEAR_WORD0 - 0x00000000, // CB_COLOR2_CLEAR_WORD1 + 0x00000000, // CB_COLOR2_FDCC_CONTROL + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE 0x00000000, // CB_COLOR2_DCC_BASE 0, // HOLE 0x00000000, // CB_COLOR3_BASE - 0x00000000, // CB_COLOR3_PITCH - 0x00000000, // CB_COLOR3_SLICE + 0, // HOLE + 0, // HOLE 0x00000000, // CB_COLOR3_VIEW 0x00000000, // CB_COLOR3_INFO 0x00000000, // CB_COLOR3_ATTRIB - 0x00000000, // CB_COLOR3_DCC_CONTROL - 0x00000000, // CB_COLOR3_CMASK - 0x00000000, // CB_COLOR3_CMASK_SLICE - 0x00000000, // CB_COLOR3_FMASK - 0x00000000, // CB_COLOR3_FMASK_SLICE - 0x00000000, // CB_COLOR3_CLEAR_WORD0 - 0x00000000, // CB_COLOR3_CLEAR_WORD1 + 0x00000000, // CB_COLOR3_FDCC_CONTROL + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE 0x00000000, // CB_COLOR3_DCC_BASE 0, // HOLE 0x00000000, // CB_COLOR4_BASE - 0x00000000, // CB_COLOR4_PITCH - 0x00000000, // CB_COLOR4_SLICE + 0, // HOLE + 0, // HOLE 0x00000000, // CB_COLOR4_VIEW 0x00000000, // CB_COLOR4_INFO 0x00000000, // CB_COLOR4_ATTRIB - 0x00000000, // CB_COLOR4_DCC_CONTROL - 0x00000000, // CB_COLOR4_CMASK - 0x00000000, // CB_COLOR4_CMASK_SLICE - 0x00000000, // CB_COLOR4_FMASK - 0x00000000, // CB_COLOR4_FMASK_SLICE - 0x00000000, // CB_COLOR4_CLEAR_WORD0 - 0x00000000, // CB_COLOR4_CLEAR_WORD1 + 0x00000000, // CB_COLOR4_FDCC_CONTROL + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE 0x00000000, // CB_COLOR4_DCC_BASE 0, // HOLE 0x00000000, // CB_COLOR5_BASE - 0x00000000, // CB_COLOR5_PITCH - 0x00000000, // CB_COLOR5_SLICE + 0, // HOLE + 0, // HOLE 0x00000000, // CB_COLOR5_VIEW 0x00000000, // CB_COLOR5_INFO 0x00000000, // CB_COLOR5_ATTRIB - 0x00000000, // CB_COLOR5_DCC_CONTROL - 0x00000000, // CB_COLOR5_CMASK - 0x00000000, // CB_COLOR5_CMASK_SLICE - 0x00000000, // CB_COLOR5_FMASK - 0x00000000, // CB_COLOR5_FMASK_SLICE - 0x00000000, // CB_COLOR5_CLEAR_WORD0 - 0x00000000, // CB_COLOR5_CLEAR_WORD1 + 0x00000000, // CB_COLOR5_FDCC_CONTROL + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE 0x00000000, // CB_COLOR5_DCC_BASE 0, // HOLE 0x00000000, // CB_COLOR6_BASE - 0x00000000, // CB_COLOR6_PITCH - 0x00000000, // CB_COLOR6_SLICE + 0, // HOLE + 0, // HOLE 0x00000000, // CB_COLOR6_VIEW 0x00000000, // CB_COLOR6_INFO 0x00000000, // CB_COLOR6_ATTRIB - 0x00000000, // CB_COLOR6_DCC_CONTROL - 0x00000000, // CB_COLOR6_CMASK - 0x00000000, // CB_COLOR6_CMASK_SLICE - 0x00000000, // CB_COLOR6_FMASK - 0x00000000, // CB_COLOR6_FMASK_SLICE - 0x00000000, // CB_COLOR6_CLEAR_WORD0 - 0x00000000, // CB_COLOR6_CLEAR_WORD1 + 0x00000000, // CB_COLOR6_FDCC_CONTROL + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE 0x00000000, // CB_COLOR6_DCC_BASE 0, // HOLE 0x00000000, // CB_COLOR7_BASE - 0x00000000, // CB_COLOR7_PITCH - 0x00000000, // CB_COLOR7_SLICE + 0, // HOLE + 0, // HOLE 0x00000000, // CB_COLOR7_VIEW 0x00000000, // CB_COLOR7_INFO 0x00000000, // CB_COLOR7_ATTRIB - 0x00000000, // CB_COLOR7_DCC_CONTROL - 0x00000000, // CB_COLOR7_CMASK - 0x00000000, // CB_COLOR7_CMASK_SLICE - 0x00000000, // CB_COLOR7_FMASK - 0x00000000, // CB_COLOR7_FMASK_SLICE - 0x00000000, // CB_COLOR7_CLEAR_WORD0 - 0x00000000, // CB_COLOR7_CLEAR_WORD1 + 0x00000000, // CB_COLOR7_FDCC_CONTROL + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE 0x00000000, // CB_COLOR7_DCC_BASE 0, // HOLE 0x00000000, // CB_COLOR0_BASE_EXT @@ -927,22 +937,22 @@ static const unsigned int gfx11_SECT_CONTEXT_def_8[] = 0x00000000, // CB_COLOR5_BASE_EXT 0x00000000, // CB_COLOR6_BASE_EXT 0x00000000, // CB_COLOR7_BASE_EXT - 0x00000000, // CB_COLOR0_CMASK_BASE_EXT - 0x00000000, // CB_COLOR1_CMASK_BASE_EXT - 0x00000000, // CB_COLOR2_CMASK_BASE_EXT - 0x00000000, // CB_COLOR3_CMASK_BASE_EXT - 0x00000000, // CB_COLOR4_CMASK_BASE_EXT - 0x00000000, // CB_COLOR5_CMASK_BASE_EXT - 0x00000000, // CB_COLOR6_CMASK_BASE_EXT - 0x00000000, // CB_COLOR7_CMASK_BASE_EXT - 0x00000000, // CB_COLOR0_FMASK_BASE_EXT - 0x00000000, // CB_COLOR1_FMASK_BASE_EXT - 0x00000000, // CB_COLOR2_FMASK_BASE_EXT - 0x00000000, // CB_COLOR3_FMASK_BASE_EXT - 0x00000000, // CB_COLOR4_FMASK_BASE_EXT - 0x00000000, // CB_COLOR5_FMASK_BASE_EXT - 0x00000000, // CB_COLOR6_FMASK_BASE_EXT - 0x00000000, // CB_COLOR7_FMASK_BASE_EXT + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE 0x00000000, // CB_COLOR0_DCC_BASE_EXT 0x00000000, // CB_COLOR1_DCC_BASE_EXT 0x00000000, // CB_COLOR2_DCC_BASE_EXT @@ -976,8 +986,7 @@ static const struct cs_extent_def gfx11_SECT_CONTEXT_defs[] = {gfx11_SECT_CONTEXT_def_4, 0x0000a1ff, 158 }, {gfx11_SECT_CONTEXT_def_5, 0x0000a2a0, 2 }, {gfx11_SECT_CONTEXT_def_6, 0x0000a2a3, 1 }, - {gfx11_SECT_CONTEXT_def_7, 0x0000a2a5, 66 }, - {gfx11_SECT_CONTEXT_def_8, 0x0000a2f5, 203 }, + {gfx11_SECT_CONTEXT_def_7, 0x0000a2a6, 282 }, { 0, 0, 0 } }; static const struct cs_section_def gfx11_cs_data[] = { -- cgit v1.2.3 From 1d3182006cf6eea26d0cd752f8042c3cae43139b Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Tue, 14 Jun 2022 15:21:48 +0800 Subject: drm/amd/pm: enable VR0 HOT support for SMU 13.0.0 Enable VR0 Hot support for SMU 13.0.0. Signed-off-by: Evan Quan Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index 6fb2b072a730..ce2fa04e3926 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -308,6 +308,8 @@ smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu, *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_UCLK_BIT); + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT); + return 0; } -- cgit v1.2.3 From ca0cb8959f7b84742c3dd612f5b044788cddfcc7 Mon Sep 17 00:00:00 2001 From: Chandan Vurdigere Nataraj Date: Thu, 23 Jun 2022 12:48:49 +0530 Subject: drm/amd/display : Log DP link training failure reason [Why] Existing logs doesn't print DP LT failure reason [How] Update the existing log with DP LT failure reason Signed-off-by: Chandan Vurdigere Nataraj Reviewed-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 4027f439a5a4..c8355acd3672 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2786,9 +2786,9 @@ bool perform_link_training_with_retries( break; } - DC_LOG_WARNING("%s: Link(%d) training attempt %u of %d failed @ rate(%d) x lane(%d)\n", + DC_LOG_WARNING("%s: Link(%d) training attempt %u of %d failed @ rate(%d) x lane(%d) : fail reason:(%d)\n", __func__, link->link_index, (unsigned int)j + 1, attempts, cur_link_settings.link_rate, - cur_link_settings.lane_count); + cur_link_settings.lane_count, status); dp_disable_link_phy(link, &pipe_ctx->link_res, signal); -- cgit v1.2.3 From fe4e9ff9873758ad07e6f7b3088ae3a9dd3ff1b3 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Thu, 2 Jun 2022 16:37:56 +0800 Subject: drm/amdgpu: add mc wptr addr support for mes MES requires mc wptr address for usermode queues. Export bo gart address for mc wptr address. Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 10 ++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h | 1 + drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 8 +++++++- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 6 +++--- 5 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 521e35d93d67..0c9cb493a85c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -675,6 +675,7 @@ int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id, queue_input.doorbell_offset = qprops->doorbell_off; queue_input.mqd_addr = queue->mqd_gpu_addr; queue_input.wptr_addr = qprops->wptr_gpu_addr; + queue_input.wptr_mc_addr = qprops->wptr_mc_addr; queue_input.queue_type = qprops->queue_type; queue_input.paging = qprops->paging; queue_input.is_kfd_process = 0; @@ -802,6 +803,8 @@ amdgpu_mes_ring_to_queue_props(struct amdgpu_device *adev, props->hqd_base_gpu_addr = ring->gpu_addr; props->rptr_gpu_addr = ring->rptr_gpu_addr; props->wptr_gpu_addr = ring->wptr_gpu_addr; + props->wptr_mc_addr = + ring->mes_ctx->meta_data_mc_addr + ring->wptr_offs; props->queue_size = ring->ring_size; props->eop_gpu_addr = ring->eop_gpu_addr; props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL; @@ -962,7 +965,8 @@ int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev, r = amdgpu_bo_create_kernel(adev, sizeof(struct amdgpu_mes_ctx_meta_data), PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, - &ctx_data->meta_data_obj, NULL, + &ctx_data->meta_data_obj, + &ctx_data->meta_data_mc_addr, &ctx_data->meta_data_ptr); if (!ctx_data->meta_data_obj) return -ENOMEM; @@ -976,7 +980,9 @@ int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev, void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data) { if (ctx_data->meta_data_obj) - amdgpu_bo_free_kernel(&ctx_data->meta_data_obj, NULL, NULL); + amdgpu_bo_free_kernel(&ctx_data->meta_data_obj, + &ctx_data->meta_data_mc_addr, + &ctx_data->meta_data_ptr); } int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 85ebb5fdba0b..074418c63e4b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -176,6 +176,7 @@ struct amdgpu_mes_queue_properties { uint64_t hqd_base_gpu_addr; uint64_t rptr_gpu_addr; uint64_t wptr_gpu_addr; + uint64_t wptr_mc_addr; uint32_t queue_size; uint64_t eop_gpu_addr; uint32_t hqd_pipe_priority; @@ -208,6 +209,7 @@ struct mes_add_queue_input { uint32_t doorbell_offset; uint64_t mqd_addr; uint64_t wptr_addr; + uint64_t wptr_mc_addr; uint32_t queue_type; uint32_t paging; uint32_t gws_base; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h index c000f656aae5..912a5be2ece6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h @@ -107,6 +107,7 @@ struct amdgpu_mes_ctx_meta_data { struct amdgpu_mes_ctx_data { struct amdgpu_bo *meta_data_obj; uint64_t meta_data_gpu_addr; + uint64_t meta_data_mc_addr; struct amdgpu_bo_va *meta_data_va; void *meta_data_ptr; uint32_t gang_ids[AMDGPU_HW_IP_DMA+1]; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 7dfc6ea21397..89b99dc827a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -156,7 +156,13 @@ static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, input->gang_global_priority_level; mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; mes_add_queue_pkt.mqd_addr = input->mqd_addr; - mes_add_queue_pkt.wptr_addr = input->wptr_addr; + + if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> + AMDGPU_MES_API_VERSION_SHIFT) >= 2) + mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; + else + mes_add_queue_pkt.wptr_addr = input->wptr_addr; + mes_add_queue_pkt.queue_type = convert_to_mes_queue_type(input->queue_type); mes_add_queue_pkt.paging = input->paging; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 74a1f8a6f53f..21e451acfa59 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -197,12 +197,12 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, AMDGPU_MES_PRIORITY_LEVEL_NORMAL; queue_input.doorbell_offset = q->properties.doorbell_off; queue_input.mqd_addr = q->gart_mqd_addr; + queue_input.wptr_addr = (uint64_t)q->properties.write_ptr; if (q->wptr_bo) { wptr_addr_off = (uint64_t)q->properties.write_ptr - (uint64_t)q->wptr_bo->kfd_bo->va; - queue_input.wptr_addr = ((uint64_t)q->wptr_bo->tbo.resource->start << PAGE_SHIFT) + wptr_addr_off; - } else - queue_input.wptr_addr = (uint64_t)q->properties.write_ptr; + queue_input.wptr_mc_addr = ((uint64_t)q->wptr_bo->tbo.resource->start << PAGE_SHIFT) + wptr_addr_off; + } queue_input.is_kfd_process = 1; -- cgit v1.2.3 From 5c4904ac34b76eb58abc15a52603ee59bf8be85d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 27 Jun 2022 12:52:17 +0800 Subject: drm/amdgpu: Remove useless amdgpu_display_freesync_ioctl() declaration Signed-off-by: Leslie Shi Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h index 7b6d83e2b13c..560352f7c317 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h @@ -35,8 +35,6 @@ #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) -int amdgpu_display_freesync_ioctl(struct drm_device *dev, void *data, - struct drm_file *filp); void amdgpu_display_update_priority(struct amdgpu_device *adev); uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, uint64_t bo_flags); -- cgit v1.2.3 From dd70748eda3f63217d5284f48651239a9721245e Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Mon, 20 Jun 2022 13:08:52 -0400 Subject: drm/amdgpu: Add put fence in amdgpu_fence_driver_clear_job_fences MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This function should drop the fence refcount when it extracts the fence from the fence array, just as it's done in amdgpu_fence_process. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 957437a5558c..a9ae3beaa1d3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -595,8 +595,10 @@ void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring) for (i = 0; i <= ring->fence_drv.num_fences_mask; i++) { ptr = &ring->fence_drv.fences[i]; old = rcu_dereference_protected(*ptr, 1); - if (old && old->ops == &amdgpu_job_fence_ops) + if (old && old->ops == &amdgpu_job_fence_ops) { RCU_INIT_POINTER(*ptr, NULL); + dma_fence_put(old); + } } } -- cgit v1.2.3 From 9e225fb9e636b31b97e9d35324c2f9e43ee0aab4 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Sat, 18 Jun 2022 00:28:50 -0400 Subject: drm/amdgpu: Prevent race between late signaled fences and GPU reset. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Problem: After we start handling timed out jobs we assume there fences won't be signaled but we cannot be sure and sometimes they fire late. We need to prevent concurrent accesses to fence array from amdgpu_fence_driver_clear_job_fences during GPU reset and amdgpu_fence_process from a late EOP interrupt. Fix: Before accessing fence array in GPU disable EOP interrupt and flush all pending interrupt handlers for amdgpu device's interrupt line. v2: Switch from irq_get/put to full enable/disable_irq for amdgpu Signed-off-by: Andrey Grodzovsky Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 18 ++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 + 3 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index f2a4c268ac72..9d2395ab4f70 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4606,6 +4606,8 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, amdgpu_virt_fini_data_exchange(adev); } + amdgpu_fence_driver_isr_toggle(adev, true); + /* block all schedulers and reset given job's ring */ for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { struct amdgpu_ring *ring = adev->rings[i]; @@ -4621,6 +4623,8 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, amdgpu_fence_driver_force_completion(ring); } + amdgpu_fence_driver_isr_toggle(adev, false); + if (job && job->vm) drm_sched_increase_karma(&job->base); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index a9ae3beaa1d3..c1d04ea3c67f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -532,6 +532,24 @@ void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev) } } +/* Will either stop and flush handlers for amdgpu interrupt or reanble it */ +void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop) +{ + int i; + + for (i = 0; i < AMDGPU_MAX_RINGS; i++) { + struct amdgpu_ring *ring = adev->rings[i]; + + if (!ring || !ring->fence_drv.initialized || !ring->fence_drv.irq_src) + continue; + + if (stop) + disable_irq(adev->irq.irq); + else + enable_irq(adev->irq.irq); + } +} + void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev) { unsigned int i, j; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 7d89a52091c0..82c178a9033a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -143,6 +143,7 @@ signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, uint32_t wait_seq, signed long timeout); unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); +void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop); /* * Rings. -- cgit v1.2.3 From 45ecaea738830b9d521c93520c8f201359dcbd95 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Mon, 20 Jun 2022 16:39:47 -0400 Subject: drm/sched: Partial revert of 'drm/sched: Keep s_fence->parent pointer' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Problem: This patch caused negative refcount as described in [1] because for that case parent fence did not signal by the time of drm_sched_stop and hence kept in pending list the assumption was they will not signal and so fence was put to account for the s_fence->parent refcount but for amdgpu which has embedded HW fence (always same parent fence) drm_sched_fence_release_scheduled was always called and would still drop the count for parent fence once more. For jobs that never signaled this imbalance was masked by refcount bug in amdgpu_fence_driver_clear_job_fences that would not drop refcount on the fences that were removed from fence drive fences array (against prevois insertion into the array in get in amdgpu_fence_emit). Fix: Revert this patch and by setting s_job->s_fence->parent to NULL as before prevent the extra refcount drop in amdgpu when drm_sched_fence_release_scheduled is called on job release. Also - align behaviour in drm_sched_resubmit_jobs_ext with that of drm_sched_main when submitting jobs - take a refcount for the new parent fence pointer and drop refcount for original kref_init for new HW fence creation (or fake new HW fence in amdgpu - see next patch). [1] - https://lore.kernel.org/all/731b7ff1-3cc9-e314-df2a-7c51b76d4db0@amd.com/t/#r00c728fcc069b1276642c325bfa9d82bf8fa21a3 Signed-off-by: Andrey Grodzovsky Tested-by: Yiqing Yao Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/scheduler/sched_main.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c index 76fd2904c7c6..68317d3a7a27 100644 --- a/drivers/gpu/drm/scheduler/sched_main.c +++ b/drivers/gpu/drm/scheduler/sched_main.c @@ -419,6 +419,8 @@ void drm_sched_stop(struct drm_gpu_scheduler *sched, struct drm_sched_job *bad) if (s_job->s_fence->parent && dma_fence_remove_callback(s_job->s_fence->parent, &s_job->cb)) { + dma_fence_put(s_job->s_fence->parent); + s_job->s_fence->parent = NULL; atomic_dec(&sched->hw_rq_count); } else { /* @@ -548,7 +550,6 @@ void drm_sched_resubmit_jobs_ext(struct drm_gpu_scheduler *sched, int max) if (found_guilty && s_job->s_fence->scheduled.context == guilty_context) dma_fence_set_error(&s_fence->finished, -ECANCELED); - dma_fence_put(s_job->s_fence->parent); fence = sched->ops->run_job(s_job); i++; @@ -558,7 +559,11 @@ void drm_sched_resubmit_jobs_ext(struct drm_gpu_scheduler *sched, int max) s_job->s_fence->parent = NULL; } else { - s_job->s_fence->parent = fence; + + s_job->s_fence->parent = dma_fence_get(fence); + + /* Drop for orignal kref_init */ + dma_fence_put(fence); } } } @@ -955,6 +960,9 @@ static int drm_sched_main(void *param) if (!IS_ERR_OR_NULL(fence)) { s_fence->parent = dma_fence_get(fence); + /* Drop for original kref_init of the fence */ + dma_fence_put(fence); + r = dma_fence_add_callback(fence, &sched_job->cb, drm_sched_job_done_cb); if (r == -ENOENT) @@ -962,7 +970,6 @@ static int drm_sched_main(void *param) else if (r) DRM_DEV_ERROR(sched->dev, "fence add callback failed (%d)\n", r); - dma_fence_put(fence); } else { if (IS_ERR(fence)) dma_fence_set_error(&s_fence->finished, PTR_ERR(fence)); -- cgit v1.2.3 From 9ae55f030dc523fc4dc6069557e4a887ea815453 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Mon, 20 Jun 2022 17:33:55 -0400 Subject: drm/amdgpu: Follow up change to previous drm scheduler change. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Align refcount behaviour for amdgpu_job embedded HW fence with classic pointer style HW fences by increasing refcount each time emit is called so amdgpu code doesn't need to make workarounds using amdgpu_job.job_run_counter to keep the HW fence refcount balanced. Also since in the previous patch we resumed setting s_fence->parent to NULL in drm_sched_stop switch to directly checking if job->hw_fence is signaled to short circuit reset if already signed. Signed-off-by: Andrey Grodzovsky Tested-by: Yiqing Yao Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 27 +++++++++++++++++++++------ drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 7 ++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 4 ---- 4 files changed, 29 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 44da025502ac..567597469a8a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -684,6 +684,8 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, goto err_ib_sched; } + /* Drop the initial kref_init count (see drm_sched_main as example) */ + dma_fence_put(f); ret = dma_fence_wait(f, false); err_ib_sched: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 9d2395ab4f70..0a1c47ccd1ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5010,16 +5010,32 @@ static void amdgpu_device_recheck_guilty_jobs( /* clear job's guilty and depend the folowing step to decide the real one */ drm_sched_reset_karma(s_job); - /* for the real bad job, it will be resubmitted twice, adding a dma_fence_get - * to make sure fence is balanced */ - dma_fence_get(s_job->s_fence->parent); drm_sched_resubmit_jobs_ext(&ring->sched, 1); + if (!s_job->s_fence->parent) { + DRM_WARN("Failed to get a HW fence for job!"); + continue; + } + ret = dma_fence_wait_timeout(s_job->s_fence->parent, false, ring->sched.timeout); if (ret == 0) { /* timeout */ DRM_ERROR("Found the real bad job! ring:%s, job_id:%llx\n", ring->sched.name, s_job->id); + + amdgpu_fence_driver_isr_toggle(adev, true); + + /* Clear this failed job from fence array */ + amdgpu_fence_driver_clear_job_fences(ring); + + amdgpu_fence_driver_isr_toggle(adev, false); + + /* Since the job won't signal and we go for + * another resubmit drop this parent pointer + */ + dma_fence_put(s_job->s_fence->parent); + s_job->s_fence->parent = NULL; + /* set guilty */ drm_sched_increase_karma(s_job); retry: @@ -5048,7 +5064,6 @@ retry: /* got the hw fence, signal finished fence */ atomic_dec(ring->sched.score); - dma_fence_put(s_job->s_fence->parent); dma_fence_get(&s_job->s_fence->finished); dma_fence_signal(&s_job->s_fence->finished); dma_fence_put(&s_job->s_fence->finished); @@ -5221,8 +5236,8 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, * * job->base holds a reference to parent fence */ - if (job && job->base.s_fence->parent && - dma_fence_is_signaled(job->base.s_fence->parent)) { + if (job && (job->hw_fence.ops != NULL) && + dma_fence_is_signaled(&job->hw_fence)) { job_signaled = true; dev_info(adev->dev, "Guilty job already signaled, skipping HW reset"); goto skip_hw_reset; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index c1d04ea3c67f..39597ab807d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -164,11 +164,16 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, struct amd if (job && job->job_run_counter) { /* reinit seq for resubmitted jobs */ fence->seqno = seq; + /* TO be inline with external fence creation and other drivers */ + dma_fence_get(fence); } else { - if (job) + if (job) { dma_fence_init(fence, &amdgpu_job_fence_ops, &ring->fence_drv.lock, adev->fence_context + ring->idx, seq); + /* Against remove in amdgpu_job_{free, free_cb} */ + dma_fence_get(fence); + } else dma_fence_init(fence, &amdgpu_fence_ops, &ring->fence_drv.lock, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 26ede765eed8..22735790fe50 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -262,10 +262,6 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) DRM_ERROR("Error scheduling IBs (%d)\n", r); } - if (!job->job_run_counter) - dma_fence_get(fence); - else if (finished->error < 0) - dma_fence_put(&job->hw_fence); job->job_run_counter++; amdgpu_job_free_resources(job); -- cgit v1.2.3 From 1c4dae3e4639540fb567e570cc56a3c292afb6fe Mon Sep 17 00:00:00 2001 From: Rahul Kumar Date: Tue, 28 Jun 2022 01:36:38 +0530 Subject: drm/amdgpu/display/dc: Fix null pointer exception We observed hard hang due to NULL derefrence This issue is seen after running system all the time after two or three days struct dc *dc = plane_state->ctx->dc; Randomly in long run we found plane_state or plane_state->ctx is found NULL which causes exception. BUG: kernel NULL pointer dereference, address: 0000000000000000 PF: supervisor read access in kernel mode PF: error_code(0x0000) - not-present page PGD 1dc7f2067 P4D 1dc7f2067 PUD 222c75067 PMD 0 Oops: 0000 [#1] SMP NOPTI CPU: 5 PID: 29855 Comm: kworker/u16:4 ... ... Workqueue: events_unbound commit_work [drm_kms_helper] RIP: 0010:dcn10_update_pending_status+0x1f/0xee [amdgpu] Code: 41 5f c3 0f 1f 44 00 00 b0 01 c3 0f 1f 44 00 00 41 55 41 54 55 53 48 8b 1f 4c 8b af f8 00 00 00 48 8b 83 88 03 00 00 48 85 db <4c> 8b 20 0f 84 bf 00 00 00 48 89 fd 48 8b bf b8 00 00 00 48 8b 07 RSP: 0018:ffff942941997ab8 EFLAGS: 00010286 RAX: 0000000000000000 RBX: ffff8d7fd98d2000 RCX: 0000000000000000 RDX: 0000000000000000 RSI: ffff8d7e3e87c708 RDI: ffff8d7f2d8c0690 RBP: ffff8d7f2d8c0000 R08: ffff942941997a34 R09: 00000000ffffffff R10: 0000000000005000 R11: 00000000000000f0 R12: ffff8d7f2d8c0690 R13: ffff8d8035a41680 R14: 00000000000186a0 R15: ffff8d7f2d8c1dd8 FS: 0000000000000000(0000) GS:ffff8d8037340000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000000 CR3: 0000000148030000 CR4: 00000000003406e0 Call Trace: dc_commit_state+0x6a2/0x7f0 [amdgpu] amdgpu_dm_atomic_commit_tail+0x460/0x19bb [amdgpu] Tested-by: Rodrigo Siqueira Reviewed-by: Harry Wentland Signed-off-by: Rahul Kumar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index fff724e94eed..aaa0bf321bce 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -3243,7 +3243,7 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct timing_generator *tg = pipe_ctx->stream_res.tg; bool flip_pending; - struct dc *dc = plane_state->ctx->dc; + struct dc *dc = pipe_ctx->stream->ctx->dc; if (plane_state == NULL) return; -- cgit v1.2.3 From 8c07f33ea096a1d25fcefa4e904ce50aa2358876 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Mon, 27 Jun 2022 13:23:27 -0400 Subject: Revert "drm/amdkfd: Free queue after unmap queue success" This reverts commit ab8529b0cdb271d9b222cbbddb2641f3fca5df8f. This causes KFDTest KFDMemoryTest.MemoryRegister test failed on gfx9. Signed-off-by: Philip Yang Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 28 +++++++++------------- .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +- 2 files changed, 12 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 21e451acfa59..93a0b6995430 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -1881,22 +1881,6 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm, } - if (q->properties.is_active) { - if (!dqm->dev->shared_resources.enable_mes) { - retval = execute_queues_cpsch(dqm, - KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); - if (retval == -ETIME) - qpd->reset_wavefronts = true; - } else { - retval = remove_queue_mes(dqm, q, qpd); - } - - if (retval) - goto failed_unmap_queue; - - decrement_queue_count(dqm, qpd, q); - } - mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( q->properties.type)]; @@ -1910,6 +1894,17 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm, list_del(&q->list); qpd->queue_count--; + if (q->properties.is_active) { + if (!dqm->dev->shared_resources.enable_mes) { + decrement_queue_count(dqm, qpd, q); + retval = execute_queues_cpsch(dqm, + KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); + if (retval == -ETIME) + qpd->reset_wavefronts = true; + } else { + retval = remove_queue_mes(dqm, q, qpd); + } + } /* * Unconditionally decrement this counter, regardless of the queue's @@ -1926,7 +1921,6 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm, return retval; -failed_unmap_queue: failed_try_destroy_debugged_queue: dqm_unlock(dqm); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index a46e2a37b4a6..c9c205df4a14 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -422,6 +422,7 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) } if (pqn->q) { + kfd_procfs_del_queue(pqn->q); dqm = pqn->q->device->dqm; retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q); if (retval) { @@ -445,7 +446,6 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) amdgpu_amdkfd_free_gtt_mem(dev->adev, pqn->q->wptr_bo); } - kfd_procfs_del_queue(pqn->q); uninit_queue(pqn->q); } -- cgit v1.2.3 From 0b58162e1207db5052d1fadd5a16eeb90720d765 Mon Sep 17 00:00:00 2001 From: "Souptick Joarder (HPE)" Date: Sat, 25 Jun 2022 07:11:57 +0530 Subject: drm/amd/display: Removed unused variable ret Kernel test robot throws below warning -> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c: In function 'dc_link_reduce_mst_payload': drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:3782:32: warning: variable 'ret' set but not used [-Wunused-but-set-variable] 3782 | enum act_return_status ret; Removed the unused ret variable. Reported-by: kernel test robot Signed-off-by: Souptick Joarder (HPE) Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 1206a3dd746f..518a63f45442 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -3783,7 +3783,6 @@ enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw struct fixed31_32 pbn_per_slot; struct dp_mst_stream_allocation_table proposed_table = {0}; uint8_t i; - enum act_return_status ret; const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); DC_LOGGER_INIT(link->ctx->logger); @@ -3857,7 +3856,7 @@ enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw &link->mst_stream_alloc_table); /* poll for immediate branch device ACT handled */ - ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( + dm_helpers_dp_mst_poll_for_allocation_change_trigger( stream->ctx, stream); -- cgit v1.2.3 From d193b12b2fa6dc316e3ee8871b4ec05992bcb7b1 Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Tue, 28 Jun 2022 10:40:59 -0400 Subject: drm/amdgpu: Fix typos in amdgpu_stop_pending_resets Change amdggpu to amdgpu and pedning to pending Signed-off-by: Kent Russell Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 0a1c47ccd1ea..41f68b3427f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5076,7 +5076,7 @@ retry: } } -static inline void amdggpu_device_stop_pedning_resets(struct amdgpu_device *adev) +static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); @@ -5257,7 +5257,7 @@ retry: /* Rest of adevs pre asic reset from XGMI hive. */ * Drop all pending non scheduler resets. Scheduler resets * were already dropped during drm_sched_stop */ - amdggpu_device_stop_pedning_resets(tmp_adev); + amdgpu_device_stop_pending_resets(tmp_adev); } tmp_vram_lost_counter = atomic_read(&((adev)->vram_lost_counter)); -- cgit v1.2.3 From 7bb97c5a39ecebc8ff5db1491fe4e7a8129f93d5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 23 Jun 2022 12:34:18 -0400 Subject: drm/amdgpu/display: drop set but unused variable No longer used so drop it. Fixes: ec457f837890 ("drm/amd/display: Drop unnecessary detect link code") Reported-by: kernel test robot Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 518a63f45442..335ca5b14fa7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1022,7 +1022,6 @@ static bool detect_link_and_local_sink(struct dc_link *link, struct dc_sink *prev_sink = NULL; struct dpcd_caps prev_dpcd_caps; enum dc_connection_type new_connection_type = dc_connection_none; - enum dc_connection_type pre_connection_type = dc_connection_none; const uint32_t post_oui_delay = 30; // 30ms DC_LOGGER_INIT(link->ctx->logger); @@ -1059,7 +1058,6 @@ static bool detect_link_and_local_sink(struct dc_link *link, link_disconnect_sink(link); if (new_connection_type != dc_connection_none) { - pre_connection_type = link->type; link->type = new_connection_type; link->link_state_valid = false; -- cgit v1.2.3 From 70f1fcbc83582419fd753701c5abe674e05db785 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Sun, 26 Jun 2022 10:20:53 -0400 Subject: drm/amd/display: Remove unused globals FORCE_RATE and FORCE_LANE_COUNT sparse reports drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:3885:6: warning: symbol 'FORCE_RATE' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:3886:10: warning: symbol 'FORCE_LANE_COUNT' was not declared. Should it be static? Neither of thse variables is used in dc_link_dp.c. Reviewing the commit listed in the fixes tag shows neither was used in the original patch. So remove them. Fixes: 265280b99822 ("drm/amd/display: add CLKMGR changes for DCN32/321") Reviewed-by: Aurabindo Pillai Signed-off-by: Tom Rix Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index c8355acd3672..b2295bc08609 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -3882,9 +3882,6 @@ static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_ return true; } -bool FORCE_RATE = false; -uint32_t FORCE_LANE_COUNT = 0; - void decide_link_settings(struct dc_stream_state *stream, struct dc_link_settings *link_setting) { -- cgit v1.2.3 From 01752681f1ee5febc9dd2da23f5dc0289ea125a6 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Sun, 26 Jun 2022 10:46:15 -0400 Subject: drm/amd/display: change to_dal_irq_source_dnc32() storage class specifier to static sparse reports drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn32/irq_service_dcn32.c:39:20: warning: symbol 'to_dal_irq_source_dcn32' was not declared. Should it be static? to_dal_irq_source_dnc32() is only referenced in irq_service_dnc32.c, so change its storage class specifier to static. Fixes: 0efd4374f6b4 ("drm/amd/display: add dcn32 IRQ changes") Reviewed-by: Aurabindo Pillai Signed-off-by: Tom Rix Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c index 3a213ca2f077..b1012fa1977b 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c @@ -36,7 +36,7 @@ #define DCN_BASE__INST0_SEG2 0x000034C0 -enum dc_irq_source to_dal_irq_source_dcn32( +static enum dc_irq_source to_dal_irq_source_dcn32( struct irq_service *irq_service, uint32_t src_id, uint32_t ext_id) -- cgit v1.2.3 From 2639d3e44f9c15b3f29f79943ed58f769faeaef2 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 28 Jun 2022 10:46:13 +0100 Subject: drm/amdgpu/amdgpu_dm: fix kernel-doc markups There are 4 undocumented fields at struct amdgpu_display_manager. Add documentation for them, fixing those warnings: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:544: warning: Function parameter or member 'dmub_outbox_params' not described in 'amdgpu_display_manager' drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:544: warning: Function parameter or member 'num_of_edps' not described in 'amdgpu_display_manager' drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:544: warning: Function parameter or member 'disable_hpd_irq' not described in 'amdgpu_display_manager' drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:544: warning: Function parameter or member 'dmub_aux_transfer_done' not described in 'amdgpu_display_manager' drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:544: warning: Function parameter or member 'delayed_hpd_wq' not described in 'amdgpu_display_manager' Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 547fc1547977..73755b304299 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -242,6 +242,13 @@ struct hpd_rx_irq_offload_work { * @force_timing_sync: set via debugfs. When set, indicates that all connected * displays will be forced to synchronize. * @dmcub_trace_event_en: enable dmcub trace events + * @dmub_outbox_params: DMUB Outbox parameters + * @num_of_edps: number of backlight eDPs + * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the + * driver when true + * @dmub_aux_transfer_done: struct completion used to indicate when DMUB + * transfers are done + * @delayed_hpd_wq: work queue used to delay DMUB HPD work */ struct amdgpu_display_manager { -- cgit v1.2.3 From 46d44516aa6e142fd70287e829e3bbad0d2ed35b Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 28 Jun 2022 10:46:15 +0100 Subject: drm/amd/amd_shared.h: Add missing doc for PP_GFX_DCS_MASK This symbol is missing documentation: drivers/gpu/drm/amd/include/amd_shared.h:224: warning: Enum value 'PP_GFX_DCS_MASK' not described in enum 'PP_FEATURE_MASK' Document it. Fixes: 680602d6c2d6 ("drm/amd/pm: enable DCS") Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/amd_shared.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index bcdf7453a403..2e02a6fc1717 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -193,6 +193,7 @@ enum amd_powergating_state { * @PP_ACG_MASK: Adaptive clock generator. * @PP_STUTTER_MODE: Stutter mode. * @PP_AVFS_MASK: Adaptive voltage and frequency scaling. + * @PP_GFX_DCS_MASK: GFX Async DCS. * * To override these settings on boot, append amdgpu.ppfeaturemask= to * the kernel's command line parameters. This is usually done through a system's -- cgit v1.2.3 From 7268f0a9e842c52fa73b9f5afc1bebcf9f7d48b7 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Tue, 28 Jun 2022 15:07:16 -0400 Subject: drm/amd: Load TA firmware for DCN321/DCN32 [Why&How] TA firmware is needed to enable HDCP. Changes in v2: Load separate firmware for PSP 13.0.0 Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c index 9e1ef81933ff..30386d34d0d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c @@ -39,7 +39,9 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); /* For large FW files the time to complete can be very long */ #define USBC_PD_POLLING_LIMIT_S 240 @@ -103,6 +105,10 @@ static int psp_v13_0_init_microcode(struct psp_context *psp) case IP_VERSION(13, 0, 0): case IP_VERSION(13, 0, 7): err = psp_init_sos_microcode(psp, chip_name); + if (err) + return err; + /* It's not necessary to load ras ta on Guest side */ + err = psp_init_ta_microcode(psp, chip_name); if (err) return err; break; -- cgit v1.2.3 From ff15cea338d2c78e0086d55c8a9dd637a5dd3ccc Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Tue, 28 Jun 2022 16:25:28 -0400 Subject: drm/amd/display: expose additional modifier for DCN32/321 [Why&How] Some userspace expect a backwards compatible modifier on DCN32/321. For hardware with num_pipes more than 16, we expose the most efficient modifier first. As a fall back method, we need to expose slightly inefficient modifier AMD_FMT_MOD_TILE_GFX9_64K_R_X after the best option. Also set the number of packers to fixed value as required per hardware documentation. This value is cached during hardware initialization and can be read through the base driver. Signed-off-by: Aurabindo Pillai Reviewed-by: Bas Nieuwenhuizen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 3 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 66 ++++++++++++----------- 2 files changed, 36 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 8ef489fad707..97fff4727724 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -744,8 +744,7 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) switch (version) { case AMD_FMT_MOD_TILE_VER_GFX11: pipe_xor_bits = min(block_size_bits - 8, pipes); - packers = min(block_size_bits - 8 - pipe_xor_bits, - ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs)); + packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs); break; case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: pipe_xor_bits = min(block_size_bits - 8, pipes); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9195d6a8a51f..1bd65b41ba4d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5203,6 +5203,7 @@ add_gfx11_modifiers(struct amdgpu_device *adev, int num_pkrs = 0; int pkrs = 0; u32 gb_addr_config; + u8 i = 0; unsigned swizzle_r_x; uint64_t modifier_r_x; uint64_t modifier_dcc_best; @@ -5218,37 +5219,40 @@ add_gfx11_modifiers(struct amdgpu_device *adev, num_pipes = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PIPES); pipe_xor_bits = ilog2(num_pipes); - /* R_X swizzle modes are the best for rendering and DCC requires them. */ - swizzle_r_x = num_pipes > 16 ? AMD_FMT_MOD_TILE_GFX11_256K_R_X : - AMD_FMT_MOD_TILE_GFX9_64K_R_X; - - modifier_r_x = AMD_FMT_MOD | - AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) | - AMD_FMT_MOD_SET(TILE, swizzle_r_x) | - AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | - AMD_FMT_MOD_SET(PACKERS, pkrs); - - /* DCC_CONSTANT_ENCODE is not set because it can't vary with gfx11 (it's implied to be 1). */ - modifier_dcc_best = modifier_r_x | - AMD_FMT_MOD_SET(DCC, 1) | - AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 0) | - AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | - AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B); - - /* DCC settings for 4K and greater resolutions. (required by display hw) */ - modifier_dcc_4k = modifier_r_x | - AMD_FMT_MOD_SET(DCC, 1) | - AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | - AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | - AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B); - - add_modifier(mods, size, capacity, modifier_dcc_best); - add_modifier(mods, size, capacity, modifier_dcc_4k); - - add_modifier(mods, size, capacity, modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1)); - add_modifier(mods, size, capacity, modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1)); - - add_modifier(mods, size, capacity, modifier_r_x); + for (i = 0; i < 2; i++) { + /* Insert the best one first. */ + /* R_X swizzle modes are the best for rendering and DCC requires them. */ + if (num_pipes > 16) + swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX11_256K_R_X : AMD_FMT_MOD_TILE_GFX9_64K_R_X; + else + swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX9_64K_R_X : AMD_FMT_MOD_TILE_GFX11_256K_R_X; + + modifier_r_x = AMD_FMT_MOD | + AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) | + AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | + AMD_FMT_MOD_SET(TILE, swizzle_r_x) | + AMD_FMT_MOD_SET(PACKERS, pkrs); + + /* DCC_CONSTANT_ENCODE is not set because it can't vary with gfx11 (it's implied to be 1). */ + modifier_dcc_best = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) | + AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 0) | + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B); + + /* DCC settings for 4K and greater resolutions. (required by display hw) */ + modifier_dcc_4k = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) | + AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B); + + add_modifier(mods, size, capacity, modifier_dcc_best); + add_modifier(mods, size, capacity, modifier_dcc_4k); + + add_modifier(mods, size, capacity, modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1)); + add_modifier(mods, size, capacity, modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1)); + + add_modifier(mods, size, capacity, modifier_r_x); + } add_modifier(mods, size, capacity, AMD_FMT_MOD | AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) | -- cgit v1.2.3 From c5cb2cdf23ceefd9ef319d6c0d6ac294dfe356b6 Mon Sep 17 00:00:00 2001 From: Chandan Vurdigere Nataraj Date: Sun, 26 Jun 2022 15:41:44 +0530 Subject: drm/amd/display: Re-org and cleanup the redundant code [Why] Redundant if-else cases for repeater and non-repeater checks [How] Without changing the core logic, rearranged the code by removing redundant checks Signed-off-by: Chandan Vurdigere Nataraj Reviewed-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index b2295bc08609..1982ec0b55d4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -913,19 +913,10 @@ enum dc_status dp_get_lane_status_and_lane_adjust( offset, lane01_status_address, dpcd_buf[0], lane01_status_address + 1, dpcd_buf[1]); - } else { - DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ", - __func__, - lane01_status_address, dpcd_buf[0], - lane01_status_address + 1, dpcd_buf[1]); - } - lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1; - if (is_repeater(link, offset)) lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 + ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1)); - if (is_repeater(link, offset)) { DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n" " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n", __func__, @@ -935,6 +926,13 @@ enum dc_status dp_get_lane_status_and_lane_adjust( lane01_adjust_address + 1, dpcd_buf[lane_adjust_offset + 1]); } else { + DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ", + __func__, + lane01_status_address, dpcd_buf[0], + lane01_status_address + 1, dpcd_buf[1]); + + lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1; + DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n", __func__, lane01_adjust_address, -- cgit v1.2.3 From 6e9c65f71eddef88f14b7210bbf30e6ce2409b87 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 23 Jun 2022 12:37:40 -0400 Subject: drm/amdgpu: fix documentation warning Fixes this issue: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:5094: warning: expecting prototype for amdgpu_device_gpu_recover_imp(). Prototype was for amdgpu_device_gpu_recover() instead Fixes: cf727044144d ("drm/amdgpu: Rename amdgpu_device_gpu_recover_imp back to amdgpu_device_gpu_recover") Reviewed-by: Kent Russell Reported-by: Stephen Rothwell Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 41f68b3427f2..64f37713b270 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5098,7 +5098,7 @@ static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev) /** - * amdgpu_device_gpu_recover_imp - reset the asic and recover scheduler + * amdgpu_device_gpu_recover - reset the asic and recover scheduler * * @adev: amdgpu_device pointer * @job: which job trigger hang -- cgit v1.2.3 From 90d5fd317c745a80019ed7f12a1933ce6116e0e4 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Mon, 6 Jun 2022 17:30:34 +0800 Subject: drm/amdgpu/mes11: update mes interface for acessing registers Update MES firmware api for accessing registers. Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/mes_v11_api_def.h | 37 +++++++++++++++++++-------- 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/include/mes_v11_api_def.h b/drivers/gpu/drm/amd/include/mes_v11_api_def.h index fa1b9e0d299a..1d37ec2cd737 100644 --- a/drivers/gpu/drm/amd/include/mes_v11_api_def.h +++ b/drivers/gpu/drm/amd/include/mes_v11_api_def.h @@ -508,27 +508,40 @@ union MESAPI__SET_DEBUG_VMID { }; enum MESAPI_MISC_OPCODE { - MESAPI_MISC__MODIFY_REG, + MESAPI_MISC__WRITE_REG, MESAPI_MISC__INV_GART, MESAPI_MISC__QUERY_STATUS, + MESAPI_MISC__READ_REG, + MESAPI_MISC__WAIT_REG_MEM, MESAPI_MISC__MAX, }; -enum MODIFY_REG_SUBCODE { - MODIFY_REG__OVERWRITE, - MODIFY_REG__RMW_OR, - MODIFY_REG__RMW_AND, - MODIFY_REG__MAX, -}; - enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 }; -struct MODIFY_REG { - enum MODIFY_REG_SUBCODE subcode; +struct WRITE_REG { uint32_t reg_offset; uint32_t reg_value; }; +struct READ_REG { + uint32_t reg_offset; + uint64_t buffer_addr; +}; + +enum WRM_OPERATION { + WRM_OPERATION__WAIT_REG_MEM, + WRM_OPERATION__WR_WAIT_WR_REG, + WRM_OPERATION__MAX, +}; + +struct WAIT_REG_MEM { + enum WRM_OPERATION op; + uint32_t reference; + uint32_t mask; + uint32_t reg_offset1; + uint32_t reg_offset2; +}; + struct INV_GART { uint64_t inv_range_va_start; uint64_t inv_range_size; @@ -545,9 +558,11 @@ union MESAPI__MISC { struct MES_API_STATUS api_status; union { - struct MODIFY_REG modify_reg; + struct WRITE_REG write_reg; struct INV_GART inv_gart; struct QUERY_STATUS query_status; + struct READ_REG read_reg; + struct WAIT_REG_MEM wait_reg_mem; uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS]; }; }; -- cgit v1.2.3 From 6a4a1f6054318cd3590562668798304b4351ef36 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Thu, 16 Jun 2022 21:23:45 +0800 Subject: drm/amdgpu: add common interface for mes misc op Add common interface for mes misc op, including accessing register interface. Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 46 +++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 074418c63e4b..3cec87e023b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -119,6 +119,10 @@ struct amdgpu_mes { uint32_t query_status_fence_offs; uint64_t query_status_fence_gpu_addr; uint64_t *query_status_fence_ptr; + uint32_t read_val_offs; + uint64_t read_val_gpu_addr; + uint32_t *read_val_ptr; + uint32_t saved_flags; /* initialize kiq pipe */ @@ -246,6 +250,36 @@ struct mes_resume_gang_input { uint64_t gang_context_addr; }; +enum mes_misc_opcode { + MES_MISC_OP_WRITE_REG, + MES_MISC_OP_READ_REG, + MES_MISC_OP_WRM_REG_WAIT, + MES_MISC_OP_WRM_REG_WR_WAIT, +}; + +struct mes_misc_op_input { + enum mes_misc_opcode op; + + union { + struct { + uint32_t reg_offset; + uint64_t buffer_addr; + } read_reg; + + struct { + uint32_t reg_offset; + uint32_t reg_value; + } write_reg; + + struct { + uint32_t ref; + uint32_t mask; + uint32_t reg0; + uint32_t reg1; + } wrm_reg; + }; +}; + struct amdgpu_mes_funcs { int (*add_hw_queue)(struct amdgpu_mes *mes, struct mes_add_queue_input *input); @@ -261,6 +295,9 @@ struct amdgpu_mes_funcs { int (*resume_gang)(struct amdgpu_mes *mes, struct mes_resume_gang_input *input); + + int (*misc_op)(struct amdgpu_mes *mes, + struct mes_misc_op_input *input); }; #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) @@ -293,6 +330,15 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, enum amdgpu_unmap_queues_action action, u64 gpu_addr, u64 seq); +uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg); +int amdgpu_mes_wreg(struct amdgpu_device *adev, + uint32_t reg, uint32_t val); +int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg, + uint32_t val, uint32_t mask); +int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, + uint32_t reg0, uint32_t reg1, + uint32_t ref, uint32_t mask); + int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id, int queue_type, int idx, struct amdgpu_mes_ctx_data *ctx_data, -- cgit v1.2.3 From cff35798fad565b5f8bbf4ef84ac698270dcaf64 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Sun, 26 Jun 2022 21:35:10 -0400 Subject: drm/amdkfd: fix cu mask for asics with wgps GFX10 and up have work group processors (WGP) and WGP mode is the native compile mode. KFD and ROCr have no visibility into whether a dispatch is operating in CU or WGP mode. Enforce CU masking to be pairwise continguous in enablement and round robin distribute CUs across the SEs in a pairwise manner to assume WGP mode at all times. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 12 +++++++----- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 15 +++++++++++++++ 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c index 49a283be6b57..623ccd227b7d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c @@ -100,7 +100,9 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm, { struct kfd_cu_info cu_info; uint32_t cu_per_sh[KFD_MAX_NUM_SE][KFD_MAX_NUM_SH_PER_SE] = {0}; - int i, se, sh, cu, cu_bitmap_sh_mul; + bool wgp_mode_req = KFD_GC_VERSION(mm->dev) >= IP_VERSION(10, 0, 0); + uint32_t en_mask = wgp_mode_req ? 0x3 : 0x1; + int i, se, sh, cu, cu_bitmap_sh_mul, inc = wgp_mode_req ? 2 : 1; amdgpu_amdkfd_get_cu_info(mm->dev->adev, &cu_info); @@ -167,13 +169,13 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm, se_mask[i] = 0; i = 0; - for (cu = 0; cu < 16; cu++) { + for (cu = 0; cu < 16; cu += inc) { for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++) { for (se = 0; se < cu_info.num_shader_engines; se++) { if (cu_per_sh[se][sh] > cu) { - if (cu_mask[i / 32] & (1 << (i % 32))) - se_mask[se] |= 1 << (cu + sh * 16); - i++; + if (cu_mask[i / 32] & (en_mask << (i % 32))) + se_mask[se] |= en_mask << (cu + sh * 16); + i += inc; if (i == cu_mask_count) return; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index c9c205df4a14..6e3e7f54381b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -498,6 +498,21 @@ int pqm_update_mqd(struct process_queue_manager *pqm, return -EFAULT; } + /* ASICs that have WGPs must enforce pairwise enabled mask checks. */ + if (minfo && minfo->update_flag == UPDATE_FLAG_CU_MASK && minfo->cu_mask.ptr && + KFD_GC_VERSION(pqn->q->device) >= IP_VERSION(10, 0, 0)) { + int i; + + for (i = 0; i < minfo->cu_mask.count; i += 2) { + uint32_t cu_pair = (minfo->cu_mask.ptr[i / 32] >> (i % 32)) & 0x3; + + if (cu_pair && cu_pair != 0x3) { + pr_debug("CUs must be adjacent pairwise enabled.\n"); + return -EINVAL; + } + } + } + retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, pqn->q, minfo); if (retval != 0) -- cgit v1.2.3 From 7d4705b33cb84bfbba04de153d4f5e83041ac393 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Thu, 16 Jun 2022 21:49:29 +0800 Subject: drm/amdgpu/mes11: add mes11 misc op Add misc op commands in mes11. Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 53 ++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 89b99dc827a6..72d6017964c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -274,6 +274,58 @@ static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) &mes_status_pkt, sizeof(mes_status_pkt)); } +static int mes_v11_0_misc_op(struct amdgpu_mes *mes, + struct mes_misc_op_input *input) +{ + union MESAPI__MISC misc_pkt; + + memset(&misc_pkt, 0, sizeof(misc_pkt)); + + misc_pkt.header.type = MES_API_TYPE_SCHEDULER; + misc_pkt.header.opcode = MES_SCH_API_MISC; + misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + switch (input->op) { + case MES_MISC_OP_READ_REG: + misc_pkt.opcode = MESAPI_MISC__READ_REG; + misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; + misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; + break; + case MES_MISC_OP_WRITE_REG: + misc_pkt.opcode = MESAPI_MISC__WRITE_REG; + misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; + misc_pkt.write_reg.reg_value = input->write_reg.reg_value; + break; + case MES_MISC_OP_WRM_REG_WAIT: + misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; + misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; + misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; + misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; + misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; + misc_pkt.wait_reg_mem.reg_offset2 = 0; + break; + case MES_MISC_OP_WRM_REG_WR_WAIT: + misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; + misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; + misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; + misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; + misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; + misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; + break; + default: + DRM_ERROR("unsupported misc op (%d) \n", input->op); + return -EINVAL; + } + + misc_pkt.api_status.api_completion_fence_addr = + mes->ring.fence_drv.gpu_addr; + misc_pkt.api_status.api_completion_fence_value = + ++mes->ring.fence_drv.sync_seq; + + return mes_v11_0_submit_pkt_and_poll_completion(mes, + &misc_pkt, sizeof(misc_pkt)); +} + static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) { int i; @@ -336,6 +388,7 @@ static const struct amdgpu_mes_funcs mes_v11_0_funcs = { .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, .suspend_gang = mes_v11_0_suspend_gang, .resume_gang = mes_v11_0_resume_gang, + .misc_op = mes_v11_0_misc_op, }; static int mes_v11_0_init_microcode(struct amdgpu_device *adev, -- cgit v1.2.3 From adc0e6ab0df390907228abb76c6bf82382089af1 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Thu, 16 Jun 2022 21:23:01 +0800 Subject: drm/amdgpu/mes: add mes register access interface Add mes register access routines: 1. read register 2. write register 3. wait register 4. write and wait register Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 132 +++++++++++++++++++++++++++++++- 1 file changed, 131 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 0c9cb493a85c..bffde4aa6fe7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -189,15 +189,29 @@ int amdgpu_mes_init(struct amdgpu_device *adev) r = amdgpu_device_wb_get(adev, &adev->mes.query_status_fence_offs); if (r) { + amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); dev_err(adev->dev, "(%d) query_status_fence_offs wb alloc failed\n", r); - return r; + goto error_ids; } adev->mes.query_status_fence_gpu_addr = adev->wb.gpu_addr + (adev->mes.query_status_fence_offs * 4); adev->mes.query_status_fence_ptr = (uint64_t *)&adev->wb.wb[adev->mes.query_status_fence_offs]; + r = amdgpu_device_wb_get(adev, &adev->mes.read_val_offs); + if (r) { + amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); + amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); + dev_err(adev->dev, + "(%d) read_val_offs alloc failed\n", r); + goto error_ids; + } + adev->mes.read_val_gpu_addr = + adev->wb.gpu_addr + (adev->mes.read_val_offs * 4); + adev->mes.read_val_ptr = + (uint32_t *)&adev->wb.wb[adev->mes.read_val_offs]; + r = amdgpu_mes_doorbell_init(adev); if (r) goto error; @@ -206,6 +220,8 @@ int amdgpu_mes_init(struct amdgpu_device *adev) error: amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); + amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); + amdgpu_device_wb_free(adev, adev->mes.read_val_offs); error_ids: idr_destroy(&adev->mes.pasid_idr); idr_destroy(&adev->mes.gang_id_idr); @@ -218,6 +234,8 @@ error_ids: void amdgpu_mes_fini(struct amdgpu_device *adev) { amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); + amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); + amdgpu_device_wb_free(adev, adev->mes.read_val_offs); idr_destroy(&adev->mes.pasid_idr); idr_destroy(&adev->mes.gang_id_idr); @@ -794,6 +812,118 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, return r; } +uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg) +{ + struct mes_misc_op_input op_input; + int r, val = 0; + + amdgpu_mes_lock(&adev->mes); + + op_input.op = MES_MISC_OP_READ_REG; + op_input.read_reg.reg_offset = reg; + op_input.read_reg.buffer_addr = adev->mes.read_val_gpu_addr; + + if (!adev->mes.funcs->misc_op) { + DRM_ERROR("mes rreg is not supported!\n"); + goto error; + } + + r = adev->mes.funcs->misc_op(&adev->mes, &op_input); + if (r) + DRM_ERROR("failed to read reg (0x%x)\n", reg); + else + val = *(adev->mes.read_val_ptr); + +error: + amdgpu_mes_unlock(&adev->mes); + return val; +} + +int amdgpu_mes_wreg(struct amdgpu_device *adev, + uint32_t reg, uint32_t val) +{ + struct mes_misc_op_input op_input; + int r; + + amdgpu_mes_lock(&adev->mes); + + op_input.op = MES_MISC_OP_WRITE_REG; + op_input.write_reg.reg_offset = reg; + op_input.write_reg.reg_value = val; + + if (!adev->mes.funcs->misc_op) { + DRM_ERROR("mes wreg is not supported!\n"); + r = -EINVAL; + goto error; + } + + r = adev->mes.funcs->misc_op(&adev->mes, &op_input); + if (r) + DRM_ERROR("failed to write reg (0x%x)\n", reg); + +error: + amdgpu_mes_unlock(&adev->mes); + return r; +} + +int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, + uint32_t reg0, uint32_t reg1, + uint32_t ref, uint32_t mask) +{ + struct mes_misc_op_input op_input; + int r; + + amdgpu_mes_lock(&adev->mes); + + op_input.op = MES_MISC_OP_WRM_REG_WR_WAIT; + op_input.wrm_reg.reg0 = reg0; + op_input.wrm_reg.reg1 = reg1; + op_input.wrm_reg.ref = ref; + op_input.wrm_reg.mask = mask; + + if (!adev->mes.funcs->misc_op) { + DRM_ERROR("mes reg_write_reg_wait is not supported!\n"); + r = -EINVAL; + goto error; + } + + r = adev->mes.funcs->misc_op(&adev->mes, &op_input); + if (r) + DRM_ERROR("failed to reg_write_reg_wait\n"); + +error: + amdgpu_mes_unlock(&adev->mes); + return r; +} + +int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg, + uint32_t val, uint32_t mask) +{ + struct mes_misc_op_input op_input; + int r; + + amdgpu_mes_lock(&adev->mes); + + op_input.op = MES_MISC_OP_WRM_REG_WAIT; + op_input.wrm_reg.reg0 = reg; + op_input.wrm_reg.ref = val; + op_input.wrm_reg.mask = mask; + + if (!adev->mes.funcs->misc_op) { + DRM_ERROR("mes reg wait is not supported!\n"); + r = -EINVAL; + goto error; + } + + r = adev->mes.funcs->misc_op(&adev->mes, &op_input); + if (r) + DRM_ERROR("failed to reg_write_reg_wait\n"); + +error: + amdgpu_mes_unlock(&adev->mes); + return r; +} + static void amdgpu_mes_ring_to_queue_props(struct amdgpu_device *adev, struct amdgpu_ring *ring, -- cgit v1.2.3 From cf6067290034b9ebbe4c39733b1a4acc94876c26 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Thu, 16 Jun 2022 21:34:24 +0800 Subject: drm/amdgpu: enable mes to access registers v2 Enable mes to access registers. v2: squash mes sched ring enablement flag Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 1 + 4 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index b697353e5a7a..222d3d7ea076 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -699,6 +699,9 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg) if (amdgpu_device_skip_hw_access(adev)) return 0; + if (adev->mes.ring.sched.ready) + return amdgpu_mes_rreg(adev, reg); + BUG_ON(!ring->funcs->emit_rreg); spin_lock_irqsave(&kiq->ring_lock, flags); @@ -766,6 +769,11 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) if (amdgpu_device_skip_hw_access(adev)) return; + if (adev->mes.ring.sched.ready) { + amdgpu_mes_wreg(adev, reg, v); + return; + } + spin_lock_irqsave(&kiq->ring_lock, flags); amdgpu_ring_alloc(ring, 32); amdgpu_ring_emit_wreg(ring, reg, v); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index a8ecf04389b3..9be57389301b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -76,6 +76,12 @@ void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, unsigned long flags; uint32_t seq; + if (adev->mes.ring.sched.ready) { + amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1, + ref, mask); + return; + } + spin_lock_irqsave(&kiq->ring_lock, flags); amdgpu_ring_alloc(ring, 32); amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index e098b69d6321..d4e9c6790c2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -274,7 +274,7 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, /* For SRIOV run time, driver shouldn't access the register through MMIO * Directly use kiq to do the vm invalidation instead */ - if (adev->gfx.kiq.ring.sched.ready && !adev->enable_mes && + if ((adev->gfx.kiq.ring.sched.ready || adev->mes.ring.sched.ready) && (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; const unsigned eng = 17; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 72d6017964c8..5bdc2babb070 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -1193,6 +1193,7 @@ static int mes_v11_0_hw_init(void *handle) * with MES enabled. */ adev->gfx.kiq.ring.sched.ready = false; + adev->mes.ring.sched.ready = true; return 0; -- cgit v1.2.3 From 395ece6f14124c2245e4b7fe74932514f999faa1 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Tue, 28 Jun 2022 12:28:43 +0800 Subject: Revert "drm/amdgpu/gmc11: avoid cpu accessing registers to flush VM" This reverts commit 8748de873fedf4d55bdd99bbb738ee7ddf329792 since drv enabled mes to access registers. Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 51 +--------------------------------- 1 file changed, 1 insertion(+), 50 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index d4e9c6790c2c..edbdc0b934ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -259,12 +259,6 @@ static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, uint32_t vmhub, uint32_t flush_type) { - struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; - struct dma_fence *fence; - struct amdgpu_job *job; - - int r; - if ((vmhub == AMDGPU_GFXHUB_0) && !adev->gfx.is_poweron) return; @@ -288,51 +282,8 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, } mutex_lock(&adev->mman.gtt_window_lock); - - if (vmhub == AMDGPU_MMHUB_0) { - gmc_v11_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); - mutex_unlock(&adev->mman.gtt_window_lock); - return; - } - - BUG_ON(vmhub != AMDGPU_GFXHUB_0); - - if (!adev->mman.buffer_funcs_enabled || - !adev->ib_pool_ready || - amdgpu_in_reset(adev) || - ring->sched.ready == false) { - gmc_v11_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); - mutex_unlock(&adev->mman.gtt_window_lock); - return; - } - - r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, - &job); - if (r) - goto error_alloc; - - job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); - job->vm_needs_flush = true; - job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; - amdgpu_ring_pad_ib(ring, &job->ibs[0]); - r = amdgpu_job_submit(job, &adev->mman.entity, - AMDGPU_FENCE_OWNER_UNDEFINED, &fence); - if (r) - goto error_submit; - - mutex_unlock(&adev->mman.gtt_window_lock); - - dma_fence_wait(fence, false); - dma_fence_put(fence); - - return; - -error_submit: - amdgpu_job_free(job); - -error_alloc: + gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0); mutex_unlock(&adev->mman.gtt_window_lock); - DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); return; } -- cgit v1.2.3 From d7cfea332cca483ccd3970ed4de73ed892643e51 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Thu, 20 Jan 2022 15:06:30 -0500 Subject: drm/amdkfd: Add KFD SMI event IDs and triggers Define new system management interface event IDs for migration, GPU recoverable page fault, user queues eviction, restore and unmap from GPU events and corresponding event triggers, those will be implemented in the following patches. Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- include/uapi/linux/kfd_ioctl.h | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 231eb010b823..280edda46faf 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -470,6 +470,43 @@ enum kfd_smi_event { KFD_SMI_EVENT_THERMAL_THROTTLE = 2, KFD_SMI_EVENT_GPU_PRE_RESET = 3, KFD_SMI_EVENT_GPU_POST_RESET = 4, + KFD_SMI_EVENT_MIGRATE_START = 5, + KFD_SMI_EVENT_MIGRATE_END = 6, + KFD_SMI_EVENT_PAGE_FAULT_START = 7, + KFD_SMI_EVENT_PAGE_FAULT_END = 8, + KFD_SMI_EVENT_QUEUE_EVICTION = 9, + KFD_SMI_EVENT_QUEUE_RESTORE = 10, + KFD_SMI_EVENT_UNMAP_FROM_GPU = 11, + + /* + * max event number, as a flag bit to get events from all processes, + * this requires super user permission, otherwise will not be able to + * receive event from any process. Without this flag to receive events + * from same process. + */ + KFD_SMI_EVENT_ALL_PROCESS = 64 +}; + +enum KFD_MIGRATE_TRIGGERS { + KFD_MIGRATE_TRIGGER_PREFETCH, + KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU, + KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU, + KFD_MIGRATE_TRIGGER_TTM_EVICTION +}; + +enum KFD_QUEUE_EVICTION_TRIGGERS { + KFD_QUEUE_EVICTION_TRIGGER_SVM, + KFD_QUEUE_EVICTION_TRIGGER_USERPTR, + KFD_QUEUE_EVICTION_TRIGGER_TTM, + KFD_QUEUE_EVICTION_TRIGGER_SUSPEND, + KFD_QUEUE_EVICTION_CRIU_CHECKPOINT, + KFD_QUEUE_EVICTION_CRIU_RESTORE +}; + +enum KFD_SVM_UNMAP_TRIGGERS { + KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY, + KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE, + KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU }; #define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1)) -- cgit v1.2.3 From 163a5a58437062ce4dbef2aab6de4d784043bcf5 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Thu, 13 Jan 2022 18:59:02 -0500 Subject: drm/amdkfd: Enable per process SMI event Process receive event from same process by default. Add a flag to be able to receive event from all processes, this requires super user permission. Event using pid 0 to send the event to all processes, to keep the default behavior of existing SMI events. Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 37 ++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c index f2e1d506ba21..55ed026435e2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c @@ -38,6 +38,8 @@ struct kfd_smi_client { uint64_t events; struct kfd_dev *dev; spinlock_t lock; + pid_t pid; + bool suser; }; #define MAX_KFIFO_SIZE 1024 @@ -151,16 +153,27 @@ static int kfd_smi_ev_release(struct inode *inode, struct file *filep) return 0; } -static void add_event_to_kfifo(struct kfd_dev *dev, unsigned int smi_event, - char *event_msg, int len) +static bool kfd_smi_ev_enabled(pid_t pid, struct kfd_smi_client *client, + unsigned int event) +{ + uint64_t all = KFD_SMI_EVENT_MASK_FROM_INDEX(KFD_SMI_EVENT_ALL_PROCESS); + uint64_t events = READ_ONCE(client->events); + + if (pid && client->pid != pid && !(client->suser && (events & all))) + return false; + + return events & KFD_SMI_EVENT_MASK_FROM_INDEX(event); +} + +static void add_event_to_kfifo(pid_t pid, struct kfd_dev *dev, + unsigned int smi_event, char *event_msg, int len) { struct kfd_smi_client *client; rcu_read_lock(); list_for_each_entry_rcu(client, &dev->smi_clients, list) { - if (!(READ_ONCE(client->events) & - KFD_SMI_EVENT_MASK_FROM_INDEX(smi_event))) + if (!kfd_smi_ev_enabled(pid, client, smi_event)) continue; spin_lock(&client->lock); if (kfifo_avail(&client->fifo) >= len) { @@ -176,9 +189,9 @@ static void add_event_to_kfifo(struct kfd_dev *dev, unsigned int smi_event, rcu_read_unlock(); } -__printf(3, 4) -static void kfd_smi_event_add(struct kfd_dev *dev, unsigned int event, - char *fmt, ...) +__printf(4, 5) +static void kfd_smi_event_add(pid_t pid, struct kfd_dev *dev, + unsigned int event, char *fmt, ...) { char fifo_in[KFD_SMI_EVENT_MSG_SIZE]; int len; @@ -193,7 +206,7 @@ static void kfd_smi_event_add(struct kfd_dev *dev, unsigned int event, len += vsnprintf(fifo_in + len, sizeof(fifo_in) - len, fmt, args); va_end(args); - add_event_to_kfifo(dev, event, fifo_in, len); + add_event_to_kfifo(pid, dev, event, fifo_in, len); } void kfd_smi_event_update_gpu_reset(struct kfd_dev *dev, bool post_reset) @@ -206,13 +219,13 @@ void kfd_smi_event_update_gpu_reset(struct kfd_dev *dev, bool post_reset) event = KFD_SMI_EVENT_GPU_PRE_RESET; ++(dev->reset_seq_num); } - kfd_smi_event_add(dev, event, "%x\n", dev->reset_seq_num); + kfd_smi_event_add(0, dev, event, "%x\n", dev->reset_seq_num); } void kfd_smi_event_update_thermal_throttling(struct kfd_dev *dev, uint64_t throttle_bitmask) { - kfd_smi_event_add(dev, KFD_SMI_EVENT_THERMAL_THROTTLE, "%llx:%llx\n", + kfd_smi_event_add(0, dev, KFD_SMI_EVENT_THERMAL_THROTTLE, "%llx:%llx\n", throttle_bitmask, amdgpu_dpm_get_thermal_throttling_counter(dev->adev)); } @@ -227,7 +240,7 @@ void kfd_smi_event_update_vmfault(struct kfd_dev *dev, uint16_t pasid) if (!task_info.pid) return; - kfd_smi_event_add(dev, KFD_SMI_EVENT_VMFAULT, "%x:%s\n", + kfd_smi_event_add(0, dev, KFD_SMI_EVENT_VMFAULT, "%x:%s\n", task_info.pid, task_info.task_name); } @@ -251,6 +264,8 @@ int kfd_smi_event_open(struct kfd_dev *dev, uint32_t *fd) spin_lock_init(&client->lock); client->events = 0; client->dev = dev; + client->pid = current->tgid; + client->suser = capable(CAP_SYS_ADMIN); spin_lock(&dev->smi_lock); list_add_rcu(&client->list, &dev->smi_clients); -- cgit v1.2.3 From e0f1e65b836c42741288a367eab565167a408b59 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Thu, 13 Jan 2022 19:22:54 -0500 Subject: drm/amdkfd: Add GPU recoverable fault SMI event Use ktime_get_boottime_ns() as timestamp to correlate with other APIs. Output timestamp when GPU recoverable fault starts and ends to recover the fault, if migration happened or only GPU page table is updated to recover, fault address, if read or write fault. Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 17 +++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h | 6 +++++- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 19 ++++++++++++++----- drivers/gpu/drm/amd/amdkfd/kfd_svm.h | 2 +- 4 files changed, 37 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c index 55ed026435e2..b7e68283925f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c @@ -244,6 +244,23 @@ void kfd_smi_event_update_vmfault(struct kfd_dev *dev, uint16_t pasid) task_info.pid, task_info.task_name); } +void kfd_smi_event_page_fault_start(struct kfd_dev *dev, pid_t pid, + unsigned long address, bool write_fault, + ktime_t ts) +{ + kfd_smi_event_add(pid, dev, KFD_SMI_EVENT_PAGE_FAULT_START, + "%lld -%d @%lx(%x) %c\n", ktime_to_ns(ts), pid, + address, dev->id, write_fault ? 'W' : 'R'); +} + +void kfd_smi_event_page_fault_end(struct kfd_dev *dev, pid_t pid, + unsigned long address, bool migration) +{ + kfd_smi_event_add(pid, dev, KFD_SMI_EVENT_PAGE_FAULT_END, + "%lld -%d @%lx(%x) %c\n", ktime_get_boottime_ns(), + pid, address, dev->id, migration ? 'M' : 'U'); +} + int kfd_smi_event_open(struct kfd_dev *dev, uint32_t *fd) { struct kfd_smi_client *client; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h index dfe101c21166..7903718cd9eb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h @@ -29,5 +29,9 @@ void kfd_smi_event_update_vmfault(struct kfd_dev *dev, uint16_t pasid); void kfd_smi_event_update_thermal_throttling(struct kfd_dev *dev, uint64_t throttle_bitmask); void kfd_smi_event_update_gpu_reset(struct kfd_dev *dev, bool post_reset); - +void kfd_smi_event_page_fault_start(struct kfd_dev *dev, pid_t pid, + unsigned long address, bool write_fault, + ktime_t ts); +void kfd_smi_event_page_fault_end(struct kfd_dev *dev, pid_t pid, + unsigned long address, bool migration); #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 7b332246eda3..a3c7dd411b77 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -32,6 +32,7 @@ #include "kfd_priv.h" #include "kfd_svm.h" #include "kfd_migrate.h" +#include "kfd_smi_events.h" #ifdef dev_fmt #undef dev_fmt @@ -43,7 +44,7 @@ /* Long enough to ensure no retry fault comes after svm range is restored and * page table is updated. */ -#define AMDGPU_SVM_RANGE_RETRY_FAULT_PENDING 2000 +#define AMDGPU_SVM_RANGE_RETRY_FAULT_PENDING (2UL * NSEC_PER_MSEC) struct criu_svm_metadata { struct list_head list; @@ -1617,7 +1618,7 @@ unreserve_out: svm_range_unreserve_bos(&ctx); if (!r) - prange->validate_timestamp = ktime_to_us(ktime_get()); + prange->validate_timestamp = ktime_get_boottime(); return r; } @@ -2694,11 +2695,12 @@ svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid, struct svm_range_list *svms; struct svm_range *prange; struct kfd_process *p; - uint64_t timestamp; + ktime_t timestamp = ktime_get_boottime(); int32_t best_loc; int32_t gpuidx = MAX_GPU_INSTANCE; bool write_locked = false; struct vm_area_struct *vma; + bool migration = false; int r = 0; if (!KFD_IS_SVM_API_SUPPORTED(adev->kfd.dev)) { @@ -2775,9 +2777,9 @@ retry_write_locked: goto out_unlock_range; } - timestamp = ktime_to_us(ktime_get()) - prange->validate_timestamp; /* skip duplicate vm fault on different pages of same range */ - if (timestamp < AMDGPU_SVM_RANGE_RETRY_FAULT_PENDING) { + if (ktime_before(timestamp, ktime_add_ns(prange->validate_timestamp, + AMDGPU_SVM_RANGE_RETRY_FAULT_PENDING))) { pr_debug("svms 0x%p [0x%lx %lx] already restored\n", svms, prange->start, prange->last); r = 0; @@ -2813,7 +2815,11 @@ retry_write_locked: svms, prange->start, prange->last, best_loc, prange->actual_loc); + kfd_smi_event_page_fault_start(adev->kfd.dev, p->lead_thread->pid, addr, + write_fault, timestamp); + if (prange->actual_loc != best_loc) { + migration = true; if (best_loc) { r = svm_migrate_to_vram(prange, best_loc, mm); if (r) { @@ -2842,6 +2848,9 @@ retry_write_locked: pr_debug("failed %d to map svms 0x%p [0x%lx 0x%lx] to gpus\n", r, svms, prange->start, prange->last); + kfd_smi_event_page_fault_end(adev->kfd.dev, p->lead_thread->pid, addr, + migration); + out_unlock_range: mutex_unlock(&prange->migrate_mutex); out_unlock_svms: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h index 2d54147b4dda..eab7f6d3b13c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h @@ -125,7 +125,7 @@ struct svm_range { uint32_t actual_loc; uint8_t granularity; atomic_t invalid; - uint64_t validate_timestamp; + ktime_t validate_timestamp; struct mmu_interval_notifier notifier; struct svm_work_list_item work_item; struct list_head deferred_list; -- cgit v1.2.3 From acac270d09828edda2d530d255ee75ceb87583ec Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Thu, 13 Jan 2022 19:28:13 -0500 Subject: drm/amdkfd: Add migration SMI event For migration start and end event, output timestamp when migration starts, ends, svm range address and size, GPU id of migration source and destination and svm range attributes, Migration trigger could be prefetch, CPU or GPU page fault and TTM eviction. Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 53 ++++++++++++++++++++++------- drivers/gpu/drm/amd/amdkfd/kfd_migrate.h | 5 +-- drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 22 ++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h | 8 +++++ drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 16 +++++---- 5 files changed, 83 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index e44376c2ecdc..eecb262270e2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -33,6 +33,7 @@ #include "kfd_priv.h" #include "kfd_svm.h" #include "kfd_migrate.h" +#include "kfd_smi_events.h" #ifdef dev_fmt #undef dev_fmt @@ -402,8 +403,9 @@ out: static long svm_migrate_vma_to_vram(struct amdgpu_device *adev, struct svm_range *prange, struct vm_area_struct *vma, uint64_t start, - uint64_t end) + uint64_t end, uint32_t trigger) { + struct kfd_process *p = container_of(prange->svms, struct kfd_process, svms); uint64_t npages = (end - start) >> PAGE_SHIFT; struct kfd_process_device *pdd; struct dma_fence *mfence = NULL; @@ -430,6 +432,11 @@ svm_migrate_vma_to_vram(struct amdgpu_device *adev, struct svm_range *prange, migrate.dst = migrate.src + npages; scratch = (dma_addr_t *)(migrate.dst + npages); + kfd_smi_event_migration_start(adev->kfd.dev, p->lead_thread->pid, + start >> PAGE_SHIFT, end >> PAGE_SHIFT, + 0, adev->kfd.dev->id, prange->prefetch_loc, + prange->preferred_loc, trigger); + r = migrate_vma_setup(&migrate); if (r) { dev_err(adev->dev, "%s: vma setup fail %d range [0x%lx 0x%lx]\n", @@ -458,6 +465,10 @@ svm_migrate_vma_to_vram(struct amdgpu_device *adev, struct svm_range *prange, svm_migrate_copy_done(adev, mfence); migrate_vma_finalize(&migrate); + kfd_smi_event_migration_end(adev->kfd.dev, p->lead_thread->pid, + start >> PAGE_SHIFT, end >> PAGE_SHIFT, + 0, adev->kfd.dev->id, trigger); + svm_range_dma_unmap(adev->dev, scratch, 0, npages); svm_range_free_dma_mappings(prange); @@ -479,6 +490,7 @@ out: * @prange: range structure * @best_loc: the device to migrate to * @mm: the process mm structure + * @trigger: reason of migration * * Context: Process context, caller hold mmap read lock, svms lock, prange lock * @@ -487,7 +499,7 @@ out: */ static int svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc, - struct mm_struct *mm) + struct mm_struct *mm, uint32_t trigger) { unsigned long addr, start, end; struct vm_area_struct *vma; @@ -524,7 +536,7 @@ svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc, break; next = min(vma->vm_end, end); - r = svm_migrate_vma_to_vram(adev, prange, vma, addr, next); + r = svm_migrate_vma_to_vram(adev, prange, vma, addr, next, trigger); if (r < 0) { pr_debug("failed %ld to migrate\n", r); break; @@ -655,8 +667,10 @@ out_oom: */ static long svm_migrate_vma_to_ram(struct amdgpu_device *adev, struct svm_range *prange, - struct vm_area_struct *vma, uint64_t start, uint64_t end) + struct vm_area_struct *vma, uint64_t start, uint64_t end, + uint32_t trigger) { + struct kfd_process *p = container_of(prange->svms, struct kfd_process, svms); uint64_t npages = (end - start) >> PAGE_SHIFT; unsigned long upages = npages; unsigned long cpages = 0; @@ -685,6 +699,11 @@ svm_migrate_vma_to_ram(struct amdgpu_device *adev, struct svm_range *prange, migrate.dst = migrate.src + npages; scratch = (dma_addr_t *)(migrate.dst + npages); + kfd_smi_event_migration_start(adev->kfd.dev, p->lead_thread->pid, + start >> PAGE_SHIFT, end >> PAGE_SHIFT, + adev->kfd.dev->id, 0, prange->prefetch_loc, + prange->preferred_loc, trigger); + r = migrate_vma_setup(&migrate); if (r) { dev_err(adev->dev, "%s: vma setup fail %d range [0x%lx 0x%lx]\n", @@ -715,6 +734,11 @@ svm_migrate_vma_to_ram(struct amdgpu_device *adev, struct svm_range *prange, svm_migrate_copy_done(adev, mfence); migrate_vma_finalize(&migrate); + + kfd_smi_event_migration_end(adev->kfd.dev, p->lead_thread->pid, + start >> PAGE_SHIFT, end >> PAGE_SHIFT, + adev->kfd.dev->id, 0, trigger); + svm_range_dma_unmap(adev->dev, scratch, 0, npages); out_free: @@ -732,13 +756,15 @@ out: * svm_migrate_vram_to_ram - migrate svm range from device to system * @prange: range structure * @mm: process mm, use current->mm if NULL + * @trigger: reason of migration * * Context: Process context, caller hold mmap read lock, prange->migrate_mutex * * Return: * 0 - OK, otherwise error code */ -int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm) +int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm, + uint32_t trigger) { struct amdgpu_device *adev; struct vm_area_struct *vma; @@ -779,7 +805,7 @@ int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm) } next = min(vma->vm_end, end); - r = svm_migrate_vma_to_ram(adev, prange, vma, addr, next); + r = svm_migrate_vma_to_ram(adev, prange, vma, addr, next, trigger); if (r < 0) { pr_debug("failed %ld to migrate prange %p\n", r, prange); break; @@ -802,6 +828,7 @@ int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm) * @prange: range structure * @best_loc: the device to migrate to * @mm: process mm, use current->mm if NULL + * @trigger: reason of migration * * Context: Process context, caller hold mmap read lock, svms lock, prange lock * @@ -810,7 +837,7 @@ int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm) */ static int svm_migrate_vram_to_vram(struct svm_range *prange, uint32_t best_loc, - struct mm_struct *mm) + struct mm_struct *mm, uint32_t trigger) { int r, retries = 3; @@ -822,7 +849,7 @@ svm_migrate_vram_to_vram(struct svm_range *prange, uint32_t best_loc, pr_debug("from gpu 0x%x to gpu 0x%x\n", prange->actual_loc, best_loc); do { - r = svm_migrate_vram_to_ram(prange, mm); + r = svm_migrate_vram_to_ram(prange, mm, trigger); if (r) return r; } while (prange->actual_loc && --retries); @@ -830,17 +857,17 @@ svm_migrate_vram_to_vram(struct svm_range *prange, uint32_t best_loc, if (prange->actual_loc) return -EDEADLK; - return svm_migrate_ram_to_vram(prange, best_loc, mm); + return svm_migrate_ram_to_vram(prange, best_loc, mm, trigger); } int svm_migrate_to_vram(struct svm_range *prange, uint32_t best_loc, - struct mm_struct *mm) + struct mm_struct *mm, uint32_t trigger) { if (!prange->actual_loc) - return svm_migrate_ram_to_vram(prange, best_loc, mm); + return svm_migrate_ram_to_vram(prange, best_loc, mm, trigger); else - return svm_migrate_vram_to_vram(prange, best_loc, mm); + return svm_migrate_vram_to_vram(prange, best_loc, mm, trigger); } @@ -909,7 +936,7 @@ static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf) goto out_unlock_prange; } - r = svm_migrate_vram_to_ram(prange, mm); + r = svm_migrate_vram_to_ram(prange, mm, KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU); if (r) pr_debug("failed %d migrate 0x%p [0x%lx 0x%lx] to ram\n", r, prange, prange->start, prange->last); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h index 2f5b3394c9ed..b3f0754b32fa 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h @@ -41,8 +41,9 @@ enum MIGRATION_COPY_DIR { }; int svm_migrate_to_vram(struct svm_range *prange, uint32_t best_loc, - struct mm_struct *mm); -int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm); + struct mm_struct *mm, uint32_t trigger); +int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm, + uint32_t trigger); unsigned long svm_migrate_addr_to_pfn(struct amdgpu_device *adev, unsigned long addr); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c index b7e68283925f..ec4d278c2a47 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c @@ -261,6 +261,28 @@ void kfd_smi_event_page_fault_end(struct kfd_dev *dev, pid_t pid, pid, address, dev->id, migration ? 'M' : 'U'); } +void kfd_smi_event_migration_start(struct kfd_dev *dev, pid_t pid, + unsigned long start, unsigned long end, + uint32_t from, uint32_t to, + uint32_t prefetch_loc, uint32_t preferred_loc, + uint32_t trigger) +{ + kfd_smi_event_add(pid, dev, KFD_SMI_EVENT_MIGRATE_START, + "%lld -%d @%lx(%lx) %x->%x %x:%x %d\n", + ktime_get_boottime_ns(), pid, start, end - start, + from, to, prefetch_loc, preferred_loc, trigger); +} + +void kfd_smi_event_migration_end(struct kfd_dev *dev, pid_t pid, + unsigned long start, unsigned long end, + uint32_t from, uint32_t to, uint32_t trigger) +{ + kfd_smi_event_add(pid, dev, KFD_SMI_EVENT_MIGRATE_END, + "%lld -%d @%lx(%lx) %x->%x %d\n", + ktime_get_boottime_ns(), pid, start, end - start, + from, to, trigger); +} + int kfd_smi_event_open(struct kfd_dev *dev, uint32_t *fd) { struct kfd_smi_client *client; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h index 7903718cd9eb..ec5d74a2fef4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h @@ -34,4 +34,12 @@ void kfd_smi_event_page_fault_start(struct kfd_dev *dev, pid_t pid, ktime_t ts); void kfd_smi_event_page_fault_end(struct kfd_dev *dev, pid_t pid, unsigned long address, bool migration); +void kfd_smi_event_migration_start(struct kfd_dev *dev, pid_t pid, + unsigned long start, unsigned long end, + uint32_t from, uint32_t to, + uint32_t prefetch_loc, uint32_t preferred_loc, + uint32_t trigger); +void kfd_smi_event_migration_end(struct kfd_dev *dev, pid_t pid, + unsigned long start, unsigned long end, + uint32_t from, uint32_t to, uint32_t trigger); #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index a3c7dd411b77..e8ded7a02bcb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -2821,7 +2821,8 @@ retry_write_locked: if (prange->actual_loc != best_loc) { migration = true; if (best_loc) { - r = svm_migrate_to_vram(prange, best_loc, mm); + r = svm_migrate_to_vram(prange, best_loc, mm, + KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU); if (r) { pr_debug("svm_migrate_to_vram failed (%d) at %llx, falling back to system memory\n", r, addr); @@ -2829,12 +2830,14 @@ retry_write_locked: * VRAM failed */ if (prange->actual_loc) - r = svm_migrate_vram_to_ram(prange, mm); + r = svm_migrate_vram_to_ram(prange, mm, + KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU); else r = 0; } } else { - r = svm_migrate_vram_to_ram(prange, mm); + r = svm_migrate_vram_to_ram(prange, mm, + KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU); } if (r) { pr_debug("failed %d to migrate svms %p [0x%lx 0x%lx]\n", @@ -3157,12 +3160,12 @@ svm_range_trigger_migration(struct mm_struct *mm, struct svm_range *prange, return 0; if (!best_loc) { - r = svm_migrate_vram_to_ram(prange, mm); + r = svm_migrate_vram_to_ram(prange, mm, KFD_MIGRATE_TRIGGER_PREFETCH); *migrated = !r; return r; } - r = svm_migrate_to_vram(prange, best_loc, mm); + r = svm_migrate_to_vram(prange, best_loc, mm, KFD_MIGRATE_TRIGGER_PREFETCH); *migrated = !r; return r; @@ -3220,7 +3223,8 @@ static void svm_range_evict_svm_bo_worker(struct work_struct *work) mutex_lock(&prange->migrate_mutex); do { r = svm_migrate_vram_to_ram(prange, - svm_bo->eviction_fence->mm); + svm_bo->eviction_fence->mm, + KFD_MIGRATE_TRIGGER_TTM_EVICTION); } while (!r && prange->actual_loc && --retries); if (!r && prange->actual_loc) -- cgit v1.2.3 From c7f21978fa6aafaf7ad37155c7d3a217dc3d16b0 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Thu, 13 Jan 2022 21:24:20 -0500 Subject: drm/amdkfd: Add user queue eviction restore SMI event Output user queue eviction and restore event. User queue eviction may be triggered by svm or userptr MMU notifier, TTM eviction, device suspend and CRIU checkpoint and restore. User queue restore may be rescheduled if eviction happens again while restore. Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 12 +++++--- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 4 +-- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 +-- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 15 ++++++++-- drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 35 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h | 4 +++ drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 6 ++-- 9 files changed, 69 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index b25b41f50213..73bf8b5f2aa9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -336,7 +336,7 @@ void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) } #endif /* KGD2KFD callbacks */ -int kgd2kfd_quiesce_mm(struct mm_struct *mm); +int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger); int kgd2kfd_resume_mm(struct mm_struct *mm); int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, struct dma_fence *fence); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 0036c9e405af..2fcc6e079769 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -32,6 +32,7 @@ #include "amdgpu_dma_buf.h" #include #include "amdgpu_xgmi.h" +#include "kfd_smi_events.h" /* Userptr restore delay, just long enough to allow consecutive VM * changes to accumulate @@ -2346,7 +2347,7 @@ int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, evicted_bos = atomic_inc_return(&process_info->evicted_bos); if (evicted_bos == 1) { /* First eviction, stop the queues */ - r = kgd2kfd_quiesce_mm(mm); + r = kgd2kfd_quiesce_mm(mm, KFD_QUEUE_EVICTION_TRIGGER_USERPTR); if (r) pr_err("Failed to quiesce KFD\n"); schedule_delayed_work(&process_info->restore_userptr_work, @@ -2620,13 +2621,16 @@ static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work) unlock_out: mutex_unlock(&process_info->lock); - mmput(mm); - put_task_struct(usertask); /* If validation failed, reschedule another attempt */ - if (evicted_bos) + if (evicted_bos) { schedule_delayed_work(&process_info->restore_userptr_work, msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS)); + + kfd_smi_event_queue_restore_rescheduled(mm); + } + mmput(mm); + put_task_struct(usertask); } /** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index d07588230ed6..2b3d8bc8f0aa 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2434,7 +2434,7 @@ static int criu_restore(struct file *filep, * Set the process to evicted state to avoid running any new queues before all the memory * mappings are ready. */ - ret = kfd_process_evict_queues(p); + ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_RESTORE); if (ret) goto exit_unlock; @@ -2553,7 +2553,7 @@ static int criu_process_info(struct file *filep, goto err_unlock; } - ret = kfd_process_evict_queues(p); + ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT); if (ret) goto err_unlock; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index c8fee0dbfdcb..6ec0e9f0927d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -837,7 +837,7 @@ void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) spin_unlock_irqrestore(&kfd->interrupt_lock, flags); } -int kgd2kfd_quiesce_mm(struct mm_struct *mm) +int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) { struct kfd_process *p; int r; @@ -851,7 +851,7 @@ int kgd2kfd_quiesce_mm(struct mm_struct *mm) return -ESRCH; WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); - r = kfd_process_evict_queues(p); + r = kfd_process_evict_queues(p, trigger); kfd_unref_process(p); return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 4c4bbd493caa..d03a3b9c9c5d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -947,7 +947,7 @@ static inline struct kfd_process_device *kfd_process_device_from_gpuidx( } void kfd_unref_process(struct kfd_process *p); -int kfd_process_evict_queues(struct kfd_process *p); +int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger); int kfd_process_restore_queues(struct kfd_process *p); void kfd_suspend_all_processes(void); int kfd_resume_all_processes(void); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index a13e60d48b73..fc38a4d81420 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -43,6 +43,7 @@ struct mm_struct; #include "kfd_device_queue_manager.h" #include "kfd_iommu.h" #include "kfd_svm.h" +#include "kfd_smi_events.h" /* * List of struct kfd_process (field kfd_process). @@ -1736,7 +1737,7 @@ struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm) * Eviction is reference-counted per process-device. This means multiple * evictions from different sources can be nested safely. */ -int kfd_process_evict_queues(struct kfd_process *p) +int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger) { int r = 0; int i; @@ -1745,6 +1746,9 @@ int kfd_process_evict_queues(struct kfd_process *p) for (i = 0; i < p->n_pdds; i++) { struct kfd_process_device *pdd = p->pdds[i]; + kfd_smi_event_queue_eviction(pdd->dev, p->lead_thread->pid, + trigger); + r = pdd->dev->dqm->ops.evict_process_queues(pdd->dev->dqm, &pdd->qpd); /* evict return -EIO if HWS is hang or asic is resetting, in this case @@ -1769,6 +1773,9 @@ fail: if (n_evicted == 0) break; + + kfd_smi_event_queue_restore(pdd->dev, p->lead_thread->pid); + if (pdd->dev->dqm->ops.restore_process_queues(pdd->dev->dqm, &pdd->qpd)) pr_err("Failed to restore queues\n"); @@ -1788,6 +1795,8 @@ int kfd_process_restore_queues(struct kfd_process *p) for (i = 0; i < p->n_pdds; i++) { struct kfd_process_device *pdd = p->pdds[i]; + kfd_smi_event_queue_restore(pdd->dev, p->lead_thread->pid); + r = pdd->dev->dqm->ops.restore_process_queues(pdd->dev->dqm, &pdd->qpd); if (r) { @@ -1849,7 +1858,7 @@ static void evict_process_worker(struct work_struct *work) flush_delayed_work(&p->restore_work); pr_debug("Started evicting pasid 0x%x\n", p->pasid); - ret = kfd_process_evict_queues(p); + ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_TTM); if (!ret) { dma_fence_signal(p->ef); dma_fence_put(p->ef); @@ -1916,7 +1925,7 @@ void kfd_suspend_all_processes(void) cancel_delayed_work_sync(&p->eviction_work); cancel_delayed_work_sync(&p->restore_work); - if (kfd_process_evict_queues(p)) + if (kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_SUSPEND)) pr_err("Failed to suspend process 0x%x\n", p->pasid); dma_fence_signal(p->ef); dma_fence_put(p->ef); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c index ec4d278c2a47..3917c38204d0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c @@ -283,6 +283,41 @@ void kfd_smi_event_migration_end(struct kfd_dev *dev, pid_t pid, from, to, trigger); } +void kfd_smi_event_queue_eviction(struct kfd_dev *dev, pid_t pid, + uint32_t trigger) +{ + kfd_smi_event_add(pid, dev, KFD_SMI_EVENT_QUEUE_EVICTION, + "%lld -%d %x %d\n", ktime_get_boottime_ns(), pid, + dev->id, trigger); +} + +void kfd_smi_event_queue_restore(struct kfd_dev *dev, pid_t pid) +{ + kfd_smi_event_add(pid, dev, KFD_SMI_EVENT_QUEUE_RESTORE, + "%lld -%d %x\n", ktime_get_boottime_ns(), pid, + dev->id); +} + +void kfd_smi_event_queue_restore_rescheduled(struct mm_struct *mm) +{ + struct kfd_process *p; + int i; + + p = kfd_lookup_process_by_mm(mm); + if (!p) + return; + + for (i = 0; i < p->n_pdds; i++) { + struct kfd_process_device *pdd = p->pdds[i]; + + kfd_smi_event_add(p->lead_thread->pid, pdd->dev, + KFD_SMI_EVENT_QUEUE_RESTORE, + "%lld -%d %x %c\n", ktime_get_boottime_ns(), + p->lead_thread->pid, pdd->dev->id, 'R'); + } + kfd_unref_process(p); +} + int kfd_smi_event_open(struct kfd_dev *dev, uint32_t *fd) { struct kfd_smi_client *client; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h index ec5d74a2fef4..b23292637239 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h @@ -42,4 +42,8 @@ void kfd_smi_event_migration_start(struct kfd_dev *dev, pid_t pid, void kfd_smi_event_migration_end(struct kfd_dev *dev, pid_t pid, unsigned long start, unsigned long end, uint32_t from, uint32_t to, uint32_t trigger); +void kfd_smi_event_queue_eviction(struct kfd_dev *dev, pid_t pid, + uint32_t trigger); +void kfd_smi_event_queue_restore(struct kfd_dev *dev, pid_t pid); +void kfd_smi_event_queue_restore_rescheduled(struct mm_struct *mm); #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index e8ded7a02bcb..8bfb7b99e45d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1730,14 +1730,16 @@ out_reschedule: mutex_unlock(&svms->lock); mmap_write_unlock(mm); mutex_unlock(&process_info->lock); - mmput(mm); /* If validation failed, reschedule another attempt */ if (evicted_ranges) { pr_debug("reschedule to restore svm range\n"); schedule_delayed_work(&svms->restore_work, msecs_to_jiffies(AMDGPU_SVM_RANGE_RESTORE_DELAY_MS)); + + kfd_smi_event_queue_restore_rescheduled(mm); } + mmput(mm); } /** @@ -1793,7 +1795,7 @@ svm_range_evict(struct svm_range *prange, struct mm_struct *mm, prange->svms, prange->start, prange->last); /* First eviction, stop the queues */ - r = kgd2kfd_quiesce_mm(mm); + r = kgd2kfd_quiesce_mm(mm, KFD_QUEUE_EVICTION_TRIGGER_SVM); if (r) pr_debug("failed to quiesce KFD\n"); -- cgit v1.2.3 From 46ae2af9a8aa168cbad69f21bb1426771339ac9a Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Thu, 20 Jan 2022 16:43:42 -0500 Subject: drm/amdkfd: Add unmap from GPU SMI event SVM range unmapped from GPUs when range is unmapped from CPU, or with xnack on from MMU notifier when range is evicted or migrated. Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 9 +++++++++ drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h | 3 +++ drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 25 ++++++++++++++++++------- 3 files changed, 30 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c index 3917c38204d0..e5896b7a16dd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c @@ -318,6 +318,15 @@ void kfd_smi_event_queue_restore_rescheduled(struct mm_struct *mm) kfd_unref_process(p); } +void kfd_smi_event_unmap_from_gpu(struct kfd_dev *dev, pid_t pid, + unsigned long address, unsigned long last, + uint32_t trigger) +{ + kfd_smi_event_add(pid, dev, KFD_SMI_EVENT_UNMAP_FROM_GPU, + "%lld -%d @%lx(%lx) %x %d\n", ktime_get_boottime_ns(), + pid, address, last - address + 1, dev->id, trigger); +} + int kfd_smi_event_open(struct kfd_dev *dev, uint32_t *fd) { struct kfd_smi_client *client; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h index b23292637239..76fe4e0ec2d2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h @@ -46,4 +46,7 @@ void kfd_smi_event_queue_eviction(struct kfd_dev *dev, pid_t pid, uint32_t trigger); void kfd_smi_event_queue_restore(struct kfd_dev *dev, pid_t pid); void kfd_smi_event_queue_restore_rescheduled(struct mm_struct *mm); +void kfd_smi_event_unmap_from_gpu(struct kfd_dev *dev, pid_t pid, + unsigned long address, unsigned long last, + uint32_t trigger); #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 8bfb7b99e45d..fd89951c29fe 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1200,7 +1200,7 @@ svm_range_unmap_from_gpu(struct amdgpu_device *adev, struct amdgpu_vm *vm, static int svm_range_unmap_from_gpus(struct svm_range *prange, unsigned long start, - unsigned long last) + unsigned long last, uint32_t trigger) { DECLARE_BITMAP(bitmap, MAX_GPU_INSTANCE); struct kfd_process_device *pdd; @@ -1232,6 +1232,9 @@ svm_range_unmap_from_gpus(struct svm_range *prange, unsigned long start, return -EINVAL; } + kfd_smi_event_unmap_from_gpu(pdd->dev, p->lead_thread->pid, + start, last, trigger); + r = svm_range_unmap_from_gpu(pdd->dev->adev, drm_priv_to_vm(pdd->drm_priv), start, last, &fence); @@ -1759,7 +1762,8 @@ out_reschedule: */ static int svm_range_evict(struct svm_range *prange, struct mm_struct *mm, - unsigned long start, unsigned long last) + unsigned long start, unsigned long last, + enum mmu_notifier_event event) { struct svm_range_list *svms = prange->svms; struct svm_range *pchild; @@ -1804,6 +1808,12 @@ svm_range_evict(struct svm_range *prange, struct mm_struct *mm, msecs_to_jiffies(AMDGPU_SVM_RANGE_RESTORE_DELAY_MS)); } else { unsigned long s, l; + uint32_t trigger; + + if (event == MMU_NOTIFY_MIGRATE) + trigger = KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE; + else + trigger = KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY; pr_debug("invalidate unmap svms 0x%p [0x%lx 0x%lx] from GPUs\n", prange->svms, start, last); @@ -1812,13 +1822,13 @@ svm_range_evict(struct svm_range *prange, struct mm_struct *mm, s = max(start, pchild->start); l = min(last, pchild->last); if (l >= s) - svm_range_unmap_from_gpus(pchild, s, l); + svm_range_unmap_from_gpus(pchild, s, l, trigger); mutex_unlock(&pchild->lock); } s = max(start, prange->start); l = min(last, prange->last); if (l >= s) - svm_range_unmap_from_gpus(prange, s, l); + svm_range_unmap_from_gpus(prange, s, l, trigger); } return r; @@ -2232,6 +2242,7 @@ static void svm_range_unmap_from_cpu(struct mm_struct *mm, struct svm_range *prange, unsigned long start, unsigned long last) { + uint32_t trigger = KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU; struct svm_range_list *svms; struct svm_range *pchild; struct kfd_process *p; @@ -2259,14 +2270,14 @@ svm_range_unmap_from_cpu(struct mm_struct *mm, struct svm_range *prange, s = max(start, pchild->start); l = min(last, pchild->last); if (l >= s) - svm_range_unmap_from_gpus(pchild, s, l); + svm_range_unmap_from_gpus(pchild, s, l, trigger); svm_range_unmap_split(mm, prange, pchild, start, last); mutex_unlock(&pchild->lock); } s = max(start, prange->start); l = min(last, prange->last); if (l >= s) - svm_range_unmap_from_gpus(prange, s, l); + svm_range_unmap_from_gpus(prange, s, l, trigger); svm_range_unmap_split(mm, prange, prange, start, last); if (unmap_parent) @@ -2333,7 +2344,7 @@ svm_range_cpu_invalidate_pagetables(struct mmu_interval_notifier *mni, svm_range_unmap_from_cpu(mni->mm, prange, start, last); break; default: - svm_range_evict(prange, mni->mm, start, last); + svm_range_evict(prange, mni->mm, start, last, range->event); break; } -- cgit v1.2.3 From 414e9f520e897818302a6b1729aa2dad8cc928ca Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Fri, 8 Apr 2022 10:25:11 -0400 Subject: drm/amdkfd: Asynchronously free smi_client The synchronize_rcu may take several ms, which noticeably slows down applications close SMI event handle. Use call_rcu to free client->fifo and client asynchronously and eliminate the synchronize_rcu call in the user thread. Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c index e5896b7a16dd..0472b56de245 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c @@ -38,6 +38,7 @@ struct kfd_smi_client { uint64_t events; struct kfd_dev *dev; spinlock_t lock; + struct rcu_head rcu; pid_t pid; bool suser; }; @@ -137,6 +138,14 @@ static ssize_t kfd_smi_ev_write(struct file *filep, const char __user *user, return sizeof(events); } +static void kfd_smi_ev_client_free(struct rcu_head *p) +{ + struct kfd_smi_client *ev = container_of(p, struct kfd_smi_client, rcu); + + kfifo_free(&ev->fifo); + kfree(ev); +} + static int kfd_smi_ev_release(struct inode *inode, struct file *filep) { struct kfd_smi_client *client = filep->private_data; @@ -146,10 +155,7 @@ static int kfd_smi_ev_release(struct inode *inode, struct file *filep) list_del_rcu(&client->list); spin_unlock(&dev->smi_lock); - synchronize_rcu(); - kfifo_free(&client->fifo); - kfree(client); - + call_rcu(&client->rcu, kfd_smi_ev_client_free); return 0; } -- cgit v1.2.3 From 3db7f894549a54dd6f8dfb7fe213ede83249bb94 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Wed, 19 Jan 2022 12:57:26 -0500 Subject: drm/amdkfd: Bump KFD API version for SMI profiling event Indicate SMI profiling events available. Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- include/uapi/linux/kfd_ioctl.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 280edda46faf..d993a0d50994 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -35,9 +35,10 @@ * - 1.7 - Checkpoint Restore (CRIU) API * - 1.8 - CRIU - Support for SDMA transfers with GTT BOs * - 1.9 - Add available memory ioctl + * - 1.10 - Add SMI profiler event log */ #define KFD_IOCTL_MAJOR_VERSION 1 -#define KFD_IOCTL_MINOR_VERSION 9 +#define KFD_IOCTL_MINOR_VERSION 10 struct kfd_ioctl_get_version_args { __u32 major_version; /* from KFD */ -- cgit v1.2.3 From 0d8928a94ba18205cc7b41793af333e6731e9d76 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Thu, 30 Jun 2022 14:46:18 -0400 Subject: drm/amd/display: Fix __umoddi3 undefined for 32 bit compilation While we tried to build amdgpu on i386, we got this error: ERROR: modpost: "__umoddi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! This commit fixes this issue by replacing the standard module operator with div_u64_rem. Cc: Aurabindo Pillai Cc: Harry Wentland Cc: Alex Deucher Cc: Randy Dunlap Fixes: d3dfceb58de5 ("drm/amd/display: Add dependant changes for DCN32/321") Reported-by: Stephen Rothwell Acked-by: Randy Dunlap Tested-by: Randy Dunlap # build-tested Reviewed-by: Alex Deucher Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c index a10ec5919194..790aa2b3952c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c @@ -208,12 +208,14 @@ static uint32_t dcn32_cache_lines_for_surface(struct dc *dc, uint32_t surface_si uint32_t num_cached_bytes = 0; uint32_t remaining_size = 0; uint32_t cache_line_size = dc->caps.cache_line_size; + uint32_t remainder = 0; /* 1. Calculate surface size minus the number of bytes stored * in the first cache line (all bytes in first cache line might * not be fully used). */ - num_cached_bytes = cache_line_size - (start_address % cache_line_size); + div_u64_rem(start_address, cache_line_size, &remainder); + num_cached_bytes = cache_line_size - remainder; remaining_size = surface_size - num_cached_bytes; /* 2. Calculate number of cache lines that will be fully used with -- cgit v1.2.3 From 071ebbb0d4826ce7c47953b955a522f503dcedfb Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Thu, 30 Jun 2022 14:46:19 -0400 Subject: drm/amd/display: Fix __floatunsidf undefined for 32 bit compilation When we tried to compile DCN32/321 for 32-bit architecture, we got this error message: ERROR: modpost: "__floatunsidf" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! This was caused because we were trying to assign an unsigned int to a double value which causes issues for 32-bit architecture. This issue can be fixed by changing the value type. Cc: Aurabindo Pillai Cc: Harry Wentland Cc: Alex Deucher Cc: Randy Dunlap Fixes: 265280b99822 ("drm/amd/display: add CLKMGR changes for DCN32/321") Reported-by: Stephen Rothwell Acked-by: Randy Dunlap Tested-by: Randy Dunlap # build-tested Reviewed-by: Alex Deucher Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index 9ae9439c8f7b..5d2b028e5dad 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -208,7 +208,7 @@ struct wm_table { struct dummy_pstate_entry { unsigned int dram_speed_mts; - unsigned int dummy_pstate_latency_us; + double dummy_pstate_latency_us; }; struct clk_bw_params { -- cgit v1.2.3 From 202804b9705ce26788c443a54aec47eae20f4596 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Thu, 30 Jun 2022 14:46:20 -0400 Subject: drm/amd/display: Fix __muldf3 undefined for 32 bit compilation Sometimes when trying to enable some feature, we have to define some values with educated guesses, but we mark those values as TBD, which means "To Be Determined". However, the correct way to approach it is by loading that information from the firmware. Anyway, some of the values that we were experimenting with caused this issue: ERROR: modpost: "__muldf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! This commit fixes this issue by removing the division by two since it is harmless in this case. Cc: Aurabindo Pillai Cc: Harry Wentland Cc: Alex Deucher Cc: Randy Dunlap Fixes: 265280b99822 ("drm/amd/display: add CLKMGR changes for DCN32/321") Acked-by: Randy Dunlap Tested-by: Randy Dunlap # build-tested Reviewed-by: Alex Deucher Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 4e8059f20007..b49a4e34d39b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -213,8 +213,8 @@ static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr) clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true; clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us; clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us; - clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD - clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD + clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us; // TBD + clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; // TBD clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL; clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF; -- cgit v1.2.3 From 780f97cec866e1ec6967c66c2a1f68b8aa1e3f23 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Thu, 30 Jun 2022 14:46:21 -0400 Subject: drm/amd/display: Fix __nedf2 undefined for 32 bit compilation When we tried to compile DCN32/321 for 32-bit architecture, we got this error message: ERROR: modpost: "__nedf2" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! This commit fixes this issue by rewriting a small part of the dcn32_build_wm_range_table. Cc: Aurabindo Pillai Cc: Harry Wentland Cc: Alex Deucher Cc: Randy Dunlap Fixes: 265280b99822 ("drm/amd/display: add CLKMGR changes for DCN32/321") Acked-by: Randy Dunlap Tested-by: Randy Dunlap # build-tested Reviewed-by: Alex Deucher Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index b49a4e34d39b..1edb5aab8990 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -155,10 +155,14 @@ static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr) uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; uint16_t setb_min_uclk_mhz = min_uclk_mhz; - uint16_t setb_min_dcfclk_mhz = min_dcfclk_mhz; + uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; + /* For Set B ranges use min clocks state 2 when available, and report those to PM FW */ - if (clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz) - setb_min_dcfclk_mhz = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; + if (dcfclk_mhz_for_the_second_state) + clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state; + else + clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; + if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; @@ -181,7 +185,6 @@ static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr) clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us; clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; - clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = setb_min_dcfclk_mhz; clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF; clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz; clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF; -- cgit v1.2.3 From c5da61cf5bab30059f22ea368702c445ee87171a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 27 Jun 2022 16:35:43 -0400 Subject: drm/amdgpu/display: add missing FP_START/END checks dcn32_clk_mgr.c Properly handle FP code in dcn32_clk_mgr.c. Fixes: 265280b99822 ("drm/amd/display: add CLKMGR changes for DCN32/321") Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 1edb5aab8990..c0989a04d025 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -291,8 +291,10 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) /* Get UCLK, update bounding box */ clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base); + DC_FP_START(); /* WM range table */ dcn32_build_wm_range_table(clk_mgr); + DC_FP_END(); } static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, @@ -727,9 +729,11 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) &num_levels); clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1; + DC_FP_START(); /* Refresh bounding box */ clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box( clk_mgr->base.ctx->dc, clk_mgr_base->bw_params); + DC_FP_END(); } static bool dcn32_are_clock_states_equal(struct dc_clocks *a, -- cgit v1.2.3